TW201921649A - Array substrate and OLED display device - Google Patents

Abstract

The embodiment of the present invention discloses an array substrate and an OLED display device, wherein the array substrate includes a first thin film transistor (10) and a second thin film transistor (20). The first thin film transistor (10) includes a first gate (11), a first semiconductor (12) and a first metal layer (13). The second thin film transistor (20) includes a second gate (21), a second semiconductor (22), a second source (221) and a second metal layer (23). The second gate (21) and the second semiconductor (22) constitute a transistor structure, and the second metal layer (23) is electrically connected to the second source (221). In the first thin film transistor (10), the first gate (11) is electrically connected to the first metal layer (13), which can enhance the electrical transmission capacity of the first thin film transistor (10) and facilitate the release of static electricity to enhance the stability of the substrate.

Description

Array substrate and organic light emitting diode display device

The present invention relates to the field of display technologies, and in particular, to an array substrate and an organic light emitting diode (OLED) display device including the array substrate.

A display device such as a liquid crystal display (LCD), an Organic Light-Emitting Diode (OLED) display or the like includes an electric field generating electrode pair and an electrooptic layer disposed therebetween. A liquid crystal display (LCD) includes a liquid crystal layer as an electro-optic effect layer, and an organic light-emitting diode (OLED) display includes an organic emission layer as an electro-optic effect layer.

The display device may further include a Thin Film Transistor (TFT) which is a three-terminal element as a switching element. How to effectively set the thin film transistor to optimize the display device in terms of stability, luminous efficiency, energy consumption control, etc. has been a research topic.

In view of this, the present invention provides an array substrate and an organic light emitting diode display device, which are intended to enhance the stability of the array substrate, thereby improving the use effect.

To this end, the present invention provides an array substrate comprising a first thin film transistor and a second thin film transistor.

The first thin film transistor includes a first gate, a first semiconductor, and a first metal layer, the first gate is insulated from the first semiconductor, and the first metal layer is disposed on the first semiconductor Located away from a side of the first gate and insulated from the first semiconductor, the first metal layer is electrically connected to the first gate.

The second thin film transistor includes a second gate, a second semiconductor, a second source, and a second metal layer, the second gate is insulated from the second semiconductor, and the second source is a second semiconductor electrical connection, the second metal layer is disposed on a side of the second semiconductor away from the second gate, and is insulated from the second semiconductor, the second metal layer is The second source is electrically connected.

Optionally, the first thin film transistor further includes a bridge portion, and two ends of the bridge portion are electrically connected to the first gate and the first metal layer, respectively.

Optionally, the first thin film transistor further includes a first source and a first drain, and the first source and the first drain are respectively connected to two sides of the first semiconductor, The bridge portions are respectively insulated from the first source and the first drain.

Optionally, the first source, the first drain and the bridge are formed by etching through a same metal material layer.

Optionally, the first metal layer includes a main body portion and an extending portion extending outward from one side of the longitudinal direction of the main body portion, and the bridging portion is electrically connected to the extending portion.

Optionally, an angle between the extending direction of the extending portion and the length direction of the main body portion is between 60 degrees and 120 degrees.

Optionally, the array substrate further includes a barrier layer, a gate insulating layer and a source drain insulating layer, the barrier layer covers the first metal layer, and the first semiconductor is formed on the barrier layer a gate insulating layer is formed on the first semiconductor and the barrier layer, the first gate is formed on the gate insulating layer, and the source drain insulating layer covers the first gate, The gate insulating layer, the first semiconductor, and the barrier layer, the first source, the first drain, and the bridge layer are formed on the source drain insulating layer.

Optionally, the barrier layer is provided with a first through hole corresponding to the position of the extending portion, and the source drain insulating layer is provided with a second through hole corresponding to the first through hole, and one end of the bridge portion passes The first through hole and the second through hole are electrically connected to the extension portion.

Optionally, the source drain insulating layer is provided with a third through hole corresponding to the position of the first gate, and the other end of the bridge is electrically connected to the first gate through the third through hole .

Optionally, the second thin film transistor further includes a second drain, the barrier layer further covers the second metal layer, and the second semiconductor is formed on the barrier layer, the gate insulating layer Formed on the second semiconductor, the second gate is formed on the gate insulating layer, and the source drain insulating layer further covers the second gate and the second semiconductor, A second source and the second drain are formed on the source drain insulating layer.

Optionally, the barrier layer is provided with a fourth through hole corresponding to the position of the second metal layer, and the source drain insulating layer is provided with a fifth through hole corresponding to the fourth through hole, the source drain The insulating layer is provided with a sixth through hole corresponding to the position of the second semiconductor, and one end of the second source is electrically connected to the second semiconductor through the sixth through hole, and the other end of the second source passes The fourth through hole and the fifth through hole are electrically connected to the second metal layer.

Optionally, the source drain insulating layer further defines a seventh via hole corresponding to the position of the second semiconductor, and the second drain electrode electrically connects the second semiconductor through the seventh via hole, The fifth through hole, the sixth through hole and the seventh through hole are connected in a straight line.

Optionally, the array substrate further includes an electrostatic discharge bus bar electrically connected to the first thin film transistor for discharging static electricity.

Optionally, the first source is electrically connected to a signal trace of the second thin film transistor, and the first drain is electrically connected to the static discharge bus.

Optionally, the signal trace of the second thin film transistor is a gate line or a source line.

Optionally, the length direction of the second metal layer and the length direction of the second gate are perpendicular to each other.

Optionally, the array substrate comprises a display area and a non-display area, the first thin film transistor is located in the non-display area, and the second thin film transistor is located in the display area.

Based on the above array substrate, the present invention also provides an organic light emitting diode display device, wherein the organic light emitting diode display device includes the array substrate.

In the technical solution of the present invention, the first thin film transistor and the second thin film transistor have different structures, wherein the first metal layer in the first thin film transistor and the first a gate electrical connection, strong electrical transmission capability; a second metal layer in the second thin film transistor is electrically connected to a source of the second thin film transistor, and an electrical transmission capability is weak relative to the first thin film transistor However, the electrical transmission structure is stable to facilitate stable performance of the second thin film transistor. When the first thin film transistor is electrically connected to the second thin film transistor, one ensures that the second thin film transistor has stable use performance, and also increases the electrical transmission capability between the two. Conducive to the effective release of static electricity, so as to avoid electrostatic damage to the device.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without departing from the scope of the present invention are within the scope of the present invention.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. In the embodiment of the present invention, the descriptions of "first", "second", etc. are used for the purpose of description, and are not to be construed as indicating or implying Importance or implied indicates the number of technical features indicated. Thus, features defining "first" and "second" may include at least one of the features, either explicitly or implicitly. In addition, the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. It is also within the scope of protection required by the present invention.

It will be understood that the positional relationship between layers, such as the term "stacking" or "forming" or "applying" or "setting", is used in connection with one or more of the interlaminar materials as described herein. To carry out the expression, those skilled in the art can understand that any term such as "stacking" or "forming" or "applying" may cover all manners, types and techniques of "stacking". For example, sputtering, electroplating, molding, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, Hybrid Physical-Chemical Vapor Deposition , HPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

Referring to FIG. 1 , an embodiment of the present invention provides an array substrate 100 , which is particularly applicable to an organic light emitting diode display device. The array substrate 100 includes a first thin film transistor 10 and a second thin film transistor 20, wherein the first thin film transistor 10 and the second thin film transistor 20 are electrically connected to each other to constitute an application unit. In the embodiment, the array substrate 100 includes a display area 101 and a non-display area 102, and the non-display area 102 is disposed around the display area 101. The second thin film transistor 20 is located in the display area 101 for driving and controlling the organic light emitting diode light-emitting display; the first thin film transistor 10 is located in the non-display area 102 for Electrostatic discharge in the second thin film transistor 20 and the organic light emitting diode display device prevents electrostatic damage to the device.

It can be understood that a plurality of the second thin film transistors 20 can be integrally connected by a connecting line for driving and controlling the organic light emitting diode display device. In the embodiment, the second thin film transistors 20 are disposed substantially in an array in the display area 101.

2 to 4, FIG. 2 is a plan view showing a schematic configuration of the first thin film transistor 10 of FIG. 1, FIG. 3 is a cross-sectional view taken along line A-A of FIG. 2, and FIG. 4 is a cross-sectional view taken along line B-B of FIG.

The first thin film transistor 10 includes a first gate 11 , a first semiconductor 12 , and a first metal layer 13 . The first gate 11 is insulated from the first semiconductor 12 and their positions correspond to form a transistor structure. The first metal layer 13 is disposed on a side of the first semiconductor 12 away from the first gate 11 and is insulated from the first semiconductor 12 . The first metal layer 13 is electrically connected to the first gate 11 .

It can be understood that the first gate 11 and the first metal layer 13 are made of a conductive metal material, such as a metal material such as aluminum, copper, silver, or an alloy thereof; and the first semiconductor 12 is an oxide semiconductor material. For example, indium gallium zinc oxide (IGZO).

The first metal layer 13 can serve as a protective layer to protect the first semiconductor 12 from impurity contamination, and at the same time, the first metal layer 13 is electrically connected to the first gate 11 to cause current Enhanced transmission capacity to facilitate electrostatic discharge. It can be understood that the first metal layer 13 can adjust the characteristics of the first thin film transistor 10, and a potential of a certain value is connected thereto, which can affect the electrical properties of the first semiconductor 12.

In the embodiment, the array substrate further includes a barrier layer 30, a gate insulating layer 40, a source drain insulating layer 50, and a buffer layer 60. The first metal layer 13 is formed on the buffer layer 60, the barrier layer 30 covers the first metal layer 13, and the first semiconductor 12 is formed on the barrier layer 30, thereby making the first A metal layer 13 is insulated from the first semiconductor 12. The gate insulating layer 40 is formed on the first semiconductor 12 and the barrier layer 30, and the first gate 11 is formed on the gate insulating layer 40 and corresponds to the position of the first semiconductor 12 Thus, the first gate 11 is insulated from the first semiconductor 12. The source drain insulating layer 50 covers the first gate 11, the gate insulating layer 40, the first semiconductor 12, and the barrier layer 30. Optionally, the first metal layer 13, the first semiconductor 12, the gate insulating layer 40, and the first gate 11 may be shape-modified by an etching technique.

Optionally, the buffer layer 60, the barrier layer 30, the gate insulating layer 40, and the source drain insulating layer 50 are electrically insulating materials, for example, cerium oxide (SiO2) or tantalum nitride ( SiN) and so on. The source drain insulating layer 50 may encapsulate and protect the first gate 11 and other layer structures from oxidation contamination.

In this embodiment, the first metal layer 13 and the first gate 11 are electrically connected by using a via hole between the layers. As shown in FIGS. 2 and 3, the first thin film transistor 10 further includes a bridge portion 14, and two ends of the bridge portion 14 are electrically connected to the first metal layer 13 and the first gate electrode 11, respectively, thereby The first metal layer 13 is electrically connected to the first gate 11 . Specifically, the first metal layer 13 includes a main body portion 131 and an extending portion 132 extending outward from one side in the longitudinal direction of the main body portion 131. One end of the bridging portion 14 is electrically connected to the extending portion 132. The other end of the bridge portion 14 is connected to one end of the first gate 11. The first through hole 31 is defined in the position of the extending portion 132 of the blocking layer 30. The source through the insulating layer 50 defines a second through hole 51 corresponding to the first through hole 31. The source drain insulating layer 50 is provided with a third through hole 52 corresponding to the position of the first gate 11 . One end of the bridging portion 14 is electrically connected to the extending portion 132 through the first through hole 31 and the second through hole 51, and the other end of the bridging portion 14 passes through the third through hole 52 and the The first gate 11 is electrically connected to realize electrical connection between the first metal layer 13 and the first gate 11.

Optionally, an angle between the extending direction of the extending portion 132 and the length direction of the main body portion 131 is between 60 degrees and 120 degrees. In the embodiment, the extending direction of the extending portion 132 is The angle between the longitudinal directions of the main body portion 131 is 90 degrees.

In this embodiment, as shown in FIG. 4, the first thin film transistor 10 further includes a first source 121 and a first drain 122. The first source electrode 121 and the first drain electrode 122 are respectively connected to two sides of the first semiconductor 12 to respectively form a source and a drain of the first thin film transistor 10. The bridge portion 14 is insulated from the first source 121 and the first drain 122. Optionally, the first source 121 and the first drain 122 are formed on the source drain insulating layer 50, and are electrically connected to both sides of the first semiconductor 12 through via holes, respectively. A first connection hole 53 and a second connection hole 54 are respectively defined on the two sides of the first semiconductor 12, and the first source electrode 121 passes through the first connection hole 53 and the One side of the first semiconductor 12 is electrically connected, and the first drain 122 is electrically connected to the other side of the first semiconductor 12 through the second connection hole 54.

It can be understood that the first source 121 constitutes the source of the first thin film transistor 10, and the first drain 122 constitutes the drain of the first thin film transistor 10, the first gate The pole 11 constitutes a gate of the first thin film transistor 10.

The first source 121 , the first drain 122 , and the bridge 14 are made of a metal material. Optionally, the first source 121 , the first drain 122 , and the bridge 14 are The same metal material layer is formed on the source drain insulating layer 50 and formed by an etching process, wherein the bridge portion 14 is insulated from the first source 121 and the first drain 122, respectively. Settings. Further, the bridge portion 14, the first source 121, and the first drain 122 may be formed together in the same process, that is, a whole layer of continuous may be formed on the source drain insulating layer 50. The metal layer is then patterned by etching into the first source 121, the first drain 122, and the bridge 14.

A middle portion of the first semiconductor 12 corresponds to a position of the first gate 11 , and two sides of the first semiconductor 12 are electrically connected to the first source 121 and the first drain 122 , respectively. The first gate 11 is used on the one hand to correspond to the central position of the first semiconductor 12 to form a transistor structure, and on the other hand, it extends out of a connection end and extends with the first metal layer 13 Electrical connection to form a stable structure to ensure stable performance of the transistor, while also enhancing the current transmission capability.

Referring to FIGS. 5 and 6, the second thin film transistor 20 includes a second gate 21, a second semiconductor 22, a second source 221, a second drain 222, and a second metal layer 23. The second gate 21 is insulated from the second semiconductor 22, and their positions correspond to form a transistor structure. The second metal layer 23 is disposed on the second semiconductor 22 away from the second gate 21. One side is insulated from the second semiconductor 22, and the second metal layer 23 is electrically connected to the second source 221. Optionally, as shown in FIG. 5, the length direction of the second metal layer 23 and the length direction of the second gate 21 are perpendicular to each other.

It can be understood that the second source 221 constitutes the source of the second thin film transistor 20, and the second drain 222 constitutes the drain of the second thin film transistor 20, the second gate The pole 21 constitutes a gate of the second thin film transistor 20.

In this embodiment, as shown in FIG. 6, the second metal layer 23 is formed on the buffer layer 60, the barrier layer 30 further covers the second metal layer 23, and the second semiconductor 22 is formed in the The barrier layer 30 is disposed such that the second metal layer 23 is insulated from the second semiconductor 22. The gate insulating layer 40 is also formed on the second semiconductor 22. The second gate 21 is formed on the gate insulating layer 40 and corresponds to the position of the second semiconductor 22 such that the second gate 21 is insulated from the second semiconductor 22. The source drain insulating layer 50 also covers the second gate 21 and the second semiconductor 22.

The second source 221 is formed on the source drain insulating layer 50 and electrically connected to the second metal layer 23. Specifically, the barrier layer 30 corresponds to the position of one end of the second metal layer 23. A fourth via hole 32 is formed, and the source drain insulating layer 50 defines a fifth via hole 55 corresponding to the fourth via hole 32, and the source drain insulating layer 50 corresponds to a position of one end of the second semiconductor 22 Opening a sixth through hole 56, one end of the second source 221 is electrically connected to the second semiconductor 22 through the sixth through hole 56, and the other end of the second source 221 passes the fourth The through hole 32 and the fifth through hole 55 are electrically connected to the second metal layer 23.

The second drain 222 is formed on the source drain insulating layer 50 and electrically connected to the second semiconductor 22 through a via hole. Specifically, the source drain insulating layer 50 corresponds to the second semiconductor. A seventh through hole 57 is further defined at a position of one end of the 22, and the second drain 222 is electrically connected to the second semiconductor 22 through the seventh through hole 57. Optionally, the fifth through hole 55, the sixth through hole 56 and the seventh through hole 57 are connected in a straight line.

It can be understood that the second gate 21 and the second metal layer 23 are made of a metal material, such as a metal material such as aluminum, copper, silver, or an alloy thereof; and the second semiconductor 22 is an oxide semiconductor material, for example. , indium gallium zinc oxide (IGZO).

In this embodiment, the second metal layer 23 can serve as a protective layer to protect the second semiconductor 22 from impurity contamination, and at the same time, the second metal layer 23 and the second thin film transistor The source 221 of 20 is electrically connected. It can be understood that the second metal layer 23 can adjust the characteristics of the second thin film transistor 20, and a potential of a certain value is connected thereto, which can affect the electrical properties of the second semiconductor 22.

In this embodiment, the middle portion of the second semiconductor 22 corresponds to the position of the second gate 21, and the two sides of the second semiconductor 22 are respectively opposite to the second source 221 and the second drain The second metal layer 23 is electrically connected to the second semiconductor 22 through the second source 221 to form a stable structure to ensure stable performance of the transistor.

In summary, the first thin film transistor 10 and the second thin film transistor 20 have different structures, wherein the first metal layer 13 in the first thin film transistor 10 and the first A gate 11 is electrically connected such that a channel is formed on both the upper and lower sides of the first semiconductor 12, and the electrical transmission capability of the first thin film transistor 10 is enhanced while affecting the electrical properties of the first thin film transistor 10. The second metal layer 23 of the second thin film transistor 20 is electrically connected to the source 221 of the second thin film transistor 20, and the electrical transmission capability is weaker than that of the first thin film transistor 10. However, the electrical transmission structure is stable to facilitate the stable use performance of the second thin film transistor 20. Since the first thin film transistor 10 is an electrostatic protection transistor, the requirement for electrical transmission capability is greater than the stability requirement of the device, and thus the manner in which the first metal layer 13 is connected to the first gate 11 is adopted; The second thin film transistor 20 is a driving transistor of the panel display pixel, and the requirement for device stability is greater than the requirement of electrical transmission capability, so the second metal layer 23 and the second source 221 or the The manner in which the second drain 222 is connected. Therefore, when the first thin film transistor 10 and the second thin film transistor 20 are electrically connected, one ensures that the second thin film transistor 20 has stable use performance, and also increases between the two. Electrical transmission capability, in particular, when the second thin film transistor 20 is applied to a drive control organic light emitting diode light emitting display, the first thin film transistor 10 is applied to the second thin film transistor 20 and organic light emitting When the electrical connection between the electrostatic discharge busbars 30 in the diode display device is made, on the one hand, the second thin film transistor 20 has stable driving control capability, and on the other hand, the electrostatic discharge capability is enhanced to avoid electrostatic shock. Injury device.

Referring to FIG. 7 to FIG. 9 , in some embodiments, the array substrate 100 further includes an electrostatic discharge bus bar 30 electrically connected to the first thin film transistor 10 . A thin film transistor 10 is electrically connected to the second thin film transistor 20, so that static electricity in the unit of the second thin film transistor 20 can be effectively released to prevent electrostatic damage to the device. In this embodiment, the second thin film transistors 20 are connected to each other through signal traces to control the light-emitting display of the organic light-emitting diode. Wherein, the array substrate 100 is provided with a gate line connecting the gates of the second thin film transistor 20, the gate lines constitute signal traces, and the array substrate 100 is provided with the connection of the second thin film a source line of the source of the crystal 20, the source line constituting a signal trace, wherein the array substrate 100 is provided with a drain line connecting the drain of the second thin film transistor 20, and the drain line constitutes a signal trace .

In some embodiments, as shown in FIG. 7, the source line of the second thin film transistor 20 is electrically connected to the source of the first thin film transistor 10, and the source line of the second thin film transistor 20 passes. The first coupling capacitor C1 is electrically connected to the gate of the first thin film transistor 10, and the drain of the first thin film transistor 10 is electrically connected to the static discharge busbar 30. The static charge of the source line of the second thin film transistor 20 is concentrated at the first coupling capacitor C1, and when the voltage across the first coupling capacitor C1 causes the first semiconductor 12 to be turned on, The electrostatic charge of the source line of the second thin film transistor 20 flows out from the source of the first thin film transistor 10 toward the electrostatic discharge bus 30, thereby protecting the second thin film transistor 20 and its connected devices. .

In some embodiments, as shown in FIG. 8, the gate line of the second thin film transistor 20 is electrically connected to the source of the first thin film transistor 10, and the gate line of the second thin film transistor 20 passes. The first coupling capacitor C1 is electrically connected to the gate of the first thin film transistor 10, and the drain of the first thin film transistor 10 is electrically connected to the static discharge busbar 30. The static charge of the gate line of the second thin film transistor 20 is concentrated at the first coupling capacitor C1, and when the voltage across the first coupling capacitor C1 causes the first semiconductor 12 to be turned on, The electrostatic charge of the gate line of the second thin film transistor 20 flows out from the source of the first thin film transistor 10 toward the electrostatic discharge bus 30, thereby protecting the second thin film transistor 20 and its connected device. .

In some embodiments, as shown in FIG. 9, the static electricity release busbar 30 can also be electrically connected to the gate of the first thin film transistor 10 through the second coupling capacitor C2. The static charge of the static electricity release bus bar 30 is concentrated at the second coupling capacitor C2, and when the voltage across the second coupling capacitor C2 is such that the first semiconductor 12 is turned on, the static electricity is discharged from the bus bar 30 The static charge flows out through the first thin film transistor 10 toward the second thin film transistor 20, so that static electricity is effectively and quickly released, avoiding static electricity accumulation and electrically damaging the device.

It can be understood that the electrical connection structure of the first thin film transistor 10 and the second thin film transistor 20 can also be applied to other technical solutions. For example, the second thin film transistor 20 is used to drive and control organic The light emitting diodes are shown, and the first thin film transistor 10 is used to test the structure of the second thin film transistor 20, so that it can be verified whether the structure of the second thin film transistor 20 is normally arranged. The second thin film transistor 20 is structurally stable to ensure stability of the device. The first thin film transistor 10 has stronger electrical transmission capability than the second thin film transistor 20, and the current output is large to increase the signal output frequency. To reduce the cable area.

Based on the array substrate 100 described above, an embodiment of the present invention further provides an organic light emitting diode display device including the array substrate 100. It can be understood that the organic light emitting diode display device includes, but is not limited to, any product or component having a display function, such as a smart phone, a tablet computer, a PC end computer, a smart TV, a digital camera, or a navigator.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧First film transistor

11‧‧‧First Gate

100‧‧‧Array substrate

101‧‧‧ display area

102‧‧‧Non-display area

121‧‧‧first source

122‧‧‧First bungee

13‧‧‧First metal layer

131‧‧‧ Main body

132‧‧‧Extension

14‧‧‧Bridge

20‧‧‧Second thin film transistor

21‧‧‧second gate

22‧‧‧Second semiconductor layer

221‧‧‧second source

222‧‧‧second bungee

23‧‧‧Second metal layer

30‧‧‧Electrostatic release busbar

31‧‧‧First through hole

32‧‧‧fourth through hole

40‧‧‧ gate insulation

50‧‧‧Source 汲polar insulation

51‧‧‧Second through hole

52‧‧‧ third through hole

53‧‧‧First connection hole

54‧‧‧Second connection hole

55‧‧‧5th through hole

56‧‧‧ sixth through hole

57‧‧‧ seventh through hole

60‧‧‧buffer layer

C1‧‧‧First Coupling Capacitor

C2‧‧‧Second coupling capacitor

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. It will be apparent to those skilled in the art that other drawings may be obtained in accordance with the structures illustrated in the drawings without departing from the scope of the invention.

1 is a schematic structural view of an array substrate according to an embodiment of the present invention;

Figure 2 is a plan view showing the schematic structure of the first thin film transistor of Figure 1;

Figure 3 is a cross-sectional view taken along line A-A of Figure 2;

Figure 4 is a cross-sectional view taken along line B-B of Figure 2;

Figure 5 is a plan view showing a schematic structure of a second thin film transistor of Figure 1;

Figure 6 is a cross-sectional view taken along line C-C of Figure 5;

FIG. 7 is a schematic diagram of circuit connection of an array substrate according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic diagram of circuit connection of an array substrate according to another embodiment of the present invention; FIG.

FIG. 9 is a schematic diagram of circuit connection of an array substrate according to another embodiment of the present invention.

The implementation, functional features, and advantages of the present invention will be further described in conjunction with the embodiments.

Claims (18)

An array substrate comprising a first thin film transistor and a second thin film transistor; The first thin film transistor includes a first gate, a first semiconductor, and a first metal layer, the first gate is insulated from the first semiconductor, and the first metal layer is disposed on the first semiconductor a first side away from the first gate and insulated from the first semiconductor, the first metal layer is electrically connected to the first gate; The second thin film transistor includes a second gate, a second semiconductor, a second source, and a second metal layer, the second gate is insulated from the second semiconductor, and the second source is a second semiconductor electrical connection, the second metal layer is disposed on a side of the second semiconductor away from the second gate, and is insulated from the second semiconductor, the second metal layer is The second source is electrically connected. The array substrate of claim 1, wherein the first thin film transistor further comprises a bridge portion, and two ends of the bridge portion are electrically connected to the first gate and the first metal layer, respectively. The array substrate of claim 2, wherein the first thin film transistor further includes a first source and a first drain, and the first source and the first drain are respectively connected to the first On both sides of a semiconductor, the bridge portions are respectively insulated from the first source and the first drain. The array substrate of claim 3, wherein the first source, the first drain, and the bridge are formed by etching the same metal material layer. The array substrate according to claim 3, wherein the first metal layer includes a main body portion and an extending portion extending outward from one side in a longitudinal direction of the main body portion, and the bridging portion is electrically connected to the extending portion. The array substrate according to claim 5, wherein an angle between an extending direction of the extending portion and a longitudinal direction of the main body portion is between 60 degrees and 120 degrees. The array substrate of claim 5, wherein the array substrate further comprises a barrier layer, a gate insulating layer and a source drain insulating layer, the barrier layer covering the first metal layer, the first semiconductor forming On the barrier layer, the gate insulating layer is formed on the first semiconductor and the barrier layer, and the first gate is formed on the gate insulating layer, the source drain insulating layer Covering the first gate, the gate insulating layer, the first semiconductor, and the barrier layer, the first source, the first drain, and the bridge layer are formed at the source On the pole insulation layer. The array substrate of claim 7, wherein the barrier layer is provided with a first through hole corresponding to the extending portion, and the source drain insulating layer is provided with a second through hole corresponding to the first through hole. One end of the bridge portion is electrically connected to the extension portion through the first through hole and the second through hole. The array substrate of claim 8, wherein the source drain insulating layer is provided with a third through hole corresponding to the position of the first gate, and the other end of the bridge portion passes through the third through hole The first gate is electrically connected. The array substrate according to claim 7, wherein the second thin film transistor further includes a second drain, the barrier layer further covers the second metal layer, and the second semiconductor is formed on the barrier layer The gate insulating layer is further formed on the second semiconductor, the second gate is formed on the gate insulating layer, and the source drain insulating layer further covers the second gate The second semiconductor, the second source and the second drain are formed on the source drain insulating layer. The array substrate of claim 10, wherein the barrier layer is provided with a fourth through hole corresponding to the position of the second metal layer, and the source drain insulating layer is provided with a fifth corresponding to the fourth through hole. a through hole, the source drain insulating layer is provided with a sixth via hole corresponding to a position of the second semiconductor, and one end of the second source is electrically connected to the second semiconductor through the sixth via hole, The other end of the second source electrically connects the second metal layer to the fifth via through the fourth via. The array substrate of claim 11, wherein the source drain insulating layer is further provided with a seventh through hole corresponding to the position of the second semiconductor, and the second drain is electrically connected through the seventh through hole The second semiconductor, the fifth through hole, the sixth through hole and the seventh through hole are connected in a straight line. The array substrate of claim 10, wherein the array substrate further comprises an electrostatic discharge bus bar electrically connected to the first thin film transistor for discharging static electricity. The array substrate of claim 13, wherein the first source is electrically connected to a signal trace of the second thin film transistor, and the first drain is electrically connected to the electrostatic discharge bus. The array substrate of claim 14, wherein the signal trace of the second thin film transistor is a gate line or a source line. The array substrate according to claim 1, wherein a length direction of the second metal layer and a length direction of the second gate are perpendicular to each other. The array substrate of claim 1, wherein the array substrate comprises a display area and a non-display area, the first thin film transistor is located in the non-display area, and the second thin film transistor is located in the display area . An organic light emitting diode display device, wherein the organic light emitting diode display device comprises the array substrate according to any one of claims 1 to 17.