TW201919241A - Semiconductor structure and method for forming the same - Google Patents

Abstract

The embodiments of the present invention relate to a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a gate trench in the semiconductor substrate, a gate dielectric layer disposed on sidewalls of the gate trench, an extending portion of the gate trench below the gate trench, an insulating stud disposed in the extending portion of the gate trench, a gate electrode disposed in the gate trench and on the insulting stud, a doping well region embedded in the semiconductor substrate on opposite sides of the gate trench, and a source region disposed in the semiconductor substrate on the doping well region.

Description

 Semiconductor structure and method of forming same  

Embodiments of the present invention relate to a semiconductor structure, and more particularly to a semiconductor structure of a power MOSFET.

Semiconductor devices have been widely used in various electronic products such as, for example, personal computers, mobile phones, and digital cameras. The semiconductor device is usually fabricated by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor substrate material on a semiconductor substrate, and then using a lithography process to pattern various material layers, whereby the semiconductor substrate is formed thereon. Circuit parts and components are formed on top.

Among them, the power MOS half-field effect transistor is a field effect transistor which can be widely used in analog circuits and digital circuits, and has the advantages of small power dissipation at the input end and fast switching speed, and thus is expected in the development of power components. .

The breakdown voltage of power MOS field-effect transistor is one of its important parameters. However, according to the prior art, increasing the breakdown voltage usually makes the on resistance and threshold voltage of the transistor rise, which is not conducive to Operation of semiconductor components. Therefore, there are still many problems in today's power MOS field-effect transistors that need to be improved.

Embodiments of the present invention provide a semiconductor structure including a semiconductor substrate, a gate trench in the semiconductor substrate, a gate dielectric layer disposed on a sidewall of the gate trench, and a gate under the gate trench a pole trench extension portion, an insulating pillar disposed in the gate trench extension portion, a gate electrode disposed in the gate trench and the insulating pillar, and a semiconductor substrate embedded in both sides of the gate trench a well region, a source region disposed in the semiconductor substrate on the doped well region.

Embodiments of the present invention also provide a method of forming a semiconductor structure, including providing a semiconductor substrate, forming a gate trench in the semiconductor substrate, forming a gate dielectric layer on a sidewall of the gate trench, and etching a gate The trench is formed to form a gate trench extension under the gate trench, form an insulating pillar in the gate trench extension, form a gate electrode in the gate trench and over the insulating pillar, and form a doping well In the semiconductor substrate on both sides of the gate trench, a source region is formed in the semiconductor substrate on the doped well region.

100‧‧‧Semiconductor substrate

102‧‧‧Elobite area

104‧‧ ‧ gate trench

106‧‧‧First conformal dielectric layer

108‧‧‧Second conformal dielectric layer

108A, 108B, 108C‧‧‧Parts of the second conformal dielectric layer

110‧‧‧Extension of the gate trench

112‧‧‧Insulation column

114‧‧‧gate electrode

116‧‧‧Doped well area

118‧‧‧ source area

120‧‧‧Insulation

122‧‧‧Source contact

124‧‧‧Bungee contact

126‧‧‧One part of the semiconductor substrate

128‧‧‧First dielectric layer

130‧‧‧Second dielectric layer

200‧‧‧Back doped area

300‧‧‧Reducing surface electric field doping

10, 20, 30‧‧‧ semiconductor structure

T‧‧‧ thickness

Embodiments of the present invention will be described in detail below with reference to the drawings. It is noted that the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

1A-1L is a series of cross-sectional views for explaining the manufacturing process of the semiconductor structure of some embodiments of the present invention.

2-3 are cross-sectional views of a semiconductor structure in accordance with some other embodiments of the present invention.

The various features of the embodiments of the invention are set forth in the description of the embodiments of the invention. The examples are for illustrative purposes only and are not intended to limit the scope of the embodiments of the invention. For example, it is mentioned in the specification that the first feature is formed on the second feature, including an embodiment in which the first feature is in direct contact with the second feature, and additionally includes another feature between the first feature and the second feature. An embodiment of the feature, that is, the first feature is not in direct contact with the second feature. It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

The semiconductor structure of the embodiment of the present invention forms a gate trench extension under the gate trench, and then forms an insulating pillar in the gate trench extension portion, the insulating pillar enables the semiconductor structure to maintain a low conduction resistance The value and the threshold voltage increase its breakdown voltage.

Figure 1A depicts the initial steps of this embodiment. First, a semiconductor substrate 100 is provided that can include an epitaxial region 102 and a portion 126 of the semiconductor substrate 100 therebelow. In some embodiments, the doping concentration of portion 126 of semiconductor substrate 100 (eg, 1E18-1E20 cm ⁻³ ) is greater than the doping concentration of epitaxial region 102 (eg, 1E15-1E17 cm ⁻³ ). For example, the semiconductor substrate 100 may include germanium. In some other embodiments, the semiconductor substrate 100 may be other elemental semiconductors, such as germanium; compound semiconductors, such as: silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (indium) Arsenide, InAs) or indium phosphide (InP); alloy semiconductors such as: Silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP) Or gallium indium phosphide (GaInP). The semiconductor substrate 100 may include an epitaxial region 102. For example, a vapor phase epitaxy (VPE), a molecular-beam epitaxy (MBE), or an organometallic vapor deposition may be used. The epitaxial region 102 is formed by a metal organic chemical vapor deposition (MOCVD), a combination of the above, or other suitable methods. For example, the semiconductor substrate 100 can be an N-type substrate or a P-type substrate. For the sake of convenience, the present embodiment is described by taking an N-type field effect transistor in the N-type semiconductor substrate 100 as an example. It will be understood by those skilled in the art that in some other embodiments of the invention, a P-type field effect transistor can also be formed in a P-type semiconductor substrate.

Next, as shown in FIG. 1A, the first dielectric layer 128 and the second dielectric layer 130 are formed over the epitaxial region 102. For example, the first dielectric layer 128 can comprise hafnium oxide, other suitable dielectric materials, or a combination thereof. The first dielectric layer 128 may be formed using chemical vapor deposition (CVD), thermal oxidation, other suitable methods, or a combination thereof. For example, the second dielectric layer 130 can include tantalum nitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the second dielectric layer 130 can be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), other suitable methods, or a combination thereof.

In some embodiments, the first dielectric layer 128 can be a pad oxide layer formed of an oxide, and the second dielectric layer 130 can be a pad nitride layer formed of a nitride ( Pad nitride layer).

Next, referring to FIG. 1B, the gate trench 104 is formed in the epitaxial region 102 of the semiconductor substrate 100. For example, a patterned photoresist and/or a patterned hard mask (not shown) having an opening pattern corresponding to the gate trench 104 may be formed on the first dielectric layer 128 and the second dielectric layer 130. And then performing one or more etching processes by using the patterned photoresist and/or the patterned hard mask as the etching mask to form the second dielectric layer 130 and the first dielectric layer 128 corresponding to the above The opening of the gate trench 104. Then, the patterned photoresist and/or the patterned hard mask are removed, and then the second dielectric layer 130 and the first dielectric layer 128 are used as an etching mask to perform an etching process to form a gate in the epitaxial region 102. Pole trench 104. For example, the etching process may be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments using dry etching, it is advantageous to form a gate trench having a high aspect ratio. 104.

Next, referring to FIG. 1C, the first conformal dielectric layer 106 is formed in the gate trench 104 and covers the sidewalls and the bottom of the gate trench 104. For example, the first conformal dielectric layer 106 may include hafnium oxide, hafnium oxynitride, lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride. (HfON), zirconium oxide (ZrO ₂ ), tantalum silicon oxide (TaSiO _x ), other suitable materials, or a combination thereof. Atomic layer deposition (ALD), molecular beam deposition (MBD), chemical vapor deposition (CVD), thermal oxidation, other suitable methods, or the like may be used. The combination forms a first conformal dielectric layer 106. It should be noted that the first conformal dielectric layer 106 covering the sidewalls of the gate trenches 104 will subsequently serve as a gate dielectric layer for the semiconductor structure, which may be selected in accordance with the desired characteristics of the field effect transistor. Thickness T (for example: 50-800 Å).

Next, as shown in FIG. 1C, a second conformal dielectric layer 108 is formed over the first conformal dielectric layer 106, which may have a portion 108A on the second dielectric layer 130, located in the gate trench. Portion 108B on the sidewall of trench 104 and portion 108C at the bottom of gate trench 104. In some embodiments, the second conformal dielectric layer 108 may have a thickness T' of 3 to 10 μm. For example, the second conformal dielectric layer 108 can comprise tantalum nitride, hafnium oxynitride, or other suitable material. In some embodiments, the second conformal dielectric layer 108 can be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), other suitable methods, or a combination thereof.

Next, as shown in FIG. 1D, an etching process (eg, a dry etching process) is performed to remove portions 108A and portions 108C of the second conformal dielectric layer 108 and expose the first total of the bottom portions of the gate trenches 104. A portion of the dielectric layer 106. As shown in FIG. 1D, the etching process does not substantially remove or remove only a portion 108B of the second conformal dielectric layer 108. Therefore, after the etching process, the sidewalls of the gate trench 104 remain. Portion 108B of second conformal dielectric layer 108. In some embodiments, the second conformal dielectric layer 108 can comprise a different material than the first conformal dielectric layer 106 (eg, the first conformal dielectric layer is an oxide and the second conformal dielectric layer is Nitride), so in the subsequent etching step, the first conformal dielectric layer 106 and the semiconductor substrate 100 may be etched using the remaining portion 108B of the second conformal dielectric layer 108 as an etch mask to form a gate trench. The extension portion 110 (shown in Fig. 1E) will be described in detail later.

Next, referring to FIG. 1E, the gate trench 104 is recessed to form a gate trench extension 110 below the gate trench 104. As described above, in some embodiments, the portion 108B of the remaining second conformal dielectric layer 108 can be used as an etch mask to perform one or more etching processes to sequentially etch the first portion at the bottom of the gate trench 104. The conformal dielectric layer 106 and the epitaxial regions 102 of the semiconductor substrate 100 form the gate trench extensions 110, thereby eliminating the need for an additional mask and saving cost. For example, the etching process described above may be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments, as shown in FIG. 1E, the width of the extension 110 of the gate trench is less than the width of the gate trench 104.

Next, referring to FIG. 1F, the insulating pillar 112 is formed in the extending portion 110 of the gate trench. For example, the insulating pillars 112 can include oxides, nitrides, oxynitrides, other suitable materials, or combinations thereof. In some embodiments, a local Oxidation process is performed to form an oxide insulating pillar 112 in the extension 110 of the gate trench. For example, in performing the above partial oxidation process, a portion 108B of the remaining second conformal dielectric layer 108 can be used as an oxide mask to prevent the thickness of the first conformal dielectric layer 106 from being substantially oxidized. The change does not maintain the proper thickness selected in accordance with the desired characteristics of the field effect transistor.

Next, referring to FIG. 1G, an etching process is performed to remove the first dielectric layer 130, the second conformal dielectric layer 108, the first dielectric layer 128, and the first conformal dielectric outside the gate trench 104. Layer 106. For example, the etching process described above may be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments, the second conformal dielectric layer 108 can be removed by a wet etch process and removed from the second dielectric layer 130, the first dielectric layer 128, and the gate trench 104 by a dry etch process. First conformal dielectric layer 106. In some other embodiments, a chemical mechanical polishing (CMP) may also be used, and a removable material such as a photoresist may be filled in the gate trench 104 to protect the gate trench 104. The first conformal dielectric layer 106 and the insulating pillars 112 in the extension 110 of the gate trench.

Next, referring to FIG. 1H, the gate electrode 114 is formed in the gate trench 104. For example, the gate electrode 114 can comprise polysilicon, a metallic material, and/or a germanide thereof, other suitable electrically conductive materials, or combinations thereof. In some embodiments, it may be filled by chemical vapor deposition, sputtering, electroplating, resistance heating evaporation, electron beam evaporation (EB), or other suitable deposition methods. A suitable conductive material is implanted into the gate trench 104 to form the gate electrode 114. In addition, after depositing the conductive material, a chemical mechanical polishing process or an etch back process may be performed as needed to remove excess conductive material outside the gate trenches 104.

Next, as shown in FIG. 1I, doped well regions 116 are formed in the semiconductor substrate 100 on both sides of the gate trenches 104. In the present embodiment, the subsequently formed semiconductor structure 10 is an N-type field effect transistor, and thus the doping well region 116 may be a P-type doped region. For example, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) may be implanted in the semiconductor substrate 100 on both sides of the gate trench 104 to form a P-type doping concentration of 1E15-1E18 cm ^-3 . Doped well region 116. In other embodiments, the subsequently formed semiconductor structure is a P-type field effect transistor, and thus the doped well region 116 can be an N-type doped region. For example, phosphorus ions or arsenic ions may be implanted in the semiconductor substrate 100 on both sides of the gate trench 104 to form an N-type doping well region 116 having a doping concentration of 1E15-1E18 cm ^-3 .

Next, a source region 118 is formed in the semiconductor substrate 100 on the doped well region 116 to form the semiconductor structure 10. In the present embodiment, the semiconductor structure 10 is an N-type field effect transistor, and thus the source region 118 can be an N-type doped region. For example, phosphorous or arsenic ions may be implanted in the semiconductor substrate 100 on the well region 116 to form an N-type source region 118 having a doping concentration of 1E19-1E21Ecm ^-3 . In other embodiments, the semiconductor structure formed is a P-type field effect transistor, and thus the source region 118 can be a P-type doped region. For example, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) may be implanted in the semiconductor substrate 100 on the doped well region 116 to form a P-type source having a doping concentration of 1E19-1E21 cm ^-3 . District 118.

As shown in FIG. 1I, the semiconductor structure 10 of the embodiment of the present invention includes an insulating pillar 112 formed under the gate electrode 114 to increase its breakdown voltage without affecting its conduction resistance and threshold voltage.

Next, as shown in FIG. 1J, the insulating layer 120 and the source contact 122 may be formed on the semiconductor substrate 100 as appropriate. In some embodiments, the source contact 122 can be electrically connected to the source 118 and the doped well region 116 to prevent parasitic bipolar transistors from producing conduction behavior that affects device performance. For example, source contact 122 can comprise a metallic material (eg, tungsten, aluminum, or copper) or other suitable electrically conductive material.

It should be noted that the semiconductor substrate 100 under the insulating pillars 112 can serve as the drain region of the semiconductor structure 10. Further, as shown in FIG. 1J, the drain contact 124 may be formed under the semiconductor substrate 100 as appropriate. For example, the drain contact 124 can comprise a metallic material (eg, tungsten, aluminum, or copper) or other suitable electrically conductive material.

In addition, although in the present embodiment, the insulating pillars 112 are formed in the extension portion 110 of the gate trench, in some other embodiments, as shown in FIG. 1K, the insulating pillars 112 may be formed on the gate. The bottom of the trench 104 can further decompose the electric field and extend the area of the depletion region, thereby increasing the breakdown voltage of the device.

In addition, although the gate trenches 104 and the gate trench extensions 110 each have substantially straight sidewalls in this embodiment, in some other embodiments, the etch parameters may be appropriately controlled such that the gate trenches The grooves 104 and the extensions 110 of the gate trenches may each have a curved sidewall that tapers downward (as shown in FIG. 1L) to avoid the problem of uneven distribution of the electric field.

Various variations of embodiments of the invention are described below. For the sake of explanation, similar component symbols will be used to identify similar components. In addition, the various embodiments may be used in the various embodiments of the present invention, and are not intended to be a specific relationship between the various embodiments and/or structures discussed.

Next, please refer to FIG. 2, which illustrates a semiconductor structure 20 in accordance with another embodiment of the present invention. The semiconductor structure 20 differs from the semiconductor structure 10 in that it further includes a counter doped region 200 surrounding the insulating pillars 112 to further increase the breakdown voltage. The reverse doping region 200 may have the same conductivity type as the semiconductor substrate 100, and its doping concentration is lower than the epitaxial region 102 of the semiconductor substrate 100 (for example, the doping concentration of the epitaxial region 102 of the semiconductor substrate 100 is The doping concentration of the counter doped region 200 has a ratio of 2-8, preferably 4-6). For example, after the formation of the extension trench 110 of the gate trench (as shown in FIG. 1E), before the formation of the insulating pillar 112, the portion 108B of the second conformal dielectric layer 108 and the second dielectric remain. Layer 130 is used as a mask to carry out the implant process to form counter doped regions 200. In some embodiments in which the semiconductor structure 20 is an N-type field effect transistor, a P-type dopant (eg, boron ion, indium ion, or boron difluoride ion (BF ₂ ⁺ )) can be implanted around the insulating pillar 112. In a portion of the epitaxial region 102 of the N-type semiconductor substrate 100, the doping concentration of a portion of the epitaxial region 102 of the N-type semiconductor substrate 100 around the insulating pillar 112 is lowered to form the counter doped region 200. In some embodiments in which the semiconductor structure 20 is a P-type field effect transistor, an epitaxial region 102 of the P-type semiconductor substrate 100 surrounding the insulating pillar 112 may be implanted with an N-type dopant (eg, phosphorus or arsenic ions). In a portion thereof, the doping concentration of a portion of the epitaxial region 102 of the P-type semiconductor substrate 100 around the insulating pillar 112 is lowered to form the counter doped region 200.

Next, please refer to FIG. 3, which illustrates a semiconductor structure 30 in accordance with yet another embodiment of the present invention. The semiconductor structure 30 differs from the semiconductor structure 10 in that it further includes a reduced surface field doped region 300 formed in the semiconductor substrate 100 on both sides of the insulating pillar 112, so that the breakdown voltage can be further increased. The reduced surface electric field doping region 300 may have a conductivity type opposite to that of the semiconductor substrate 100. For example, dopants may be implanted in the semiconductor substrate 100 on both sides of the insulating pillars 112 to form a reduced surface electric field doping region 300 prior to the step of forming the source contacts 122. In some embodiments in which the semiconductor structure 30 is an N-type field effect transistor, a P-type dopant (eg, boron ion, indium ion, or boron difluoride ion (BF ₂ ⁺ )) may be implanted on the insulating pillar 112. The P-type reduced surface electric field doped region 300 is formed in the side N-type semiconductor substrate 100. In some embodiments in which the semiconductor structure 30 is a P-type field effect transistor, an N-type dopant (eg, phosphorus or arsenic ions) may be implanted in the P-type semiconductor substrate 100 on both sides of the insulating pillar 112 to form N. The type reduces the surface electric field doping region 300.

In summary, the semiconductor structure of the embodiment of the present invention forms an insulating pillar under the gate electrode, and the breakdown voltage thereof can be increased. In addition, the semiconductor structure of the embodiment of the present invention may further include the foregoing reverse doped region and/or reduced surface electric field doped region to further increase the breakdown voltage thereof.

The foregoing is a summary of the embodiments of the present invention, and the embodiments of the invention may be better understood by those skilled in the art. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on embodiments of the present invention to achieve the same objectives and/or achieve implementations as described herein. The same advantages as the example. It should be understood by those of ordinary skill in the art that the present invention is not limited by the spirit and scope of the invention. The scope of protection of the embodiments of the present invention is defined by the scope of the appended claims, as defined by the appended claims, without departing from the spirit and scope of the embodiments of the invention. Subject to it.

Claims (18)

 A semiconductor structure includes: a semiconductor substrate; a gate trench in the semiconductor substrate; a gate dielectric layer disposed on a sidewall of the gate trench; and a gate trench extension portion located at the gate Under the gate trench; an insulating pillar disposed in the gate trench extension; a gate electrode disposed in the gate trench and above the insulating pillar; a doped well region, embedded And a source region disposed on the semiconductor substrate on the sides of the gate trench; and a source region disposed in the semiconductor substrate on the doped well region.    The semiconductor structure of claim 1, further comprising: a drain region disposed in the semiconductor substrate under the insulating pillar.    The semiconductor structure of claim 1, wherein the width of the gate trench extension is less than the width of the gate trench.    The semiconductor structure of claim 1, wherein the semiconductor substrate and the source region have a first conductivity type, and the doped well region has a second conductivity type opposite to the first conductivity type. state.    The semiconductor structure of claim 4, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.    The semiconductor structure of claim 4, further comprising: a reduced surface field doped region formed in the semiconductor substrate on both sides of the insulating pillar and having the second conductivity type.    The semiconductor structure of claim 4, further comprising: a reverse doped region formed in the semiconductor substrate and surrounding the insulating pillar, wherein the reverse doped region has the same as the semiconductor substrate The first conductivity type.    The semiconductor structure of claim 7, wherein the doping concentration of the counter doped region is lower than the doping concentration of the semiconductor substrate.    The semiconductor structure of claim 1, wherein the insulating pillar comprises an oxide, a nitride, an oxynitride or a combination thereof.    The semiconductor structure of claim 1, wherein the insulating pillar is disposed at a bottom of the gate trench.    A method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a gate trench in the semiconductor substrate; forming a gate dielectric layer on sidewalls of the gate trench; etching the gate trench Forming a gate trench extension under the gate trench; forming an insulating pillar in the gate trench extension; forming a gate electrode in the gate trench and above the insulating pillar Forming a doped well region in the semiconductor substrate on both sides of the gate trench; and forming a source region in the semiconductor substrate on the doped well region.    The method of forming a semiconductor structure according to claim 11, wherein the step of forming the gate trench extension comprises: forming a first conformal dielectric layer, wherein the first conformal dielectric layer covers the a sidewall and a bottom of the gate trench; forming a second conformal dielectric layer over the first conformal dielectric layer, wherein the second conformal dielectric layer exposes a portion covering the bottom of the gate trench a portion of a conformal dielectric layer; and etching the first conformal dielectric layer and the semiconductor substrate using the second conformal dielectric layer as an etch mask to form the gate trench extension Below the pole groove.    The method of forming a semiconductor structure according to claim 12, wherein the insulating pillar comprises an oxide, a nitride, an oxynitride or a combination thereof.    The method for forming a semiconductor structure according to claim 13, wherein the step of forming the oxide comprises: performing a local Oxidation process using the second conformal dielectric layer as a mask.    The method for forming a semiconductor structure according to claim 12, further comprising: removing the second conformal dielectric layer after forming the insulating pillar and before forming the gate electrode.    The method for forming a semiconductor structure according to claim 12, further comprising: forming a counter doped region in the semiconductor substrate and surrounding the insulating pillar, wherein the counter doped region has the same semiconductor One of the substrates is in a first conductivity type, and the doping concentration of the counter doping region is lower than a doping concentration of the semiconductor substrate.    The method for forming a semiconductor structure according to claim 16, wherein the step of forming the reverse doped region comprises: performing a implantation process using the second conformal dielectric layer as a mask to Having the semiconductor substrate surrounding a portion of the insulating pillar; wherein the dopant has a second conductivity type opposite to the first conductivity type of the semiconductor substrate such that the semiconductor substrate surrounds the insulating pillar The doping concentration of the portion is lowered to form the counter doped region.    The method of forming a semiconductor structure according to claim 17, wherein the implanting process is performed prior to forming the insulating pillar.