TW201916128A - Semiconductor device manufacturing method and joint member - Google Patents

Abstract

Provided are: a manufacturing method for a semiconductor device which has low electric resistance and which exhibits high joint strength; and a joint member. This semiconductor device manufacturing method comprises a joining step for connecting a joint member, which has an electrode and has an adhesive layer and in which the electrode is exposed out of the adhesive layer, to an anisotropically conductive member having an insulative base material and a plurality of conduction passages that penetrate the insulative base material in the thickness direction thereof and that are disposed in such a manner as to be electrically insulated from each other. It is preferable to include, before the joining step, an exposure step for exposing the electrode of the joint member.

Description

Manufacturing method of semiconductor element and joining member

The present invention relates to a method for manufacturing a semiconductor element using an anisotropic conductive member and a bonding member used in the method for manufacturing a semiconductor element, and more particularly, to a method for manufacturing a semiconductor element that achieves both reduction in resistance and improvement in bonding strength, and Joining members.

A structural system formed by filling a plurality of through-holes provided on an insulating substrate with a conductive substance such as metal is one of the fields that have attracted attention in nanotechnology in recent years. For example, it is expected to be an anisotropic conductive member. use. Anisotropic conductive members can be electrically connected between electronic components and circuit substrates only by being inserted between an electronic component such as a semiconductor element and a circuit substrate and pressurized. Therefore, they are widely used as electronic components such as semiconductor components. Electrical connection members and inspection connectors when performing functional inspections. In particular, miniaturization of electronic components such as semiconductor elements is remarkable. In the method of directly connecting the wiring substrate like the conventional wire bonding, flip-chip bonding, and autoclave bonding, etc., the stability of the electrical connection of electronic components cannot be fully guaranteed. Therefore, anisotropic conductive members have been regarded as electronic connection members. Note.

Patent Document 1 describes an anisotropic conductive member. The anisotropic conductive member is provided with a plurality of conductive paths penetrating in a thickness direction of an insulating base material, and the conductive members are provided in a state of being insulated from each other. Structure; an adhesive layer is provided on the surface of the insulating base material, each of the conductive paths has a protruding portion protruding from the surface of the insulating base material, and an end portion of the protruding portion of each conductive path is exposed or protruded from the surface of the adhesive layer. In addition, Patent Document 1 describes a multilayer wiring substrate in which an anisotropic conductive member and a wiring substrate electrically connected to a conductive material of the anisotropic conductive member via an electrode are laminated.

In addition to using the anisotropic conductive member as the electronic connection member, there is a semiconductor wafer of Patent Document 2, for example. The semiconductor wafer of Patent Document 2 includes a resin layer in a semi-hardened state, which is disposed on a semiconductor substrate on which an integrated circuit is formed, and a protruding electrode which is connected to the integrated circuit and penetrates the resin layer. The central portion and a lower peripheral portion from the central portion have grooves formed between the central portion and the resin layer by the outer peripheral portion. [Prior Art Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2016/006660 [Patent Document 2] Japanese Patent Laid-Open No. 2014-033067

Regardless of the anisotropic conductive member of Patent Document 1 and the semiconductor wafer of Patent Document 2, if the resin for adhesion remains on the surface, it will cause the on-resistance. In addition, since the resin used for the bonding is sandwiched between the electrode and the conductive path, the bonding between the metals is hindered. Thereby, the electric resistance becomes large, and it is difficult to obtain sufficient bonding strength.

An object of the present invention is to provide a method for manufacturing a semiconductor element and a bonding member which eliminate the problems based on the above-mentioned prior art, have a small resistance, and have high bonding strength.

To achieve the above object, the present invention provides a method for manufacturing a semiconductor device having a bonding process, the bonding process bonding the following components: a bonding member having an electrode and a bonding layer and the electrode is exposed from the bonding layer; and an anisotropic conductive member It has an insulating base material, and a plurality of conducting paths that penetrate through the thickness direction of the insulating base material and are electrically insulated from each other. It is preferable to have an exposure process of an electrode which exposes a joining member before a joining process. The exposure process is preferably a process in which the electrode is exposed by using any of cutting, grinding, grinding, dry etching, and wet etching. The bonding member is preferably a member in which the adhesive layer is more prominently disposed than the electrode.

The conductive path protrudes from the insulating substrate in the thickness direction. The height of the protruding portion of the conductive portion of the anisotropic conductive member is Hd. The height of the bonding layer of the bonding member is Ha. The height of the electrode is set. When it is Hs, Hd≥Ha-Hs is more preferable. The bonding process is preferably a process of bonding a bonding member and an anisotropic conductive member through an adhesive layer. The adhesive layer contains a thermosetting resin, and the exposure process is preferably a process performed under the condition that the thermosetting resin is not thermally cured. The present invention also provides a bonding member used in the method for manufacturing a semiconductor element. [Inventive effect]

According to the present invention, it is possible to manufacture a semiconductor element having a small resistance and a high bonding strength. [Illustrated simple illustration]

FIG. 1 is a schematic diagram showing a first example of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a second example of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic diagram showing a process of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic diagram showing a process of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a schematic diagram showing a process of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic diagram showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic diagram showing a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a schematic enlarged view showing a part of a semiconductor element manufactured by a method of manufacturing a semiconductor element according to an embodiment of the present invention. 10 is a schematic cross-sectional view showing a semiconductor member used in a method of manufacturing a semiconductor element according to an embodiment of the present invention. 11 is a schematic plan view showing an example of an anisotropic conductive member used in a method of manufacturing a semiconductor element according to an embodiment of the present invention. 12 is a schematic cross-sectional view showing an example of an anisotropic conductive member used in a method for manufacturing a semiconductor element according to an embodiment of the present invention.

Hereinafter, a method for manufacturing a semiconductor element and a bonding member according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings. The diagrams described below are illustrative diagrams for explaining the present invention, and the present invention is not limited to the diagrams shown below. In addition, "~" which shows a numerical range below means the numerical value included in both sides. For example, ε is a numerical value α to a numerical value β, and the range of ε is a range including the numerical value α and the numerical value β. When expressed by a mathematical symbol, α ≦ ε ≦ β. If the angles such as "orthogonal" are not specifically described, they include the error range generally allowed in the technical field.

Hereinafter, as a bonding member, a method of manufacturing a semiconductor element will be described using a semiconductor member as an example. A bonding member refers to a member constituting a semiconductor element, and for example, performs a specific function as a single body. In addition, a plurality of members aggregated to perform a specific function are also included in the joining member. FIG. 1 is a schematic diagram showing a first example of a semiconductor element manufactured by a method of manufacturing a semiconductor element according to an embodiment of the present invention, and a schematic diagram showing a second example of a semiconductor element manufactured by the method of manufacturing a semiconductor element according to an embodiment of the present invention. The semiconductor element 10 shown in FIG. 1 is, for example, a semiconductor member 12 and a semiconductor member 14 that are joined and electrically connected using an anisotropic conductive member 15. The semiconductor members 12 and 14 are both bonding members, and these may have the same structure or different structures. In addition, the semiconductor element 10 may be in a form in which at least the semiconductor member 12 or the semiconductor member 14 is bonded to and electrically connected to the anisotropic conductive member 15. In addition, the semiconductor element 10 is a form in which one semiconductor member 14 is bonded to one semiconductor member 12, but it is not limited thereto. The semiconductor element 10 shown in FIG. 2 may have a form in which three anisotropic conductive members 15 are used to join three semiconductor members 12, 14, and 16. The semiconductor element 10 is constituted by three semiconductor members 12, 14, 16 and two anisotropic conductive members 15. In the semiconductor element 10 shown in FIG. 2, the semiconductor components 12, 14, and 16 may all have the same structure or different structures.

In the semiconductor element 10, the semiconductor members 12, 14, and 16 are all electrodes and an adhesive layer, and the electrodes are exposed from the adhesive layer. The semiconductor component will be described in detail later.

The semiconductor element 10 is, for example, a completer, and a single unit performs a specific function. The semiconductor members 12, 14, and 16 each perform a specific function such as wiring, a circuit, or a sensor for transmitting signals, etc., and include semiconductor elements, circuit elements, and sensor elements as a structure. The semiconductor device includes a passive device and an active device. A semiconductor element is also called a semiconductor wafer. In addition, the semiconductor component includes those for transmitting and receiving signals from a wiring board, an interposer, and the like, and transmitting and receiving voltages and currents. The anisotropic conductive member 15 will be described in detail later. The anisotropic conductive member 15 includes an insulating base material and a plurality of conductive paths that penetrate through the insulating base material in a thickness direction and are electrically insulated from each other.

Next, a method for manufacturing a semiconductor element will be described. 3 to 8 are schematic views sequentially showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a schematic enlarged view showing a part of a semiconductor element manufactured by a method of manufacturing a semiconductor element according to an embodiment of the present invention. First, as shown in FIG. 3, a semiconductor member 12 is prepared. The semiconductor member 12 is, for example, a plurality of electrodes 22 provided on the semiconductor element 20 for exchanging signals with the outside or transmitting and receiving voltages or currents. Each electrode 22 is electrically insulated by an insulating layer 24. The electrode 22 is more prominent than the surface 24 a of the insulating layer 24, for example. The semiconductor component 12 has an adhesive layer 26 covering the electrodes 22 and the insulating layer 24. The adhesive layer 26 is used to join the semiconductor member 12 and the anisotropic conductive member 15. The adhesive layer 26 is formed by, for example, spin coating.

The bonding layer 26 of the semiconductor component 12 shown in FIG. 3 is processed, and the electrode 22 of the semiconductor component 12 is exposed from the bonding layer 26 as shown in FIG. 4. Exposing the electrode 22 from the adhesive layer 26 means a state in which the adhesive layer 26 does not exist at least on the surface 22 a of the electrode 22 with respect to the adhesive layer 26. The surface 22a of the electrode 22 may be located on the same plane as the surface 26a of the bonding layer 26, may be located at a protruding portion, or may be located at a recessed portion. The process of exposing the electrode 22 from the bonding layer 26 is an exposure process. Regarding the exposure process, any process can be used as long as the electrode 22 can be exposed from the adhesive layer 26, and a process including at least one of cutting, grinding, grinding, dry etching, and wet etching is preferred. In addition, the exposure process may be constituted by, for example, a person showing liquid repellency with respect to the adhesive layer 26 so as to present a state in which the surface 22 a of the electrode 22 is not covered by the adhesive layer 26. In addition, it is also possible to form the electrode 22 based on the buried layer after the bonding layer 26 is formed. In addition, the electrode height can be reduced by etching the electrode after the exposure process, so that the electrode height is lower than the surface 26 a of the bonding layer 26.

Next, the semiconductor member 14 shown in FIG. 5 is prepared. The semiconductor member 14 and the semiconductor member 12 have the same structure. The semiconductor component 14 is, for example, a plurality of electrodes 32 provided on the interposer substrate 30 for exchanging signals with the outside or transmitting and receiving voltages or currents. Each electrode 32 is electrically insulated by an insulating layer 34. The electrode 32 protrudes more than the surface 34 a of the insulating layer 34, for example. The semiconductor component 14 has an adhesive layer 26 covering the electrodes 32 and the insulating layer 34. The interposer substrate 30 has, for example, a lead-out wiring layer, and the semiconductor element 10 is electrically connected to the outside through an electrode 32. The adhesive layer 26 of the semiconductor member 14 is used to join the semiconductor member 14 and the anisotropic conductive member 15. Next, as shown in FIG. 6, the electrode 32 is exposed from the bonding layer 26 by the above-mentioned exposure process in the same manner as the semiconductor member 12. At this time, the adhesion layer 26 does not exist on the surface 32 a of the electrode 32.

Next, an anisotropic conductive member 15 is prepared. The anisotropic conductive member 15 includes a plurality of conductive paths 42 (see FIGS. 9 and 12). For example, the anisotropic conductive member 15 does not include a member having a bonding function like the adhesive layer 26 of the semiconductor member 12. Furthermore, as long as the front end portion of the protruding portion 42a (see FIG. 12) and the front end portion of the protruding portion 42b (see FIG. 12) are not present, a resin layer 43 (see FIG. 12) having a bonding function like the adhesive layer 26 may be present. . The anisotropic conductive member 15 will be described in detail later.

Next, as shown in FIG. 7, the semiconductor member 12 and the semiconductor member 14 are disposed with the anisotropic conductive member 15 interposed therebetween. At this time, for example, alignment is performed using alignment marks (not shown) provided on the semiconductor members 12 and 14 and the anisotropic conductive member 15. Moreover, the alignment using the alignment mark is not particularly limited as long as an image of the alignment mark or a reflection image can be obtained to obtain the position information of the alignment mark, and known alignment means can be appropriately used. .

Next, the semiconductor member 12 and the anisotropic conductive member 15 are bonded, and the semiconductor member 14 and the anisotropic conductive member 15 are bonded. Thereby, as shown in FIG. 8, the semiconductor element 10 can be manufactured. Furthermore, the above-mentioned semiconductor member 12 and the anisotropic conductive member 15 are joined via the adhesive layer 26, and the joining of the semiconductor member 14 and the anisotropic conductive member 15 is a joining process. In the bonding process, for example, the bonding may be performed under a predetermined condition in a state of temporary bonding, or the temporary bonding may be omitted. In addition, the bonding in the bonding process is also called a formal bonding.

Temporary bonding means fixing in a state where the semiconductor members 12 and 14 are aligned with the anisotropic conductive member 15. The temperature conditions in the temporary bonding process are not particularly limited, but 0 ° C to 300 ° C is preferred, 10 ° C to 200 ° C is more preferred, and normal temperature (23 ° C) to 100 ° C is particularly preferred. Similarly, the pressing conditions in the temporary joining process are not particularly limited, but 10 MPa or less is more preferable, 5 MPa or less is more preferable, and 1 MPa or less is particularly preferable.

The temperature conditions in the formal joining are not particularly limited, but a temperature higher than the temperature of the temporary joining is preferable, and specifically, 150 ° C to 350 ° C is more preferable, and 200 ° C to 300 ° C is particularly preferable. In addition, the pressurizing conditions in the formal joining are not particularly limited, but 30 MPa or less is preferable, and 0.1 MPa to 20 MPa is more preferable. In addition, the time for formal joining is not particularly limited, but 1 to 60 minutes is more preferable, and 5 to 10 minutes is more preferable. By performing the actual bonding under the above-mentioned conditions, the adhesive layer 26 flows, and it is difficult to remain in the electrodes 22 and 32.

FIG. 9 is an enlarged view of a part of the semiconductor element 10 shown in FIG. 8. As shown in FIG. 9, in the semiconductor device 10 manufactured by the above-mentioned bonding process, there is no adhesive layer 26 between the electrode 22 and the conductive path 42 of the anisotropic conductive member 15. With this structure, the electrode 22 and the conductive path 42 directly Contact makes the resistance small. On the other hand, in the semiconductor component 12, there is no adhesion layer 26 on the surface 22 a of the electrode 22, and even if the range of the adhesion layer 26 is narrow, there is adhesion between the insulating layer 24 and the conductive path 42 of the anisotropic conductive member 15. The layer 26 therefore suppresses poor bonding and increases the bonding strength. In addition, the presence of the adhesive layer 26 suppresses misalignment during the temporary bonding described above, and the alignment accuracy of the semiconductor member 12 and the anisotropic conductive member 15 is increased. Furthermore, in the semiconductor member 14 and the anisotropic conductive member 15, the bonding with the semiconductor member 12 and the anisotropic conductive member 15 is also the same. The electrode 32 and the conductive path 42 are in direct contact with each other, so that the resistance becomes small, and the insulating layer is insulated. Since the adhesive layer 26 is present between the layer 34 and the conductive path 42 of the anisotropic conductive member 15, poor bonding is suppressed, and the bonding strength is increased.

When the adhesive layer 26 contains a thermosetting resin, the exposure process is preferably performed under the condition that the thermosetting resin contained in the adhesive layer 26 is not thermally cured. For example, if the thermosetting temperature is 200 ° C, it is preferable to perform the exposure process at a temperature lower than 200 ° C. Here, the condition that the thermosetting resin is not thermally cured is not limited as long as it is lower than the thermosetting temperature of the thermosetting resin. If the thermosetting temperature of the thermosetting resin is T ° C, T-50 ℃ is preferable, and T-100 ℃ is more preferable.

In addition, the semiconductor component is preferably a component in which the adhesive layer is more prominently disposed than the electrode. As shown in FIG. 10, when the height of the adhesive layer 26 of the semiconductor member 12 is Ha and the height of the electrode 22 is Hs, it is preferable that the height Ha of the adhesive layer 26 in the semiconductor member 12 is equal to or higher than the height Hs of the electrode 22. That is, Ha ≧ Hs is more preferable. The height Ha of the adhesive layer 26 is a distance from the surface 20 a of the semiconductor element 20 to the surface 26 a of the adhesive layer. The height Hs of the electrode 22 is a distance from the surface 20 a of the semiconductor element 20 to the surface 22 a of the electrode 22. The height Ha of the bonding layer 26 and the height Hs of the electrode 22 can be determined by cutting the semiconductor member by slicing and observing the cross-sectional shape of the semiconductor member.

Hereinafter, a semiconductor element used in a semiconductor component will be described. The semiconductor element used in the semiconductor member is not particularly limited, and specific examples thereof include the following. Examples of the semiconductor device include ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), and ASSP (Application Specific Standard Product). Logic integrated circuit. In addition, for example, a microprocessor such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) may be mentioned. Examples include DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube), and MRAM (Magnetoresistive Random Access Memory) ), PCM (Phase-Change Memory), ReRAM (Resistance Random Access Memory), FeRAM (Ferroelectric Random Access Memory), flash memory Body and other memory. Examples include LEDs (Light Emitting Diodes), power components, DC (Direct Current) -DC (Direct Current) converters, and Insulated Gate Bipolar Transistors. : IGBT) and other analog integrated circuits. In addition, for example, MEMS (Micro Electro Mechanical Systems) such as an acceleration sensor, a pressure sensor, a vibrator, and a gyro sensor may be mentioned. Examples include GPS (Global Positioning System), FM (Frequency Modulation), NFC (Near Field Communication), and RFEM (RF Expansion Module). ), MMIC (Monolithic Microwave Integrated Circuit), wireless components such as WLAN (Wireless Local Area Network), discrete components, CMOS (Complementary Metal Oxide Semiconductor), CMOS image sensor, CCD (Charge Coupled Device) image sensor, camera module, passive element, SAW (Surface Acoustic Wave) filter, RF (Radio Frequency) filters, IPD (Integrated Passive Devices), etc. The semiconductor component preferably has a plurality of electrodes, the diameter of the electrodes is preferably 5 to 15 μm, and the distance between the electrodes is preferably 10 to 25 μm. The aspect ratio of the electrode is preferably 1.0 to 1.8. From the viewpoint of electrical conductivity, copper, gold, aluminum, and nickel are more preferable, and copper and gold are more preferable. The number of electrodes that are electrically connected to each other through the anisotropic conductive member is preferably 1 to 5 million. In this case, the connection density of each mold is high, and the miniaturization can be promoted. The connection ratio is preferably 90% or more. In this case, reliability can be improved.

As described above, the semiconductor component further includes an interposer. The interposer is a thin wiring structure and is responsible for the electrical connection between semiconductor elements. In addition, it is also responsible for the electrical connection of semiconductor elements and wiring boards. By using the interposer, it is possible to reduce the wiring length and wiring width, reduce parasitic capacitance, and reduce variations in wiring length. The structure of the interposer is not particularly limited as long as it can achieve the functions described above, and known ones can be appropriately used. The interposer can be configured using, for example, organic materials such as polyimide, glass, ceramics, metals, silicon, and polycrystalline silicon.

The bonding layer of the semiconductor component will be described below. [Adhesive Layer] An adhesive layer is a material that provides bonding to a connection target, is provided on a semiconductor member, and exposes an electrode. The adhesive layer is preferably one that exhibits fluidity in a temperature range of 50 ° C to 200 ° C, and is hardened at 200 ° C or higher. The composition of the adhesive layer will be described below. The adhesive layer is composed of a polymer material. The adhesive layer may contain an antioxidant material. Among them, as a method for forming an adhesive layer, for example, a resin composition containing an antioxidant material, a polymer material, a solvent (such as methyl ethyl ketone), etc. is coated on the surface of the semiconductor member, dried, and sintered as required. Methods, etc. The coating method of the resin composition is not particularly limited, and for example, a spin coating method, a gravure coating method, a reverse coating method, a mold coating, a doctor blade coating, a roll coating, an air knife coating, a web, etc. can be used. Conventionally known coating methods such as plate coating, bar coating, and curtain coating. The drying method after coating is not particularly limited, and examples thereof include a treatment in which the temperature is maintained at 0 ° C to 100 ° C for several seconds to tens of minutes, or a reduced pressure at 0 ° C to 80 ° C. Keep processing for ten minutes to several hours. The method of sintering after drying is not particularly limited depending on the polymer materials used, but examples include a process of holding at a temperature of 160 to 240 ° C for 2 minutes to 1 hour, and a temperature of 30 to 80 ° C. Keep processing for 2 to 60 minutes.

<Polymer material> The polymer material included in the adhesive layer is not particularly limited. It can effectively fill the gap between the semiconductor member and the anisotropic conductive member, and the adhesiveness with the semiconductor member becomes higher. For reasons, a thermosetting resin is preferred. Specific examples of the thermosetting resin include epoxy resin, phenol resin, polyimide resin, polyester resin, polyurethane resin, bismaleimide resin, melamine resin, and the like. Isocyanate resin and acrylic resin. Among them, it is preferable to use a polyimide resin and / or an epoxy resin for reasons of better insulation reliability and excellent chemical resistance.

<Antioxidant material> Specific examples of the antioxidant material contained in the adhesive layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2,3,4-tetrazole, 1H-tetrazol-5-acetic acid, 1H-tetrazol-5-succinic acid, 1,2,3-triazole, 4-amino-1 , 2,3-triazole, 4,5-diamino-1,2,3-triazole, 4-carboxy-1H-1,2,3-triazole, 4,5-dicarboxy-1H-1 , 2,3-triazole, 1H-1,2,3-triazole-4-acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4- Triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-carboxy-1,2,4-triazole, 3,5 -Dicarboxyl-1,2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H-benzotriazole-5-carboxylic acid, benzofuran, 2 , 1,3-Benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2-mercaptobenzoxazole , Melamine and these derivatives. Of these, benzotriazole and its derivatives are preferred. Examples of the benzotriazole derivative include a hydroxyl group, an alkoxy group (for example, a methoxy group, an ethoxy group, etc.), an amine group, a nitro group, and an alkyl group (for example, a methyl group) in a benzotriazole benzene ring Group, ethyl, butyl, etc.), halogen atoms (for example, fluorine, chlorine, bromine, iodine, etc.) and the like. In addition, naphthalenetriazole, naphthalenebistriazole, and the same substituted substituted naphthalenetriazole, substituted naphthalenebistriazole, and the like can also be mentioned.

In addition, as other examples of the antioxidant material included in the adhesive layer, general antioxidants, higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, organic Amines, organic ammonium salts, etc.

The content of the antioxidant material contained in the adhesive layer is not particularly limited, but from the viewpoint of the anticorrosive effect, it is preferably 0.0001 mass% or more, and more preferably 0.001 mass% or more with respect to the total mass of the adhesive layer. . In addition, from the reason that an appropriate resistance is obtained in a formal bonding process, 5.0% by mass or less is more preferable, and 2.5% by mass or less is more preferable.

<Migration prevention material> The adhesion layer contains metal ions, halide ions, and metal ions originating from semiconductor elements and semiconductor wafers, which can be included in the adhesion layer, for reasons of further improving insulation reliability. Migration prevention materials are preferred.

As the migration preventing material, for example, an ion exchanger can be used, and specifically, a mixture of a cation exchanger and an anion exchanger can be used or only a cation exchanger can be used. Among them, the cation exchanger and the anion exchanger can be appropriately selected from, for example, an inorganic ion exchanger and an organic ion exchanger described later.

(Inorganic Ion Exchanger) Examples of the inorganic ion exchanger include hydrous oxides of metals represented by hydrous zirconia. Examples of the metal include iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, and bismuth, in addition to zirconium. Among them, zirconium-based ^compounds have an exchange capacity for cations Cu ²⁺ and Al ³⁺ . In addition, iron-based persons also have exchange capabilities for Ag ⁺ and Cu ²⁺ . Similarly, tin-based, titanium-based, and antimony-based cation exchangers are used. On the other hand, those based on bismuth, anions of Cl ^- having a switching capability. Moreover, a zirconium-based person shows anion exchange capacity depending on conditions. The same applies to aluminum and tin. As other inorganic ion exchangers, composites such as acid salts of polyvalent metals represented by zirconium phosphate, heteropoly acid salts represented by ammonium phosphomolybdate, and insoluble ferrocyanide are known. A part of these inorganic ion exchangers are commercially available, for example, various grades of TOAGOSEI CO., LTD. Are known under the trade name "IXE". Furthermore, in addition to synthetic products, powders of inorganic ion exchangers such as natural zeolites and montmorillonite can be used.

(Organic Ion Exchanger) Among the organic ion exchangers, as the cation exchanger, crosslinked polystyrene having a sulfonic acid group can be mentioned, and in addition, a carboxylic acid group, a phosphonic acid group, or a phosphinic acid can be mentioned. Acid group Examples of the anion exchanger include a crosslinked polystyrene having a quaternary ammonium group, a quaternary fluorenyl group, or a tertiary fluorenyl group.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the types of cations and anions to be captured and the exchange capacity for the ions. Of course, it is needless to say that an inorganic ion exchanger and an organic ion exchanger can be used in combination. The manufacturing process of electronic components includes a heating process, so an inorganic ion exchanger is preferred.

Regarding the mixing ratio of the migration preventing material and the above-mentioned polymer material, for example, from the viewpoint of mechanical strength, it is preferable that the migration preventing material is 10% by mass or less, and the migration preventing material is 5% by mass or less. More preferably, it is more preferable that the migration preventing material is 2.5 mass% or less. From the viewpoint of suppressing migration when a semiconductor element or a semiconductor wafer is bonded to the anisotropic conductive member, the migration prevention material is preferably 0.01% by mass or more.

<Inorganic filler> It is preferable that the adhesive layer contains an inorganic filler. The inorganic filler is not particularly limited and can be appropriately selected from known ones, and examples thereof include kaolin, barium sulfate, barium titanate, silicon oxide powder, finely powdered silicon oxide, fumed silica, and amorphous two. Silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconia, yttrium oxide, carbonization Silicon, silicon nitride, etc.

At the time of joining, for the reason that the inorganic filler is prevented from entering between the conductive paths and the conduction reliability is further improved, the average particle diameter of the inorganic filler is preferably larger than the interval between the conductive paths. The average particle diameter of the inorganic filler is preferably 30 nm to 10 μm, and more preferably 80 nm to 1 μm. The average particle diameter is a primary particle diameter measured by a laser diffraction scattering particle size measuring device (Microtrac MT3300 manufactured by NIKKISO CO., LTD.).

<Hardener> The adhesive layer may contain a hardener. When a hardener is contained, from the viewpoint of suppressing poor bonding with the surface shape of the anisotropic conductive member to be connected, it is not used as a hardener which is solid at normal temperature, but is contained as a liquid at normal temperature. Is better. Here, "a solid at normal temperature" means a substance which is solid at 25 ° C, for example, a melting point higher than 25 ° C.

Specific examples of the hardening agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylhydrazone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamine, and tetramine. Carboxylic anhydrides such as methylguanidine, thiourea addition amine, methylhexahydrophthalic anhydride, hydrazine carboxylic acid, hydrazine carboxylic acid, polyphenol compounds, novolac resins, polythiols, etc. The agent can be appropriately selected and used as a liquid at 25 ° C. The hardener may be used alone or in combination of two or more.

The adhesive layer may contain various additives such as a dispersing agent, a buffering agent, and a viscosity modifier, which are widely added to a resin insulating film of a semiconductor package, as long as the characteristics are not impaired. The adhesive layer may contain a thermal acid generator. Examples of the thermal acid generator include ammonium salts, triphenylphosphonium salts, tri-p-tolylphosphonium salts, 4- (phenylthio) phenyldiphenylphosphonium salts, and the like. Phosphonium salts; diphenyliodonium salts, di (p-tolyl) iodonium salts, bis (4-dodecylphenyl) iodonium salts, bis (4-methoxyphenyl) iodonium salts, ( 4-octyloxyphenyl) phenyliodonium salt, bis (4-decoxy) phenyliodonium salt, 4- (2-hydroxytetradecyl) phenylphenyliodonium salt, 4-iso Iodonium salts such as propylphenyl (p-tolyl) iodonium salt, 4-isobutylphenyl p-tolyl) iodonium salt, and the like.

<Shape> The thickness Ts (see Figure 10) of the adhesive layer is preferably 2 to 500 nm. The thickness Ts of the adhesive layer can be determined by slicing the semiconductor member and observing the cross-sectional shape of the semiconductor member.

The anisotropic conductive member 15 will be described below. The anisotropic conductive member 15 can be manufactured by the manufacturing method described in International Publication No. 2015/029881. 11 is a schematic plan view showing an example of an anisotropic conductive member used in a method for manufacturing a semiconductor element according to an embodiment of the present invention, and FIG. 12 is a diagram showing each direction used in a method for manufacturing a semiconductor element according to an embodiment of the present invention. A schematic cross-sectional view of an example of an anisotropic conductive member.

As shown in FIGS. 11 and 12, the anisotropic conductive member 15 includes: an insulating base material 40 including an inorganic material; and a plurality of conductive paths 42 extending in a thickness direction D of the insulating base material 40 (see FIG. 12). ) Through and installed in an electrically insulated state. The via 42 is formed by filling a conductive material in the through-hole 41 formed in the insulating base material 40 and extending in the thickness direction D, and has conductivity. Here, the “state electrically insulated from each other” refers to a state in which each of the conductive paths existing inside the insulating base material is sufficiently low in the conductivity between the conductive paths inside the insulating base material. The conducting paths 42 of the anisotropic conductive member 15 are electrically insulated from each other, and have extremely low conductivity in a direction x orthogonal to the thickness direction D (see FIG. 12) of the insulating base material 40, and have conductivity in the thickness direction D. . As described above, the anisotropic conductive member 15 is a member that exhibits anisotropic conductivity.

As shown in FIG. 12, in the state where the conductive paths 42 are electrically insulated from each other, the insulating base material 40 is provided penetrating in the thickness direction D. As shown in FIG. 12, the via 42 has a protruding portion 42 a protruding from the surface 40 a of the insulating base material 40 in the thickness direction D, and a protruding portion 42 b protruding from the back surface 40 b in the thickness direction D. The anisotropic conductive member 15 may further include a resin layer 43 provided on the front surface 40 a and the back surface 40 b of the insulating base material 40. It is preferable that the resin layer 43 does not contact the front end portion of the protruding portion 42a and the front end portion of the protruding portion 42b. The height Hd of the protruding portion 42a and the height Hd of the protruding portion 42b are preferably 6 nm or more, and more preferably 30 nm to 500 nm. The height Hd of the protruding portion 42 a is a length from the surface 40 a of the insulating base material 40. The height Hd of the protruding portion 42 b is a length from the back surface 40 b of the insulating base material 40.

Regarding the height Hd of the protruding portion 42 a and the height Hd of the protruding portion 42 b, the relationship between the height Ha (see FIG. 10) of the bonding layer of the semiconductor component and the height Hs (see FIG. 10) of the electrode is preferably Hd ≧ Ha-Hs. When the height Hd of the protruding portion 42a and the height Hd of the protruding portion 42b satisfy Hd≥Ha-Hs, the height Hd of the protruding portion 42a and the height Hd of the protruding portion 42b become larger than the height Ha of the bonding layer on the electrode. Since the conductive paths are reliably contacted, the electrical continuity becomes better, which is preferable. As a method of protruding the via from the resin layer, there is etching, and it may be either dry etching or wet etching. As an example of a method of making the vias protrude by wet etching, a method using a solvent for the adhesive layer and removing the adhesive layer on the upper part of the vias by the same method as in the single-chip development can be mentioned. In addition, as an example of a method performed by dry etching, a method of removing the adhesive layer by oxygen plasma to remove the adhesive layer on the upper portion of the via is mentioned.

In addition, in FIG. 12, the surfaces 40 a and 40 b of the insulating base material 40 are shown as having the resin layer 43. However, the present invention is not limited to this, and the resin base 43 may be provided on at least one surface of the insulating base material 40. The structure may be a structure having no resin layer 43 on both surfaces of the insulating base material 40. Similarly, the guide path 42 in FIG. 12 has protruding portions 42 a and 42 b at both ends, but is not limited thereto, and the insulating base material 40 may have a structure having protruding portions on at least one surface of the resin layer 43. .

The thickness h of the anisotropic conductive member 15 shown in FIG. 12 is, for example, 30 μm or less. The TTV (Total Thickness Variation) of the anisotropic conductive member 15 is preferably 10 μm or less. Furthermore, TTV (Total Thickness Variation) = T _Max -T _Min . T _Max is the maximum distance (thickness) from the back reference in the flatness application area. T _Min is the minimum distance (thickness) from the back reference in the flatness application area. Here, the thickness h of the anisotropic conductive member 15 is an average value of 10 points measured in a region corresponding to the thickness h. As a preferable method for measuring the thickness h of the anisotropically conductive member 15, an observation by an electric field emission scanning electron microscope at a magnification of 200,000 times can be used to obtain the outline shape of the anisotropically conductive member 15. A method of measuring an average value of 10 measured values of 10 points in an area corresponding to the thickness h of the anisotropic conductive member 15 in the outline shape. The TTV (Total Thickness Variation) of the anisotropic conductive member 15 is obtained by cutting the anisotropic conductive member 15 for each support 47 with a slice, and observing the cross-sectional shape of the anisotropic conductive member 15 to obtain it. Value.

The anisotropic conductive member 15 is provided on a support body 47 as shown in FIG. 12 for transportation, transportation, conveyance, storage, and the like. A release layer 44 is provided between the support body 47 and the anisotropic conductive member 15. The support body 47 and the anisotropic conductive member 15 are detachably bonded by the release layer 44. As described above, the one in which the anisotropic conductive member 15 is provided on the support 47 via the release layer 44 is referred to as an anisotropic conductive material. The support 47 supports an anisotropic conductive member 15 and is made of, for example, a silicon substrate. As the support body 47, in addition to a silicon substrate, for example, a ceramic substrate such as SiC, SiN, GaN, and alumina (Al ₂ O ₃ ), a glass substrate, a fiber-reinforced plastic substrate, and a metal substrate can be used. Fiber-reinforced plastic substrates also include FR-4 (Flame Retardant Type 4) substrates as printed wiring boards.

Moreover, as the support body 47, a flexible and transparent one can be used. Examples of the flexible and transparent support 47 include PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), and PE (Polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride and TAC (cellulose triacetate) and other plastic films. Here, the term “transparency” refers to a light transmittance of 80% or more based on light having a wavelength used for alignment. Therefore, the transmittance in the entire region of visible light with a wavelength of 400 to 800 nm may be low, but the transmittance in the entire region of visible light with a wavelength of 400 to 800 nm is preferably 80% or more. The transmittance was measured with a spectrophotometer.

It is preferable that the release layer 44 is a laminated layer having a support layer 45 and a release agent 46. The release agent 46 is in contact with the anisotropic conductive member 15, and the support body 47 and the anisotropic conductive member 15 are separated with the release layer 44 as a starting point. For example, by heating to a predetermined temperature, the adhesive force of the release agent 46 is weakened, and the support body 47 is removed from the anisotropic conductive member 15. As the release agent 46, for example, REVALPHA (registered trademark) manufactured by NITTO DENKO CORPORATION. And SOMATAC (registered trademark) manufactured by SOMAR Corporation. Can be used.

The anisotropic conductive member 15 will be described in more detail below. [Insulating base material] The insulating base material is made of an inorganic material, so long as it has a resistivity (approximately 10 ¹⁴ Ω ･ cm) equivalent to that of an insulating base material such as a conventionally-known anisotropic conductive film, It is not particularly limited. In addition, "consisting of an inorganic material" means a rule for distinguishing from a polymer material constituting a resin layer described later, and is not limited to a rule for an insulating base material consisting only of an inorganic material. The material is specified as the main component (50% by mass or more).

Examples of the insulating substrate include metal oxide substrates, metal nitride substrates, glass substrates, ceramic substrates such as silicon carbide and silicon nitride, carbon substrates such as diamond-like carbon, and polyimide groups. Materials and these composite materials. As the insulating base material, for example, it is also possible to form a film from an inorganic material containing a ceramic material or a carbon material in an amount of 50% by mass or more on an organic raw material having through holes.

As the insulating base material, a metal oxide base material is preferable, and an anodized film of a valve metal is more preferable for the reason that micropores having a desired average pore diameter are formed as through holes, and a conductive path described later is easily formed. . Among them, specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, from the viewpoint of good dimensional stability and relatively low cost, an anodized film (base material) of aluminum is preferred.

The distance between the conductive paths in the insulating substrate is preferably 5 nm to 800 nm, 10 nm to 200 nm is more preferable, and 50 nm to 140 nm is more preferable. When the distance between the conductive paths in the insulating substrate is within this range, the insulating substrate sufficiently functions as an insulating partition wall. Here, the interval between each conductive path means that the width between adjacent conductive paths is called w, and the cross section of the anisotropic conductive member is observed at a magnification of 200,000 times with an electric field emission scanning electron microscope, and the phase The width between adjacent channels was measured by an average of 10 points.

[Conductive Path] The plurality of conductive paths are made of a conductive material. <Conductive material> The conductive material constituting the conductive path is not particularly limited as long as it has a resistivity of 10 ³ Ω ･ cm or less. As specific examples thereof, gold (Au), silver (Ag), Copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), indium-doped tin oxide (ITO), etc. Among them, copper, gold, aluminum, and nickel are preferred, and copper and gold are more preferred from the viewpoint of conductivity.

<Protrusions> When the anisotropic conductive member and the electrode are electrically connected or physically joined by a method such as crimping, the reason for the sufficient conduction of the surface direction insulation of the protrusions when the protrusions are collapsed is that of the conductive path. The aspect ratio of the protruding portion (height of the protruding portion / diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and further preferably 1 to 10.

Moreover, from the viewpoint of following the surface shape of the semiconductor member to be connected, the height of the protruding portion of the via is as described above, preferably 20 nm or more, and more preferably 100 nm to 500 nm. The height of the protruding portion of the conductive path refers to the observation of the cross section of the anisotropic conductive member at a magnification of 20,000 times using an electric field emission scanning electron microscope, and the average height of the protruding portion of the conductive path was measured at 10 points. The diameter of the protruding portion of the conductive path means that the cross section of the anisotropic conductive member was observed with an electric field emission scanning electron microscope, and the average diameter of the protruding portion of the conductive path was measured at 10 points.

＜ Other shapes ＞ The channel is cylindrical. The diameter d of the channel is the same as the diameter of the protruding part. It is more than 5 nm and less than 10 μm, more preferably 20 nm to 1000 nm, and more preferably less than 100 nm.

In addition, the conductive paths exist in a state of being electrically insulated from each other by an insulating substrate, but the density is preferably 20,000 pieces / mm ² or more, more preferably 2 million pieces / mm ² or more, and 10 million pieces. / mm ² or more is further preferred, 50,000,000 / mm ² or more is particularly preferably, 100 million / mm ² or more is preferred.

In addition, the distance p between the centers of adjacent conductive paths is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and 50 nm to 140 nm is more preferred.

[Resin layer] The resin layer may be provided on the front surface and the back surface of the insulating base material, for example, and the above-mentioned conductive path may be buried. The resin layer can be the same as the above-mentioned adhesive layer. Therefore, the resin layer may have a member having a function of joining the same as the adhesive layer. <Shape> From the reason of protecting the conduction path, the thickness of the resin layer is larger than the height of the protruding portion of the conduction path, and 1 μm to 5 μm is preferable.

The present invention is basically constituted as described above. The manufacturing method and the semiconductor member of the semiconductor element of the present invention have been described in detail above, but the present invention is not limited to the above-mentioned embodiment, and various improvements or changes can be made without departing from the scope of the present invention. . [Example]

Hereinafter, the present invention will be described in more detail with reference to examples. The materials, reagents, usage amounts, substance amounts, ratios, processing contents, processing steps, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present disclosure. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In this embodiment, a semiconductor member is bonded using an anisotropic conductive member shown below to fabricate semiconductor devices of Examples 1 to 6 and Comparative Examples 1 and 2 described below, and evaluate the conductivity And joint strength.

TEG wafers are used for semiconductor components. <TEG chip> Prepare a TEG chip (Test Element Group chip) with Cu pads and an interposer. These include a daisy-chain pattern for measuring the on-resistance and a comb-tooth pattern for measuring the insulation resistance. The insulating layers are SiN. A TEG wafer was prepared with a wafer size of 8 mm square and a ratio of electrode area (copper pillar) to wafer area of 25%. The diameter of the electrode was set to 5 μm, the height was set to 7 μm, and the thickness of the insulating layer existing between the electrodes was set to 2 μm. The TEG wafer corresponds to a semiconductor component. The interposer contains extraction wiring around it, so a square with a wafer size of 10 mm is prepared. Next, using a wafer bonder (DB250, manufactured by Shibuya Kogyo Co., Ltd.) and bonding at a temperature of 270 ° C for 10 minutes, the TEG wafer, the anisotropic conductive member, and the interposer were bonded as described above. Sequential layering. At this time, the alignment marks formed on the corners of the wafer are used for alignment and bonding, so as to prevent the position of the TEG wafer and the Cu pad of the interposer from deviating. In this embodiment, as described below, an electrode of a TEG wafer is used as an electrode of a semiconductor member, and a bonding layer shown below is provided on the surface of the TEG wafer.

The anisotropic conductive member will be described below. [Anisotropic conductive member] <Preparation of aluminum substrate> Using Si: 0.06 mass%, Fe: 0.30 mass%, Cu: 0.005 mass%, Mn: 0.001 mass%, Mg: 0.001 mass%, and Zn: 0.001 mass %, Ti: 0.03% by mass, and the remaining part is an aluminum alloy made of Al and unavoidable impurities to prepare molten metal. After the molten metal is processed and filtered, the thickness is made by DC (Direct Chill) casting method. 500 mm ingot with a width of 1200 mm. Next, the surface was cut with a surface cutting machine with an average thickness of 10 mm, and then held at 550 ° C for 5 hours, and when the temperature was lowered to 400 ° C, a hot-rolled mill was used to make a 2.7 mm-thick rolled sheet. Then, a heat treatment was performed at 500 ° C. using a continuous annealing machine, and a thickness of 1.0 mm was completed by cold rolling to obtain an aluminum substrate of JIS 1050 material. After forming the aluminum substrate into a wafer shape with a diameter of 200 mm (8 feet), each of the processes described below was performed.

<Electrolytic Polishing Process> An electrolytic polishing process was performed on the aluminum substrate with the following composition, and the electrolytic polishing process was performed under the conditions of a voltage of 25 V, a liquid temperature of 65 ° C, and a liquid flow rate of 3.0 m / min. The cathode was a carbon electrode, and GP0110-30R (manufactured by Takasago, Ltd.) was used as a power source. The flow rate of the electrolytic solution was detected using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation). (Composition of electrolytic polishing solution) ･ 85% by mass phosphoric acid (reagent manufactured by Wako Pure Chemical Industries, Ltd.) 660 mL ･ pure water ･ ･ ･ 160 mL ･ sulfuric acid ･ ･ ･ 150 mL ･ ethylene glycol ester ･ ･ ･ 30 mL

<Anodizing Process> Next, an aluminum substrate subjected to electrolytic polishing treatment is subjected to anodizing treatment by a self-regularization method in accordance with the procedure described in Japanese Patent Application Laid-Open No. 2007-204802. A 0.50 mol / L oxalic acid electrolyte was applied to the aluminum substrate after the electrolytic polishing treatment, and a pre-anodization treatment was performed for 5 hours at a voltage of 40 V, a liquid temperature of 16 ° C, and a liquid flow rate of 3.0 m / min. After that, the aluminum substrate after the pre-anodization treatment was subjected to a stripping treatment for 12 hours in a mixed aqueous solution (liquid temperature: 50 ° C.) of 0.2 mol / L chromic anhydride and 0.6 mol / L phosphoric acid. Then, a 0.50 mol / L oxalic acid electrolytic solution was subjected to a re-anodizing treatment under conditions of a voltage of 40 V, a liquid temperature of 16 ° C, and a liquid flow rate of 3.0 m / min for 3 hours and 45 minutes to obtain a film thickness of 30 μm. Anodized film. In addition, in the pre-anodizing treatment and the re-anodizing treatment, the cathode was a stainless steel electrode, and GP0110-30R (manufactured by Takasago, Ltd.) was used as a power source. Moreover, NeoCool BD36 (made by Yamato Scientific Co., Ltd.) was used as a cooling device, and Pairstirrer PS-100 (made by TOKYO RIKAKIKAI CO., LTD.) Was used as a stirring and heating device. The flow rate of the electrolytic solution was detected using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation).

<Barrier Layer Removal Process> Next, under the same treatment liquid and processing conditions as the above-mentioned anodizing treatment, the voltage was continuously decreased from 40 V to 0 V at a voltage drop rate of 0.2 V / sec, and an electrolytic treatment (electrolytic removal treatment) was performed. ). Thereafter, an etching treatment (etching removal treatment) was performed by immersing in 5 mass% phosphoric acid at 30 ° C for 30 minutes to remove the barrier layer on the bottom of the micropores of the anodized film, and aluminum was exposed through the micropores.

The average pore diameter of the micropores of the anodic oxide film existing in the barrier layer removal process is 60 nm. The average pore diameter was calculated by taking a photograph of the surface (magnification of 50,000 times) with a field emission-scanning electron microscope (FE-SEM) and measuring the average value of 50 points. The average thickness of the anodized film after the barrier layer removal process was 80 μm. In addition, the average thickness is obtained by cutting the anodized film with FIB (Focused Ion Beam) with respect to the thickness direction, and taking a photograph of the surface of the cross-section with a FE-SEM (magnification of 50000 times) and measuring 10 points. The average value is calculated. The density of micropores existing in the anodized film was about 100 million pieces / mm ² . The density of micropores is measured and calculated by the methods described in paragraphs <0168> and <0169> of Japanese Patent Application Laid-Open No. 2008-270158. The degree of regularity of the micropores existing in the anodized film was 92%. In addition, the degree of regularity was measured and calculated by taking a photograph of the surface (magnification 20,000 times) by FE-SEM, and using the method described in paragraphs <0024> to <0027> of JP-A-2008-270158.

<Metal Filling Process> Next, an electrolytic plating process was performed using an aluminum substrate as a cathode and platinum as a positive electrode. Specifically, a copper-plated metal having the composition shown below was used and constant-current electrolysis was performed to produce a metal-filled microstructure with copper filled inside the micropores. Here, for constant current electrolysis, a plating device manufactured by Yamamoto-MS Co., Ltd was used, and a power source (HZ-3000) manufactured by HOKUTO DENKO CORPORATION was used. Cyclic voltammetry was performed in the plating solution to confirm the precipitation potential. Perform the treatment under the conditions indicated. (Composition and conditions of copper plating solution) 铜 Copper sulfate 100 g / L ･ Sulfuric acid 50 g / L ･ Hydrochloric acid 15 g / L ･ Temperature 25 ° C ･ Current density 10 A / dm ²

The surface of the anodic oxide film after the metal is filled in the micropores is observed by FE-SEM, and whether or not the sealing caused by the metal in 1000 micropores is observed is used to calculate the sealing rate (the number of sealing micropores / 1000) , Which is 96%. In addition, FIB was used to cut the anodic oxide film after filling the micropores with metal in the thickness direction, and the surface of the cross section was taken by FE-SEM (50,000 times magnification) to confirm the inside of the micropores. The sealed micropores are completely filled with metal inside.

<Substrate Removal Process> Next, an aluminum substrate was dissolved and removed by immersion in a 20% by mass mercury chloride aqueous mercury solution (liters of mercury) at 20 ° C for 3 hours, thereby preparing a metal-filled fine structure.

<Trimming process> The metal-filled microstructure after the substrate removal process is immersed in an aqueous sodium hydroxide solution (concentration: 5% by mass, liquid temperature: 20 ° C), and the immersion time is adjusted and selected so that the height of the protruding portion becomes 500 nm. The surface of the anodic oxide film that dissolves aluminum is then washed with water and dried to produce an anisotropic conductive member that protrudes from a copper cylinder that is a conductive path.

(Example 1) In Example 1, a bonding layer was formed on the entire surface of the electrode of the TEG wafer, and then the surface of the electrode and the surface of the bonding layer were made the same surface by cutting to expose the electrode. The height of the electrode after cutting was 4 μm. The solution dissolved in methyl ethyl ketone (MEK) was spin-coated on the surface of the TEG wafer by the following mixing method, and baked at a temperature of 130 ° C. for 2 minutes to form a 5 μm thick adhesive layer. The thickness of the adhesive layer is adjusted by the amount of a solvent (MEK: methyl ethyl ketone). <Composition of coating solution> ･ Elastomer: Acrylic polymer based on butyl acrylate-acrylonitrile as the main component (product name: SG-28GM, manufactured by NAGASE & CO., LTD.) ･ ･ ･ 5 parts by mass ･ Epoxy resin 1: jER (registered trademark) 828 (manufactured by Mitsubishi Chemical Corporation) ･ ･ ･ 33 parts by mass ･ Epoxy resin 2: jER (registered trademark) 1004 (manufactured by Mitsubishi Chemical Corporation) ･ ･ ･ 11 parts by mass of phenol Resin: MIREX XLC-4L (manufactured by Mitsui Chemicals, Inc.) ･ ･ ･ 44 parts by mass ･ organic acid: o-anisic acid (orthoanisic acid, manufactured by Tokyo Chemical Industry Co., Ltd.) ･ ･ ･ 0.5 part by mass ･ Hardener: Imidazole catalyst (2PHZ-PW, manufactured by Shikoku Kasei KK) ･ ･ ･ 0.5 part by mass. As a cutting device, Surface Planer manufactured by DISCO Corporation was used. The rotation speed was set to 1500 rpm (revolution per minute) and the feed speed was set to 0.5 mm / sec to make the surface of the electrode and the surface of the adhesive layer the same surface.

Example 2 Example 2 is the same as Example 1 except that the height of the adhesive layer is 500 nm lower than the electrode height by wet etching after cutting. . As the etching solution, MEK (methyl ethyl ketone) was used, and wet etching was performed by a spray method using a single-plate developing device. The etching liquid discharge pressure was set to 0.5 mL / sec / mm ² , and the etching time was performed for 20 sec. (Example 3) Example 3 is compared with Example 1 except that the electrode is etched 200 nm by wet etching after cutting and the height of the electrode is set lower than the height of the adhesive layer. Example 1 is the same. The electrode etching solution and etching conditions are as follows. ･ Etching solution: 0.1% hydrogen peroxide, 0.1% iminodiacetic acid and 99.8% ultrapure water ･ Etching conditions (immersion time): 20 sec

(Example 4) Compared with Example 3, except that the wet etching time of the electrode was set to 100 sec, the difference between the height of the adhesive layer and the height of the electrode was set to 1000 nm, and the ratio was set to Except that the height of the protruding portion of the conductive path is 500 nm, it is the same as that of Example 3. (Example 5) Example 5 was the same as Example 1 except that an insulating film was used between the electrodes of the TEG wafer and the electrode height after cutting was 3 μm. (Example 6) Example 6 was the same as Example 1 except that the following adhesive layer was used. <Coating liquid composition> 60 parts by mass of phenoxy resin (YP-50, NIPPON STEEL & SUMIKIN CHEMICAL CO., LTD.) 10 parts by mass of diepoxydicyclohexane compound (CELLOXIDE8000, Daicel Corporation), low 20 parts by mass of a polar oxycyclobutane compound (OXBP, Ube Industries, Ltd.), a quaternary ammonium salt-based thermal acid generator (product name CXC-1612, Kusumoto Chemicals, Ltd.), 2 parts by mass of a solvent for the thickness of the adhesive layer MEK: methyl ethyl ketone).

Comparative Example 1 Comparative Example 1 was the same as Example 1 except that an adhesive layer was formed on the entire electrode surface of the TEG wafer and the electrodes were not exposed. The dilution ratio was adjusted so that the height of the adhesion layer on the electrode became 5 μm, and coating was performed. (Comparative Example 2) Comparative Example 2 was the same as Example 1 except that an adhesive layer was not provided on the TEG wafer, and an anisotropic conductive member was provided. The dilution ratio was adjusted so that the height of the adhesive layer on the anisotropic conductive member became 5 μm, and the coating was performed.

The continuity and bonding strength will be described below. The continuity is evaluated by the on-resistance. The on-resistance will be described. <Evaluation of continuity> The probe was brought into contact with the lead pad of the daisy chain pattern portion of the interposer, and the continuity evaluation was performed in the atmosphere. As a measuring device, a SourceMeter company of KEITHLEY was used to measure the impedance value. Based on the results of the impedance values, evaluation was performed using the evaluation criteria shown below. The evaluation results are shown in the continuity column in Table 1 below. "A": The impedance value is less than 10 times the design impedance. "B": The impedance value is more than 10 times and less than 100 times the design impedance. "C": The impedance value is more than 100 times and less than 1000 times the design impedance. " D ”: The impedance value is more than 1000 times the design impedance

The joint strength was evaluated by measuring the shear strength using a universal welding tester Dage-4000 (Nordson Advanced Technology (Japan) K.K.). Bonding strength The bonding strength value per unit area of the semiconductor element was obtained from the obtained breaking load. The joint strength was evaluated according to the evaluation criteria shown below. "A": 20 MPa ≤ joint strength "B": 10 MPa ≤ joint strength <20 MPa "C": joint strength <10 MPa

[Table 1]

As shown in Table 1, Examples 1 to 6 are superior to Comparative Examples 1 and 2 in which the electrodes are not exposed, and have excellent continuity and bonding strength. In addition, as in Example 4, if the protrusion of the conductive path is greater than the difference between the height of the adhesive layer and the height of the electrode, both the conductivity and the bonding strength are very excellent.

10‧‧‧Semiconductor

12, 14, 16‧‧‧‧ semiconductor components

15‧‧‧ Anisotropic conductive member

20‧‧‧Semiconductor element

22, 32‧‧‧ electrodes

20a, 22a, 24a, 26a, 32a, 34a

24‧‧‧ Insulation

26‧‧‧ Adhesive layer

30‧‧‧ Interposer

34‧‧‧ Insulation

40‧‧‧ insulating substrate

40a‧‧‧ surface

40b‧‧‧Back

41‧‧‧through hole

42‧‧‧ channel

42a, 42b‧‧‧ protruding

43‧‧‧resin layer

44‧‧‧ peeling layer

45‧‧‧ support layer

46‧‧‧ peeling agent

47‧‧‧ support

D‧‧‧thickness direction

Ha‧‧‧ height of adhesive layer

Hd‧‧‧ height of protruding part

Hs‧‧‧ height of electrode

h‧‧‧ thickness

p‧‧‧center distance

x‧‧‧ direction

Claims (8)

A method for manufacturing a semiconductor device, which has a bonding process for bonding the following members: a bonding member having an electrode and a bonding layer and the electrode is exposed from the bonding layer; and an anisotropic conductive member having an insulating base And a plurality of conductive paths provided in a state of being electrically insulated from each other in a thickness direction of the insulating base material. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, which includes an exposure process for exposing the electrode of the bonding member before the bonding process. The method for manufacturing a semiconductor device according to item 2 of the scope of patent application, wherein the exposure process is a process of exposing the electrode using any one of cutting, grinding, grinding, dry etching, and wet etching. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the bonding member is a member in which the electrode is more prominently disposed than the bonding layer. The method for manufacturing a semiconductor device according to item 4 of the scope of patent application, wherein the conductive path protrudes from the insulating base material in the thickness direction, a height of a protruding portion of the conductive portion is set to Hd, and the bonding When the height of the layer is set to Ha and the height of the electrode is set to Hs, Hd ≧ Ha-Hs. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the bonding process is a process of bonding the bonding member and the anisotropic conductive member through the bonding layer. The method for manufacturing a semiconductor device according to item 2 or item 3 of the scope of patent application, wherein the bonding layer contains a thermosetting resin, and the exposing process is a process performed without the thermosetting resin being subjected to thermosetting. . A bonding member used in the method for manufacturing a semiconductor element according to any one of claims 1 to 7 of the scope of patent application.