TW201915503A - A lifetime testing method of minority carriers in silicon wafer, and a testing apparatus - Google Patents

Abstract

The present invention provides a lifetime testing apparatus of minority carriers in silicon wafer. The apparatus comprises of an etching tank, the top of the etching tank has an opening and the bottom of the etching tank has shelves to vertically hold the wafers in the etching tank. By using the lifetime testing apparatus of minority carriers in silicon wafer, it can avoid the leakage of the chemical solution, and therefore, to reduce the potential damage to the machines and operators.

Description

Test method and test device for lifetime of silicon minority carriers

The present invention relates to the field of semiconductor technology, and in particular, to a device for testing the minority carrier lifetime of a silicon wafer.

In semiconductor devices, although MOS devices are mainly controlled by majority carriers (multiple carriers), the lifetime of minority carriers also plays an important role. For example, a higher minority carrier lifetime helps reduce the refresh time of DRAM (refresh time). ). Therefore, the minority carrier lifetime is one of the important indicators used to determine the perfection of silicon crystals. In addition, micro-defects in the crystal itself or after processing will have a certain effect on the minority carrier lifetime, and the current minority carrier lifetime testing equipment has a mapping function, so the minority carrier lifetime is important for long crystals. The improvement of the process plays an important role.

At present, there are many methods for testing the minority carrier lifetime of silicon wafers, such as the photoconductive attenuation method and surface photovoltage method. Among them, the microwave photoconductive attenuation method (μ-PCD) is simple to operate and the test accuracy meets the detection requirements. The mainstream test method for the minority carrier lifetime. In the μ-PCD method, the lifetime of the minority carriers finally tested is actually the effective lifetime of the entire sample. It is the net result of all the composite superposition that occurs on the surface of the silicon wafer and in the body. In order to obtain the true body lifetime of the silicon wafer, it is necessary to use The passivation method reduces the effect of surface recombination. However, the safety of the existing passivation devices is not high.

Therefore, it is necessary to propose a device for testing the minority carrier lifetime of silicon to solve the above problems.

A series of simplified forms of concepts are introduced in the summary section, which will be explained in further detail in the detailed description section. The summary of the present invention does not mean trying to define the key features and necessary technical features of the claimed technical solution, let alone trying to determine the protection scope of the claimed technical solution.

In view of the shortcomings of the prior art, the present invention provides a device for testing the minority carrier lifetime of a silicon wafer. The device includes an etching groove capable of accommodating a silicon wafer. The silicon wafer is vertically fixed to a slot in the etching slot.

Exemplarily, the bottom of the etching groove is arc-shaped.

Exemplarily, the device further includes a detector located outside the etching groove and facing the surface of the silicon wafer.

Exemplarily, the width of the etching groove is 2mm-3mm.

Exemplarily, the slot pitch of the slot is 0.8 mm-1 mm.

Exemplarily, the apparatus further includes a chemical liquid inlet provided on a sidewall of the etching tank.

Exemplarily, the apparatus further includes a water inlet provided on a sidewall of the etching tank.

Exemplarily, the apparatus further includes a waste liquid discharge port provided at the bottom of the etching tank.

Exemplarily, the apparatus further includes an etch tank top cover for sealing the top opening of the etch tank.

The device for testing the minority carrier life of the silicon wafer provided by the present invention is not prone to leakage of chemical liquid and avoids causing harm to personnel and machines.

In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described.

It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals denote the same elements throughout.

It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. Layers, adjacent, connected, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or Floor. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below can be represented as a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relation terms such as "below", "below", "below", "below", "above", "above", etc., in It may be used here for convenience of description to describe the relationship between one element or feature and other elements or features shown in the figure. It should be understood that in addition to the orientation shown in the figures, the spatial relationship terminology is intended to include different orientations of the elements in use and operation. For example, if an element in the drawing is turned over, then an element or feature described as "below" or "beneath" other elements or features would then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "below" can include both an orientation of above and below. The elements may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended as a limitation of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be limited to the specific shape of the region shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle generally has round or curved features and / or implanted concentration gradients at its edges, rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried area formed by implantation may result in some implantation in the area between the buried area and the surface through which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of an element and are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, a detailed structure will be proposed in the following description in order to explain the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

Minority carrier lifetime is one of the important indicators used to determine the perfection of silicon crystals. At present, there are many methods for testing the lifetime of minority carriers in silicon wafers, such as the photoconductive attenuation method and surface photovoltage method. Among them, the microwave photoconductive attenuation method (μ-PCD) is simple to operate and the test accuracy meets the detection requirements. Mainstream test device for minority carrier lifetime. The test life obtained by the μ-PCD method is the test lifetime τ _meas of the sample. The true bulk minority carrier lifetime τ _{bulk of the} silicon chip itself can be corrected by the following formula: 1 / τ _meas = 1 / τ _bulk + 1 / (τ _diff + τ _surf) where τ _diff is the time required for the minority carrier diffusion Xipian from the body to the surface, it is related to the diffusion coefficient and the thickness of the carrier of Xipian; τ _surf is the surface since the surface recombination lifetime of the sample produced, it silicon The thickness of the sheet is related to the recombination speed Sr. τ _surf has a great influence on the test life, and it deviates from the body life τ _bulk . In order to reduce the effect of surface recombination, it is necessary to perform surface passivation treatment on the silicon wafer to reduce the recombination speed Sr. There are three methods of surface passivation treatment: 1. oxidation treatment; 2. chemical passivation treatment; 3. RTA (rapid thermal annealing) + arc treatment. Among them, the repeatability of the oxidation treatment is good, but the treatment time is long, which is likely to cause silicon metal contamination; the repeatability of the RTA + arc treatment is good, but the cost is high; and the chemical passivation treatment is relatively fast and simple, but the operation is more dangerous. Traditional chemical passivation usually puts silicon wafers in plastic bags, seals them with chemical solution, and then tests. This method is prone to leakage of chemical fluids, causing harm to personnel and equipment.

In view of the above problems, the present invention provides a device for testing the minority carrier lifetime of a silicon wafer. The device includes an etching groove capable of accommodating a silicon wafer. The top of the etching groove has an opening. The silicon wafer is vertically fixed in a slot in the etching slot.

The bottom of the etching groove is arc-shaped.

The device further includes a detector located outside the etch groove and facing the surface of the silicon wafer.

The width of the etching groove is 2mm-3mm.

The slot pitch of the slot is 0.8mm-1mm.

The device further includes a chemical liquid inlet provided on a side wall of the etching tank.

The apparatus further includes a water inlet provided on a side wall of the etching tank.

The apparatus further includes a waste liquid discharge port provided at the bottom of the etching tank.

The apparatus further includes an etching tank top cover for sealing an opening on the top of the etching tank.

The device for testing the minority carrier life of the silicon wafer provided by the present invention is not prone to leakage of chemical liquid and avoids causing harm to personnel and machines.

In order to thoroughly understand the present invention, detailed structures and / or steps will be proposed in the following description in order to explain the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments. [Exemplary embodiment]

Hereinafter, a test apparatus for testing the minority carrier lifetime of a silicon wafer according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1B. FIG. 1A is a cross-sectional view of the test device along a length direction, and FIG. 1B is a cross-sectional view of the test device along a width direction.

As shown in FIG. 1A and FIG. 1B, the device for testing the minority carrier lifetime of the silicon wafer includes an etching groove 101 capable of accommodating the silicon wafer 103, the top of the etching groove 101 has an opening, and the bottom of the etching groove 101 A slot 108 is provided for vertically fixing the silicon wafer 103 in the etching slot 101.

When the test is performed, the silicon wafer 103 may be first put into the etching tank 101 through the opening on the top of the etching tank 101. The length, width, and height of the etching groove 101 must be larger than the silicon wafer 103 to ensure that the silicon wafer 103 can be placed vertically therein. After the silicon wafer 103 is placed in the etching tank 101, the top opening of the etching tank 101 can be sealed by using the etching tank top cover 102. When the silicon wafer 103 is circular, the length and height of the internal space of the etching groove 101 are larger than the diameter of the silicon wafer 103, and its width is greater than the thickness of the silicon wafer 103. A slot 108 is provided at the bottom of the etching groove 101, and the groove pitch of the slot 108 is slightly larger than the thickness of the silicon wafer 103, thereby ensuring that the silicon wafer 103 remains vertical and does not shake in the etching groove 101. As an example, the slot pitch of the slot 108 is 0.8-1 mm.

In one embodiment, the bottom of the etching groove 101 is arc-shaped. Since the cross-sectional shape of the silicon wafer 103 is generally circular, setting the bottom of the etching groove 101 to an arc shape can make the bottom of the etching groove 101 more closely match the bottom of the silicon wafer 103, so that the slot 108 can better The silicon wafer 103 is vertically fixed in the etching groove 101.

A chemical liquid inlet 105 and a water inlet 106 are disposed on a side wall of the etching tank. After the silicon wafer 103 is placed in the etching tank 101, a high-concentration chemical solution 104 for surface passivation can be first passed through the chemical solution inlet 105 into the etching tank 101 to prevent the operator from contacting the chemical solution and improve the operation. Security. The etching tank 101 may be made of an anti-corrosive material to prevent the chemical solution from corroding it.

A detector 109 facing the surface of the silicon wafer 103 is also provided on the outside of the etching tank 101, and the detector 109 is used to perform a minority carrier lifetime test on the silicon wafer 103 immersed in the chemical solution 104. In this embodiment, the detector 109 is a device for testing the minority carrier lifetime of the silicon wafer by using a microwave photoelectric attenuation (μ-PCD) method. The detector 109 is mainly used for laser injection of the silicon wafer 103 to generate electron-hole pairs and microwave detection signals. Exemplarily, the detector 109 uses a laser with a wavelength of 904 nm to inject the silicon wafer 103 to generate an electron-hole pair, so as to increase the conductivity of the silicon wafer 103, and its implantation depth is about 30 μm. When the external light injection is removed, the conductivity decays exponentially with time. This trend indirectly reflects the decay trend of minority carriers. The lifetime of minority carriers can be obtained by detecting the trend of conductivity with time by microwave. The test life obtained by the μ-PCD method is the test lifetime τ _meas of the sample. The true bulk minority carrier lifetime τ _{bulk of the} silicon wafer 103 itself can be modified by the following formula: 1 / τ _meas = 1 / τ _bulk + 1 / (τ _diff + τ _surf ) where τ _diff is the time required for the minority carriers to diffuse from the silicon wafer 103 to the surface, and it is related to the thickness of the silicon wafer 103 and the diffusion coefficient of the carriers; τ _surf is the surface life due to the recombination of the sample surface, It is related to the thickness of the silicon wafer 103 and the recombination speed Sr. The chemical passivation of the chemical solution 104 can reduce the recombination speed Sr, thereby reducing the effect of surface recombination on the test results.

After the test is performed, the chemical solution 104 can be discharged through a waste liquid discharge port 107 provided at the bottom of the etching tank. After that, deionized water can be passed into the etching tank 101 through the water inlet 106 to clean the etching tank 101 and the silicon wafer 103. The waste liquid generated by cleaning can also be discharged through a waste liquid discharge port 107 provided at the bottom of the etching tank. The arrangement of the medicinal solution inlet 105, the water inlet 106, and the waste liquid discharge port 107 can prevent the operator from contacting the medicinal solution 104, which improves the safety and makes the operation easier.

The device for testing the minority carrier life of the silicon wafer provided by the present invention is not prone to leakage of chemical liquid and avoids causing harm to personnel and machines.

The present invention has been described through the above embodiments, but it should be understood that the above embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments. According to the teachings of the present invention, more variations and modifications can be made, and these variations and modifications all fall within the scope of protection of the present invention. Within range. The scope of protection of the present invention is defined by the appended claims and their equivalents.

101‧‧‧etching groove

102‧‧‧ Etching top cover

103‧‧‧ Silicon

104‧‧‧High concentration liquid medicine

105‧‧‧ Import of liquid medicine

106‧‧‧ Water Import

107‧‧‧ waste liquid discharge port

108‧‧‧ Slot

109‧‧‧ Detector

The following drawings of the present invention are used herein as a part of the present invention to understand the present invention. The drawings illustrate embodiments of the invention and their descriptions to explain the principles of the invention. In the drawings:

1A-1B are schematic diagrams of a device for testing the minority carrier lifetime of a silicon chip according to an embodiment of the present invention.

Claims (9)

A device for testing the minority carrier lifetime of a silicon wafer, wherein the device includes an etching groove capable of accommodating a silicon wafer, the top of the etching groove has an opening, and the bottom of the etching groove is provided for vertically fixing the silicon wafer A slot in the etching slot. The apparatus according to claim 1, wherein a bottom of the etching groove is arc-shaped. The apparatus according to claim 1, further comprising a detector located outside the etching groove and facing the surface of the silicon wafer. The apparatus according to claim 1, wherein the width of the etching groove is 2mm-3mm. The device according to claim 1, wherein a slot pitch of the slot is 0.8 mm-1 mm. The apparatus according to claim 1, further comprising a chemical liquid inlet provided on a side wall of the etching tank. The apparatus according to claim 1, further comprising a water inlet provided on a side wall of the etching tank. The apparatus according to claim 1, further comprising a waste liquid discharge port provided at the bottom of the etching tank. The apparatus according to claim 1, further comprising an etching tank top cover for sealing an opening on the top of the etching tank.