TW201909306A - Integrated circuit test block with integrated signal and power integrity module - Google Patents

Integrated circuit test block with integrated signal and power integrity module Download PDF

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Publication number
TW201909306A
TW201909306A TW106124791A TW106124791A TW201909306A TW 201909306 A TW201909306 A TW 201909306A TW 106124791 A TW106124791 A TW 106124791A TW 106124791 A TW106124791 A TW 106124791A TW 201909306 A TW201909306 A TW 201909306A
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conductive
signal
integrated circuit
adhesive layer
conductor
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TW106124791A
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Chinese (zh)
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TWI623996B (en
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李文聰
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中華精測科技股份有限公司
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Priority to TW106124791A priority Critical patent/TWI623996B/en
Priority to CN201711034304.XA priority patent/CN109298208A/en
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Publication of TW201909306A publication Critical patent/TW201909306A/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0416Connectors, terminals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

An integrated circuit test socket with signal and power integration module includes a first conductive adhesive layer, a second conductive adhesive layer, a conductor module, and a signal and power integration module. The second conductive adhesive layer is disposed opposite to the first conductive adhesive layer. The conductor module includes at least one pair of conductors. The signal and power integration module is disposed between the first conductive adhesive layer and the second conductive adhesive layer. At least one pair of conductors penetrates through the first conductive adhesive layer and the second conductive adhesive layer, respectively, in electrical contact with the signal and power integration module.

Description

整合信號及電源完整性模組之積體電路測試座    Integrated circuit test stand for integrated signal and power integrity modules   

本發明是有關於一種測試裝置,且特別是有關於一種整合信號及電源完整性模組之積體電路測試座。 The invention relates to a test device, and in particular to an integrated circuit test stand for integrating signal and power integrity modules.

隨著電子科技、網路等相關技術的進步,同時全球電子市場的消費水準逐步提升,致使消費性電子產品的需求量激增,進而帶動半導體產業的蓬勃發展。 With the advancement of related technologies such as electronic technology and the Internet, and the gradual increase in the consumption level of the global electronics market, the demand for consumer electronics products has soared, which has led to the vigorous development of the semiconductor industry.

半導體製造(或稱晶圓加工)包括以下幾個步驟:積體電路(integrated circuit,IC)設計、晶圓製程(wafer fabrication)、晶圓測試(wafer probe)、晶圓封裝(packaging)以及封裝後測試(final test,意指IC測試)等,而其中所謂的晶圓測試及封裝後測試,指的是對未單切之晶圓上的一個或多個晶粒或從晶圓切下來的一個或多個晶粒(封裝或未封裝)進行電性功能的測試,藉以找出不合格晶粒並將其淘汰。一般來說,半導體晶粒在進行測試時,測試機須透過探針卡接觸待測物(device under test,DUT),亦即將探針卡作為測試機與待測物間之測試信號與電源信號的傳輸介面,並配合探針卡與測試機的控制與分析程序,達到量測待測物之電性特徵的目的。 Semiconductor manufacturing (or wafer processing) includes the following steps: integrated circuit (IC) design, wafer fabrication, wafer probe, wafer packaging, and packaging Final test (meaning IC test), etc. Among them, the so-called wafer test and post-package test refer to one or more dies on or not cut from wafers. One or more dies (packaged or unpackaged) are tested for electrical functions to identify substandard dies and eliminate them. Generally, when testing semiconductor chips, the tester must contact the device under test (DUT) through the probe card, that is, the probe card is used as the test signal and power signal between the test machine and the test object. The transmission interface, together with the control and analysis program of the probe card and the testing machine, achieve the purpose of measuring the electrical characteristics of the object under test.

更進一步來說,電子元件越趨高速化與高頻發展,電子元件就更加需要有高標準的電性規格(如:元件運算條件、操作頻率、信號傳輸 特性等),所以探針卡在設計上須至少考量到測試條件、測試頻寬與信號傳輸的完整性。然而,為滿足封裝後測試(final test)之需求,對於高速(頻)信號或電源信號的傳輸路徑上都需要電容器,但功能有所不同。 Furthermore, the more high-speed and high-frequency development of electronic components, the more high-level electrical specifications are required for electronic components (such as component operating conditions, operating frequency, signal transmission characteristics, etc.), so the probe card is in the design At least the test conditions, test bandwidth and signal transmission integrity must be considered. However, in order to meet the requirements of final test, capacitors are required for transmission paths of high-speed (frequency) signals or power signals, but the functions are different.

請參考圖1,為習知的積體電路測試探針卡的結構示意圖。習知的積體電路測試探針卡10在封裝後測試過程中,因為受限於產品結構及測試機構,通常係將電子元件11,例如為電容器或記憶體配置於積體電路測試介面板12(意指載體印刷電路板,loadboard print circuit board)上,由於測試路徑(例如圖1所繪示的接地訊號測試路徑T1及電源訊號測試路徑T2)過長,高頻測試電感效應更趨顯著,而影響整個測試結果。儲存在記憶體內的測試訊息也因為測試路徑過長,容易造成訊號失真。此外,測試路徑過長會產生較大的電阻,且在電流流經的途徑中,能量損失較大,在待測物13,例如多顆積體電路同時測試時,往往無法及時供應電流,而產生測試失敗。 Please refer to FIG. 1, which is a schematic structural diagram of a conventional integrated circuit test probe card. In the conventional integrated circuit test probe card 10, during the post-packaging test, electronic components 11 such as capacitors or memories are usually arranged on the integrated circuit test interface panel 12 due to limited product structures and test institutions. (Meaning carrier load circuit board, loadboard print circuit board), because the test paths (such as the ground signal test path T1 and the power signal test path T2 shown in Figure 1) are too long, the high frequency test inductance effect becomes more significant, And affect the entire test result. The test information stored in the memory is also prone to signal distortion because the test path is too long. In addition, if the test path is too long, a large resistance will be generated, and in the path through which the current flows, the energy loss is large. When the DUT 13, such as multiple integrated circuits, is tested at the same time, it is often impossible to supply current in time, and Generate test failure.

故,有需要提供一種整合信號及電源完整性模組之積體電路測試座,以解決習知技術存在的問題。 Therefore, there is a need to provide an integrated circuit test stand that integrates signal and power integrity modules to solve the problems existing in the conventional technology.

本發明之主要目的在於提供一種整合信號及電源完整性模組之積體電路測試座,其能及時供應電流,提供穩定的測試結果。 The main object of the present invention is to provide an integrated circuit test socket for integrating signals and power integrity modules, which can supply current in time and provide stable test results.

為達上述之目的,本發明提供一種整合信號及電源完整性模組之積體電路測試座包括一第一導電膠層、一第二導電膠層、一導體模組以及一信號及電源完整性模組。第二導電膠層與第一導電膠層相對設置。導體模組包括至少一對導體。信號及電源完整性模組設置於第一導電膠層及第二導電膠層之間。至少一對導體分別貫穿第一導電膠層及第二導電膠層而與信號及電源完整性模組電性接觸。 In order to achieve the above object, the present invention provides an integrated circuit test stand for integrating signal and power integrity modules, which includes a first conductive adhesive layer, a second conductive adhesive layer, a conductor module, and a signal and power integrity Module. The second conductive adhesive layer is disposed opposite to the first conductive adhesive layer. The conductor module includes at least one pair of conductors. The signal and power integrity module is disposed between the first conductive adhesive layer and the second conductive adhesive layer. At least one pair of conductors penetrate the first conductive adhesive layer and the second conductive adhesive layer, respectively, and are in electrical contact with the signal and power integrity module.

在本發明之一實施例中,信號及電源完整性模組包括一電容模組,電容模組包括一電容板及分別設置在電容板之相對上表面及下表面的二第一導電接點。 In one embodiment of the present invention, the signal and power integrity module includes a capacitor module. The capacitor module includes a capacitor plate and two first conductive contacts respectively disposed on the upper surface and the lower surface of the capacitor plate.

在本發明之一實施例中,至少一對導體分別與二個第一導電接點接觸。 In one embodiment of the present invention, at least one pair of conductors are in contact with two first conductive contacts, respectively.

在本發明之一實施例中,信號及電源完整性模組包括一板體及一導電體模組,導電體模組包括至少一接地導電體單元及一訊號導電體單元。 In one embodiment of the present invention, the signal and power integrity module includes a board and a conductor module, and the conductor module includes at least one grounded conductor unit and a signal conductor unit.

在本發明之一實施例中,至少一接地導電體單元包括二接地導電體單元,訊號導電體單元設置二接地導電體單元之間。 In one embodiment of the present invention, at least one grounded conductor unit includes two grounded conductor units, and the signal conductor unit is disposed between the two grounded conductor units.

在本發明之一實施例中,訊號導電體單元與至少一接地導電體單元形成一同軸結構。 In one embodiment of the present invention, the signal conductor unit and the at least one grounded conductor unit form a coaxial structure.

在本發明之一實施例中,接地導電體單元包括一接地導電體及二接地導電接點,二接地導電接點分別設置於板體之相對上表面及下表面,接地導電體貫穿板體並與二接地導電接點電性接觸。 In one embodiment of the present invention, the grounding conductor unit includes a grounding conductor and two grounding conductive contacts. The two grounding conductive contacts are respectively disposed on opposite upper and lower surfaces of the board. The grounding conductor runs through the board and Make electrical contact with two grounded conductive contacts.

在本發明之一實施例中,訊號導電體單元包括一訊號導電體及二訊號導電接點,二訊號導電接點分別設置於板體之相對上表面及下表面,訊號導電體貫穿板體並與二訊號導電接點電性接觸。 In one embodiment of the present invention, the signal conductor unit includes a signal conductor and two signal conductive contacts. The two signal conductive contacts are respectively disposed on the upper surface and the lower surface of the board. The signal conductor runs through the board and Make electrical contact with the two signal conductive contacts.

在本發明之一實施例中,信號及電源完整性模組包括一板體及一導電體模組,導電體模組包括一電源導電體單元。 In one embodiment of the present invention, the signal and power integrity module includes a board and a conductor module, and the conductor module includes a power conductor unit.

在本發明之一實施例中,電源導電體單元包括一電源導電體及整合於板體內之一電子元件。 In one embodiment of the present invention, the power conductor unit includes a power conductor and an electronic component integrated in the board.

在本發明之一實施例中,其中該電子元件為一電容結構、一記憶體或一積體電路。 In one embodiment of the present invention, the electronic component is a capacitor structure, a memory or an integrated circuit.

在本發明之一實施例中,電源導電體單元更包括一第一電源導電接點及一第二電源導電接點,分別設置於板體之相對上表面及下表面,電源導電體貫穿板體,並與第一電源導電接點及第二電源導電接點電性接觸,電子元件與第一電源導電接點電性接觸。 In an embodiment of the present invention, the power supply conductor unit further includes a first power supply conductive contact and a second power supply conductive contact, which are respectively disposed on opposite upper and lower surfaces of the board, and the power supply conductor penetrates the board. And is in electrical contact with the first power supply conductive contact and the second power supply conductive contact, and the electronic component is in electrical contact with the first power supply conductive contact.

在本發明之一實施例中,第一電源導電接點的寬度大於第二電源導電接點的寬度。 In one embodiment of the present invention, the width of the first power contact is greater than the width of the second power contact.

在本發明之一實施例中,導電模組更包括複數個導電接點設置於第一導電膠層的相對之上表面及下表面以及第二導電膠層的相對之上表面及下表面。 In one embodiment of the present invention, the conductive module further includes a plurality of conductive contacts disposed on opposite upper and lower surfaces of the first conductive adhesive layer and opposite upper and lower surfaces of the second conductive adhesive layer.

在本發明之一實施例中,每一該導電接點包括一導電層及設置於導電層上之至少一導電結構。 In one embodiment of the present invention, each of the conductive contacts includes a conductive layer and at least one conductive structure disposed on the conductive layer.

在本發明之一實施例中,導電結構係選自於由三角柱導電結構或梯形柱導電結構所構成之群組。 In one embodiment of the present invention, the conductive structure is selected from the group consisting of a triangular pillar conductive structure or a trapezoidal pillar conductive structure.

在本發明之一實施例中,積體電路測試座更包括一針座設置於第一導電膠層及第二導電膠層上。 In one embodiment of the present invention, the integrated circuit test base further includes a needle base disposed on the first conductive adhesive layer and the second conductive adhesive layer.

在本發明之一實施例中,積體電路測試座更包括一第一鎖固件及一第二鎖固件,其中第一鎖固件穿過第二導電膠層及針座,第二鎖固件穿過第二導電膠層、信號及電源完整性模組、第一導電膠層及針座。 In one embodiment of the present invention, the integrated circuit test socket further includes a first locking element and a second locking element, wherein the first locking element passes through the second conductive adhesive layer and the needle base, and the second locking element passes through The second conductive adhesive layer, the signal and power integrity module, the first conductive adhesive layer, and the pin base.

由於本發明實施例之信號及電源完整性模組整合於積體電路測試座內,且至少一對導體分別貫穿第一導電膠層及第二導電膠層而與信號及電源完整性模組電性接觸,因此使信號及電源完整性模組對待測物所提供的電流路徑縮短,使待測物測試時,可近距離取得電流,有助於功 能複雜的待測物,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果。 Because the signal and power integrity module of the embodiment of the present invention is integrated in the integrated circuit test stand, and at least one pair of conductors penetrates the first conductive adhesive layer and the second conductive adhesive layer, respectively, and communicates with the signal and power integrity module. Sexual contact, thus shortening the current path provided by the signal and power integrity module to the object under test, so that when the object is tested, the current can be obtained at a short distance, which is helpful for the object with complex functions, such as integrated circuits integrated circuit (IC), the amount of current required for the simultaneous switching of signals, so that the test product can have stable test results.

10‧‧‧積體電路測試探針卡 10‧‧‧Integrated Circuit Test Probe Card

11‧‧‧電容器 11‧‧‧Capacitor

12‧‧‧積體電路測試介面板 12‧‧‧Integrated Circuit Test Interface Panel

13‧‧‧待測物 13‧‧‧DUT

20‧‧‧積體電路測試座 20‧‧‧Integrated Circuit Test Block

21‧‧‧第一導電膠層 21‧‧‧The first conductive adhesive layer

22‧‧‧第二導電膠層 22‧‧‧Second conductive adhesive layer

23‧‧‧信號及電源完整性模組 23‧‧‧Signal and Power Integrity Module

23a‧‧‧信號及電源完整性模組 23a‧‧‧Signal and Power Integrity Module

23b‧‧‧信號及電源完整性模組 23b‧‧‧Signal and Power Integrity Module

24‧‧‧導體模組 24‧‧‧Conductor Module

25‧‧‧針座 25‧‧‧ Needle Block

26‧‧‧第一鎖固件 26‧‧‧First Lock Firmware

27‧‧‧第二鎖固件 27‧‧‧Second Lock Firmware

231‧‧‧電容模組 231‧‧‧Capacitor Module

232‧‧‧電容板 232‧‧‧Capacitor board

233‧‧‧第一導電接點 233‧‧‧First conductive contact

234‧‧‧板體 234‧‧‧board

234a‧‧‧板體 234a‧‧‧board

234b‧‧‧板體 234b‧‧‧board

235‧‧‧導電體模組 235‧‧‧Conductor Module

235a‧‧‧導電體模組 235a‧‧‧Conductor Module

235b‧‧‧導電體模組 235b‧‧‧Conductor Module

236a‧‧‧接地導電體單元 236a‧‧‧ Ground Conductor Unit

236b‧‧‧接地導電體 236b‧‧‧ ground conductor

236c‧‧‧接地導電接點 236c‧‧‧ ground conductive contact

237‧‧‧訊號導電體單元 237‧‧‧Signal Conductor Unit

237a‧‧‧訊號導電體 237a‧‧‧Signal conductor

237b‧‧‧訊號導電接點 237b‧‧‧Signal contact

238‧‧‧電源導電體單元 238‧‧‧Power conductor unit

238a‧‧‧電源導電體 238a‧‧‧Power Conductor

238b‧‧‧第一電源導接點 238b‧‧‧First power contact

238c‧‧‧第二電源導接點 238c‧‧‧Second power contact

238d‧‧‧電子元件 238d‧‧‧Electronic components

241‧‧‧導體 241‧‧‧Conductor

242‧‧‧導電接點 242‧‧‧Conductive contact

243‧‧‧導電層 243‧‧‧ conductive layer

244‧‧‧導電結構 244‧‧‧ conductive structure

C‧‧‧同軸結構 C‧‧‧ coaxial structure

G‧‧‧接地區域 G‧‧‧ Grounding area

P‧‧‧電源傳輸區域 P‧‧‧ Power Transmission Area

S‧‧‧訊號傳輸區域 S‧‧‧Signal transmission area

S1‧‧‧第一導電膠層之上表面 S1‧‧‧ Upper surface of the first conductive adhesive layer

S2‧‧‧第一導電膠層之下表面 S2‧‧‧ the lower surface of the first conductive adhesive layer

S3‧‧‧第二導電膠層之上表面 S3‧‧‧ Upper surface of the second conductive adhesive layer

S4‧‧‧第二導電膠層之下表面 S4‧‧‧The lower surface of the second conductive adhesive layer

S5‧‧‧電容板之上表面 S5‧‧‧Capacitor board top surface

S6‧‧‧電容板之下表面 S6‧‧‧Capacitor board under surface

S7‧‧‧板體之上表面 S7‧‧‧ Upper surface of the board

S8‧‧‧板體之下表面 S8‧‧‧ the lower surface of the board

T1‧‧‧接地訊號測試路徑 T1‧‧‧ ground signal test path

T2‧‧‧電源訊號測試路徑 T2‧‧‧Power signal test path

T3‧‧‧電流路徑 T3‧‧‧ current path

第1圖為習知之積體電路測試探針卡的結構示意圖。 FIG. 1 is a schematic structural diagram of a conventional integrated circuit test probe card.

第2圖為本發明一實施例之整合信號及電源完整性模組之積體電路測試座結構示意圖。 FIG. 2 is a schematic structural diagram of an integrated circuit test stand for integrated signal and power integrity modules according to an embodiment of the present invention.

第3A圖為顯示第2圖之導體接點之結構示意圖。 Figure 3A is a schematic diagram showing the structure of the conductor contacts of Figure 2.

第3B圖為顯示第2圖之導體接點之結構示意圖。 Figure 3B is a schematic diagram showing the structure of the conductor contacts of Figure 2.

第3C圖為顯示第2圖之導體接點之結構示意圖。 Figure 3C is a schematic diagram showing the structure of the conductor contacts of Figure 2.

第3D圖為顯示第2圖之導體接點之結構示意圖。 Figure 3D is a schematic diagram showing the structure of the conductor contacts of Figure 2.

第4圖為本發明另一實施例之整合信號及電源完整性模組之結構示意圖。 FIG. 4 is a schematic structural diagram of an integrated signal and power integrity module according to another embodiment of the present invention.

第5圖為本發明又一實施例之整合信號及電源完整性模組之結構示意圖。 FIG. 5 is a schematic structural diagram of an integrated signal and power integrity module according to another embodiment of the present invention.

為了讓本發明之上述及其他目的、特徵、優點能更明顯易懂,下文將特舉本發明較佳實施例,並配合所附圖式,作詳細說明如下。再者,本發明所提到的方向用語,例如上、下、頂、底、前、後、左、右、內、外、側面、周圍、中央、水平、橫向、垂直、縱向、軸向、徑向、最上層或最下層等,僅是參考附加圖式的方向。因此,使用的方向用語是用以說明及理解本發明,而非用以限制本發明。 In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments of the present invention and the accompanying drawings in detail, as follows. Furthermore, the directional terms mentioned in the present invention include, for example, top, bottom, top, bottom, front, back, left, right, inside, outside, side, periphery, center, horizontal, horizontal, vertical, vertical, axial, The radial direction, the uppermost layer, or the lowermost layer, etc., are only directions referring to the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, but not for limiting the present invention.

請參照第2圖,本發明實施例之整合信號及電源完整性模組之積體電路測試座20包括一第一導電膠層21、一第二導電膠層22、一信號及電源完整性模組23以及一導體模組24。第二導電膠層22與第一導電膠層21相對設置。導體模組24包括至少一對導體241。信號及電源完整性模組23 設置於第一導電膠層21及第二導電膠層22之間。至少一對導體241分別貫穿第一導電膠層21及第二導電膠層22而與信號及電源完整性模組23電性接觸。 Please refer to FIG. 2. The integrated circuit test socket 20 of the integrated signal and power integrity module according to the embodiment of the present invention includes a first conductive adhesive layer 21, a second conductive adhesive layer 22, a signal and power integrity module. Group 23 and a conductor module 24. The second conductive adhesive layer 22 is disposed opposite to the first conductive adhesive layer 21. The conductor module 24 includes at least a pair of conductors 241. The signal and power integrity module 23 is disposed between the first conductive adhesive layer 21 and the second conductive adhesive layer 22. At least one pair of conductors 241 penetrate the first conductive adhesive layer 21 and the second conductive adhesive layer 22 respectively, and are in electrical contact with the signal and power integrity module 23.

積體電路測試座20還包括一針座25、一第一鎖固件26及一第二鎖固件27。針座25設置於第一導電膠層21及第二導電膠層22上。第一鎖固件26穿過第二導電膠層22及針座25,以鎖固第二導電膠層22及針座25。第二鎖固件27穿過第二導電膠層22、信號及電源完整性模組23、第一導電膠層21及針座25,以鎖固第二導電膠層22、信號及電源完整性模組23、第一導電膠層21及針座25。在本發明之一實施例中,第一導電膠層21及第二導電膠層22分別為一垂直導電膠層。在本發明之一實施例中,第一導電膠層21及第二導電膠層22為可加工之板體,板體被加工以具有多個孔洞供至少一對導體241貫穿。 The integrated circuit test base 20 further includes a pin base 25, a first locking member 26 and a second locking member 27. The needle base 25 is disposed on the first conductive adhesive layer 21 and the second conductive adhesive layer 22. The first locking member 26 passes through the second conductive adhesive layer 22 and the needle base 25 to lock the second conductive adhesive layer 22 and the needle base 25. The second locking member 27 passes through the second conductive adhesive layer 22, the signal and power integrity module 23, the first conductive adhesive layer 21, and the pin holder 25 to lock the second conductive adhesive layer 22, the signal and power integrity module. Group 23, the first conductive adhesive layer 21 and the needle seat 25. In one embodiment of the present invention, the first conductive adhesive layer 21 and the second conductive adhesive layer 22 are vertical conductive adhesive layers, respectively. In one embodiment of the present invention, the first conductive adhesive layer 21 and the second conductive adhesive layer 22 are processable boards. The board is processed to have a plurality of holes for at least one pair of conductors 241 to pass through.

由於本發明實施例之信號及電源完整性模組23整合於積體電路測試座20內,且至少一對導體241分別貫穿第一導電膠層21及第二導電膠層22而與信號及電源完整性模組23電性接觸,因此使信號及電源完整性模組23對待測物13(device under test,DUT)所提供的電流路徑T3縮短,使待測物測試時,可近距離取得電流,有助於待測物,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果,亦有助於信號完整性(signal Integration,SI)及電源完整性(power Integration,PI)之改善。 Because the signal and power integrity module 23 of the embodiment of the present invention is integrated in the integrated circuit test base 20, and at least a pair of conductors 241 penetrate the first conductive adhesive layer 21 and the second conductive adhesive layer 22, respectively, and communicate with the signal and power supply. The integrity module 23 is in electrical contact, so the signal and power integrity module 23 shortens the current path T3 provided by the device under test 13 (device under test, DUT), so that the current can be obtained at a short distance during the test of the device under test. It helps the DUT, such as the amount of current required for the simultaneous switching of all signals in an integrated circuit (IC), allows the test product to have stable test results, and also helps signal integrity (signal integration (SI) and power integration (PI) improvements.

此外,本發明實施例之積體電路測試座20內,使用至少一對導體241做為連接的導體,導體241包括垂直的導電材料,其傳輸長度短,電感效應小,適於高頻(速)上使用。 In addition, in the integrated circuit test base 20 of the embodiment of the present invention, at least one pair of conductors 241 are used as the connected conductors. The conductor 241 includes a vertical conductive material, which has a short transmission length and a small inductance effect, and is suitable for high frequency (speed ).

請參照第2圖,本發明之實施例的信號及電源完整性模組23 包括一電容模組231,電容模組231包括一電容板232及分別設置在電容板232之相對上表面S5及下表面S6的二第一導電接點233。至少一對導體241分別與二第一導電接點233電性接觸。在實施例中,由於電容模組231整合於積體電路測試座20內,電容模組231設置於靠近待測物13之位置,電流路徑T3短,意即電容蓄電後供電到待測物13的路徑短,使待測物13測試時,可近距離取得電流,有助於待測物13,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果,且有助於檢視IC的效能。 Please refer to FIG. 2. The signal and power integrity module 23 according to the embodiment of the present invention includes a capacitor module 231. The capacitor module 231 includes a capacitor plate 232 and is disposed on the upper surface S5 and the lower surface of the capacitor plate 232, respectively. Two first conductive contacts 233 on the surface S6. At least one pair of conductors 241 are in electrical contact with two first conductive contacts 233, respectively. In the embodiment, since the capacitor module 231 is integrated in the integrated circuit test base 20, the capacitor module 231 is disposed near the DUT 13 and the current path T3 is short, which means that the capacitor supplies power to the DUT 13 after being stored. The short path allows the current to be obtained at a short distance when the DUT 13 is tested, which helps the DUT 13 such as the amount of current required for the simultaneous switching of various signals in an integrated circuit (IC) to allow testing. The product has stable test results and helps to check the performance of the IC.

此外,電容模組231整合於積體電路測試座20內,不會造成電容模組231的結構改變,可維持電容模組231原來的結構及佈線密度。再者,電容模組231整合於積體電路測試座20內,當檢查維修時,可直接更換電容模組231,以電容模組231的備品取代,而可節省檢查維修人力及時間,且易於檢查維修。 In addition, the capacitor module 231 is integrated in the integrated circuit test base 20, which does not cause the structural change of the capacitor module 231, and can maintain the original structure and wiring density of the capacitor module 231. In addition, the capacitor module 231 is integrated in the integrated circuit test base 20, and the capacitor module 231 can be directly replaced during inspection and maintenance, and replaced with a spare of the capacitor module 231, which saves labor and time for inspection and maintenance, and is easy Inspection and repair.

請參照第2、3A至3D圖,在本發明之實施例中,導電模組24包括至少一對導體241及複數個導電接點242。這些導電接點242設置於第一導電膠層21的相對之上表面S1及下表面S2以及第二導電膠層22的相對之上表面S3及下表面S4。每一導電接點242包括一導電層243及設置於導電層243上之至少一導電結構244。導電結構244包括三角柱導電結構或梯形柱導電結構。三角柱導電結構的數量可為一個或多個。梯形柱導電結構的數量可為一個或多個,藉由設置凸起的導電結構244有助於與IC上的接觸點接觸。 Referring to FIGS. 2, 3A to 3D, in the embodiment of the present invention, the conductive module 24 includes at least a pair of conductors 241 and a plurality of conductive contacts 242. These conductive contacts 242 are disposed on the opposite upper surfaces S1 and S2 of the first conductive adhesive layer 21 and the opposite upper surfaces S3 and S4 of the second conductive adhesive layer 22. Each conductive contact 242 includes a conductive layer 243 and at least one conductive structure 244 disposed on the conductive layer 243. The conductive structure 244 includes a triangular pillar conductive structure or a trapezoidal pillar conductive structure. The number of triangular pillar conductive structures may be one or more. The number of the conductive structures of the trapezoidal pillars can be one or more, and the protruding conductive structures 244 can help to make contact with the contact points on the IC.

請參照第4圖,在本發明之另一實施例中,信號及電源完整性模組23a包括一板體234a及一導電體模組235a,導電體模組235a包括至少一接地導電體單元以及一訊號導電體單元237。至少一接地導電體單元以及一訊號導電體單元237分別於信號及電源完整性模組23a中形成至少一接地 區域G以及一訊號傳輸區域S。在實施例中,由於信號及電源完整性模組23a整合於積體電路測試座20內,至少一接地導電體單元以及一訊號導電體單元237設置於靠近待測物之位置,電流路徑T3短,使待測物測試時,可近距離取得電流,有助於待測物,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果,且有助於檢視IC的效能。 Please refer to FIG. 4. In another embodiment of the present invention, the signal and power integrity module 23a includes a board 234a and a conductor module 235a. The conductor module 235a includes at least one grounded conductor unit and One signal conductor unit 237. At least one ground conductor unit and a signal conductor unit 237 form at least one ground area G and a signal transmission area S in the signal and power integrity module 23a, respectively. In the embodiment, since the signal and power integrity module 23a is integrated in the integrated circuit test base 20, at least one ground conductor unit and a signal conductor unit 237 are disposed near the object to be measured, and the current path T3 is short. When the DUT is tested, the current can be obtained at a short distance, which is helpful for the DUT, such as the amount of current required for the simultaneous switching of various signals in an integrated circuit (IC), so that the test product can be stable. Test results and help to check the performance of the IC.

請參照第4圖,至少一接地導電體單元包括二接地導電體單元236a。訊號導電體單元237設置二接地導電體單元236a之間。在本發明之一實施例中,訊號導電體單元237及至少一接地導電體單元形成同軸結構C,可實行阻抗控制,有助於信號完整性(signal Integration,SI)之改善。在本發明之實施例中,同軸結構C是指同軸結構或相似於同軸結構之類同軸結構。在本發明之一實施例中,訊號導電體單元237及二接地導電體單元236a形成同軸結構C,可實行阻抗控制,有助於信號完整性(signal Integration,SI)之改善。 Referring to FIG. 4, at least one grounded conductor unit includes two grounded conductor units 236a. The signal conductor unit 237 is disposed between the two grounded conductor units 236a. In one embodiment of the present invention, the signal conductor unit 237 and the at least one grounded conductor unit form a coaxial structure C, which can implement impedance control and help improve signal integrity (SI). In the embodiment of the present invention, the coaxial structure C refers to a coaxial structure or a coaxial structure similar to the coaxial structure. In one embodiment of the present invention, the signal conductor unit 237 and the two grounded conductor units 236a form a coaxial structure C, which can implement impedance control and contribute to the improvement of signal integrity (SI).

請參照第4圖,接地導電體單元236a包括一接地導電體236b及二接地導電接點236c,二接地導電接點236c分別設置於板體234a之相對上表面S7及下表面S8,接地導電體236b貫穿板體234a並與二接地導電接點236c電性接觸。訊號導電體單元237包括一訊號導電體237a及二訊號導電接點237b。二訊號導電接點237b分別設置於板體234a之相對上表面S7及下表面S8,訊號導電體237a貫穿板體234a並與二訊號導電接點237b電性接觸。在本發明之一實施例中,訊號導電體237a及接地導電體236b形成同軸結構C,可實行阻抗控制,有助於信號完整性(signal Integration,SI)之改善。 Please refer to FIG. 4. The grounded conductor unit 236a includes a grounded conductor 236b and two grounded conductive contacts 236c. The two grounded conductive contacts 236c are respectively disposed on the upper surface S7 and the lower surface S8 of the board 234a. 236b penetrates the board 234a and is in electrical contact with the two ground conductive contacts 236c. The signal conductor unit 237 includes a signal conductor 237a and two signal conductive contacts 237b. The two signal conductive contacts 237b are respectively disposed on the upper surface S7 and the lower surface S8 of the board 234a. The signal conductor 237a penetrates the board 234a and is in electrical contact with the two signal conductive contacts 237b. In one embodiment of the present invention, the signal conductor 237a and the ground conductor 236b form a coaxial structure C, which can implement impedance control and help to improve signal integrity (SI).

請參照第5圖,在本發明之另一實施例中,信號及電源完整性模組23b包括一板體234b及一導電體模組235b,導電體模組235b包括電源 導電體單元238。在本發明之實施例中,電源導電體單元238包括一電源導電體238a、一第一電源導電接點238b、一第二電源導電接點238c及整合於板體234b內之一電子元件238d。第一電源導電接點238b設置於板體234b之上表面S7,第二電源導電接點238c設置於板體234b之下表面S8。電源導電體238a貫穿板體234b,並與第一電源導電接點238b及第二電源導電接點238c電性接觸,電子元件238c與設置於上表面S7上的第一電源導電接點238b電性接觸。第一電源導電接點238b的寬度大於第二電源導電接點238c的寬度,因此,第一電源導電接點238b可穩定地電性接觸電源導電體238a及電子元件238d,使電性接觸良好。由於本發明實施例之電子元件238d整合於板體234b內,因此使信號及電源完整性模組23對待測物(device under test,DUT)所提供的電流路徑T3縮短,使待測物測試時,可近距離取得電流,有助於待測物,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果,亦有助於電源完整性(power Integration,PI)之改善。在本發明之另一實施例中,信號及電源完整性模組可包括信號及電源完整性模組23a及信號及電源完整性模組23b,但本發明不限於此。在本發明的實施例中,電子元件238d例如為電容結構。在本發明的一實施例中,電子元件238d例如為記憶體或積體電路(integrated circuit,IC),由於電流路徑T3縮短,記憶體或積體電路可近距離傳輸電流或訊號,可提升測試效率。儲存在記憶體內的測試訊息因為測試路徑縮短,可有效改善訊號失真的問題。 Referring to FIG. 5, in another embodiment of the present invention, the signal and power integrity module 23 b includes a board 234 b and a conductor module 235 b. The conductor module 235 b includes a power conductor unit 238. In the embodiment of the present invention, the power supply conductor unit 238 includes a power supply conductor 238a, a first power supply conductive contact 238b, a second power supply conductive contact 238c, and an electronic component 238d integrated in the board 234b. The first power source conductive contact 238b is disposed on the upper surface S7 of the board 234b, and the second power source conductive contact 238c is disposed on the lower surface S8 of the board 234b. The power supply conductor 238a penetrates the board 234b and is in electrical contact with the first power supply conductive contact 238b and the second power supply conductive contact 238c. The electronic component 238c is electrically connected to the first power supply conductive contact 238b provided on the upper surface S7. contact. The width of the first power conductive contact 238b is greater than the width of the second power conductive contact 238c. Therefore, the first power conductive contact 238b can stably and electrically contact the power conductive body 238a and the electronic component 238d, making the electrical contact good. Since the electronic component 238d of the embodiment of the present invention is integrated in the board 234b, the signal and power integrity module 23 shortens the current path T3 provided by the device under test (DUT). The current can be obtained at a short distance, which is helpful for the object under test, such as the amount of current required for the simultaneous switching of various signals in an integrated circuit (IC), so that the test product can have stable test results, and also help Improvement of power integration (PI). In another embodiment of the present invention, the signal and power integrity module may include a signal and power integrity module 23a and a signal and power integrity module 23b, but the present invention is not limited thereto. In the embodiment of the present invention, the electronic component 238d is, for example, a capacitor structure. In an embodiment of the present invention, the electronic component 238d is, for example, a memory or an integrated circuit (IC). Since the current path T3 is shortened, the memory or the integrated circuit can transmit a current or a signal at a short distance, which can improve the test. effectiveness. The test information stored in the memory can effectively improve the signal distortion problem because the test path is shortened.

綜上所述,由於本發明實施例之信號及電源完整性模組23整合於積體電路測試座20內,且至少一對導體241分別貫穿第一導電膠層21及第二導電膠層22而與信號及電源完整性模組23電性接觸,因此使信號及電源完整性模組23對待測物13所提供的電流路徑T3縮短,使待測物13測試 時,可近距離取得電流,有助於功能複雜的待測物13,例如積體電路(integrated circuit,IC)內各訊號同時的切換所需的電流量,讓測試產品能有穩定的測試結果。 In summary, since the signal and power integrity module 23 of the embodiment of the present invention is integrated in the integrated circuit test socket 20, and at least one pair of conductors 241 penetrate the first conductive adhesive layer 21 and the second conductive adhesive layer 22, respectively. And the electrical contact with the signal and power integrity module 23 makes the current path T3 provided by the signal and power integrity module 23 to be shortened, so that the current can be obtained at a short distance when the object 13 is tested. It is helpful for the DUT 13 with complex functions, such as the amount of current required for the simultaneous switching of various signals in an integrated circuit (IC), so that the test product can have stable test results.

雖然本發明已以較佳實施例揭露,然其並非用以限制本發明,任何熟習此項技藝之人士,在不脫離本發明之精神和範圍內,當可作各種更動與修飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (18)

一種整合信號及電源完整性模組之積體電路測試座,包括:一第一導電膠層;一第二導電膠層,與該第一導電膠層相對設置;一導體模組,包括至少一對導體;以及一信號及電源完整性模組,設置於該第一導電膠層及該第二導電膠層之間,其中該至少一對導體分別貫穿該第一導電膠層及該第二導電膠層而與該信號及電源完整性模組電性接觸。     An integrated circuit test stand for integrating signal and power integrity modules, comprising: a first conductive adhesive layer; a second conductive adhesive layer opposite to the first conductive adhesive layer; a conductor module including at least one A pair of conductors; and a signal and power integrity module disposed between the first conductive adhesive layer and the second conductive adhesive layer, wherein the at least one pair of conductors penetrates the first conductive adhesive layer and the second conductive layer, respectively The adhesive layer is in electrical contact with the signal and power integrity module.     如申請專利範圍第1項所述之積體電路測試座,其中該信號及電源完整性模組包括一電容模組,該電容模組包括一電容板及分別設置在該電容板之相對上表面及下表面的二第一導電接點。     According to the integrated circuit test stand described in item 1 of the scope of patent application, wherein the signal and power integrity module includes a capacitor module, the capacitor module includes a capacitor plate and are disposed on opposite upper surfaces of the capacitor plate, respectively. And two first conductive contacts on the lower surface.     如申請專利範圍第2項所述之積體電路測試座,其中該至少一對導體分別與該二第一導電接點電性接觸。     According to the integrated circuit test stand described in item 2 of the scope of patent application, wherein the at least one pair of conductors are in electrical contact with the two first conductive contacts, respectively.     如申請專利範圍第1項所述之積體電路測試座,其中該信號及電源完整性模組包括一板體及一導電體模組,該導電體模組包括至少一接地導電體單元及一訊號導電體單元。     According to the integrated circuit test stand described in item 1 of the scope of patent application, the signal and power integrity module includes a board and a conductor module, and the conductor module includes at least one grounded conductor unit and a Signal conductor unit.     如申請專利範圍第4項所述之積體電路測試座,其中該至少一接地導電體單元包括二接地導電體單元,該訊號導電體單元設置該二接地導電體單元之間。     According to the integrated circuit test stand described in item 4 of the scope of patent application, the at least one grounded conductor unit includes two grounded conductor units, and the signal conductor unit is disposed between the two grounded conductor units.     如申請專利範圍第4項所述之積體電路測試座,其中該訊號導電體單元與該至少一接地導電體單元形成一同軸結構。     According to the integrated circuit test stand described in item 4 of the scope of patent application, wherein the signal conductor unit and the at least one grounded conductor unit form a coaxial structure.     如申請專利範圍第4項所述之積體電路測試座,其中該接地導電體單元包括一接地導電體及二接地導電接點,該二接地導電接點分別設置於該板體之相對上表面及下表面,該接地導電體貫穿該板體並與該二接地導電接點電性接觸。     According to the integrated circuit test stand described in item 4 of the scope of patent application, the grounded conductor unit includes a grounded conductor and two grounded conductive contacts, and the two grounded conductive contacts are respectively disposed on opposite upper surfaces of the board. And the lower surface, the grounded conductor penetrates the board and is in electrical contact with the two grounded conductive contacts.     如申請專利範圍第4項所述之積體電路測試座,其中該訊號導電體單元包括一訊號導電體及二訊號導電接點,該二訊號導電接點分別設置於該板體之相對上表面及下表面,該訊號導電體貫穿該板體並與該二訊號導電接點電性接觸。     According to the integrated circuit test stand described in item 4 of the scope of patent application, the signal conductor unit includes a signal conductor and two signal conductive contacts, and the two signal conductive contacts are respectively disposed on opposite upper surfaces of the board. And the lower surface, the signal conductor penetrates the board and is in electrical contact with the two signal conductive contacts.     如申請專利範圍第1項所述之積體電路測試座,其中該信號及電源完整性模組包括一板體及一導電體模組,該導電體模組包括一電源導電體單元。     According to the integrated circuit test stand described in item 1 of the scope of patent application, the signal and power integrity module includes a board and a conductor module, and the conductor module includes a power conductor unit.     如申請專利範圍第9項所述之積體電路測試座,其中該電源導電體單元包括一電源導電體及整合於該板體內之一電子元件。     According to the integrated circuit test stand described in item 9 of the scope of patent application, wherein the power conductor unit includes a power conductor and an electronic component integrated in the board.     如申請專利範圍第10項所述之積體電路測試座,其中該電子元件為一電容結構、一記憶體或一積體電路。     According to the integrated circuit test stand described in item 10 of the scope of patent application, wherein the electronic component is a capacitor structure, a memory or an integrated circuit.     如申請專利範圍第10項所述之積體電路測試座,其中該電源導電體單元更包括一第一電源導電接點及一第二電源導電接點,分別設置於該板體之相對上表面及下表面,該電源導電體貫穿該板體,並與該第一電源導電接點及該第二電源導電接點電性接觸,該電子元件與該第一電源導電接點電性接觸。     According to the integrated circuit test stand described in item 10 of the scope of patent application, the power supply conductor unit further includes a first power supply conductive contact and a second power supply conductive contact, which are respectively disposed on opposite upper surfaces of the board. And the lower surface, the power source conductor penetrates the board and is in electrical contact with the first power source conductive contact and the second power source conductive contact, and the electronic component is in electrical contact with the first power source conductive contact.     如申請專利範圍第12項所述之積體電路測試座,其中該第一電源導電接點的寬度大於該第二電源導電接點的寬度。     According to the integrated circuit test stand described in item 12 of the scope of the patent application, the width of the conductive contact of the first power source is greater than the width of the conductive contact of the second power source.     如申請專利範圍第1項所述之積體電路測試座,其中該導電模組更包括複數個導電接點設置於該第一導電膠層的相對之上表面及下表面以及該第二導電膠層的相對之上表面及下表面。     According to the integrated circuit test stand described in item 1 of the scope of patent application, the conductive module further includes a plurality of conductive contacts disposed on opposite upper and lower surfaces of the first conductive adhesive layer and the second conductive adhesive. The opposite upper and lower surfaces of the layer.     如申請專利範圍第14項所述之積體電路測試座,其中每一該導電接點包括一導電層及設置於該導電層上之至少一導電結構。     According to the integrated circuit test stand described in item 14 of the scope of the patent application, each of the conductive contacts includes a conductive layer and at least one conductive structure disposed on the conductive layer.     如申請專利範圍第15項所述之積體電路測試座,其中該導電結構係選自於由三角柱導電結構或梯形柱導電結構所構成之群組。     According to the integrated circuit test stand described in item 15 of the scope of patent application, the conductive structure is selected from the group consisting of a triangular pillar conductive structure or a trapezoidal pillar conductive structure.     如申請專利範圍第1項所述之積體電路測試座,更包括一針座,設置於該第一導電膠層及該第二導電膠層上。     The integrated circuit test base described in item 1 of the scope of patent application, further includes a needle base disposed on the first conductive adhesive layer and the second conductive adhesive layer.     如申請專利範圍第1項所述之積體電路測試座,更包括一第一鎖固件及一第二鎖固件,其中該第一鎖固件穿過該第二導電膠層及該針座,該第二鎖固件穿過該第二導電膠層、該信號及電源完整性模組、該第一導電膠層及該針座。     According to the integrated circuit test socket described in item 1 of the scope of the patent application, it further includes a first locking element and a second locking element, wherein the first locking element passes through the second conductive adhesive layer and the pin base. A second fastener passes through the second conductive adhesive layer, the signal and power integrity module, the first conductive adhesive layer, and the pin base.    
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