TW201906329A - Method of shift-coefficient table design of qc-ldpc code for smaller code block sizes in mobile communications - Google Patents

Abstract

A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Description

Shift coefficient table design for QC-LDPC codes for small block size in mobile communication

The present invention relates generally to mobile communications, and more particularly to a shift coefficient table for quasi-cyclic low-density parity-check (QC-LDPC) codes for smaller code block sizes in mobile communications. design.

The methods described in this section are not prior art to the claims listed below, and are not intended to be prior art as they are included in this section.

Third Generation Partnership Project (3GPP) has approved the acceleration fifth-generation (5 ^th -generation, 5G) New Radio (New Radio, NR) specification development plans, it can be expected based on wireless communication standard 5G NR The service will be available in the near future. 3GPP also agreed that QC-LDPC will be used for 5G NR data channels. However, details on how QC-LDPC-based encoding (eg, encoding and decoding) can be implemented have not been defined.

The following summary is merely illustrative and is not intended to be limiting in any way. That is, the following summary is provided to introduce the concepts, concepts, advantages and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described below in the detailed description. The following summary is not intended to identify essential features of the claimed subject matter,

In one aspect, a method of wireless communication can involve a processor of a device establishing a wireless communication link with at least one other device via a transceiver of the device. The method may also involve the processor wirelessly communicating with other devices via the wireless communication link by: (a) selecting a first shift coefficient table from the plurality of shift coefficient tables; (b) using the first shift At least a portion of the coefficient table and the base matrix generate a QC-LDPC code; (c) selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; (d) storing the selected codebook to the processor Corresponding memory; (e) encoding the data using the selected codebook to generate a plurality of modulation symbols of the data; and (f) controlling the transceiver to multiplex, convert, filter, amplify, and pass the modulation symbols One or more antennas radiate the modulation symbols as electromagnetic waves to transmit modulation symbols of the data to the other devices via a wireless communication link. When selecting the first shift coefficient table from the plurality of shift coefficient tables, the method may involve the processor according to one or more of any one or two of a code block size of the material and a code rate of the material. A rule that selects the first shift coefficient table for a relatively small code block size.

It is worth noting that although the following description of the proposed scheme and various examples is provided in the context of 5G NR wireless communication, other protocols, standards and specifications, proposed concepts, schemes and any of them are applicable according to the implementation. The deformation/derivative can be implemented in communication. Therefore, the scope of the proposed solution is not limited to the description provided herein.

Detailed embodiments and implementations of the claimed subject matter are disclosed herein. It should be understood, however, that the disclosed embodiments and embodiments are only illustrative of the claimed subject matter, which may be embodied in various forms. The present disclosure, however, may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments and embodiments set forth herein. Rather, the exemplary embodiments and implementations are provided so that the description of the disclosure will be thorough and complete, and the scope of the disclosure will be fully conveyed by those skilled in the art. In the following description, details of the known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments and embodiments presented.

Overview

The proposed concepts and schemes generally cover the following areas: multi-codebook embedded LDPC code design, hybrid orthogonal LDPC layer design, very low bit rate (CR) QC-LDPC support, core matrix design and shift factor design. The areas of hybrid orthogonal LDPC layer design include quasi-row orthogonal layer design and new concepts and schemes for hybrid orthogonal layer design. A description of the proposed concepts and aspects is provided below with reference to Figures 1 through 9.

FIG. 1 illustrates an exemplary multi-codebook embedded LDPC code design in accordance with an embodiment of the present invention. Referring to FIG. 1, a basic parity check matrix (referred to interchangeably herein as "base matrix") 100 of a QC-LDPC code according to the present invention may have a plurality of codebooks embedded therein.

As shown in FIG. 1, the basic matrix 100 may include: a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. In other words, the basic matrix 100 can be defined by a parity matrix having relatively few non-zero/non-null bits (each represented by "1" in FIG. 1) and a majority of zero/vacancy bits, and an information matrix. Yuan (each is represented by "0" in Figure 1). The parity matrix can also define a set of linear constraints on the code bits. Therefore, each of the plurality of codebooks embedded in the QC-LDPC code of the basic matrix 100 may include a parity matrix and respective portions of the information matrix of the corresponding size such that the sizes of the plurality of codebooks are different from each other. Thus, each codebook can form at least a portion of the basic matrix regardless of size. In the example shown in Figure 1, the codebook can be represented as follows: Codebook = (I1 or I2 or I3) + P

The label "I1" represents the first part of the information matrix, the label "I2" represents the second part of the information matrix, the label "I3" represents the third part of the information matrix, and the label "P" represents the parity matrix. Here, the size of I1 (e.g., in terms of the number of bits and/or the size of the memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.

Therefore, the size of the resulting codebook can vary depending on the size of the partial information matrix that forms the codebook together with the parity matrix. It should be noted that although the embodiment shown in FIG. 1 describes three codebooks of different sizes formed by the combination of I1 + P, I2 + P and I3 + P, different sizes according to various embodiments of the present invention The number of codebooks is not limited to three (possibly less than three or more than three).

In some embodiments, each of the plurality of codebooks may correspond to a corresponding HARQ thread in a plurality of hybrid automatic repeat request (HARQ) threads, wherein the plurality of HARQ threads are different from each other. For example, the first codebook may correspond to the first HARQ thread, and the first codebook may have a value ranging from 0.33 to 0.89. The second codebook may correspond to the second HARQ thread, and the second codebook has a value ranging from 0.2 to 0.66. The third codebook may correspond to a third HARQ thread, and the third codebook has a small codeblock size of less than 400. Therefore, in HARQ-based communication between two communication devices, each of a plurality of HARQ threads can be associated with or otherwise associated with a respective codebook of a plurality of codebooks. Therefore, the HARQ thread currently used in HARQ-based communication can be identified. Correspondingly, one of the plurality of codebooks may be selected, and one of the plurality of codebooks corresponds to the identified HARQ thread for encoding the data for transmission.

In some embodiments, each of the plurality of codebooks corresponds to one or a plurality of registers used in storing the codebook, one or a plurality of buffers, one or a plurality of caches, and/or Or the corresponding memory size (Kb) in one or more memory cells. For example, the first codebook may correspond to the first storage size Kb = 16. The second codebook may correspond to the second storage size Kb = 12. The third codebook may correspond to the third storage size Kb=5. In the solution proposed according to the present invention, if a large codebook corresponding to a large memory size is used (for example, because the code block size of the material to be encoded is relatively large, or because the initial code rate is relatively high), the encoding is not If necessary, a small codebook corresponding to a small storage size can be selected for encoding. Therefore, it is possible to avoid using a larger storage space (because the codebook larger than necessary is being selected), so the processing delay of the encoding is shortened.

In some embodiments, all codebooks can share a single matrix, using different zero-padding sizes. In some embodiments, different codebooks may be designed for different shift coefficients or share one shift factor design.

In some embodiments, which of the plurality of codebooks is to be used is selected based on the initial code rate for transmitting the material, the code block size of the material, or both. In some embodiments, if a large codebook corresponding to a large number of encoding processing delays is not necessary for encoding, in order to shorten the processing delay of encoding in the communication device, the codebook is selected such that a small codebook requiring a small amount of encoding processing delay is selected for encoding. .

FIG. 2 illustrates an example logic flow 200 associated with multi-codebook embedded LDPC code design in accordance with an embodiment of the present invention. Logic flow 200 may be implemented in an encoder or processor, or implemented by an encoder or processor to implement various features and/or aspects of the concepts and/or aspects of the present disclosure. More specifically, the logic flow 200 may involve selecting one or a plurality of rules used in the codebook from a plurality of codebooks embedded in a basic matrix of the QC-LDPC code, such that if a large number of codes corresponding to a large number of encoding processes are delayed This is not necessary for encoding, and a small codebook that requires a small amount of encoding processing delay is selected for encoding. Logic flow 200 may include one or more operations, actions or functions represented by one or more of blocks 210, 220, 230, 240, and 250. Although shown as discrete blocks, depending on the desired implementation, the various blocks of logic flow 200 can be divided into additional blocks, merged into fewer blocks, or deleted. The logic flow 200 can be implemented by each of the first device 1005 and the second device 1050 as described below. The description of logic flow 200 below is provided in the context of second device 1050, for purposes of illustration only and not limitation. Logic flow 200 can begin at 210.

At 210, the logic flow 200 can involve the second device 1050 determining whether the code block size of the material to be encoded is less than a threshold code block size. In the event that it is determined that the code block size of the material is less than the threshold code block size, logic flow 200 may proceed from 210 to 220. In the event that it is determined that the code block size of the material is not less than the threshold code block size, logic flow 200 may proceed from 210 to 230.

At 220, the logic flow 200 can involve the second device 1050 selecting a first codebook of the plurality of codebooks.

At 230, logic flow 200 can involve the second device 1050 determining whether the initial code rate for transmitting the material is greater than the threshold code rate. In the event that it is determined that the initial code rate is not greater than the threshold code rate, logic flow 200 may proceed from 230 to 240. In the event that it is determined that the initial code rate is greater than the threshold code rate, logic flow 200 may proceed from 230 to 250.

At 240, logic flow 200 can involve second device 1050 selecting a second codebook of the plurality of codebooks.

At 250, logic flow 200 can involve second device 1050 selecting a third codebook of the plurality of codebooks.

Here, the size of the third codebook is larger than the size of the second codebook. In addition, the size of the second codebook is larger than the size of the first codebook. Therefore, if a large codebook corresponding to a large memory size (eg, a code block size greater than a threshold code block size or an initial code rate greater than a threshold code rate) is not necessary for encoding, logic flow 200 will select a small code corresponding to a small memory size. This, thereby minimizing the amount of storage or storage size used to store the selected codebook. That is, the logic flow 200 can help to shorten the processing delay of the encoding.

FIG. 3 illustrates an exemplary quasi-row orthogonal layer design 300 in accordance with an embodiment of the present invention. Orthogonality facilitates the throughput efficiency of the LDPC decoder. In an LDPC code, several rows may be grouped together to form a layer, and the degree of each column in the layer may be 1 or 0 (ie, orthogonality). In this case, the layer is referred to as a pure row orthogonal layer.

Referring to FIG. 3, in the quasi-orthogonal layer design 300, several columns can be grouped together to form a quasi-row orthogonal layer, such as layer 1, layer 2, layer shown in FIG. 3 and layer 4. In this example, each column in each of Layer 1, Layer 2, Layer 3, and Layer 4 may be a degree of 1 or 0, except for one or a plurality of punctured columns. That is, orthogonality). In the example shown in part (A) of Fig. 3, the two leftmost columns are the perforated lines. Each of the other columns in each of Layer 1, Layer 2, Layer 3, and Layer 4 is a degree of 1 or 0 (ie, having one or 0 non-null/non-null bits) Yuan, denoted by "1", and other bits are zero/empty, denoted by "0"). Advantageously, the quasi-orthogonal layer design 300 provides orthogonality to help improve efficiency in the amount of decoder throughput.

Moreover, in the quasi-orthogonal layer design 300, there is no cycle in the perforated rows in the quasi-orthogonal layers. In the example shown in part (B) of Fig. 3, according to the present invention, since a ring exists in two perforated columns, the corresponding layer is not considered to be a quasi-orthogonal layer.

FIG. 4 is an exemplary hybrid orthogonal layer design 400 illustrated in accordance with an embodiment of the present invention. In the hybrid orthogonal layer design 400, the QC-LDPC code can include a plurality of ports of different degree orthogonality. In the example shown in Fig. 4, the darker patches represent bit 1, and the lighter patches represent bit 0. For example, the first of the plurality of portions may be low degree orthogonal and may correspond to a high code rate. Similarly, the second portion of the plurality of portions can be medium degree orthogonal and can correspond to a medium rate. Similarly, the third portion of the plurality of portions may be orthogonal in height and may correspond to a low code rate.

In the example shown in FIG. 4, the plurality of portions of different orthogonal degrees include the following: (1) a non-row orthogonal portion including a plurality of rows and a plurality of columns, the plurality of rows and complex numbers Columns form at least one non-row orthogonal layer corresponding to a relatively higher code rate; (2) a quasi-column orthogonal portion including a plurality of rows and a plurality of columns, the plurality of rows and a plurality of columns Forming at least one quasi-orthogonal orthogonal layer corresponding to a medium code rate; (3) a pure-row orthogonal portion comprising a plurality of rows and a plurality of columns, the plurality of rows and the plurality of columns forming a corresponding relative At least one pure column orthogonal layer of low bit rate. Here, each of the plurality of columns in the non-row orthogonal portion is a line having a degree of 2 or higher. Further, one or a plurality of the plurality of rows of the orthogonal portion of the quasi-column includes the perforated rows having a degree of 2 or higher. Moreover, the remaining rows of the plurality of rows of the quasi-column orthogonal portion may include non-punctured rows of degree 1 or 0. Moreover, each of the plurality of rows of the pure column orthogonal portion includes a row having a degree of 1 or 0.

FIG. 5 shows an exemplary QC-LDPC code 500 supporting an extremely low code rate based on an embodiment of the present invention. Referring to FIG. 5, the QC-LDPC code 500 may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. The information matrix may include one or a plurality of rows of bits in each column with a degree of two. Moreover, each of the plurality of bits of degree 2 having a degree of 2 or a plurality of row bits may be a previously used parity bit or a previously transmitted information bit. Moreover, for very low code rates, one or more previous transmissions can be retransmitted. Accordingly, the extended column can have a weight of 2. Check the node split for a row with a large weight.

Figure 6 illustrates an example core matrix design 600 in accordance with an embodiment of the present invention. Referring to FIG. 6, in the core matrix design 600, the QC-LDPC code may include a basic matrix, a portion of which forms a core matrix corresponding to a code rate of at least one threshold. For example, in the example shown in Figure 6, the core matrix supports a code rate of 0.89.

FIG. 7 illustrates an example concept 700 of a core base matrix in accordance with an embodiment of the present invention. Referring to FIG. 7, the core matrix may include a plurality of columns and a plurality of rows of a plurality of bits, wherein two or more columns are punched rows, and the plurality of punched rows have specific A bit style (for example, one or a plurality of bits 0). In some embodiments, a particular bit pattern in the plurality of punctured lines may comprise an isosceles right triangle formed by a plurality of bits 0, the right angle of the triangle corresponding to the upper left of the plurality of punctured lines Bit 0 at the corner.

The core matrix may include a parity matrix comprising a plurality of bits of a plurality of rows and a plurality of columns. The core matrix may also include an information matrix comprising a plurality of bits of a plurality of rows and a plurality of columns. The parity matrix may include a matrix having a Wi-Fi pattern (for example, a Wi-Fi-like parity matrix). Moreover, a plurality of bits of more than one row of the information matrix may include a plurality of rows having a high density of bit 1 without or having one bit 0. The bits of the bottom column of the plurality of columns may include a first number of bits 1. The first number may be equal to the number of punched rows or one greater than the number of punched rows.

In the example shown in part (A) of Fig. 7, the first few rows (e.g., three columns) are composed of a Wi-Fi-like parity matrix, and the information matrix has an ultra-high density bit 1. In particular, the bits included in each column in the information matrix, if not all of bit 1, are mostly bit 1, have no bit 0 or have 1 bit 0. After any number of column permutations and/or row permutations (eg, at least one column permutation, at least one row permutation, or a combination thereof), the perforated rows include one or a plurality of bits 0 of a particular pattern. The bottom row may have 3 or 4 edge blocks, and one edge block may correspond to a parity variable node (VN) block. Two edge blocks may correspond to two punctured lines (eg, VN0 and VN1). In the case where there are four edge blocks, a fourth edge block can be added to increase the shortest distance.

In the example shown in part (B) of Fig. 7, an example pattern of the punched line is shown. For a basic matrix of size mxn (m columns by n rows), and assuming that p rows are punctured, an isosceles right triangle of a plurality of bits 0 is used to construct an mxp matrix whose right angle corresponds to the Bit 0 of an upper left corner of a plurality of punched lines. The other bits in the punctured row can be randomly selected to be 0 or 1. Since row permutation and/or column permutation may be performed, the actual position of a particular pattern may be different from the upper left corner of the perforated line.

FIG. 8 is an exemplary concept 800 showing a core base matrix based on another embodiment of the present invention. In concept 800, the core base matrix includes Wi-Fi styles (or Wi-Fi-like parity matrices), punctured lines, and the remainder of the information matrix. The remainder of the information matrix can be designed to have one of a plurality of degree distributions. For example, the core matrix can include 5 row bits and 20 column bits. The variable node (VN) degree of 20 rows of bits may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3] , [2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], and [2, 2, 3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. The test node (CN) degree of 5 row bits may include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13 , 18, 3], [13, 11, 13, 18, 2], [13, 10, 14, 18, 2], [13, 10, 13, 19, 2], [14, 10, 13, 18 , 1], [13, 11, 13, 18, 1], [13, 10, 14, 18, 1], [13, 11, 13, 19, 1], [13, 10, 13, 18, 2 ], and [13, 10, 13, 18, 1].

Figure 9 is a diagram showing a shift factor design 900 based on an embodiment of the present invention. For each lifting factor, there is a table of corresponding shift values. Tables in different lifting factors can be nested design. In the shift coefficient design 900, an effective set of lifting factors can be defined for use in LDPC encoding. In the example shown in Figure 9, the effective set of lifting factors includes: lifting factors for different values: Z = 16, Z = 24, Z = 32, Z = 48, Z = 64, Z = 96, Z = 128, Z = 192, Z = 256 and Z = 384. In the shift factor design 900, an effective set of lift factors can be optimized to obtain an optimized set of lift factors. The number of lifting factors in the optimized set is less than the number of lifting factors in the active set. The shift coefficient table of the optimized set can be used as the shift coefficient table that is closest and less than or equal to the lift factor. For example, a table designed to increase the shift value of the factor Z = 32 can be shared by the boost factor Z = 48. Similarly, a table designed to increase the shift value of the factor Z = 128 can be shared by the boost factor Z = 192.

For purposes of illustration and not limitation, in an LDPC codebook based on the present invention, Z is used Ҳ = { a x 2 ^j } a {9, 11, 13, 15}, j {0, 1, 2, 3, 4, 5}, the optimized set of lifting factors (Z) can be defined as 4 groups. Use Z φ = { a x 2 ^j } a {9, 10, 11, 12, 13, 14, 15, 16}, j {0, 1, 2, 3, 4, 5}, the effective set of lifting factors can be defined as 8 groups. The corresponding shift value can be represented by four shift coefficient tables, which can correspond to shift coefficients {288, 352, 416, 480}. For any lifting factor Z = a x 2 ^j in the effective set φ, the corresponding shift coefficient can be obtained by p _z ^m,n = ( p ^m,n mod Ẑ) + f(Z), where p ^m,n Is the shift coefficient of the (m, n)th element in the shift coefficient table of â x 2 ⁵ , where â is the maximum value in {9, 11, 13, 15} and â is less than or equal to a , and Ẑ = â x 2 ^j . Moreover, f(Z) is a perturbation, a function of Z, and can be represented using a table.

The use of a lifting factor allows encoding of packets of various sizes using a relatively small set of basic matrices and a relatively small set of lifting factors. For example, the base matrix size m x n can be used to encode packets of up to k = n - m information bits to obtain an encoded packet or codeword of n code bits. Using the boost factor Z, the base matrix can be lifted to produce a parity check matrix with an extended dimension of Z· m x Z· n . The extended parity check matrix can then be utilized to encode packets of up to Z· k information bits to obtain codewords for Z· n code bits. Moreover, the use of boosting factors can also allow for efficient parallel encoding and decoding, thereby improving performance and reducing the descriptive complexity of LDPC codes for small sizes.

Shift coefficient table design for larger code block sizes

For purposes of illustration, Figure 15 (A-T22(B) illustrates a plurality of exemplary shift coefficient tables for relatively small code block sizes.

Each of the 15th (A)th to 15th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 1500 based on an embodiment of the present invention. Specifically, the shift coefficient table 1500 is composed of the (A) portion in the 15Ath picture and the (B) portion in the 15Bth picture. Moreover, the shift coefficient table 1500 may correspond to the base chart 2 (BG2) having the primitive element 2 (a = 2) and the boost factor 256.

Each of the 16th (A)th to 16th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 1600 based on an embodiment of the present invention. In particular, the shift coefficient table 1600 is composed of the (A) portion of the 16A diagram and the (B) portion of the 16B diagram. Moreover, the shift coefficient table 1600 may correspond to BG2 having the original element 9 (a = 9) and the boost factor 144.

Each of the 17th (A)th to 17th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 1700 based on an embodiment of the present invention. In particular, the shift coefficient table 1700 is composed of a portion (A) in the 17A diagram and a portion (B) in the 17B diagram. Moreover, the shift coefficient table 1700 can correspond to BG2 having the original element 5 (a = 5) and the boost factor 160.

Each of the 18th (A)th to 18th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 1800 based on an embodiment of the present invention. Specifically, the shift coefficient table 1800 is composed of a portion (A) in the FIG. 18A and a portion (B) in the FIG. 18B. Moreover, the shift coefficient table 1800 may correspond to BG2 having the original element 11 (a = 11) and the boost factor 176.

Each of the 19th (A)th - 19th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 1900 based on an embodiment of the present invention. Specifically, the shift coefficient table 1900 is composed of a portion (A) in the 19A diagram and a portion (B) in the 19B diagram. Moreover, the shift coefficient table 1900 can correspond to BG2 having the original element 3 (a = 3) and the boost factor 192.

Each of the 20th (A)th to 20th (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 2000 based on an embodiment of the present invention. Specifically, the shift coefficient table 2000 is composed of the (A) portion in the 20Ath picture and the (B) portion in the 20Bth picture. Moreover, the shift coefficient table 2000 may correspond to BG1 having the original element 13 (a = 13) and the boost factor 208.

Each of the 21st (A)th to 21st (B)th drawings is a schematic diagram of a portion of an exemplary shift coefficient table 2100 based on an embodiment of the present invention. Specifically, the shift coefficient table 2100 is composed of a portion (A) in the 21A and a portion (B) in the 21B. Moreover, the shift coefficient table 2100 may correspond to BG2 having the original element 7 (a = 7) and the boost factor 224.

Each of the 22(A)- 22(B) diagrams is a schematic diagram of a portion of an exemplary shift coefficient table 2200 based on an embodiment of the present invention. Specifically, the shift coefficient table 2200 is composed of the portion (A) in the 22A diagram and the portion (B) in the 22B diagram. Moreover, the shift coefficient table 2200 may correspond to BG2 having the original element 15 (a = 15) and the boost factor 240.

Figure 23 illustrates an exemplary logic flow 2300 associated with selecting a shift coefficient table in accordance with an embodiment of the present invention. The logic flow 2300 can be implemented in an encoder or processor, or implemented by an encoder or processor to implement various features and/or aspects of the concepts and aspects presented herein. In particular, logic flow 2300 may involve selecting one or a plurality of rules used by the shift coefficient table from some of the shift coefficient tables such that a shift coefficient table suitable for data of a relatively small code block size is selected. Logic flow 2300 can include one or more operations, actions or functions represented by one or more of blocks 2310, 2320, 2330, and 2340. Although shown as discrete blocks, depending on the desired implementation, the various blocks of logic flow 2300 can be divided into additional blocks, merged into fewer blocks, or deleted. The logic flow 2300 can be implemented by each of the first device 1005 and the second device 1050 as described below. The description of the logic flow 2300 is provided in the context of the first device 1005 for illustrative purposes only and not limited to scope. Logic flow 2300 can begin at 2310.

At 2310, logic flow 2300 can involve the processor of first device 1005 determining whether the code block size of the material to be encoded is less than or equal to the threshold code block size. In the event that it is determined that the code block size of the material is less than or equal to the threshold code block size, logic flow 2300 can be performed from 2310 to 2320. Where the processor 1010 determines that the code block size of the material is greater than the threshold code block size, the logic flow 2300 can execute from 2310 to 2330.

At 2320, logic flow 2300 can involve processor 1010 determining whether the code rate of the material to be encoded is less than or equal to a threshold code rate. Where the processor 1010 determines that the code rate of the material is less than or equal to the threshold code rate, the logic flow 2300 can execute from 2320 to 2340. Otherwise, at processor 1010 determining that the code rate of the data is determined to be greater than the threshold code rate, logic flow 2300 can be performed from 2320 to 2330.

At 2330, logic flow 2300 can involve processor 1010 selecting or otherwise using a shift factor table corresponding to base chart 1 (BG1).

At 2340, logic flow 2300 can involve processor 1010 selecting or otherwise using a shift factor table corresponding to base chart 2 (BG2).

In the solution proposed based on the present invention, part or all (integral) of the selected shift coefficient table can be used in encoding regardless of which shift coefficient table is selected. Moreover, the mod result of the value in the shift coefficient table selected or otherwise used for one or a plurality of lifting factors is the same as that shown in Fig. 15(A)-22(B) The modulo results in the shift factor table are the same, either partially or collectively.

Illustrative implementation

FIG. 10 shows an exemplary communication system 1000 in accordance with an embodiment of the present invention. The communication system can include a first device 1005 and a second device 1050, which can communicate with each other via a communication link. Communication link 1040 may be a wireless link in some embodiments. Alternatively, communication link 1040 may be a wired link in some other implementations. In the context of 5G NR communication, communication link 1040 is a wireless communication link, such as a multi-user multiple-input-and-multiple-output (MU-MIMO) communication link. Each of the first device 1005 and the second device 1050 can perform various functions as a communication device to implement the concepts, schemes, techniques, processes, and methods described herein with respect to QC-LDPC encoding, including with respect to FIG. Some or all of FIG. 9 and those of the processes 1100, 1200, 1300, 1400, and 2400 described below. More specifically, each of the first device 1005 and the second device 1050 can implement the proposed multi-codebook embedded LDPC code design, hybrid orthogonal LDPC layer design, very low bit rate QC-LDPC support, basic Matrix design, core matrix design, and the concept of shift factor design and aspects of the solution.

Each of the first device 1005 and the second device 1050 can be part of an electronic device, which can be a communication device, a computing device, a portable or mobile device, or a wearable device. For example, the first device 1005 can be at a Wi-Fi access point, a smart phone, a smart watch, a smart bracelet, a smart necklace, a personal digital assistant or a tablet, laptop, laptop, desktop or servo. Implemented in a computing device such as a device. Similarly, the second device 1050 can be on a Wi-Fi mobile client or site, a smart phone, a smart watch, a smart bracelet, a smart necklace, a personal digital assistant or a tablet, laptop, desktop or servo. Implemented in a computing device such as a device. Alternatively, each of the first device 1005 and the second device 1050 may be implemented in the form of one or a plurality of integrated circuit (IC) chips, such as, but not limited to, one or a plurality of single core processors, one or more A multi-core processor, or one or a plurality of complex-instruction-set-computing (CISC) processors.

Each of the first device 1005 and the second device 1050 may include at least a portion of those elements shown in FIG. 10, respectively. For example, the first device 1005 can include at least a processor 1010, and the second device 1050 can include at least a processor 1060. Additionally, the first device can include a memory 1020, a transceiver 1030, and one or more antennas (represented by antenna 1036), the transceiver 1030 configured to wirelessly transmit and receive data (eg, following one or more 3GPP standards, protocols , specifications, and/or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1020 and the transceiver 1030 can be communicative or operatively coupled to the processor 1010. Similarly, the second device 1050 can also include a memory 1070, a transceiver 1080, and one or more antennas (represented by an antenna 1086) configured to wirelessly transmit and receive data (eg, following one or more 3GPPs) Standards, agreements, specifications, and/or any applicable wireless protocols and standards, such as 5G NR). Each of the memory 1070 and the transceiver 1080 is communicably or operatively coupled to the processor 1060. Each of the first device 1005 and the second device 1050 may further include other components (eg, a power system, a display device, and a user interface device) that are not related to the solution proposed by the present invention, so for simplicity and simplicity, there is no Also shown in Fig. 10 is not described.

The transceiver 1030 can be configured to communicate wirelessly in a single band or in multiple bands. The transceiver 1030 can include a transmitter 1032 capable of wirelessly transmitting data and a receiver 1034 capable of wirelessly receiving data. In some embodiments, the transceiver 1030 can transmit/modulate (via the transmitter 1032) and receive/demodulate (via the receiver 1034) as orthogonal frequency-division multiplexed (OFDM) radiated through the antenna 1036. ) The symbol of the symbol. Likewise, transceiver 1080 can be configured to communicate wirelessly in a single frequency band or in multiple frequency bands. The transceiver 1080 can include a transmitter 1082 capable of wirelessly transmitting data and a receiver 1084 capable of wirelessly receiving data. In some embodiments, the transceiver 1080 can transmit/modulate (via the transmitter 1082) and receive/demodulate (via the receiver 1084) as the data symbols of the OFDM symbols radiated by the antenna 1086.

Each of memory 1020 and memory 1070 can be a storage device configured to store one or more sets of code, programs, and/or instructions and/or materials therein. In the example shown in FIG. 10, memory 1020 stores therein one or more sets of processor-executable instructions 1022 and material 1024, and memory 1070 stores therein one or more sets of processor-executable instructions 1072 and Information 1074. Each of memory 1020 and memory 1070 can be implemented by any suitable technique and can include volatile memory and/or nonvolatile memory. For example, each of memory 1020 and memory 1070 can include one type of random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and/or Zero capacitor RAM (Z-RAM). Alternatively or additionally, the memory 520 may include a read only memory (ROM) such as a mask ROM, a programmable ROM (PROM), an erasable programmable ROM (EPROM), and/or an erasable Programmable ROM (erasable programmable ROM, EEPROM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include one type of non-volatile random-access memory (NVRAM), such as a flash memory. Solid state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and/or phase-change memory.

In one aspect, each of processor 1010 and processor 1060 can be implemented in the form of one or a plurality of single core processors, one or more multi-core processors, or one or more CISC processors. That is, in accordance with the present invention, even though the singular term "processor" is used herein to refer to each of processor 1010 and processor 1060, in accordance with the present invention, each of processor 1010 and processor 1060 is implemented in some implementations. A plurality of processors may be included and in other implementations a single processor may be included. In another aspect, each of processor 1010 and processor 1060 can be implemented in the form of a hardware (and optionally firmware) having electronic components including, for example but not limited to, one or more a crystal, one or a plurality of diodes, one or a plurality of capacitors, one or a plurality of resistors, one or a plurality of inductors, one or a plurality of memristors and/or one or more varactors A varactor, which is configured and arranged in accordance with the present invention to achieve a particular purpose. In other words, in at least some embodiments, each of processor 1010 and processor 1060 is a special purpose processor that is specifically designed, arranged, and configured to perform particular tasks, in accordance with various embodiments of the present invention, Specific tasks include shift coefficient table design for QC-LDPC codes for smaller code block sizes in mobile communications.

In accordance with various embodiments of the present invention, processor 1010 as a dedicated machine may include non-generic and specially designed hardware circuits that are designed, arranged, and configured to perform QC for use in smaller communication block sizes in mobile communications. - The specific task of the shift coefficient table design of the LDPC code. In one aspect, processor 1010 can execute one or more sets of code, programs, and/or instructions 1022 stored in memory 1020 to perform various operations to render in mobile communications, in accordance with various embodiments of the present invention. Shift coefficient table design for QC-LDPC codes of smaller code block sizes. In another aspect, in accordance with various embodiments of the present invention, processor 1010 can include an encoder 1012 and a decoder 1014 that together perform specific tasks and functions to render a QC-LDPC code. For example, encoder 1012 can be configured to encode material in accordance with various concepts and aspects of the present invention. Similarly, decoder 1014 can be configured to decode data in accordance with various concepts and aspects of the present invention.

In some implementations, processor 1010 can also include memory 1016, which can include one or more registers, one or more buffers, and/or one or more caches. In some implementations, the processor 1016 can utilize the memory 1016 to store a base matrix of QC-LDPC codes, a selected codebook, a lifting factor, and/or one or a plurality of shift coefficient matrices. For example, processor 1010 can generate a base matrix and store it in memory 1020, and when selecting a codebook from a plurality of codebooks embedded in the base matrix, processor 1010 can store the selected codebook in In memory 1016. Thus, according to one or more of the rules of logic flow 200, the processing delay of the encoding can be shortened by selecting a codebook from a plurality of codebooks embedded in the basic matrix. Thus, by implementing various aspects in accordance with the present invention (e.g., by encoding a code from a plurality of codebooks embedded in a QC-LDPC code for encoding), not only is the functionality of the processor 1010 improved (e.g., The processing delay is shorter) and the underlying techniques of data encoding are also improved (e.g., shorter processing delays and improved decoder throughput efficiency).

In accordance with various embodiments of the present invention, processor 1060, which is a dedicated machine, may include non-generic and specially designed hardware circuits that are designed, arranged, and configured to perform particular tasks related to QC-LDPC encoding. In one aspect, processor 1060 can execute one or more sets of code, programs, and/or instructions 1072 stored in memory 1070 to perform various operations related to QC-LDPC encoding, in accordance with various embodiments of the present invention. In another aspect, processor 1060 can include an encoder 1062 and a decoder 1064 that perform specific tasks and functions to render QC-LDPC encoding, in accordance with various embodiments of the present invention. For example, encoder 1062 can be configured to encode material in accordance with various concepts and aspects of the present invention. Similarly, decoder 1064 can be configured to decode data in accordance with various concepts and aspects of the present invention.

In some implementations, the processor 1060 can also include a memory 1066 that can include one or more registers, one or more buffers, and/or one or more cache memories. In some implementations, the processor 1060 can utilize the memory 1066 to store a base matrix of QC-LDPC codes, a selected codebook, a lifting factor, and/or a matrix of shift coefficients. For example, processor 1060 can generate a base matrix and store it in memory 1070, and when selecting a codebook from a plurality of codebooks embedded in the base matrix, processor 1060 can store the selected codebook in In memory 1066. Therefore, by selecting a codebook from a plurality of codebooks embedded in the basic matrix according to one or a plurality of rules of the logic flow 200, the processing delay of the encoding can be shortened.

Each of encoder 1012 and encoder 1062 can be configured with a plurality of electronic components that operate as a code chain to perform some operations related to encoding. For example, the encoding chain in each of the encoder 1012 and the encoder 1062 can be implemented as follows: bit reordering, tone interleaving, and redundancy version (RV) design, Self-adjusting HARQ buffering, and code block grouping. Each of decoder 1014 and decoder 1064 can be configured to support various code rates of the codebook. The lowest code rate of the codebook supported by each of decoder 1014 and decoder 1064 may depend on the size of the corresponding boost factor. In the proposed scheme, an upper limit of the size of a log-likelihood ratio (LLR) memory can be set. The boost factor can be stored in the LLR memory, and the size of the LLR memory can define or otherwise limit how large the boost factor can be. Accordingly, by setting the upper limit of the LLR memory size, the maximum size of the lifted parity check matrix generated from the basic matrix can be set, thereby setting the memory of the parity check matrix that needs to be stored. The upper limit of the body size. In the first device 1005, one or a plurality of registers, one or a plurality of buffers, one or a plurality of cache memories, and/or one or a plurality of memory cells in the processor 1010 may be used (eg, The memory 1016) or one or a plurality of memory cells in the memory 1020 implement LLR memory. In the second device 1050, by using one or more registers, one or more buffers, one or more cache memories, and/or one or more memory cells in the processor 1060 (eg, memory) The body 1066) or one or a plurality of memory cells in the memory 1070 implement LLR memory.

In operation, for a forward link on the transmitting side, the encoder 1012 can receive the data packet from the data source, process the data by performing encoding, interleaving, and symbol mapping on the data, and provide modulation symbols for the encoded data. Transmitter 1032 can multiplex the modulation symbols with the pilot symbols, perform spatial processing, and provide one or a plurality of output symbol streams. Transmitter 1032 (which may include one or more transponders) may condition one or a plurality of output symbol streams by performing digital to analog conversion, filtering, amplification, and up-conversion to produce one or a plurality of forward chains The path signal is radiated as an electromagnetic wave by one or a plurality of antennas of the antenna 1036. On the receive (RX) side, receiver 1084 (which may include one or more receivers) may receive one or more forward link signals as electromagnetic waves via one or more antennas of antenna 1086. Receiver 1084 can also process the received signal by performing filtering, amplification, down conversion, and analog to digital conversion to obtain a plurality of samples. Receiver 1084 may also process a plurality of samples to obtain received symbols and perform multiple input multiple output (MIMO) detection on the received symbols to provide detected symbols. The decoder 1064 can process the detected symbols by performing symbol de-mapping, de-interleaving, and decoding to provide decoded data to the sink.

Similarly, on a reverse link, encoder 1062 can receive a data packet from a data source and process the data by encoding, interleaving, and symbol mapping to provide modulation symbols for the encoded data. Transmitter 1082 can multiplex the modulation symbols with the pilot symbols, perform spatial processing, and provide one or a plurality of output symbol streams. Transmitter 1082 (which may include one or more transponders) may condition one or a plurality of output symbol streams by performing digital to analog conversion, filtering, amplification, and up-conversion to produce one or more inverse chains The path signal, the one or more reverse link signals are radiated as electromagnetic waves through one or more antennas of the antenna 1086. On the receive (RX) side, receiver 1034 (which may include one or more receivers) may receive one or more reverse link signals as electromagnetic waves via one or more antennas of antenna 1036. Receiver 1034 can process the received signals by performing filtering, amplification, down conversion, and analog to digital conversion to obtain a plurality of samples. Receiver 1034 can also process a plurality of samples to obtain received symbols and perform MIMO detection on the received symbols to provide detected symbols. The decoder 1014 can process the detected symbols by performing symbol demapping, deinterleaving, and decoding to recover the data sent by the second device 1050.

The processor 1010 can be configured to control or otherwise direct the operation of the first device 1005. The processor 1060 can be configured to control or otherwise direct the operation of the first device 1050. In accordance with the aspects and concepts of the present application, processor 1010 can determine the size of the packet to be transmitted and/or received, and, correspondingly, control the encoding by encoder 1012 and the decoding by decoder 1014, respectively. Likewise, in accordance with the aspects and concepts of the present application, processor 1060 can determine the size of the packet to be transmitted and/or received, and, correspondingly, control the encoding by encoder 1062 and the decoding by decoder 1064, respectively. For example, each of processor 1010 and processor 1060 can be configured to select a codebook from a plurality of codebooks embedded in a base matrix of QC-LDPC codes for encoding such that if a large number of encoding processing delays are associated The large codebook is not necessary for encoding, and a small codebook that requires a small amount of encoding processing delay is selected for encoding.

Each of the first device 1005 and the second device 1050 can be configured to perform each of the processes 1100, 1200, 1300, 1400, and 2400 described below. Therefore, to avoid redundancy and for brevity, the operations of the first device 1005 and the second device 1050, as well as the operations of the processor 1010 and the processor 1060, are described in the context of the processes 1100, 1200, 1300, 1400, and 2400 below. It is to be noted that although the following description is provided in the environment of the first device 1005, the following description is also applicable to the second device 1050.

Regarding the shift coefficient table design of the QC-LDPC code for small code block size in mobile communication, the processor 1010 of the first device 1005 can establish a wireless communication link with the second device 1050 via the transceiver 1030 of the device 1005. The processor 1010 can wirelessly communicate with the second device 1050 via the transceiver 1030 via a wireless communication link. In wireless communication with the second device 1050, the processor 1010 can perform a plurality of operations. For example, the processor 1010 can perform the following steps: (1) selecting a first shift coefficient table from a plurality of shift coefficient tables; (2) generating a QC-LDPC code using at least a portion of the first shift coefficient table and a base matrix; (3) selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; (4) storing the selected codebook to a memory associated with the processor; (5) using the selected codebook to encode the data, Generating a plurality of modulation symbols for the data; and (6) controlling the transceiver 1030 to multiplex, convert, filter, amplify the modulation symbols, and radiate the modulation symbols as electromagnetic waves through one or more antennas 1036 of the first device for wireless communication The link transmits the modulation symbols of the data to the second device 1050.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table arranged in four columns of 14 columns in the following pattern:

In some embodiments, the first shift coefficient table may include a shift coefficient table as shown in FIGS. 15A and 15B.

In some embodiments, when the first shift coefficient table is selected from the plurality of shift coefficient tables, the processor 1010 can be based on one or more of any one or both of the code block size and the code rate of the material. A rule that selects the first shift coefficient table for a relatively small code block size.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the processor 1010 can generate the QC using the full portion and the base matrix of the first shift coefficient table. - LDPC code.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the processor 1010 can generate a QC using a partial portion and a base matrix of the first shift coefficient table. - LDPC code.

In some embodiments, when selecting the first shift coefficient table from the plurality of shift coefficient tables, the processor 1010 may select a second shift coefficient table, the values in the second shift coefficient table being one or plural The modulo result of the lifting factor is the same as the modulo result in at least the first shift coefficient table.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the processor 1010 can generate a QC using the full portion and the base matrix of the second shift coefficient table. - LDPC code.

In some embodiments, when at least a portion of the first shift coefficient table and the base matrix are used to generate the QC-LDPC code, the processor 1010 can generate a QC using a partial portion and a basic matrix of the second shift coefficient table. - LDPC code.

In some implementations, processor 1010 can perform a plurality of operations (eg, with respect to logic flow 2300) while selecting a first shift coefficient table from a plurality of shift coefficient tables. For example, processor 1010 can determine if the code block size is less than or equal to a threshold code block size. Additionally, processor 1010 can determine if the code rate is less than or equal to a threshold code rate. Moreover, in response to determining that the code block size is greater than the threshold code block size or in response to determining that the code rate is greater than the threshold code rate, the processor 1010 can select the first shift coefficient table corresponding to the base chart 1 (BG1). Alternatively, in response to determining that the code block size is less than or equal to the threshold code block size and in response to determining that the code rate is less than or equal to the threshold code rate, the processor 1010 may select the first shift corresponding to the base chart 2 (BG2) Coefficient table.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 2 (a = 2) and the boost factor 256. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 9 (a = 9) and the boost factor 144. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 5 (a = 5) and the boost factor 160. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 11 (a = 11) and the boost factor 176. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 3 (a = 3) and the boost factor 192. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 13 (a = 13) and the boost factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 7 (a = 7) and the boost factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 15 (a = 15) and the boost factor 240.

In some embodiments, each of the plurality of codebooks may correspond to a respective HARQ thread of the plurality of hybrid automatic repeat request HARQ threads, and the plurality of HARQ threads are different from each other.

In some embodiments, processor 1010 can perform a plurality of operations when selecting a codebook from a plurality of codebooks. For example, processor 1010 can determine if the code block size of the material is less than a threshold code block size. Moreover, in response to the code block size of the data being less than the threshold code block size, the processor 1010 can select the third codebook of the plurality of codebooks. Moreover, in response to the code block size of the data being no less than the threshold code block size, the processor 1010 can determine whether the initial code rate for transmitting the data is greater than a threshold code rate. Moreover, in response to the initial code rate not being greater than the threshold code rate, the processor 1010 can select the second codebook of the plurality of codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, the processor 1010 can select the first codebook of the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some embodiments, processor 1010 can perform some operations when selecting a codebook from a plurality of codebooks. For example, processor 1010 can determine the code block size of the material. In addition, the processor 1010 may select a codebook by: (1) selecting a first codebook of the plurality of codebooks in response to the determined code block size being greater than a first threshold codeblock size; and (2) responding to the determining The code block size is greater than the second threshold code block size, and the second codebook in the plurality of codebooks is selected; (3) in response to the determined code block size being greater than the third threshold code block size, selecting a plurality of codebooks The third codebook. The first threshold code block size may be greater than the second threshold code block size. The second threshold code block size may be greater than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Explanatory process

FIG. 11 shows an exemplary process 1100 based on an embodiment of the present application. Process 1100 may represent aspects of implementing the proposed concepts and aspects, which may be described, for example, with respect to some or all of Figures 1 - 10. In particular, process 1100 can represent aspects of the proposed concepts and aspects related to QC-LDPC coding. Process 1100 can include one or more of the operations, actions, or functions illustrated by one or more of blocks 1110, 1120, 1130, and 1140. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1100 can be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1100 may be performed in the order illustrated in FIG. 11 or in a different order. Process 1100 can be implemented by communication system 1000 and any variations thereof. For example, process 1100 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Process 1100 is described in the context of first device 1005 as follows, for purposes of illustration only and not limitation. Process 1100 can begin at block 1110.

At 1110, process 1100 can involve the processor 1010 of the first device 1005 generating a QC-LDPC code having a plurality of codebooks embedded therein. Process 1100 executes from 1110 to 1120.

At 1120, process 1100 can involve processor 1010 selecting a codebook from a plurality of codebooks. Processor 1010 can execute from 1120 to 1130.

At 1130, process 1100 can involve processor 1010 encoding the material using the selected codebook. Process 1100 executes from 1130 to 1140.

At 1140, process 1100 can involve processor 1010 transmitting the encoded material via transceiver 1030 (eg, to second device 1050).

In some embodiments, each of the plurality of codebooks may correspond to a respective HARQ thread of the plurality of HARQ threads, the plurality of HARQ threads being different from each other. For example, process 1100 can involve processor 1010 communicating with processor 1060 of second device 1050 using HARQ. In selecting a codebook from a plurality of codebooks, process 1100 can involve processor 1010 performing: (1) associating or otherwise associating each of a plurality of HARQ threads with a corresponding code in a plurality of codebooks (2) identifying a HARQ thread currently used for communication with the second device 1050; and (3) selecting one of the plurality of codebooks, one of the plurality of codebooks and the identified HARQ thread correspond. The selected codebook can be used in encoding the material to be sent to the second device 1050.

In some embodiments, when generating a QC-LDPC code having a plurality of codebooks embedded therein, the process 1100 can involve the processor 1010 generating a QC-LDPC code consisting of a base matrix and one or a plurality of shift coefficient matrices. . The basic matrix may include a parity matrix of a plurality of parity bits and an information matrix of a plurality of information bits. Each of the plurality of codebooks may include a parity matrix and a corresponding portion of the information matrix of a corresponding size such that the sizes of the plurality of codebooks are different from each other.

In some embodiments, each of the plurality of codebooks can correspond to a respective one of a plurality of designs of the shift coefficient matrix.

In some embodiments, when generating a QC-LDPC code having a plurality of codebooks embedded therein, the process 1100 can involve the processor 1010 generating a respective shift value for each of the first set of lifting factors. table. Moreover, process 1100 can involve processor 1010 optimizing a first set of lifting factors to generate a second set of lifting factors. The number of first set of lifting factors may be greater than the number of second set of lifting factors. The first boost factor may share a respective shift value table of the second boost factor, wherein the first boost factor is in the first set but not in the second set, and the second boost factor is in both the first set and the second set. The value of the second boost factor may be less than the value of the first boost factor, and the second boost factor is closer to the first boost factor than the other boost factors in the first set.

In some embodiments, when selecting a codebook from a plurality of codebooks, process 1100 can involve processor 1010 selecting from a plurality of codebooks based on a code rate of an initial code rate and/or material used to transmit the material. Codebook.

In some implementations, when selecting a codebook from a plurality of codebooks, process 1100 can involve processor 1010 performing some operations (eg, similar to those involved in logic flow 200). For example, process 1100 can involve processor 1010 determining if the code block size of the material is less than a threshold code block size. In response to the code block size of the data being less than the threshold code block size, process 1100 can involve processor 1010 selecting a third codebook of the plurality of codebooks. In response to the code block size of the data being no less than the threshold code block size, the process 1100 can involve the processor 1010 determining whether the initial code rate for transmitting the material is greater than a threshold code rate. In response to the initial code rate not being greater than the threshold code rate, process 1100 can involve processor 1010 selecting a second codebook of the plurality of codebooks. In response to the initial code rate being greater than the threshold code rate, process 1100 can involve processor 1010 selecting a first codebook of the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Alternatively or additionally, when selecting a codebook from a plurality of codebooks, process 1100 can involve processor 1010 performing some other operations. For example, process 1100 can involve processor 1010 determining a code block size of a material. Based on the determined result, in response to determining that the code block size is greater than the first threshold code block size, the process 1100 can involve the processor 1010 selecting the first codebook of the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the second threshold code block size, the process 1100 can involve the processor 1010 selecting a second codebook of the plurality of codebooks. Moreover, in response to determining that the code block size is greater than the third threshold code block size, the process 1100 can involve the processor 1010 selecting a third codebook of the plurality of codebooks. The first threshold code block size may be greater than the second threshold code block size. The second threshold code block size may be greater than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.

Figure 12 shows an exemplary process 1200 based on an embodiment of the present invention. Process 1200 may represent aspects of implementing the proposed concepts and aspects, which may be described, for example, with respect to some or all of Figures 1 - 10. Moreover, process 1200 can represent aspects of the proposed concepts and aspects related to hybrid orthogonal LDPC layer design and very low bit rate QC-LDPC support. Process 1200 can include one or a plurality of operations, actions, and functions illustrated by one or a plurality of blocks in blocks 1210, 1220, and 1230. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1200 can be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1200 may be performed in the order illustrated in Figure 12, or in a different order. Process 1200 can be implemented by communication system 1000 and any variations thereof. For example, process 1200 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Process 1200 is described in the context of first device 1005 as follows, without limitation to the scope, for illustrative purposes only. Process 1200 can begin at block 1210.

At 1210, process 1200 can be a processor 1010 involving a first device 1005 that generates a QC-LDPC code, the QC-LDPC code including at least a quasi-row orthogonal layer. Process 1200 can be performed from 1210 to 1220.

At 1220, process 1200 can involve processor 1010 encoding the material using a QC-LDPC code. Process 1200 can be performed from 1220 to 1230.

At 1230, process 1200 can involve processor 1010 transmitting the encoded material (to second device 1050) via transceiver 1030.

In some embodiments, at least one of the quasi-column orthogonal layers can include a plurality of rows and a plurality of columns of bits. One or a plurality of the plurality of columns of at least one of the quasi-column orthogonal layers may include at least one perforated line having a degree of 2 or more. The remaining rows of the plurality of rows of the at least one quasi-orthogonal layer may include non-punctured rows of degree 1 or 0.

In some embodiments, there may be no cycles in the perforation row.

In some embodiments, the QC-LDPC code can include a hybrid orthogonality design of a plurality of portions having different degrees of orthogonality. The first portion of the plurality of portions of the low degree orthogonality may correspond to a high code rate, and the second portion of the plurality of portions of the height number orthogonality may correspond to a low code rate.

In some embodiments, the plurality of portions of different degree orthogonality include the following: (1) a non-column orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns forming at least one with the plurality of rows a non-column orthogonal layer; (2) a quasi-column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming at least one quasi-orthogonal orthogonal layer with the plurality of rows; and (3) a pure column The orthogonal layer includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one pure column orthogonal layer. Here, the plurality of rows of the non-column orthogonal portions may include at least one punctured line having a degree of 2 or more and a non-punctured line having a degree of 1 or 0. One or a plurality of rows of the plurality of rows of the quasi-column orthogonal portion may include at least one puncture row having a degree of 2 or higher. The remaining rows of the plurality of rows of the quasi-column orthogonal portion may include non-punctured rows of degree 1 or 0. Each of the plurality of rows of the orthogonal portion of the pure column may include a row having a degree of 1 or 0.

In some embodiments, the QC-LDPC code can include a parity matrix of a plurality of parity bits, and an information matrix of a plurality of information bits. One or a plurality of row bits through the information matrix and the parity matrix may include one or a plurality of column bits each having a degree of two bits.

In some embodiments, each of the plurality of bits of degree 2 of the plurality of bits of degree 2 or a plurality of columns of degree 2 may include previously used parity bits or previously transmitted information bits. .

FIG. 13 shows an exemplary process 1300 based on an embodiment of the present application. Process 1300 may represent aspects and aspects of implementing the proposed concepts and aspects, such as the concepts and aspects described with respect to some or all of Figures 1 - 10. More specifically, process 1300 can represent aspects of the proposed concepts and aspects of the core matrix design. Process 1300 can include one or a plurality of operations, actions, and functions illustrated by one or a plurality of blocks in blocks 1310, 1320, and 1330. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1300 can be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1300 may be performed in the order illustrated in Figure 13, or in a different order. Process 1300 can be implemented by communication system 1000 and any variations thereof. For example, process 1300 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Process 1300 is described in the context of first device 1005 as follows, for purposes of illustration only and not limitation. Process 1300 can begin at block 1310.

At 1310, process 1300 can involve processor 1010 of first device 1005 generating a QC-LDPC code that includes a base matrix that forms a core matrix corresponding to a code rate of at least one threshold. Process 1300 can be performed from 1310 to 1320.

At 1320, process 1300 can involve processor 1010 encoding the material using a QC-LDPC code. Process 1300 can be performed from 1320 to 1330.

At 1330, process 1300 can involve processor 1010 transmitting the encoded material via transceiver 1030 (eg, to second device 1050).

In some embodiments, the code rate can be 0.89.

In some embodiments, the core matrix can include a plurality of rows and a plurality of columns of bits, and two or more of the plurality of rows can include a punctured row having a particular bit pattern.

In some embodiments, after any number of row permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination of the two), in a plurality of perforated rows A particular bit pattern may include one or a plurality of bits 0 in a plurality of punctured lines. Two examples of a particular pattern comprising one or a plurality of bit 0 after row permutation and/or column permutation are shown in part (A) of Figure 7. In some embodiments, the particular bit pattern in the punctured row can include an isosceles right triangle of bit 0, the right angle of the triangle corresponding to bit 0 at the upper left corner in the punctured row. An example of the bit 0 of such an isosceles right triangle is shown in part (B) of Fig. 7.

In some embodiments, the core matrix can include a parity matrix of a plurality of rows and a plurality of columns of bits. The core matrix may also include an information matrix of a plurality of rows and a plurality of columns of bits. The parity matrix may include a matrix having a Wi-Fi style. In addition to the punctured rows of the core matrix, more than one row of rows of the information matrix may include rows with high density bits 1 and no or only one bit 0. A row of high density bits can correspond to a Wi-Fi style column.

In some embodiments, the bits of the bottom column of the plurality of columns can include the first number of bits 1. The first number may be equal to the number of punched rows, or greater than the number of punched rows by 0, 1, 2, or 3 (eg, larger). In some embodiments, a portion of the first number of bits 1 in the bottom column may correspond to a perforated row and a rightmost column of the core matrix, wherein the rightmost row of the core matrix is in Wi-Fi On the right side of the style.

In some embodiments, the core matrix can include 5 columns of bits and 20 rows of bits. The degree of the variable node of 20 rows of bits may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], [ 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3], and [2, 2, 3, 3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. The degree of the check node of the five columns may include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13, 18, 3 ], [13, 11, 13, 18, 2], [13, 10, 14, 18, 2], [13, 10, 13, 19, 2], [14, 10, 13, 18, 1], [13, 11, 13, 18, 1], [13, 10, 14, 18, 1], [13, 11, 13, 19, 1], [13, 10, 13, 18, 2], and [ 13, 10, 13, 18, 1].

Figure 14 illustrates an exemplary process 1400 based on an embodiment of the present invention. Process 1400 may represent aspects of implementing the proposed concepts and aspects, and the proposed concepts and aspects may be described, for example, with respect to FIG. More specifically, process 1300 can represent aspects of the proposed concepts and aspects related to shift factor design. Process 1400 can include one or a plurality of blocks of blocks 1410, 1420, and 1430 and one or more of the operations, actions, or functions illustrated by sub-blocks 1412 and 1414. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 1400 can be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 1400 may be performed in the order illustrated in Figure 14, or in a different order. Process 1400 can be implemented by communication system 1000 and any variations thereof. For example, process 1400 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Process 1400 is described in the context of first device 1005 as follows, for purposes of illustration only and not limitation. Process 1400 can begin at block 1410.

At 1410, process 1400 can be a processor 1010 involving a first device 1005 that generates a QC-LDPC code. Process 1400 can be performed from 1410 to 1420.

At 1420, process 1400 can involve processor 1010 encoding the material using the QC-LDPC code. Process 1400 can be performed from 1420 to 1430.

At 1430, process 1400 can involve processor 1010 transmitting the encoded material via transceiver 1030 (eg, to second device 1050).

In generating the QC-LDPC code, process 1400 can involve processor 1010 executing a plurality of operations represented by sub-blocks 1412-1414.

At 1412, process 1400 can involve processor 1010 generating a corresponding shift value table for each of the first set of lifting factors. Process 1400 can be performed from 1412 to 1414.

At 1414, the process 1400 can involve the processor 1010 optimizing the first set of lifting factors to generate a second set of lifting factors.

The number of lifting factors of the first set may be greater than the number of lifting factors of the second set. The first lifting factor may share a corresponding shift value table of the second lifting factor, wherein the first lifting factor is located in the first set and not in the second set, and the second lifting factor is located in the first set and the second set. The value of the second boost factor may be less than the value of the first boost factor and closer to the first boost factor than the other boost factors in the first set.

Figure 24 illustrates an exemplary process 2400 for wireless communication in accordance with an embodiment of the present invention. Process 2400 may represent aspects of implementing the proposed concepts and aspects, which may be described, for example, with respect to some or all of Figures 1 - 10 and 15 (A) - Figure 23. More specifically, process 2400 can represent aspects of the proposed concepts and aspects associated with shift coefficient table design for QC-LDPC codes for small code block sizes in mobile communications. Process 2400 can include one or more of the operations, functions, and functions of blocks 2410 and 2420 and sub-blocks 24202, 24204, 24206, 24208, 24210, and 24212. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 2400 can be divided into additional blocks, merged into fewer blocks, or deleted. Moreover, the blocks/sub-blocks of process 2400 may be performed in the order illustrated in Figure 24, or in a different order. Process 2400 can be implemented by communication system 1000 and any variations thereof. For example, process 2400 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. For purposes of illustration only and not limitation, process 1400 is described in the context of first device 1005 as follows, but may equally be applied to device 1050. Process 2400 can begin at block 2410.

At 2410, process 2400 can involve the processor 1010 of the first device 1005 establishing a wireless communication link with at least one other device (eg, the second device 1050) via the transceiver 1030 of the device 1005. Process 2400 can be performed from 2410 to 2420.

At 2420, process 2400 can involve processor 1010 wirelessly communicating with other devices over a wireless communication link via transceiver 1030. In wireless communication with other devices, process 2400 may involve processor 1010 executing a plurality of operations represented by 24202, 24204, 24206, 24208, 24210, and 24212.

At 24202, process 2400 can involve processor 1010 selecting a first shift coefficient table from a plurality of shift coefficient tables. Process 2400 can be performed from 24202 to 24204.

At 24204, process 2400 can involve processor 1010 generating a QC-LDPC code using at least a portion of the first shift coefficient table and the base matrix. Process 2400 can be performed from 24204 to 24206.

At 24206, process 2400 can involve processor 1010 selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code. Process 2400 can be performed from 24206 to 24208.

At 24208, process 2400 can involve processor 1010 storing the selected codebook to memory associated with the processor. Process 2400 can be performed from 24208 to 24210.

At 24410, process 2400 can involve processor 1010 using the selected codebook encoded material to generate a plurality of modulation symbols for the data. Process 2400 can be performed from 24210 to 24212.

At 24212, the process 2400 can involve the processor 1010 controlling the transceiver 1030 to multiplex, convert, filter, amplify the modulation symbols, and radiate modulation symbols as electromagnetic waves through one or more of the first threads 1036 of the first device 1005 to communicate via the wireless communication link. The way to send the modulation symbols of the data to other devices.

In some embodiments, the first shift coefficient table may include a basic shift coefficient table arranged in 4 columns and 14 rows in the following form:

In some embodiments, the first shift coefficient table may include a shift coefficient table as shown in FIGS. 15A-15B.

In some embodiments, when selecting a first shift coefficient table from a plurality of shift coefficient tables, process 2400 can involve processor 1010 selecting a first smaller block size based on one or more rules. A shift coefficient table, wherein the one or more rules are related to either or both of a code block size of the material and a code rate of the material.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the process 2400 can involve the processor 1010 using the full portion and the base matrix of the first shift coefficient table. A QC-LDPC code is generated.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the process 2400 can involve the processor 1010 using a partial portion and a base matrix of the first shift coefficient table. A QC-LDPC code is generated.

In some embodiments, when selecting a first shift coefficient table from a plurality of shift coefficient tables, process 2400 can involve processor 1010 selecting a second shift coefficient table, the pair of values in the second shift coefficient table The modulo result of one or a plurality of lifting factors is the same as the modulo result in at least the first shift coefficient table.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the process 2400 can involve the processor 1010 using the full portion of the second shift coefficient table and the base matrix A QC-LDPC code is generated.

In some embodiments, when the QC-LDPC code is generated using at least a portion of the first shift coefficient table and the base matrix, the process 2400 can involve the processor 1010 using a partial portion and a base matrix of the second shift coefficient table. A QC-LDPC code is generated.

In some embodiments, when selecting a first shift coefficient table from a plurality of shift coefficient tables, the processor 2400 can involve the processor 1010 performing a plurality of operations. For example, processor 2400 can involve processor 1010 determining if the code block size is less than or equal to a threshold code block size. Moreover, process 2400 can involve processor 1010 determining if the code rate is less than or equal to a threshold code rate. Moreover, the process 2400 can involve the processor 1010 selecting a first shift coefficient table corresponding to the base chart BG1 in response to determining that the code block size is greater than a threshold code block size or in response to determining that the code rate is greater than a threshold code rate. Alternatively, process 2400 can involve processor 1010 selecting a first shift coefficient table corresponding to base chart BG2 in response to determining that the code block size is less than or equal to the threshold code block size or in response to determining that the code rate is less than or equal to the threshold code rate.

In some embodiments, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 2 (a=2) and the boost factor 256. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 9 (a = 9) and the boost factor 144. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 5 (a = 5) and the boost factor 160. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 11 (a = 11) and the boost factor 176. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 3 (a = 3) and the boost factor 192. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 13 (a = 13) and the boost factor 208. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 7 (a = 7) and the boost factor 224. Alternatively, the first shift coefficient table may include a shift coefficient table corresponding to BG2 having the original element 15 (a = 15) and the boost factor 240.

In some embodiments, each of the plurality of codebooks may correspond to a corresponding one of a plurality of HARQ threads, wherein the plurality of HARQ threads are different from each other.

In some implementations, when selecting a codebook from a plurality of codebooks, process 2400 can involve processor 1010 performing a plurality of operations. For example, process 2400 can involve processor 1010 executing a plurality of operations. For example, process 2400 can involve processor 1010 determining if the code block size of the material is less than a threshold code block size. Additionally, the process 2400 can involve the processor 1010 selecting a third codebook of the plurality of codebooks in response to the code block size of the data being less than the threshold code block size. Moreover, in response to the code block size of the data being no less than the threshold code block size, process 2400 can involve processor 1010 determining whether the initial code rate for transmitting the material is greater than a threshold code rate. Moreover, in response to the initial code rate not being greater than the threshold code rate, process 2400 can involve processor 1010 selecting a second codebook of the plurality of codebooks. Moreover, in response to the initial code rate being greater than the threshold code rate, process 2400 can involve processor 1010 selecting a first codebook of the plurality of codebooks. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

In some implementations, when selecting a codebook from a plurality of codebooks, process 2400 can involve processor 1010 performing a plurality of operations. For example, process 2400 can involve processor 1010 determining a code block size of the material. Moreover, the process 2400 can involve the processor 1010 selecting a codebook by: (1) selecting a first codebook of the plurality of codebooks in response to determining that the code block size is greater than the first threshold codeblock size; (2) responding to the determining The code block size is greater than the second threshold code block size, and the second codebook of the plurality of codebooks is selected; (3) selecting the third code of the plurality of codebooks in response to determining that the code block size is greater than the third threshold code block size this. The first threshold code block size may be greater than the second threshold code block size. The second threshold code block size may be greater than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook, and the size of the second codebook may be larger than the size of the third codebook.

Attach Say Bright

The subject matter described herein sometimes shows different elements that are included within or connected to other different elements. It is to be understood that the architecture so depicted is merely an example, and that many other architectures can be implemented to implement the same functionality. In a conceptual sense, any component arrangement that achieves the same function is effectively "associated" to enable the desired function. Hence, any two components herein combined to achieve a particular function can be seen as "associated" with each other, such that the desired functionality is implemented, regardless of architecture or intermediate components. Likewise, any two elements so associated are also considered to be "operably connected" or "operably coupled" to each other to achieve the desired function, and any two elements that can be so associated are also considered "Operably coupled" to achieve the desired functionality. Specific examples of operably coupled include, but are not limited to, physically configurable and/or physically interacting elements and/or wirelessly interactable and/or wirelessly interacting elements and/or logically interacting and/or logically Interactive components.

In addition, with regard to the use of any plural and/or singular terms herein, those skilled in the art can change from plural to singular and/or from singular to plural, depending on the context and/or application. For the sake of clarity, various singular/plural permutations can be explicitly set forth herein.

In addition, those skilled in the art will understand that, in general, the terms used herein, particularly the terms used in the scope of the appended claims, such as the subject matter of the appended claims, are generally intended to be "open" Terms, for example, the term "comprising" is to be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least" and the term "comprising" should be interpreted as "including but not limited to", and so on. Those having ordinary skill in the art should further understand that if a certain number of patent applications are required to be recited, this intention should be clearly stated in the scope of the patent application. Without this description, there is no such intention. For example, as an aid to understanding, the scope of the following appended claims may include the use of "at least one" and "one or a plurality of" However, the use of these terms should not be construed as a limitation of the scope of the claims, which is incorporated by the indefinite article "a" or "an". Such statements, even when the same claims are intended to be inclusive of the singular terms "a" or "an" or "an" or "an" or "an", such as "a" or "an" , should be interpreted to mean “at least one” or “one or plural”; the same applies to the use of the limited articles used to introduce the scope of the patent application. In addition, even if the specific number recited in the scope of the patent application is explicitly described, those skilled in the art will recognize that such a description should be construed as indicating at least the number recited, for example, only "two records" There are no other modifiers, referring to at least two records, or two or more. Further, in the case of using a convention similar to at least one of "A, B, and C", etc., such a configuration is generally intended to have a meaning in the art that a person of ordinary skill will understand the convention, such as "having A, B. The system of at least one of C and C will include, but is not limited to, only A, only B, only C, A and B together, A and C together, B and C together, and/or A, System with B and C, etc. In those cases where a convention similar to at least one of "A, B or C" is used, such a structure is generally intended to have a general knowledge in a certain sense that the person skilled in the art will understand the convention, for example, "having A," A system of at least one of B or C" will include, but is not limited to, systems having only A, only B, only C, A and B together, systems with A and C, systems with B and C together, And / or A, B and C together. It will be further understood by those of ordinary skill in the art that, in fact, in the embodiments, the scope of the claims or the drawings, any of the separate words and/or terms that represent two or more alternative conditions should be understood to include consideration of the terms. One possibility, the possibility of any one term or the possibility of two terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

It is to be understood that the various embodiments of the present invention have been described herein, and various modifications may be made without departing from the scope and spirit of the invention. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are determined by the scope of the appended claims.

100‧‧‧Basic Matrix

The first part of the I1‧‧‧ information matrix

Part II of the I2‧‧ Information Matrix

Part III of the I3‧‧‧ Information Matrix

200‧‧‧ Process

210,220,230,240,250‧‧‧

300‧‧ ‧ quasi-orthogonal layer design

400‧‧‧Mixed Orthogonal Layer Design

500‧‧‧QC-LDPC

600‧‧‧core matrix

700‧‧‧ core basic matrix

800‧‧‧ core basic matrix

900‧‧‧Shift coefficient design

1000‧‧‧Communication system

1005‧‧‧ first device

1050‧‧‧second device

1036, 1086‧‧‧ antenna

1030, 1080‧‧‧ transceiver

1032, 1082‧‧‧ Transmitter

1034, 1084‧‧‧ Receiver

1010, 1060‧‧‧ processor

1012, 1062‧‧ ‧ encoder

1014, 1064‧‧‧ decoder

1016, 1066‧‧‧ memory

1020, 1070‧‧‧ memory

1022, 1072‧‧ directive

1024, 1074‧‧‧Information

1040‧‧‧Communication link

1100‧‧‧ Process

1110, 1120, 1130, 1140‧‧‧

1200‧‧‧ Process

1210, 1220, 1230‧‧ ‧ blocks

1300‧‧‧ Process

1310, 1320, 1330‧‧‧

1400‧‧‧ Process

1410, 1420, 1430, 1412, 1414‧‧ ‧ blocks

1500‧‧‧Shift coefficient table

1600‧‧‧Shift coefficient table

1700‧‧‧Shift coefficient table

1800‧‧‧Shift coefficient table

1900‧‧‧Shift coefficient table

2000‧‧‧Shift coefficient table

2100‧‧‧Shift coefficient table

2200‧‧‧Shift coefficient table

2300‧‧‧ Process

2310, 2320, 2330, 2340‧‧‧

2400‧‧‧ Process

2410, 2420‧‧‧

24202, 24204, 24206, 24208, 24210, 24212‧‧ ‧ sub-blocks

The drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present application and, together with It is understood that the drawings are not necessarily to scale unless the 1 is a schematic diagram of an exemplary multi-codebook embedded LDPC code design based on an embodiment of the present application; FIG. 2 is a schematic diagram of an example logic flow related to a multi-codebook embedded LDPC code according to an embodiment of the present application; 3 is a schematic diagram of an exemplary quasi-row orthogonal layer design based on an embodiment of the present application; FIG. 4 is a schematic diagram of an exemplary hybrid orthogonal layer design based on an embodiment of the present application; 5 is a schematic diagram of an exemplary QC-LDPC code supporting extremely low code rate based on an embodiment of the present application; FIG. 6 is a schematic diagram of an exemplary kernel matrix design based on an embodiment of the present application; A schematic diagram of an exemplary concept of a core basic matrix of an embodiment of the present application; FIG. 8 is a schematic diagram of an exemplary concept of a core basic matrix based on another embodiment of the present application; FIG. 9 is an exemplary shift based on an embodiment of the present application Schematic diagram of a bit coefficient design; FIG. 10 is a block diagram of an exemplary communication system based on an embodiment of the present application; FIG. 11 is a flow of an exemplary process based on an embodiment of the present application 12 is a flowchart of an exemplary process based on another embodiment of the present application; FIG. 13 is a flowchart of an exemplary process based on another embodiment of the present application; FIG. 14 is another embodiment based on the present application. Flowchart of an exemplary process of the manner; each of the 15th (A) and 15th (B) figures is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; 16(A) and Each of the 16(B) diagrams is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; each of the 17th (A) and 17th (B) diagrams is a partial example based on an embodiment of the present application. Schematic diagram of a sexual shift coefficient table; each of the 18th (A) and 18th (B) graphs is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; 19th (A) and 19th (B) Each of the figures is a schematic diagram of a partial exemplary shift coefficient table based on an embodiment of the present application; each of the 20th (A) and 20th (B) drawings is based on a partial exemplary embodiment of the present application Schematic diagram of the shift coefficient table; each of the 21st (A) and 21 (B) graphs is based on the implementation of the present application A schematic diagram of a portion of an exemplary shift coefficient table of the formula; each of the 22 (A) and 22 (B) graphs is a schematic diagram of a portion of an exemplary shift coefficient table based on an embodiment of the present application; A schematic diagram of an exemplary logic flow for selecting a shift coefficient table in an embodiment of the present application; FIG. 24 is a flow chart of an exemplary process based on another embodiment of the present application.

Claims (20)

A method of wireless communication, comprising: a processor of a device establishing a wireless communication link with at least one other device via a transceiver of the device; and the processor wirelessly communicating with the other device via the wireless communication link by : selecting a first shift coefficient table from a plurality of shift coefficient tables; generating a quasi-loop low density parity check (QC-LDPC) code using at least a portion of the first shift coefficient table and a base matrix; Selecting a codebook embedded in a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook to a memory associated with the processor; encoding the data using the selected codebook to generate a Generating a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify the modulation symbols, and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus for transmission via the wireless Transmitting, by the communication link, a modulation symbol of the data to the other device, wherein the selecting the first shift coefficient table from the plurality of shift coefficient tables includes The first shift coefficient table for a relatively small code block size is selected according to one or a plurality of rules associated with either or both of the code block size of the material and the code rate of the material. The method of claim 1, wherein the first shift coefficient table comprises: a basic shift coefficient table arranged in 4 columns and 14 rows in the following pattern: . The method of claim 1, wherein the first shift coefficient table comprises a shift coefficient table as shown in FIGS. 15A and 15B. The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 2 having the original element 2 (a = 2) and the boost factor 256. The method of claim 1, wherein the first shift coefficient table comprises a shift coefficient table corresponding to the basic chart 2 having the original element 9 (a = 9) and the boost factor 144. The method of claim 1, wherein the first shift coefficient table comprises a shift coefficient table corresponding to the basic chart 2 having the original element 5 (a = 5) and the boost factor 160. The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 2 having the original element 11 (a = 11) and the boost factor 176. The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 2 having the original element 3 (a = 3) and the boost factor 192. The method of claim 1, wherein the first shift coefficient table comprises a shift coefficient table corresponding to the basic chart 2 having the original element 13 (a = 13) and the boost factor 208. The method of claim 1, wherein the first shift coefficient table comprises a shift coefficient table corresponding to the basic chart 2 having the original element 7 (a = 7) and the boost factor 224. The method of claim 1, wherein the first shift coefficient table includes a shift coefficient table corresponding to the basic chart 2 having the original element 15 (a = 15) and the boost factor 240. The method of claim 1, wherein the generating the QC-LDPC code using at least a portion of the first shift coefficient table and the basic matrix comprises: using all of the first shift coefficient table And the basic matrix generates the QC-LDPC code. The method of claim 1, wherein the generating the QC-LDPC code using at least a portion of the first shift coefficient table and the base matrix comprises: using a portion of the first shift coefficient table And the basic matrix generates the QC-LDPC code. The method of claim 1, wherein the selecting the first shift coefficient table from the plurality of shift coefficient tables comprises: selecting a second shift coefficient table, wherein the second shift coefficient table The modulo result of the value for one or a plurality of lifting factors is the same as the modulo result of the at least first shift coefficient table. The method of claim 14, wherein the generating the QC-LDPC code using at least a portion of the first shift coefficient table and the basic matrix comprises: using all of the second shift coefficient table The basic matrix is generated to generate the QC-LDPC code. The method of claim 14, wherein the generating the QC-LDPC code using at least a portion of the first shift coefficient table and the base matrix comprises: using a portion of the second shift coefficient table and The basic matrix generates the QC-LDPC code. The method of claim 1, wherein the selecting the first shift coefficient table from the plurality of shift coefficient tables comprises: determining whether the code block size is less than or equal to a threshold code block size; and determining the Whether the code rate is less than or equal to the threshold code rate. The method of claim 17, wherein selecting the first shift coefficient table from the plurality of shift coefficient tables further comprises: responsive to determining that the code block size is greater than a threshold code block size or in response to determining The code rate is greater than the threshold code rate, and the first shift coefficient table corresponding to the basic chart 1 is selected. The method of claim 17, wherein the selecting the first shift coefficient table from the plurality of shift coefficient tables further comprises: responsive to determining that the code block size is less than or equal to the threshold code block size or In response to determining that the code rate is less than or equal to the threshold code rate, the first shift coefficient table corresponding to the basic chart 2 is selected. The method of claim 1, wherein each of the plurality of codebooks corresponds to a corresponding HARQ thread in a plurality of hybrid automatic repeat request (HARQ) threads, wherein the complex number The HARQ threads are different from each other.