TW201904014A - Semiconductor device, laminated body, method of manufacturing semiconductor device, and method of manufacturing laminated body - Google Patents

Abstract

Provided are: a semiconductor device and a laminate having good electrical insulation properties, high operational reliability, and high conductivity even when an anisotropic conductive member has a crack; and a manufacturing method of the semiconductor device, and a manufacturing method of the laminate. The semiconductor device has: an anisotropic conductive member that has an insulating base material, and a plurality of conductive paths which are provided so as to penetrate the insulating base material in the thickness direction and to be electrically insulated from one another; and at least two connection members each provided with electrodes. At least one of said at least two connection members is a semiconductor element. The anisotropic conductive member has an electrode connection region connected to the electrodes, and an electrode non-connection region not connected to the electrodes. Said at least two connection members are electrically connected by means of the anisotropic conductive member. The average value of a total crack length per unit area is 1 [mu]m/mm2 or lower in the electrode connection region.

Description

Semiconductor element, laminate and method for manufacturing semiconductor element and method for manufacturing laminate

The present invention relates to a semiconductor device, a laminated body, a method for manufacturing a semiconductor device, and a method for manufacturing a laminated body that are electrically connected using at least two connected members using cracked anisotropic conductive members, and particularly relates to an anisotropy A semiconductor device, a laminate, a method of manufacturing a semiconductor device, and a method of manufacturing a laminate, in which the amount of cracking of a conductive member is specified.

In recent years, the metal-filled microstructure system formed by filling metal in the micropores provided in the insulating base material has also attracted attention in the nanotechnology. For example, its use as an anisotropic conductive member is expected. The anisotropic conductive member is inserted between the electronic component such as a semiconductor element and the circuit board, and the electrical connection between the electronic component and the circuit board is obtained only by pressing, so it is used as the electrical connection of the electronic component such as the semiconductor element It is widely used for components and connectors for inspection when performing functional inspections. In particular, the miniaturization of electronic components such as semiconductor devices is remarkable, and the method of directly connecting a wiring board, flip chip bonding, and thermocompression bonding is carried out as in the conventional wire bonding. Etc., the stability of the connection cannot be fully guaranteed. Therefore, as an electrical connection member, an anisotropic conductive member has attracted attention.

Patent Document 1 describes a method of manufacturing an anisotropic conductive member capable of suppressing damage to an insulating base material. In Patent Document 1, an anisotropic conductive member having a plurality of conductive vias is processed to relax residual stress, and the plurality of conductive vias are formed in a plurality of micropores in an insulating base material composed of an anodized film The conductive member is filled in. Patent Document 2 describes a method of manufacturing a semiconductor package including a process of mounting a semiconductor element on at least one surface of a multilayer substrate. The multilayer substrate of Patent Document 2 includes an anisotropic conductive member, an insulating base material and a plurality of conductive paths, the insulating base material is an anodized film of an aluminum substrate, and a through hole is provided along the thickness direction Each conductive path includes a conductive material filled in the through hole and penetrates the insulating base material in the thickness direction in a state of being insulated from each other; a heat conductive layer having a heat conductive portion provided on at least one surface of the anisotropic conductive member; and a heat radiation portion, It protrudes from the insulating base material and contains a conductive material. Patent Document 2 describes the following: when mounting a semiconductor element on a multilayer substrate, mounting with heating is accompanied. From the viewpoint of suppressing the cracks generated in the anodized film due to the difference in thermal expansion coefficient between the aluminum substrate and the anodized film, before reaching the maximum temperature, take 5 seconds to 10 minutes at a desired temperature. More preferably, the heat treatment method is 10 seconds to 5 minutes, and particularly preferably 20 seconds to 3 minutes.

In addition, Patent Document 3 describes a circuit board connection structure for the purpose of enabling stable electrical connection and no damage during attachment and detachment. The circuit board connection structure system of Patent Document 3 supports a rigid circuit board having a first electrode, an anisotropic conductive member, and a flexible circuit board having a second electrode as a land formed on the circuit board to support The board is arranged in direct contact with at least a part of another plane of the flexible circuit board that does not face the rigid circuit board. The pressing member for pressing the anisotropic conductive member to the rigid circuit board and the flexible circuit board via the support plate is used for connection. Patent Document 4 describes a multilayer wiring board formed by laminating an anisotropic conductive member and a wiring board, the anisotropic conductive member including: an insulating base material, including an inorganic material; A plurality of conductive paths of the conductive member penetrate through the thickness direction of the insulating base material and are provided in a mutually insulated state; and a bonding layer is provided on the surface of the insulating base material, and each conductive path has a secondary insulating material The protruding part of the surface protruding, the wiring board has a substrate and one or more electrodes formed on the substrate. In the multilayer wiring board of Patent Document 4, among the plurality of conductive paths, the conductive paths that are in contact with the electrodes are deformed so that adjacent conductive paths are in contact with each other. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2015/12234 [Patent Document 2] Japanese Patent Laid-Open No. 2014-82447 [Patent Document 3] Japanese Patent Laid-Open No. 2012-7822 [Patent Document 4] International Publication No. 2016/98865

Although the above-mentioned Patent Document 1 describes the number of cracks, it is not in a state of being bonded to a semiconductor wafer. In addition, Patent Document 1 does not show a specific number of cracks. In Patent Document 2, as described above, heat treatment is performed from the viewpoint of suppressing the occurrence of cracks, but the specific number of cracks is not shown.

When joining an anisotropic conductive member to a semiconductor wafer or the like, it is necessary to process the anisotropic conductive member or to transport the anisotropic conductive member. Cracks may occur due to processing of the anisotropic conductive member and transportation of the anisotropic conductive member, and there may be cracks when the anisotropic conductive member and the semiconductor wafer are bonded. In Patent Document 1 and Patent Document 2, regarding the fact that cracks actually exist in the anisotropic conductive member, the conductivity and the like are not evaluated. In addition, in the circuit board connection structure using the anisotropic conductive member of Patent Document 3 and the multilayer wiring board using the anisotropic conductive member of Patent Document 4, there are also processes and processes due to the anisotropic conductive member. There may be cracks in the transport of the anisotropic conductive member, and there may be cracks in the joined state. However, similar to Patent Document 1 and Patent Document 2, the actual situation in the anisotropic conductive member is There were cracks, and no evaluation of conductivity or the like was made.

The object of the present invention is to solve the problems based on the aforementioned prior art, and to provide a semiconductor device and a laminate having good conduction, good electrical insulation, and high operational reliability even if cracks exist in the anisotropic conductive member And a method of manufacturing a semiconductor device and a method of manufacturing a laminate.

In order to achieve the above object, the present invention provides a semiconductor device having an anisotropic conductive member, having an insulating substrate and a plurality of conductive vias, the plurality of conductive vias along the thickness direction of the insulating substrate Penetrating and provided in a state of being electrically insulated from each other; and at least two connected members each having an electrode, and at least one of the at least two connected members is a semiconductor element. In this semiconductor device, the anisotropic conductive member has The electrode connection area connected to the electrode and the electrode non-connection area not connected to the electrode, at least two connected members are electrically connected by an anisotropic conductive member. In the electrode connection area connected to the electrode, per unit area The average value of the total crack length is 1 μm/mm ² or less.

In addition, in the electrode non-connection region not connected to the electrode, the average value of the total crack length per unit area is preferably 0.01 μm/mm ² or more.

The average value of the total crack length per unit area of the electrode connection region connected to the electrode is preferably smaller than the average value of the total crack length per unit area of the electrode non-connection region not connected to the electrode. In addition, it is preferable that the surface of the connected member on which the electrode is provided has an insulating layer, and the electrode protrudes from the surface of the insulating layer. Furthermore, at least two connected members electrically connected by an anisotropic conductive member include: a connected member having an electrode having a convex portion; and a quilt having an electrode having a concave portion partially recessed corresponding to the convex portion The connecting member is preferred. In addition, the surface roughness of the surface of the connected member having electrodes is preferably 10 nm or less.

Furthermore, the present invention provides a laminate having an anisotropic conductive member, having an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating in the thickness direction of the insulating base material, and It is provided in a state of being electrically insulated from each other; and at least two connected members, each having an electrode, in the laminate, at least one of the connecting members is a semiconductor element, and the anisotropic conductive member has an electrode connecting region connected to the electrode At least two connected members are electrically connected by an anisotropic conductive member to an electrode non-connected region that is not connected to the electrode. In the electrode connected region connected to the electrode, the average value of the total crack length per unit area It is 1 μm/mm ² or less.

In the electrode non-connection region not connected to the electrode, the average value of the total crack length per unit area is preferably 0.01 μm/mm ² or more. The average value of the total crack length per unit area of the electrode connection region connected to the electrode is preferably smaller than the average value of the total crack length per unit area of the electrode non-connection region not connected to the electrode. It is preferable that the surface of the connected member on which the electrode is provided has an insulating layer, and the electrode protrudes from the surface of the insulating layer. The at least two connected members electrically connected by the anisotropic conductive member include: a connected member having an electrode having a convex portion; and a connected member having an electrode having a concave portion partially recessed corresponding to the convex portion Is better. The surface roughness of the surface of the connected member having electrodes is preferably 10 nm or less.

The present invention provides a method of manufacturing a semiconductor device having an anisotropic conductive member, having an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating in the thickness direction of the insulating base material, And at least two connected members, each having electrodes, and at least one of the at least two connected members is a semiconductor element. The method of manufacturing the semiconductor device has the following process: A state in which an anisotropic conductive member is arranged between the two connected members, at least two connected members are electrically connected by the anisotropic conductive member, and the surface of the connected member on which the electrode is provided has insulation Layer, the electrode protrudes with respect to the surface of the insulating layer. The at least two connected members electrically connected by the anisotropic conductive member include: a connected member having an electrode having a convex portion; and a connected member having an electrode having a concave portion partially recessed corresponding to the convex portion Is better.

In addition, the present invention provides a method for manufacturing a laminate including: an anisotropic conductive member having an insulating base material and a plurality of conductive paths, the plurality of conductive paths being along the thickness direction of the insulating base material Penetrated and provided in a state of being electrically insulated from each other; and at least two connected members, each having an electrode, at least one of the aforementioned connecting members is a semiconductor element, and the method of manufacturing the laminate has the following process: in at least two A state where an anisotropic conductive member is arranged between the connected members, at least two connected members are electrically connected by the anisotropic conductive member, and an insulating layer is provided on the surface of the connected member where the electrode is provided, the electrode It protrudes relative to the surface of the insulating layer. The at least two connected members electrically connected by the anisotropic conductive member include: a connected member having an electrode having a convex portion; and a connected member having an electrode having a concave portion partially recessed corresponding to the convex portion Is better. [Effect of the invention]

According to the present invention, it is possible to obtain a semiconductor device having good conduction, good electrical insulation, and high operational reliability. According to the present invention, it is possible to obtain a laminate having good conduction, good electrical insulation, and high operational reliability.

Hereinafter, based on the preferred embodiments shown in the drawings, the semiconductor device, the laminate, the method for manufacturing the semiconductor device, and the method for manufacturing the laminate will be described in detail. In addition, the drawings described below are examples for explaining the present invention, and the present invention is not limited to the drawings shown below. In addition, "~" which shows the numerical range below includes the numerical value described on both sides. For example, the range where ε is the numerical value α to the numerical value β is the range including the numerical value α and the numerical value β, and expressed in mathematical notation as α≦ε≦β. The angle and temperature are included in the error range generally allowed in the corresponding technical field unless otherwise specified. In addition, "same" includes the error range generally allowed in the corresponding technical field. In addition, "average" etc. include the error range generally allowed in the corresponding technical field.

The laminate of the present invention includes an anisotropic conductive member and at least two connected members each provided with an electrode, and at least one of the at least two connected members is a semiconductor element. At least two connected members are electrically connected by an anisotropic conductive member. That is, at least two non-connecting members are electrically connected by the anisotropic conductive member. Here, the connected members are semiconductor elements, circuit elements, sensor elements, etc. The semiconductor elements include passive elements and active elements. The semiconductor element is also called a semiconductor wafer. In addition, the connected member also includes an acceptor such as an interposer for signals. The semiconductor device of the present invention is a device having the layered body of the present invention as a part or all of the configuration, for example, one device is completed, and a single device performs a specific function. The anisotropic conductive member will be described in detail later. The anisotropic conductive member has an insulating base material and a plurality of conductive paths that penetrate through the thickness direction of the insulating base material and are provided in a state of being electrically insulated from each other. In addition, the anisotropic conductive member has an electrode connection region connected to the electrode and an electrode non-connection region not connected to the electrode.

FIG. 1 is a schematic diagram showing a first example of a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 shown in FIG. 1 is formed by, for example, stacking and bonding a semiconductor wafer 12, an anisotropic conductive member 20, and a semiconductor wafer 14 in the stacking direction Ds. The semiconductor wafer 12 and the semiconductor wafer 14 are electrically conductive by anisotropy Sex member 20 to be electrically connected. In addition, even if it has the same configuration as the semiconductor device 10 shown in FIG. 1, it is handled as the laminate 11 when it is assembled and used in a device as described above. Hereinafter, the semiconductor device 10 will be described. In addition to the semiconductor device 10 that functions as an optical sensor shown in FIG. 15, it can be used as the laminate 11. The layered body 11 exerts the same effect as the semiconductor device 10.

2 is a plan view showing an example of the configuration of an anisotropic conductive member used in a semiconductor device according to an embodiment of the present invention, and FIG. 3 is an anisotropic conductivity used in a semiconductor device according to an embodiment of the present invention. A schematic cross-sectional view of an example of the structure of a member. FIG. 3 is a cross-sectional view taken along line IB-IB of FIG. 2. 4 is a schematic cross-sectional view showing an example of the structure of an anisotropic conductive material. The anisotropic conductive member 20 shown in FIGS. 2 and 3 is a member provided with an insulating base material 40 made of an inorganic material and a plurality of conductive paths 42 containing a conductive material. The thickness direction Z of the base material 40 (see FIG. 3) penetrates and is provided in a state of being electrically insulated from each other. The anisotropic conductive member 20 further includes a resin layer 44 provided on the surfaces 40 a and 40 b of the insulating base material 40. The insulating base material 40 is composed of, for example, an anodized film of aluminum. The via 42 is formed by filling the inside of the through via 41 penetrating in the thickness direction of the insulating base material 40 with metal. For example, the inside of the micropores formed in the anodized film of aluminum is filled with metal to constitute the via 42. Here, the "state of mutual electrical insulation" refers to a state where each conduction path existing inside the insulating base material is inside the insulating base material, and the conduction between the conduction paths is sufficiently low from each other. In the anisotropic conductive member 20, the conductive paths 42 are electrically insulated from each other, the conductivity is sufficiently low in the direction x orthogonal to the thickness direction Z (see FIG. 3) of the insulating base material 40, and has conductivity in the thickness direction Z Sex. In this way, the anisotropic conductive member 20 is a member exhibiting anisotropic conductivity. The anisotropic conductive member 20 is arranged so that the thickness direction Z coincides with the stacking direction Ds of the semiconductor device 10.

As shown in FIGS. 2 and 3, the conductive paths 42 are provided through the insulating base material 40 in the thickness direction Z while being electrically insulated from each other. In addition, the symbol Z1 represents the direction from the back surface to the front surface of FIG. 2, and the symbol Z2 represents the direction from the front surface to the back surface of FIG. 2. In addition, as shown in FIG. 3, the via 42 may have a protruding portion 42 a and a protruding portion 42 b that protrude from the surfaces 40 a and 40 b of the insulating base material 40. The anisotropic conductive member 20 may further include a resin layer 44 provided on the front surface 40 a and the back surface 40 b of the insulating base material 40. The resin layer 44 is one that has adhesiveness and imparts adhesion. The length of the protrusion 42a and the protrusion 42b is preferably 6 nm or more, and more preferably 30 nm to 500 nm.

In addition, FIGS. 3 and 4 show that the insulating substrate 40 has resin layers 44 on the surfaces 40a and 40b, but it is not limited to this, and may have resin on at least one surface of the insulating substrate 40 The composition of layer 44. Similarly, the via 42 of FIGS. 3 and 4 has protruding portions 42a and protruding portions 42b at both ends, but it is not limited to this, and may be at least one side of the insulating base material 40 having the resin layer 44 The surface has a protruding part.

The thickness h of the anisotropic conductive member 20 shown in FIGS. 3 and 4 is, for example, 30 μm or less. In addition, the TTV (Total Thickness Variation) of the anisotropic conductive member 20 is preferably 10 μm or less. Here, the thickness h of the anisotropic conductive member 20 is observed by the field emission scanning electron microscope at a magnification of 200,000 times to obtain the outline shape of the anisotropic conductive member 20, The average value obtained by measuring 10 points for the area corresponding to the thickness h. In addition, in the TTV (Total Thickness Variation) of the anisotropic conductive member 20, the anisotropic conductive member 20 and the support 46 are cut by dicing, and the anisotropic conductive member 20 is observed The value of the cross-sectional shape.

As shown in FIG. 4, the anisotropic conductive member 20 is provided on the support 46 for transfer, transportation, transportation, storage, and the like. An adhesive member 47 is provided between the support 46 and the anisotropic conductive member 20. The support 46 and the anisotropic conductive member 20 are detachably adhered by the adhesive member 47. As described above, the anisotropic conductive member 20 is provided on the support 46 via the adhesive member 47 and is referred to as an anisotropic conductive material 50. The support 46 supports the anisotropic conductive member 20 and is composed of, for example, a silicon substrate. As the support 46, in addition to a silicon substrate, for example, a ceramic substrate such as SiN and aluminum oxide (Al ₂ O ₃ ), a compound semiconductor substrate such as SiC and GaN, a sapphire substrate, a glass substrate, a fiber-reinforced plastic substrate, a resin substrate, and a metal Substrate. Fiber-reinforced plastic substrates also include FR-4 (Flame Retardant Type 4: 4 type flame retardant) substrates as printed wiring boards.

In addition, as the support 46, those that are flexible and transparent can be used. Examples of the flexible and transparent support 46 include PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), Plastic films such as PE (polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride and TAC (triethyl acetyl cellulose). Here, the transparency means that the transmittance of the light of the wavelength used in the alignment is 80% or more. Therefore, the transmittance may be low in the entire visible light region with a wavelength of 400 to 800 nm, but the transmittance is preferably 80% or more in the entire visible light region with a wavelength of 400 to 800 nm. The transmittance is measured by a spectrophotometer.

The adhesive member 47 is preferably formed by laminating the supporting layer 48 and the adhesive layer 49. The adhesive layer 49 is in contact with the anisotropic conductive member 20, and the support 46 is separated from the anisotropic conductive member 20 using the adhesive member 47 as a starting point. In the anisotropic conductive material 50, for example, by heating to a predetermined temperature, the adhesive force of the adhesive layer 49 becomes weak, and the support 46 is removed from the anisotropic conductive member 20. The adhesive layer 49 is configured to be provided on the anisotropic conductive member 20 side of the support layer 48, but it is not limited to this, and may be provided on the support body 46 side of the support layer 48. For the adhesive layer 49, for example, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation and Somatac (registered trademark) manufactured by Somar Corporation can be used.

The adhesion member 47 is preferably, for example, one in which the adhesion force is reduced by heat or light, and is preferably one-fifth or less of the original adhesion force. The above REVALPHA (registered trademark) manufactured by Nitto Denko Corporation and Somatac (registered trademark) manufactured by Somar Corporation are equivalent to one-fifth or less of the original adhesive strength due to heat. In addition to the above, there is a base-type thermal peeling tape NWS series manufactured by Nitto Denko Corporation as a bonding force that becomes one-fifth or less of the original bonding force due to heat. Examples of those whose adhesion strength is less than 1/5 of the original adhesion strength due to light include UC-228W-110 (tape name) manufactured by Furukawa Electric Co., Ltd. and HUV-D1000 series manufactured by MYTECH Inc. . In the adhesive member 47, when the adhesive layer 49 is formed on both sides of the support layer 48, the adhesive force of the adhesive layer 49 on at least one side is preferably reduced by heat or light, and then becomes the original adhesive force Less than 1 in 5 is preferred.

In the anisotropic conductive material 50, when floating occurs between the adhesive member 47 and the anisotropic conductive member 20, cracks are likely to occur in the floating portion, so the smaller the floating area The better. Therefore, it is preferable that the area where floating occurs is 5% or less of the area of the anisotropic conductive member 20. In addition, when floating occurs between the adhesive member 47 and the support 46, cracks are likely to occur in the floating portion, so the smaller the floating area, the better. Therefore, it is preferable that the area where the floating occurs is 5% or less of the area of the adhesive member 47. In addition, if the entire surface is measured with a spectroscopic interference wafer thickness meter, flat data can be obtained without floating, but if there is floating, data corresponding to the thickness of the floating portion will be obtained. For example, the spectro-interferometric wafer thickness gauge uses the SI-F80R series manufactured by KEYENCE. With this device, it is possible to perform two-dimensional measurement, so it is possible to calculate the area where floating has occurred. In this method, both the floating between the adhesive member 47 and the anisotropic conductive member 20 and the floating between the adhesive member 47 and the support 46 can be measured. Also, for example, the area of the anisotropic conductive member 20 is 90% to 99% or less of the area of the adhesive member 47.

In the anisotropic conductive material 50, for example, the adhesion process of the adhesion member 47 and the anisotropic conductive member 20 is performed in an environment where the cleanliness is higher than the 1000 level specified in the US Federal Standard. With this, it is possible to carry out the attachment in an environment where the number of foreign objects is small, and it is possible to prevent foreign materials from being mixed into the bonding interface between the adhesive member 47 and the anisotropic conductive member 20. In addition, the adhesion process of the adhesive member 47 and the anisotropic conductive member 20 may be performed under a reduced pressure environment. By performing the attaching process under a reduced-pressure environment, the attaching can be performed in an environment where the number of foreign materials is small, and foreign materials can be prevented from being mixed into the bonding interface of the adhesive member 47 and the anisotropic conductive member 20. In addition, for example, the attaching process of the adhesive member 47 and the support 46 may be performed in an environment with a cleanliness level higher than Class 1000 specified in the US Federal Standard. With this, it is possible to carry out the attachment in an environment where the number of foreign materials is small, and it is possible to prevent foreign materials from being mixed into the bonding interface between the adhesive member 47 and the support 46. In addition, the adhesion process of the adhesive member 47 and the support 46 may be performed under a reduced pressure environment. By performing the attaching process under a reduced-pressure environment, the attaching can be performed in an environment where the number of foreign materials is small, and foreign materials can be prevented from being mixed into the bonding interface of the adhesive member 47 and the support 46.

As shown in FIG. 2, the anisotropic conductive member 20 may have cracks 22 in use. Cracks 22 are generated in the insulating base material 40 of the anisotropic conductive member 20. The crack 22 is sometimes generated to cross the guide path 42. Specifically, there are cracks 22 shown in FIGS. 5 and 6. The anisotropic conductive member 20 has an electrode connection region 24 (see FIG. 7) connected to the electrode and an electrode non-connection region 26 (see FIG. 7) not connected to the electrode. The average crack length per unit area of the anisotropic conductive member 20 in the electrode connection region 24 (see FIG. 7) connected to the electrode is 1 μm/mm ² or less. In addition, the anisotropic conductive member 20 preferably has an average crack length per unit area of 0.01 μm/mm ² or more in the electrode non-connection region 26 (see FIG. 7) that is not connected to the electrode. Electrodes refer to electrodes such as semiconductor wafers and inserts.

The average value of the total crack length per unit area is the value in the state of the semiconductor device 10. The method of measuring the average value of the total crack length per unit area will be described later. In addition, cracks will be described later.

In the anisotropic conductive member 20, as described above, if the average value of the total crack length per unit area in the electrode connection region 24 (see FIG. 7) connected to the electrode is 1 μm/mm ² or less, it is possible A semiconductor device with good conduction, good electrical insulation, and high operational reliability is obtained. In addition, it is preferable that there is no crack in the electrode connection region 24 (see FIG. 7), so as the lower limit of the average value of the total crack length per unit area in the electrode connection region 24 (see FIG. 7), close to zero is Preferably, ideally zero.

In addition, in the anisotropic conductive member 20, as described above, the average value of the total crack length per unit area in the electrode non-connection region 26 (see FIG. 7) that is not connected to the electrode is 0.01 μm/mm ² or more, a semiconductor device with good conduction, good electrical insulation, and high operational reliability can also be obtained. In addition, from the viewpoint of preventing the anisotropic conductive member from falling off, overlapping, and bonding, the average value of the total crack length of the electrode non-connection region 26 is preferably 1000 μm/mm ² or less.

For example, the anisotropic conductive member 20 shown in FIG. 7 has cracks 22, but the amount of cracks 22 is different between the electrode connection region 24 connected to the electrode and the electrode non-connection region 26 not connected to the electrode. The average value of the total crack length per unit area of the electrode connection region 24 is preferably smaller than the average value of the total crack length per unit area of the electrode non-connection region 26. Since the average value of the total crack length per unit area of the electrode connection region 24 is small, the conductivity of the anisotropic conductive member 20 can be ensured. In this case, the average value of the total crack length of the electrode non-connection region 26 is relatively large, and there are many cracks 22. In the anisotropic conductive member 20, the conductivity is reduced by the presence of the crack 22, and as a result, the electrode non-connection region 26 with many cracks 22 and the thickness direction Z of the insulating base material 40 (see FIG. 3) (See Fig. 3) The electrical insulation in the orthogonal direction x (see Fig. 3) becomes higher. According to the above, as the semiconductor device 10, the electrical conductivity is maintained and the electrical insulation becomes higher, and the operational reliability becomes higher.

As described above, the average value of the total crack length per unit area is the value in the state of the semiconductor device 10. The method of measuring the average value of the total crack length per unit area will be described. First, the inside of the semiconductor device is observed with an infrared microscope. The semiconductor wafer transmits infrared light, but the anisotropic conductive member 20 does not transmit infrared light. Therefore, if infrared light is used, cracking of the anisotropic conductive member can be clearly detected. An infrared microscope is used to acquire an inspection image of the semiconductor device that overlooks the entire area, and the acquired inspection image is subjected to a binarization process to obtain a binarized image of the inspection image. Among the black parts in the binarized image, those of 10 μm or more are equivalent to cracks. The length of the black part of the binarized image is measured. As described above, the length of the crack is 10 μm or more, so the crack is extracted from the black portion with 10 μm as a threshold. The total length is obtained for the extracted cracks. In addition, the area of the binarized image is obtained from the area of the field of view. The total crack length per unit area is obtained from the crack length and the area of the binarized image. Then, the average value of the total crack lengths per unit area obtained was obtained. In this way, the average value of the total crack length per unit area can be obtained.

8 is a schematic cross-sectional view showing a first example of the configuration of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention, and FIG. 9 is a second showing the structure of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention. Example of a schematic cross-sectional view. 10 is a schematic cross-sectional view showing a third example of the configuration of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention, and FIG. 11 is a structure of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a fourth example. FIG. 12 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention.

For example, as shown in FIG. 8, the semiconductor wafers 12 and 14 have a semiconductor layer 32, a redistribution layer 34 and a passivation layer 36. The redistribution layer 34 and the passivation layer 36 are electrically insulating layers. On the surface 32 a of the semiconductor layer 32, an element region (not shown) in which circuits and the like that play a specific function is formed is provided. The component area will be described later. In addition, the surface 32a of the semiconductor layer 32 corresponds to the surface of the connected member on which the electrode is provided. A redistribution layer 34 is provided on the surface 32 a of the semiconductor layer 32. The rewiring layer 34 is provided with wiring 37 electrically connected to the element region of the semiconductor layer 32. A pad 38 is provided on the wiring 37, and the wiring 37 is electrically connected to the pad 38. With the wiring 37 and the pad 38, signals to and from the device area can be transmitted and received, and voltage and the like can be supplied to the device area.

A passivation layer 36 is provided on the surface 34 a of the redistribution layer 34. In the passivation layer 36, an electrode 30a is provided on the pad 38 provided on the wiring 37. The electrode 30a is electrically connected to the semiconductor layer 32. In addition, the wiring 37 is not provided in the redistribution layer 34, and only the pad 38 is provided. The electrode 30b is provided on the pad 38 that is not provided on the wiring 37. The electrode 30b and the semiconductor layer 32 are not electrically connected.

Both the end surface 30c of the electrode 30a and the end surface 30c of the electrode 30b coincide with the surface 36a of the passivation layer 36. In a so-called surface-to-surface state, the electrode 30a and the electrode 30b do not protrude from the surface 36a of the passivation layer 36. For example, the electrode 30a and the electrode 30b shown in FIG. 8 are polished so that the end surface 30c and the surface 36a of the passivation layer 36 become the same surface.

The electrode 30a and the electrode 30b of the semiconductor wafers 12 and 14 are not limited to the state where the end surface 30c and the surface 36a of the passivation layer 36 are on the same plane. As shown in FIG. 9, they may protrude from the surface 36a of the passivation layer 36. In this case, the protrusion amount δ of the electrode 30a and the electrode 30b with respect to the surface 36a of the passivation layer 36 is, for example, 20 nm or more and 1 μm or less. If the protrusion amount δ is 20 nm or more and 1 μm or less, the electrode 30 a and the electrode 30 b are in contact with the anisotropic conductive member 20 first, which can suppress the occurrence of cracks in the electrode connection region 24 (see FIG. 7) and can be shortened The total crack length in the electrode connection area 24 (see FIG. 7). In the configuration shown in FIG. 9, the electrodes 30 a and 30 b of the semiconductor wafers 12 and 14 do not protrude from the surface 36 a of the passivation layer 36. Therefore, the surface 36 a of the passivation layer 36 can be provided to protect one of the electrodes 30 a and 30 b. Resin layer 39. In the configuration shown in FIG. 9, the electrode 30 a and the electrode 30 b protrude from the surface 36 a, and the end surface 30 c is flat.

The above-mentioned protrusion amount δ can be obtained by acquiring an image of the cross section including the electrode 30a and the electrode 30b in the semiconductor wafers 12, 14 and acquiring the outline of the electrode 30a and the outline of the electrode 30b by image analysis to detect the electrode The end surface 30c of 30a and the end surface 30c of the electrode 30b; the distance from the surface 36a of the passivation layer 36 to the end surface 30c of the electrode 30a and the distance to the end surface 30c of the electrode 30b are obtained. The end surface 30c of the electrode 30a and the end surface 30c of the electrode 30b are the surfaces located farthest from the surface 36a of the passivation layer 36, and are generally referred to as the upper surface.

As shown in FIG. 10, the electrodes 30 a and 30 b of the semiconductor wafers 12 and 14 may be recessed with respect to the surface 36 a of the passivation layer 36. In this case, with respect to the surface 36 a of the passivation layer 36, the end surface 30 c of the electrode 30 a and the end surface 30 c of the electrode 30 b are located in the passivation layer 36. The depression amount γ of the electrode 30a and the electrode 30b, that is, the distance between the end surface 30c of the electrode 30a and the end surface 30c of the electrode 30b and the surface 36a of the passivation layer 36 is, for example, 20 nm or more and 1 μm or less. In the configuration shown in FIG. 10, the electrode 30a and the electrode 30b are buried with respect to the surface 36a, and the end surface 30c is flat. In the case of having the resin layer 39, the protrusion amount δ of the electrode 30a and the electrode 30b shown in FIG. 9 and the depression amount γ of the electrode 30a and the electrode 30b shown in FIG. 10 need to satisfy the space of the non-electrode portion, so they protrude The amount δ ≥ the depression amount γ is preferable. In addition, the protruding electrodes 30a and 30b (hereinafter, also referred to as convex electrodes) shown in FIG. 9 and the recessed electrodes 30a and 30b (hereinafter, also referred to as concave electrodes) shown in FIG. 10 correspond to the alignment , The size of the convex electrode ≥ the size of the concave electrode is better. The size of the convex electrode and the size of the concave electrode are areas when viewed from a direction perpendicular to the surface 32a of the semiconductor layer 32.

In addition, in the semiconductor wafers 12 and 14, as shown in the electrode 31 a shown in FIG. 11, the end surface 30 c may have a convex portion 30 d. The number of the convex portions 30d with respect to one electrode 31a is not particularly limited, and may be one or plural. In the semiconductor wafers 12 and 14, as shown in the electrode 31b shown in FIG. 11, the end surface 30c may have a recess 30e. The number of recesses 30e with respect to one electrode 31b is not particularly limited, and may be one or plural. The electrode 31a and the electrode 31b are preferably used in pairs such that the convex portions 30d and the concave portions 30e correspond. In the case of having the resin layer 39, the amount of protrusion of the electrode 31a having the convex portion 30d shown in FIG. 11 and the amount of depression of the electrode 31b having the concave portion 30e shown in FIG. 11 need to satisfy the space of the non-electrode portion, so The amount of protrusion ≥ the amount of depression is better. In addition, the protruding electrodes 30a and 30b (hereinafter also referred to as convex electrodes) shown in FIG. 9 and the electrode 31b having the concave portion 30e shown in FIG. 11 correspond to the offset of the alignment, and therefore have the convex portion 30d The size of the electrode 31a is preferably ≥ the size of the electrode 31b having the recess 30e. The size of the electrode 31a having the convex portion 30d and the size of the electrode 31b having the concave portion 30e are areas when viewed from a direction perpendicular to the surface 32a of the semiconductor layer 32.

As shown in FIG. 12, when the semiconductor wafer 12 with the electrode 30 a recessed and the semiconductor wafer 14 with the electrode 30 a protruding are joined via the anisotropic conductive member 20, the semiconductor wafer 12 and the semiconductor wafer 14 are arranged between In the state of the anisotropic conductive member 20, the recessed electrode 30 a of the semiconductor wafer 12 and the protruding electrode 30 a of the semiconductor wafer 14 are opposed to each other via the anisotropic conductive member 20. That is, the protruding electrode 30a of the semiconductor wafer 14 and the recessed electrode 30a of the semiconductor wafer 12 are arranged correspondingly. When the semiconductor wafer 12 and the semiconductor wafer 14 are bonded via the anisotropic conductive member 20 in this arrangement state, the protruding electrode 30a of the semiconductor wafer 14 contacts the anisotropic conductive before the recessed electrode 30a of the semiconductor wafer 12 Sexual member 20. The recessed electrode 30a of the semiconductor wafer 12 is arranged so that the portion of the protruding electrode 30a of the semiconductor wafer 14 that presses the anisotropic conductive member 20 is well fitted. Thereby, the occurrence of cracks 22 (see FIG. 7) in the electrode connection region 24 (see FIG. 7) of the anisotropic conductive member 20 connected to the electrode 30 a can be suppressed. However, cracks 22 are generated around the recessed electrode 30a and the protruding electrode 30a, that is, the electrode non-connection region 26 (see FIG. 7). Furthermore, the total crack length in the electrode non-connection region 26 (see FIG. 7) becomes longer. By this, the electrical insulation in the electrode non-connection region 26 (see FIG. 7) becomes higher. In addition, the semiconductor wafer 12 with the electrode 30a recessed corresponds to another semiconductor, and the semiconductor wafer 14 with the electrode 30a protruding corresponds to one semiconductor.

In addition, in the case of having the resin layer 39, the protruding electrode 30a of the semiconductor wafer 14 shown in FIG. 12 and the recessed electrode 30a of the semiconductor wafer 12 need to meet the space of the non-electrode portion, so the amount of protrusion δ ≥ the amount of depression γ is preferred. In addition, the protruding electrode 30a (hereinafter, also referred to as a convex electrode) shown in FIG. 12 and the concave electrode 30a (hereinafter, also referred to as a concave electrode) shown in FIG. 12 correspond to the offset of alignment, so The size of the convex electrode ≥ the size of the concave electrode is preferred. The size of the convex electrode and the size of the concave electrode are areas when viewed from a direction perpendicular to the surface 32a of the semiconductor layer 32.

The electrode 31a having the convex portion 30d and the electrode 31b having the concave portion 30e shown in FIG. 11 are similar to the protruding electrode 30a and the recessed electrode 30a shown in FIG. 12 via an anisotropic conductive member 20 and the opposite configuration. That is, the electrode 31a having the convex portion 30d and the electrode 31b having the concave portion 30e are arranged correspondingly. In this case, the concave portion 30e of the electrode 31b absorbs the convex portion 30d of the electrode 31a to press and absorb the amount of the anisotropic conductive member 20. In this way, if the electrode shape is a nested shape with a combination of irregularities, cracks 22 (see FIG. 7) in the electrode connection region 24 (see FIG. 7) of the anisotropic conductive member 20 connected to the electrodes 31 a and 31 b can be suppressed 7) Generation. However, cracks 22 are generated around the electrode 31 a and the electrode 31 b, that is, in the electrode non-connection region 26 (see FIG. 7 ). Furthermore, the total crack length in the electrode non-connection region 26 (see FIG. 7) becomes longer, and the electrical insulation in the electrode non-connection region 26 (see FIG. 7) becomes higher. Moreover, the semiconductor wafer provided with the electrode 31a which has the convex part 30d corresponds to one semiconductor, and the semiconductor wafer provided with the electrode 31b which has the concave part 30e corresponds to another semiconductor.

The semiconductor layer 32 is not particularly limited as long as it is a semiconductor material, and is composed of silicon or the like, but is not limited thereto, and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like. The redistribution layer 34 is made of an electrically insulating material, for example, made of polyimide. In addition, the passivation layer 36 is also made of an electrically insulating material, for example, silicon nitride (SiN) or polyimide. The wiring 37 and the pad 38 are made of a conductive material, for example, made of copper, copper alloy, aluminum or aluminum alloy.

Like the wiring 37 and the pad 38, the electrode 30a and the electrode 30b are made of a conductive material, for example, a metal or an alloy. Specifically, the electrode 30a and the electrode 30b are made of copper, copper alloy, aluminum, or aluminum alloy, for example. In addition, as long as the electrode 30a and the electrode 30b are electrically conductive, they are not limited to being made of metal or alloy, and materials used for terminals or electrode pads in the field of semiconductor devices can be appropriately used. In addition, the semiconductor wafers 12 and 14 are configured to include the electrode 30b, but it is not limited to this, and the electrode 30b may not be provided.

The surface roughness of the end surface 30c of the electrode 30a and the end surface 30c of the electrode 30b is preferably 10 nm or less. If the surface roughness is 10 nm or less, the occurrence of cracks in the surface of the anisotropic conductive member 20 connected to the electrodes 30a and 30b can be suppressed. Here, the surface roughness is the arithmetic average roughness Ra (JIS (Japanese Industrial Standards) B 0601-2001). The end surface 30c of the electrode 30a and the end surface 30c of the electrode 30b correspond to the surface of the connected member having the electrode.

As shown in FIG. 13, the semiconductor device 10 may be configured such that the semiconductor wafer 12 and the interposer 18 are laminated and electrically connected via the anisotropic conductive member 20 in the stacking direction Ds. Like the semiconductor device 10 shown in FIG. 1, the semiconductor device 10 shown in FIG. 13 has good conduction, good electrical insulation, and high operational reliability.

The interposer 18 is responsible for electrical connections between semiconductor wafers. It also serves as an electrical connector for semiconductor wafers and wiring boards. By using the interposer 18, the wiring length and wiring width can be reduced, and the parasitic capacitance and the variation in wiring length can be reduced. The structure of the insert 18 is not particularly limited as long as it can achieve the above-mentioned functions, and it can be appropriately used including well-known ones. The insert 18 can be configured using, for example, organic materials such as polyimide, glass, ceramics, metal, silicon, polycrystalline silicon, and the like. In addition, the printed circuit board is not included in the insert 18.

In addition, for example, as in the semiconductor device 10 shown in FIG. 14, the semiconductor wafer 12, the semiconductor wafer 14, and the semiconductor wafer 16 may be stacked and electrically connected via the anisotropic conductive member 20 in the stacking direction Ds. Pose. Similar to the semiconductor device 10 shown in FIG. 1, the semiconductor device 10 shown in FIG. 14 also has good conduction, good electrical insulation, and high operational reliability.

In addition, as in the semiconductor device 10 shown in FIG. 15, it may also function as an optical sensor. In the semiconductor device 10 shown in FIG. 15, the semiconductor wafer 52 and the sensor wafer 54 are stacked in the stacking direction Ds via the anisotropic conductive member 20 and bonded and electrically connected. In addition, a lens 56 is provided on the sensor wafer 54. As with the semiconductor device 10 shown in FIG. 15, as an optical sensor, as in the semiconductor device 10 shown in FIG. 1, it is also well-connected, has good electrical insulation, and has high operational reliability.

The semiconductor wafer 52 is not particularly limited as long as it has a logic circuit formed and can process the signal obtained by the sensor wafer 54. The sensor wafer 54 is a light sensor that detects light. The photo sensor is not particularly limited as long as it can detect light. For example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor can be used. . In addition, in the semiconductor device 10 shown in FIG. 15, the semiconductor wafer 52 and the sensor wafer 54 are connected via the anisotropic conductive member 20, but it is not limited to this, and the semiconductor wafer 52 and The sensor wafer 54 is directly bonded. As long as the lens 56 can collect light on the sensor wafer 54, its configuration is not particularly limited. For example, what is called a microlens can be used.

The semiconductor wafer 12, the semiconductor wafer 14, and the semiconductor wafer 16 have the semiconductor layer 32 and have an element region (not shown). The element area is an area where various elements such as capacitors, resistors, and coils that function as electronic elements form circuits and the like. In the component area, for example, there are areas where memory circuits such as flash memory, microprocessors, and logic circuits such as FPGA (field-programmable gate array) are formed; communication modules such as radio frequency identification tags are formed Group and wiring area. In addition, a transmission circuit or MEMS (Micro Electro Mechanical Systems) may be formed in the element area. MEMS are, for example, sensors, actuators and antennas. The sensors include various sensors such as acceleration, sound, and light.

As described above, the element region is formed with the element configuration circuit and the like, and as described above, the redistribution layer 34 is provided in the semiconductor element (see FIG. 8 ). In the semiconductor device, for example, a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit can be used. Furthermore, all semiconductor elements may be provided with memory circuits, or all may be provided with logic circuits. In addition, the combination of the semiconductor elements in the semiconductor device 10 may be a combination of a sensor, an actuator, an antenna, etc. and a memory circuit and a logic circuit, and may be appropriately determined according to the use of the semiconductor device 10 and the like.

Hereinafter, a method of manufacturing a semiconductor device will be described. [Manufacturing method of semiconductor device] FIGS. 16 to 22 are schematic diagrams showing the first example of the manufacturing method of the semiconductor device according to the embodiment of the present invention in order of process. In the first example of the method of manufacturing the semiconductor device shown in FIGS. 16 to 22, the same components as those of the semiconductor device 10 shown in FIG. 1 and the anisotropic conductive material 50 shown in FIG. 4 are denoted by the same symbols, And its detailed description is omitted. The first example of a method of manufacturing a semiconductor device relates to a chip on wafer, and shows a method of manufacturing the semiconductor device 10 shown in FIG. 1.

First, as shown in FIG. 16, an anisotropic conductive material 50 and a semiconductor wafer 58 provided with an anisotropic conductive member 20 formed in a predetermined pattern are provided on a support 46. Furthermore, the anisotropic conductive material 50 is arranged toward the anisotropic conductive member 20 in the element region (not shown) of the semiconductor wafer 58. The anisotropic conductive material 50 shown in FIG. 16 indicates that the anisotropic conductive member 20 is provided on the support 46 in a singulated state. The semiconductor wafer 58 includes a plurality of element regions (not shown) on the surface 58a. An alignment mark (not shown) for alignment and electrodes 30a and 30b shown in FIG. 8 are provided in the element area. In the anisotropic conductive material 50, an anisotropic conductive member 20 is formed corresponding to the element region.

Next, as shown in FIG. 17, a predetermined pressure is applied, heated to a predetermined temperature and maintained for a predetermined time, and bonded to the element region on the surface 58 a of the semiconductor wafer 58. Next, as shown in FIG. 18, the support 46 of the anisotropic conductive material 50 is removed, and only the anisotropic conductive member 20 is bonded to the surface 58 a of the semiconductor wafer 58. In this case, the anisotropic conductive material 50 is heated to a predetermined temperature to reduce the adhesive force of the adhesive layer 49 of the adhesive member 47, and removed using the adhesive member 47 of the anisotropic conductive material 50 as a starting point Support body 46.

Next, as shown in FIG. 19, for the semiconductor wafer 58 to which the anisotropic conductive member 20 is bonded, a plurality of semiconductors are obtained by singulation for each device region by dicing or laser scribing, etc. Wafer 14. In addition, in FIG. 19, in the process of cutting the semiconductor wafer 58, it is preferable to perform in an environment with a cleanliness level higher than the 1000 level specified in the US Federal Standard. In addition, in the process of cutting the semiconductor wafer 58, it is preferable to cut from the anisotropic conductive member 20 side.

Here, a semiconductor wafer 60 having a plurality of element regions (not shown) is prepared. A plurality of element regions are provided on the surface 60a of the semiconductor wafer 60. An alignment mark (not shown) for alignment and electrodes 30a and 30b shown in FIG. 8 are provided in the element area. The semiconductor wafer 60 is cut in units including one device region to become the semiconductor wafer 12. The semiconductor wafer 14 is bonded to the element region of the semiconductor wafer 12 to become a semiconductor device 10.

Next, the semiconductor wafer 14 and the anisotropic conductive member 20 are arranged toward the semiconductor wafer 60. Next, the semiconductor wafer 14 is aligned using the alignment mark of the semiconductor wafer 14 and the alignment mark of the semiconductor wafer 60.

Next, the semiconductor wafer 14 is placed on the element region of the semiconductor wafer 60 via the anisotropic conductive member 20, for example, a predetermined pressure is applied, and heated to a predetermined temperature for a predetermined period of time, using the resin layer 44 (See Figure 3) Temporary joining. All the semiconductor wafers 14 are operated as described above, and as shown in FIG. 21, all the semiconductor wafers 14 are temporarily bonded to the element region of the semiconductor wafer 60. The use of the resin layer 44 during temporary bonding is one of the methods, and the method shown below may also be used. For example, a sealing resin or the like may be supplied to the semiconductor wafer 60 by a dispenser or the like, and the semiconductor wafer 14 may be temporarily bonded to the element area of the semiconductor wafer 60, or the semiconductor wafer 60 may be provided with previously supplied insulation A resin film (NCF (Non-conductive Film)) temporarily bonds the semiconductor wafer 14 to the element region.

Next, in a state where all the semiconductor wafers 14 are temporarily bonded to the element region of the semiconductor wafer 60, a predetermined pressure is applied to the semiconductor wafer 14 and heated to a predetermined temperature for a predetermined time, and a plurality of All the semiconductor wafers 14 are bonded to the element region of the semiconductor wafer 60 at once. This joining system is called a formal joining person. As a result, the electrodes 30 a and 30 b of the semiconductor wafer 14 are bonded to the anisotropic conductive member 20, and the electrodes 30 a and 30 b of the semiconductor wafer 60 are bonded to the anisotropic conductive member 20. Next, as shown in FIG. 22, the semiconductor wafer 60 to which the semiconductor wafer 14 is bonded via the anisotropic conductive member 20 is singulated for each element region by dicing, laser scoring, or the like. With this, the semiconductor device 10 in which the semiconductor wafer 12, the anisotropic conductive member 20 and the semiconductor wafer 14 are bonded can be obtained.

The semiconductor wafer 58 to which the anisotropic conductive member 20 is bonded shown in FIG. 19 is not limited to being manufactured as described above. For example, as shown in FIG. 23, an anisotropic conductive material 50 in which an anisotropic conductive member 20 is provided on the entire surface of the support 46 is prepared. The anisotropic conductive material 50 is cut for each support 46 and singulated. Thereby, the individualized anisotropic conductive material 51 can be obtained. Furthermore, as shown in FIG. 24, the individualized anisotropic conductive material 51 is bonded to the element region on the surface 58 a of the semiconductor wafer 58. Next, with respect to the anisotropic conductive material 51, the adhesive force of the adhesive layer 49 of the adhesive member 47 is reduced, and the support 46 is removed using the adhesive member 47 of the anisotropic conductive material 50 as a starting point. As a result, as shown in FIG. 18, only the anisotropic conductive member 20 is bonded to the surface 58 a of the semiconductor wafer 58. The anisotropic conductive member 20 may be bonded to the surface 58a of the semiconductor wafer 58 in this way. In addition, when the anisotropic conductive material 50 is cut for each support 46 to be singulated, as in the process of cutting the semiconductor wafer 58, the cleanliness is higher than the 1000 level specified in the US Federal Standard. It is better to proceed in the environment. In addition, when the anisotropic conductive material 50 is cut for each support 46 and singulated, it is also preferable to cut from the anisotropic conductive member 20 side.

In addition, during temporary joining, if the temporary joining strength is weak, positional shift occurs in the conveying process and the process up to the joining, so the temporary joining strength is important. In addition, the temperature conditions in the temporary bonding process are not particularly limited, but 0°C to 300°C is preferred, 10°C to 200°C is more preferred, and normal temperature (23°C) to 100°C is particularly preferred. Similarly, the pressure conditions in the temporary joining process are not particularly limited, but 10 MPa or less is preferable, 5 MPa or less is more preferable, and 1 MPa or less is particularly preferable.

The temperature conditions in the full joining are not particularly limited, but the temperature is preferably higher than the temperature of the temporary joining, specifically, 150°C to 350°C is more preferable, and 200°C to 300°C is particularly preferable. In addition, the pressurization conditions in the actual joining are not particularly limited, but 30 MPa or less is preferable, and 0.1 MPa to 20 MPa is more preferable. In addition, the time for the full joining is not particularly limited, but 1 second to 60 minutes is more preferable, and 5 seconds to 10 minutes is more preferable. By performing the main bonding under the above conditions, the resin layer flows between the electrodes of the semiconductor wafer 14 and it is difficult for the resin layer to remain in the bonding portion. As described above, in the formal bonding, by bonding a plurality of semiconductor wafers 14 at one time, production time can be reduced, and productivity can be improved.

In the first example of the method of manufacturing the semiconductor device, the semiconductor wafer 14 in which the anisotropic conductive member 20 is provided on the surface 14a is used, but it is not limited thereto. The semiconductor wafer 14 not provided with the anisotropic conductive member 20 may be bonded to the semiconductor wafer 60 provided with the anisotropic conductive member 20 on the surface 60a.

A second example of the method of manufacturing a semiconductor device will be described. 25 to 27 are schematic diagrams showing a second example of the method of manufacturing the semiconductor device according to the embodiment of the present invention in order of process. Compared with the first example of the method of manufacturing a semiconductor device, the second example of the method of manufacturing a semiconductor device except that three semiconductor wafers 12, 14, 16 are stacked and bonded via an anisotropic conductive member 20 and electrically connected, It is the same as the first example of the manufacturing method of the semiconductor device. Therefore, a detailed description of the manufacturing method common to the first example of the manufacturing method of the semiconductor device is omitted. The second example of the manufacturing method of the semiconductor device shows the manufacturing method of the semiconductor device 10 shown in FIG. 14.

As described above, the alignment mark (not shown) is provided on the back surface 14b of the semiconductor wafer 14, and the electrode 30a and the electrode 30b are provided. In addition, an anisotropic conductive member 20 is provided on the surface 14 a of the semiconductor wafer 14. In addition, an anisotropic conductive member 20 is also provided on the surface 16a of the semiconductor wafer 16.

As shown in FIG. 25, in a state where all the semiconductor wafers 14 are temporarily bonded to the element region of the semiconductor wafer 60 via the anisotropic conductive member 20, the alignment mark of the back surface 14b of the semiconductor wafer 14 and the alignment of the semiconductor wafer 16 are used The quasi-marking aligns the semiconductor wafer 16 to the semiconductor wafer 14.

Next, as shown in FIG. 26, the semiconductor wafer 16 is temporarily bonded to the back surface 14 b of the semiconductor wafer 14 via the anisotropic conductive member 20. Next, in a state where all semiconductor wafers 14 are temporarily bonded to the element region of the semiconductor wafer 60 via the anisotropic conductive member 20 and the semiconductor wafer 16 is temporarily bonded to all semiconductor wafers 14 via the anisotropic conductive member 20 In the state, the formal bonding is performed under predetermined conditions. With this, the semiconductor wafer 14 and the semiconductor wafer 16 are bonded via the anisotropic conductive member 20, and the semiconductor wafer 14 and the semiconductor wafer 60 are bonded via the anisotropic conductive member 20. The electrodes 30 a and 30 b of the semiconductor wafer 14, the semiconductor wafer 16 and the semiconductor wafer 60 are bonded to the anisotropic conductive member 20.

Next, as shown in FIG. 27, the semiconductor wafer 60 to which the semiconductor wafer 14 and the semiconductor wafer 16 are bonded via the anisotropic conductive member 20 is singulated for each element region, for example, by dicing or laser scoring, etc. . With this, the semiconductor device 10 in which the semiconductor wafer 12, the semiconductor wafer 14, and the semiconductor wafer 16 are joined via the anisotropic conductive member 20 can be obtained.

A third example of the method of manufacturing a semiconductor device will be described. 28 to 29 are schematic diagrams showing a third example of the method of manufacturing the semiconductor device according to the embodiment of the present invention in order of process. The third example of a method of manufacturing a semiconductor device relates to a wafer on wafer (wafer on wafer), and shows a method of manufacturing the semiconductor device 10 shown in FIG. 1. Compared with the first example of the method of manufacturing a semiconductor device, the third example of the method of manufacturing a semiconductor device is that the semiconductor wafer 58 and the semiconductor wafer 60 are laminated and bonded via the anisotropic conductive member 20 and electrically connected. It is the same as the first example of the manufacturing method of the semiconductor device. Therefore, a detailed description of the manufacturing method common to the first example of the manufacturing method of the semiconductor device is omitted. In addition, the anisotropic conductive member 20 is also the same as the above description, so a detailed description thereof is omitted.

First, the semiconductor wafer 58 and the semiconductor wafer 60 are prepared. The anisotropic conductive member 20 is provided on any one of the surface 58 a of the semiconductor wafer 58 and the surface 60 a of the semiconductor wafer 60. Next, the surface 58 a of the semiconductor wafer 58 is opposed to the surface 60 a of the semiconductor wafer 60. Then, the semiconductor wafer 58 is aligned using the alignment mark of the semiconductor wafer 58 and the alignment mark of the semiconductor wafer 60. Next, the surface 58 a of the semiconductor wafer 58 is opposed to the surface 60 a of the semiconductor wafer 60, and as shown in FIG. 28, the semiconductor wafer 58 and the semiconductor wafer 60 are bonded via the anisotropic conductive member 20 using the method described above . In this case, the formal joining may be performed after the temporary joining, or only the formal joining may be performed.

Next, as shown in FIG. 29, for example, by dicing or laser scoring, etc., in a state where the semiconductor wafer 58 and the semiconductor wafer 60 are bonded via the anisotropic conductive member 20, each element region is singulated . With this, the semiconductor device 10 in which the semiconductor wafer 12 and the semiconductor wafer 14 are joined via the anisotropic conductive member 20 can be obtained. In this way, the semiconductor device 10 can be obtained even if the wafer on the wafer is used. In addition, the simplification is as described above, so detailed description is omitted. Also, as shown in FIG. 29, if there is a semiconductor wafer that needs to be thinned between the semiconductor wafer 58 and the semiconductor wafer 60 in a state where the semiconductor wafer 58 and the semiconductor wafer 60 are joined, it is possible to use chemical Thin by mechanical polishing (CMP: Chemical Mechanical Polishing).

In the third example of the manufacturing method of the semiconductor device, the two-layer structure in which the semiconductor wafer 12 and the semiconductor wafer 14 are stacked is described as an example, but it is not limited to this, and of course it may be three or more layers. In this case, as in the third example of the method of manufacturing the semiconductor device 10 described above, three layers can be obtained by providing alignment marks (not shown), electrodes 30a and electrodes 30b on the back surface 58b of the semiconductor wafer 58 The above semiconductor device 10. In the above, the first example, the second example, and the third example have been described as the method of manufacturing the semiconductor device. However, any method of manufacturing the semiconductor device can be used as the method of manufacturing the laminate. The laminate can also be manufactured by the same manufacturing method as the semiconductor device.

Hereinafter, the anisotropic conductive member 20 will be described more specifically. [Insulating base material] As long as the insulating base material contains an inorganic material and has the same degree of resistivity (approximately 10 ¹⁴ Ωcm) as the insulating base material that constitutes a conventionally known anisotropic conductive film, etc., then There is no particular limitation. In addition, "including inorganic materials" is a regulation for distinguishing from the polymer materials constituting the resin layer described later, and is not limited to the regulation of an insulating base material composed only of inorganic materials, but uses inorganic materials as a main component (50% by mass or more).

Examples of insulating substrates include metal oxide substrates, metal nitride substrates, glass substrates, silicon carbide, silicon nitride and other ceramic substrates, diamond-like carbon and other carbon substrates, and polyimide groups. Materials, such composite materials, etc. As an insulating base material, in addition, for example, it may be formed of an inorganic material containing 50% by mass or more of a ceramic material or a carbon material on an organic material having a through hole.

As the insulating base material, for the reason that the micropores having the desired average opening diameter are formed as through-holes and it is easy to form a conductive path described later, a metal oxide base material is preferable, and the anodic oxide film of the valve metal is Better. Here, specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, the anodic oxidation film (base material) of aluminum has good dimensional stability and is relatively inexpensive, so it is preferable.

The interval between the conductive paths in the insulating substrate is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, and even more preferably 50 nm to 140 nm. If the distance between the conductive paths in the insulating base material is within this range, the insulating base material fully functions as an insulating partition wall. Here, the interval of each conductive path refers to the width w between adjacent conductive paths, and refers to the cross-section of the anisotropic conductive member observed by a field emission scanning electron microscope at a magnification of 200,000 times. The average value obtained by measuring the width between adjacent conduction paths.

[Conducting Via] A plurality of conducting vias penetrate through the thickness direction of the insulating base material, are provided in a state of being electrically insulated from each other, and include a conductive material. The conductive path may have a protruding portion protruding from the surface of the insulating base material, and the end of the protruding portion of each conductive path may be buried in a resin layer described later.

<Conductive material> The conductive material constituting the conductive path is not particularly limited as long as it has a resistivity of 10 ³ Ωcm or less. As a specific example thereof, gold (Au), silver (Ag), and copper (Cu ), aluminum (Al), magnesium (Mg), nickel (Ni), indium-doped tin oxide (ITO), etc. Among them, from the viewpoint of electrical conductivity, copper, gold, aluminum, and nickel are preferred, and copper and gold are more preferred.

<Protruding portion> The protruding portion of the conductive path is a portion where the conductive path protrudes from the surface of the insulating base material, and the end of the protruding portion is buried in the resin layer.

When the anisotropic conductive member and the electrode are electrically connected or physically joined by a method such as crimping, the reason for ensuring sufficient insulation in the plane direction when the protruding portion is crushed is that The aspect ratio (the height of the protruding portion/the diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8-20, and further preferably 1-10.

In addition, from the viewpoint of following the surface shape of the semiconductor wafer or the semiconductor wafer to be connected, as described above, the height of the protruding portion of the via is preferably 20 nm or more, and more preferably 100 nm to 500 nm. The height of the protruding part of the conductive path means that the cross-section of the anisotropic conductive member is observed with a field emission scanning electron microscope at a magnification of 20,000 times, and the height of the protruding part of the conductive path is measured at 10 points average value. The diameter of the protruding portion of the conductive path refers to an average value obtained by observing the cross section of the anisotropic conductive member with a field emission scanning electron microscope and measuring the diameter of the protruding portion of the conductive path at 10 points.

<Other shapes> The conductive path is columnar, and the diameter d of the conductive path is preferably more than 5 nm and less than 10 μm, more preferably 20 nm to 1000 nm, and even more preferably 100 nm or less, similar to the diameter of the protruding portion.

In addition, the conductive paths exist in a state of being electrically insulated from each other by an insulating base material, and the density is preferably 20,000 pieces/mm ² or more, more preferably 2 million pieces/mm ² or more, and 10 million pieces/ to further preferred mm ² or more, 50,000,000 / mm ² or more is particularly preferably, 100 million / mm ² or more is preferred.

In addition, the distance p between the centers of adjacent conductive paths is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and even more preferably 50 nm to 140 nm.

[Resin Layer] The resin layer is provided on the surface of the insulating base material, and the above-mentioned conductive path is embedded. That is, the resin layer covers the surface of the insulating base material and the end of the conductive path protruding from the insulating base material. The resin layer is one that imparts bondability to the connected object. The resin layer system, for example, has a viscosity decrease at 25°C in a temperature range of 50°C to 200°C, and it is preferable that the curing reaction starts at 200°C or higher. Hereinafter, the composition of the resin layer will be described. The resin layer contains polymer materials. The resin layer may also contain an antioxidant material.

<Polymer material> The polymer material contained in the resin layer is not particularly limited, because it can efficiently fill the gap between the semiconductor wafer or the semiconductor wafer and the anisotropic conductive member, and can be further improved with the semiconductor wafer or semiconductor The reason for the tightness of the wafer is preferably thermosetting resin. Specific examples of thermosetting resins include epoxy resins, phenol resins, polyimide resins, polyester resins, polyurethane resins, bismaleimide resins, melamine resins, and isocyanate resins. Wait. Among them, it is preferable to use polyimide resin and/or epoxy resin for the reason that the insulation reliability related to electrical insulation is further improved and the chemical resistance is excellent.

<Antioxidant material> As the antioxidant material contained in the resin layer, specifically, for example, 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole , 5-methyl-1,2,3,4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino- 1,2,3-triazole, 4,5-diamino-1,2,3-triazole, 4-carboxy-1H-1,2,3-triazole, 4,5-dicarboxy-1H- 1,2,3-triazole, 1H-1,2,3-triazole-4-acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4 -Triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-carboxy-1,2,4-triazole, 3, 5-dicarboxy-1,2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H-benzotriazole-5-carboxylic acid, benzofuran (Benzofuroxan), 2,1,3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2- Mercaptobenzoxazole, melamine and derivatives of these. Among these, benzotriazole and its derivatives are preferred. Examples of benzotriazole derivatives include hydroxy groups, alkoxy groups (eg, methoxy, ethoxy, etc.), amine groups, nitro groups, and alkyl groups (eg, Methyl, ethyl, butyl, etc.), halogen atoms (for example, fluorine, chlorine, bromine, iodine, etc.) substituted benzotriazole. In addition, naphthalene triazole, naphthalene bis triazole, substituted naphthalene triazole, substituted naphthalene bis triazole and the like as described above can also be mentioned.

In addition, as other examples of the antioxidant material contained in the resin layer, higher fatty acids, copper higher fatty acids, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, etc., which are general antioxidants, can be cited. Organic amines, organic ammonium salts, etc.

The content of the antioxidant material contained in the resin layer is not particularly limited, but from the viewpoint of the anticorrosive effect, it is preferably 0.0001 mass% or more relative to the total mass of the resin layer, and more preferably 0.001 mass% or more. In addition, for the reason of obtaining an appropriate resistance in the formal bonding process, 5.0% by mass or less is preferable, and 2.5% by mass or less is more preferable.

<Migration prevention material> The reason why the resin layer contains a migration prevention material is that the resin layer contains a migration prevention material for the reason of further improving insulation reliability by capturing metal ions, halogen ions, and metal ions derived from the semiconductor wafer and the semiconductor wafer in the resin layer. good.

As the material for preventing migration, for example, an ion exchanger can be used, specifically, a mixture of a cation exchanger and an anion exchanger, or only a cation exchanger can be used. Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, inorganic ion exchangers and organic ion exchangers to be described later.

(Inorganic ion exchanger) Examples of the inorganic ion exchanger include hydrous oxides of metals represented by hydrous zirconia. As the type of metal, for example, in addition to zirconium, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, etc. are known. Among these, zirconium has exchange energy for cation Cu ²⁺ and Al ³⁺ . In addition, regarding the iron system, it also has exchange energy for Ag ⁺ and Cu ²⁺ . Tin-based, titanium-based, and antimony-based systems are also cation exchangers. On the other hand, the bismuth system has exchange energy for the anionic Cl ^- . In addition, the zirconium system exhibits anion exchange energy according to production conditions. The aluminum system and the tin system are also the same. As inorganic ion exchangers other than these, there are known compositions of acid salts of polyvalent metals represented by zirconium phosphate, heterogeneous multiple acid salts represented by ammonium phosphomolybdate, insoluble ferrocyanide, and the like. Some of these inorganic ion exchangers are already commercially available. For example, various grades under the trade name "IXE" of TOAGOSEI CO., LTD. are known. In addition to synthetic products, powders of inorganic ion exchangers such as natural zeolite or montmorillonite can also be used.

(Organic ion exchanger) As the organic ion exchanger, as the cation exchanger, cross-linked polystyrene having a sulfonic acid group may be mentioned, and those having a carboxylic acid group, phosphonic acid group or phosphinic acid group may also be mentioned. . In addition, examples of the anion exchanger include crosslinked polystyrene having a quaternary ammonium group, a quaternary phosphonium group, or a tertiary ammonium group.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the types of cations and anions to be captured and the exchange capacity of the ions. Of course, inorganic ion exchangers and organic ion exchangers can also be used in combination. The manufacturing process of electronic components includes a heating process, so inorganic ion exchangers are preferred.

In addition, for example, from the viewpoint of mechanical strength, in the mixing ratio of the migration prevention material and the polymer material, it is more preferable to set the migration prevention material to 10% by mass or less, and to set the migration prevention material to 5% by mass or less. Preferably, the migration prevention material is more preferably 2.5% by mass or less. In addition, from the viewpoint of suppressing migration when joining the semiconductor wafer or the semiconductor wafer and the anisotropic conductive member, it is preferable to set the migration prevention material to 0.01% by mass or more.

<Inorganic filler> The resin layer may contain an inorganic filler. The inorganic filler is not particularly limited, and can be appropriately selected from known ones, and examples thereof include kaolin, barium sulfate, barium titanate, silicon oxide powder, finely powdered silicon oxide, vapor-phase growth silicon dioxide, and amorphous Silicon dioxide, crystalline silicon dioxide, fused silicon dioxide, spherical silicon dioxide, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, Silicon carbide, silicon nitride, etc.

In order to prevent the inorganic filler from entering between the vias and further improve the conduction reliability, the average particle diameter of the inorganic filler is preferably larger than the interval between the vias. The average particle size of the inorganic filler is preferably 30 nm to 10 μm, and more preferably 80 nm to 1 μm. Here, regarding the average particle diameter, the primary particle diameter measured by a laser diffraction scattering particle size measuring device (MICROTRAC MT3300 manufactured by Nikkiso Co., Ltd.) is used as the average particle diameter.

<Hardener> The resin layer may contain a hardener. When a hardener is contained, from the viewpoint of suppressing poor bonding to the semiconductor wafer or the surface shape of the semiconductor wafer to be connected, the hardener that is solid at normal temperature is not used but the hardener that is liquid at normal temperature is Better. Here, "solid at normal temperature" refers to a solid at 25°C, for example, a substance having a melting point of higher than 25°C.

Specific examples of the curing agent include imidazole derivatives such as aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, 4-methylimidazole, and dicyandiamide. Carboxylic anhydrides such as amines, tetramethylguanidine, thiourea addition amines, methylhexahydrophthalic anhydride, carboxylic acid hydrazines, carboxylic acid amides, polyphenol compounds, novolac resins, polythiols, etc. can be selected from Among these hardeners, those that are liquid at 25°C are appropriately selected and used. In addition, one kind of hardener may be used alone, or two or more kinds may be used in combination.

The resin layer may contain various additives, such as a dispersant, a buffer, and a viscosity modifier, which are generally widely added to the resin insulating film of the semiconductor package within a range that does not impair its characteristics.

<Shape> For the purpose of protecting the conductive path of the anisotropic conductive member, the thickness of the resin layer is larger than the height of the protruding portion of the conductive path and is preferably 1 μm to 5 μm.

<Transparent Insulator> The transparent insulator is composed of those having the visible light transmittance of 80% or more among the materials mentioned in the above [resin layer]. Therefore, detailed description of each material is omitted. In the transparent insulator, when the main component (polymer material) is the same as the polymer material of the above [resin layer], the adhesiveness between the transparent insulator and the resin layer becomes good, which is preferable. The transparent insulator is formed in a portion where there is no electrode or the like, so it is preferable that the <resistance material> of the above [resin layer] and the <migration prevention material> of the above [resin layer] are not included. When the CTE (Linear Expansion Coefficient) of the transparent insulating system is close to the CTE of the support such as silicon, the warpage of the anisotropic conductive material is reduced, so the <inorganic filler> containing the above [resin layer] is preferable. In the transparent insulator, when the polymer material and the hardener are the same as the polymer material and the hardener of the above [resin layer], the curing conditions such as temperature and time become the same, which is preferable. In addition, "visible light transmittance is 80% or more" means that the light transmittance is 80% or more in the visible light wavelength region with a wavelength of 400 to 800 nm. The light transmittance is measured using the "Plastics-Method for finding the total light transmittance and total light reflectance" specified in JIS K 7375:2008.

[Manufacturing method of anisotropic conductive member] The manufacturing method of the anisotropic conductive member is not particularly limited, and for example, a manufacturing method having the following processes may be mentioned: a conductive path forming process in which conductive materials are present in the The through hole of the insulating base material forms a conductive path; the trimming process, after the conductive path forming process, only a part of the surface of the insulating base material is removed to protrude the conductive path; and the resin layer forming process, after the trimming process, in A resin layer is formed on the surface of the insulating base material and the protruding portion of the conductive path.

[Preparation of insulating base material] For the insulating base material, for example, a glass substrate with a through hole (Through Glass Via: TGV) can be used directly, but the opening diameter of the via and the aspect ratio of the protruding portion are set From the viewpoint of the above range, the substrate formed by anodizing the valve metal is preferable. It can be produced by sequentially performing the following processes: for example, in the case where the insulating base material is anodized film of aluminum, as the anodizing process, anodizing the aluminum substrate by anodizing; and after the anodizing process, The holes formed by micropores generated by anodizing are subjected to penetration treatment. Regarding the aluminum substrate used in the production of the insulating base material and each processing process performed on the aluminum substrate, the same ones described in paragraphs <0041> to <0121> of JP-A-2008-270158 can be used.

[Conducting Path Forming Process] The conducting path forming process is a process in which conductive material exists in the through hole provided in the insulating base material. Here, as a method of allowing the metal to exist in the through hole, for example, the methods described in paragraphs <0123> to <0126> and [FIG. 4] described in Japanese Patent Laid-Open No. 2008-270158 (electrolytic plating) Method or electroless plating method) the same method. In addition, in the electrolytic plating method or the electroless plating method, it is preferable to provide an electrode layer using gold, nickel, copper, or the like in advance. Examples of the method for forming the electrode layer include gas phase treatment such as sputtering, liquid layer treatment such as electroless plating, and treatment combining these. Through the metal filling process, an anisotropic conductive member before forming the protruding portion of the via is obtained.

On the other hand, the via formation process may be, for example, a method having the following process instead of the method described in Japanese Patent Laid-Open No. 2008-270158: anodizing process, on the surface of one side of the aluminum substrate (hereinafter, also It is called "single-sided".) Anodizing treatment is performed to form an anodic oxide film with micropores existing in the thickness direction and a barrier layer at the bottom of the micropores on one side of the aluminum substrate; the process of removing the barrier layer at the anode After the oxidation treatment process, the barrier layer of the anodized film is removed; the metal filling process, after the barrier layer removal process, electrolytic plating is performed to fill the inside of the micropores; and the substrate removal process, after the metal filling process, is removed An aluminum substrate is used to obtain a metal-filled fine structure.

<Anodic oxidation process> The anodizing process is to form an anode having micropores existing in the thickness direction and a barrier layer present at the bottom of the micropores by performing anodization on one side of the aluminum substrate Process of oxide film. The anodizing treatment can use a conventionally well-known method, but from the viewpoint of improving the regularity of the micropore arrangement and guaranteeing anisotropic conductivity, it is preferable to use the self-regulation method or constant voltage treatment. Here, regarding the self-regulation method of anodizing treatment or constant voltage treatment, it is possible to implement the same treatments as those described in paragraphs <0056> to <0108> and [FIG. 3] of JP-A-2008-270158. deal with.

<Barrier layer removal process> The barrier layer removal process is a process of removing the barrier layer of the anodized film after the anodizing process. By removing the barrier layer, a part of the aluminum substrate is exposed through the micropores. The method of removing the barrier layer is not particularly limited. For example, a method of electrochemically dissolving the barrier layer at a lower potential than that in the anodizing process of the anodizing process (hereinafter, also referred to as "electrolytic removal process" "); The method of removing the barrier layer by etching (hereinafter, also referred to as "etching removal treatment".); The method of combining these (especially, after performing the electrolytic removal treatment, removing by etching removal treatment) Remaining barrier method); etc.

<Electrolytic Removal Treatment> The electrolytic removal treatment is not particularly limited as long as it is performed at a potential lower than the potential (electrolytic potential) in the anodizing treatment process of the anodizing treatment process. The electrolytic dissolution treatment can be carried out continuously with the anodizing treatment, for example, by reducing the electrolytic potential at the end of the anodizing treatment process.

Regarding the conditions other than the electrolytic potential in the electrolytic removal treatment, the same electrolytic solution and treatment conditions as the above-mentioned conventionally known anodizing treatment can be used. In particular, as described above, when the electrolytic removal treatment and the anodizing treatment are continuously performed, it is preferable to use the same electrolytic solution for the treatment.

(Electrolysis Potential) It is preferable to reduce the electrolytic potential in the electrolytic removal process continuously or stepwise (stepwise) to a potential lower than the electrolytic potential in the anodizing process. Here, from the viewpoint of the withstand voltage of the barrier layer, the reduction (step width) when the electrolytic potential is reduced stepwise is preferably 10 V or less, more preferably 5 V or less, and even more preferably 2 V or less. In addition, from the viewpoint of productivity and the like, the voltage drop rate when continuously or stepwise reducing the electrolytic potential is preferably 1 V/sec or less, more preferably 0.5 V/sec or less, and further preferably 0.2 V/sec or less. .

<Etching and Removal Treatment> The etching and removal treatment is not particularly limited, and may be chemical etching treatment using acid aqueous solution or alkaline aqueous solution to dissolve, or dry etching treatment.

(Chemical etching treatment) The removal of the barrier layer by chemical etching treatment is, for example, immersing the structure after the anodizing process in an acid aqueous solution or an alkaline aqueous solution, filling the pores with an acid aqueous solution or an alkaline aqueous solution, and then adjusting the pH ( (Hydrogen ion index) The method of contacting the buffer solution with the surface of the opening side of the micropores of the anodized film can selectively dissolve only the barrier layer.

Here, when an acid aqueous solution is used, it is preferable to use an aqueous solution of inorganic acids such as sulfuric acid, phosphoric acid, nitric acid, and hydrochloric acid or a mixture of these. In addition, the concentration of the acid aqueous solution is preferably 1% by mass to 10% by mass. The temperature of the acid aqueous solution is preferably 15°C to 80°C, more preferably 20°C to 60°C, and even more preferably 30°C to 50°C. On the other hand, when an aqueous alkali solution is used, it is preferable to use an aqueous solution selected from at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. In addition, the concentration of the alkaline aqueous solution is preferably 0.1% by mass to 5% by mass. The temperature of the alkaline aqueous solution is preferably 10°C to 60°C, more preferably 15°C to 45°C, and even more preferably 20°C to 35°C. In addition, the alkaline aqueous solution may contain zinc and other metals. Specifically, for example, a 50 g/L, 40° C. phosphoric acid aqueous solution, 0.5 g/L, 30° C. sodium hydroxide aqueous solution, 0.5 g/L, 30° C. potassium hydroxide aqueous solution, or the like can be suitably used. In addition, as the pH buffer solution, a buffer solution corresponding to the above-mentioned acid aqueous solution or alkaline aqueous solution can be suitably used.

In addition, the immersion time in the acid aqueous solution or the alkali aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and still more preferably 15 minutes to 60 minutes.

(Dry etching process) It is preferable to use a gas type such as Cl ₂ /Ar mixed gas for the dry etching process.

<Metal Filling Process> The metal filling process is a process of performing electrolytic plating to fill the inside of the micropores in the anodized film after the barrier removal process, for example, Japanese Patent Laid-Open No. 2008-270158 The methods described in paragraphs <0123> to <0126> of the gazette and [FIG. 4] are the same (electrolytic plating method or electroless plating method). In addition, in the electrolytic plating method or the electroless plating method, an aluminum substrate exposed through micropores after the above-mentioned barrier layer removal process can be used as an electrode.

<Substrate Removal Process> The substrate removal process is the process of removing the aluminum substrate to obtain the metal-filled microstructure after the metal-filling process. As a method of removing the aluminum substrate, for example, a method of using a processing liquid to dissolve only the aluminum substrate without dissolving the metal filled in the micropores in the metal filling process and the anodized film as an insulating base material, etc. .

Examples of the treatment liquid include mercury chloride, bromine/methanol mixtures, bromine/ethanol mixtures, aqua regia, and hydrochloric acid/copper chloride mixtures. Among them, hydrochloric acid/copper chloride mixtures are preferred. As the concentration of the treatment liquid, 0.01 mol/L to 10 mol/L is preferable, and 0.05 mol/L to 5 mol/L is more preferable. The treatment temperature is preferably -10°C to 80°C, and more preferably 0°C to 60°C.

[Finishing Process] The trimming process is a process in which only a part of the insulating base material on the surface of the anisotropic conductive member after the formation process of the conductive path is removed to make the conductive path protrude. Here, the trimming treatment is not particularly limited as long as it does not dissolve the metal constituting the conductive path. For example, when an acid aqueous solution is used, an aqueous solution using inorganic acids such as sulfuric acid, phosphoric acid, nitric acid, and hydrochloric acid or a mixture of these is preferred good. Among them, an aqueous solution not containing chromic acid is preferred from the viewpoint of excellent safety. The concentration of the acid aqueous solution is preferably 1% by mass to 10% by mass. The temperature of the acid aqueous solution is preferably 25°C to 60°C. On the other hand, when an aqueous alkali solution is used, it is preferable to use an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1% by mass to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20°C to 50°C. Specifically, for example, a 50 g/L phosphoric acid aqueous solution at 40° C., a 0.5 g/L sodium hydroxide aqueous solution at 30° C. or a 0.5 g/L potassium hydroxide aqueous solution at 30° C. can be suitably used. The immersion time in the acid aqueous solution or the alkali aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and even more preferably 15 minutes to 60 minutes. Here, when the immersion treatment (dressing treatment) for a short time is repeated, the immersion time refers to the total of each immersion time. In addition, a cleaning process can be performed between each immersion process.

When the height of the protruding portion of the via is strictly controlled during the trimming process, after the process of forming the via, the insulating substrate and the end of the via are processed into the same plane, then the insulation is selectively removed (trimmed) Sexual substrates are preferred. Here, as a method of processing into the same plane, for example, physical polishing (for example, free abrasive particle polishing, back surface polishing, planing, etc.), electrochemical polishing, or a combination of these, etc. may be mentioned.

In addition, after the above-mentioned via formation process or trimming process, it is possible to perform heat treatment for the purpose of reducing strain in the via formed with the filling of the metal. From the viewpoint of suppressing the oxidation of the metal, the heat treatment is preferably performed in a reducing environment. Specifically, it is preferably performed at an oxygen concentration of 20 Pa or less, and more preferably performed under vacuum. Here, vacuum refers to the state of a space where the gas density or gas pressure is lower than the atmosphere. In addition, it is preferable to perform heat treatment while pressurizing the material for the purpose of correction.

[Resin layer forming process] The resin layer forming process is a process of forming a resin layer on the surface of the insulating base material and the protruding portion of the via after the finishing process. Here, as a method of forming the resin layer, for example, a resin composition containing the above-mentioned antioxidant material, a polymer material, a solvent (for example, methyl ethyl ketone, etc.) and the like can be applied to the surface of the insulating substrate And the protruding part of the guide path, and let it dry, and the method of firing according to need. The coating method of the resin composition is not particularly limited, and for example, gravure coating method, reverse coating method, die coating method, blade coating method, roll coating method, air knife coating method, screen coating method can be used , Bar coating method, curtain coating method and other conventionally known coating methods. In addition, the drying method after coating is not particularly limited, and examples thereof include treatment in the atmosphere at 0°C to 100°C for several seconds to tens of minutes, and under reduced pressure at 0°C to 80°C. Heating at a temperature of ten minutes to several hours, etc. In addition, the firing method after drying differs depending on the polymer material used, so it is not particularly limited. When a polyimide resin is used, for example, heating at 160°C to 240°C for 2 minutes to For a treatment of 60 minutes, etc., when an epoxy resin is used, for example, a treatment of heating at a temperature of 30°C to 80°C for 2 to 60 minutes can be mentioned.

In the manufacturing method, each of the above-mentioned processes can perform each process in a single piece, or it can continuously process the aluminum coil as a raw material with a web. Moreover, when performing continuous processing, it is preferable to provide an appropriate cleaning process and a drying process between each process.

The present invention is basically constructed as described above. In the above, the semiconductor device, the laminated body, the manufacturing method of the semiconductor device, and the manufacturing method of the laminated body of the present invention have been described in detail, but the present invention is not limited to the above-mentioned embodiment, and can be carried out without departing from the gist of the present invention Various improvements or changes. [Example]

Hereinafter, examples will be given to more specifically describe the features of the present invention. The materials, reagents, usage amount, material quality, ratio, processing contents, processing steps, etc. shown in the following examples can be appropriately changed as long as they do not depart from the spirit of the present invention. Therefore, the scope of the present invention should not be limitedly interpreted by the specific examples shown below. In this example, the semiconductor devices of Examples 1 to 12 and Comparative Examples 1 to 3 were fabricated. For the semiconductor devices of Examples 1 to 12 and Comparative Examples 1 to 3, any of the anisotropic conductive members of the anisotropic conductive materials of Samples 1 to 3 shown in Table 1 below was used . For the semiconductor devices of Examples 1 to 12 and Comparative Examples 1 to 3, the crack length was measured, and the conduction reliability and the insulation reliability related to electrical insulation were evaluated. The evaluation results of conduction reliability and insulation reliability are shown in Table 2 below.

Next, a method of measuring the average value of the total crack length per unit area will be described. For each semiconductor device of Examples 1 to 12 and Comparative Examples 1 to 3, the inside was observed with an infrared microscope. The semiconductor wafer and the interposer transmit infrared light, but the anisotropic conductive member does not transmit infrared light. Therefore, if infrared light is used, cracking of the anisotropic conductive member can be clearly detected. For the infrared microscope, the semiconductor/FPD inspection microscope MX61 (trade name) manufactured by Olympus Corporation was used. For the lens, an objective lens LMRLN5XIR (trade name) for observation in the near infrared region (700 nm to 1300 nm) manufactured by Olympus Corporation was used. In addition, an automatic XY stage for an orthophotoscope manufactured by Marzhauser was used for the stage.

An infrared microscope is used to acquire an inspection image of the semiconductor device looking down on the entire area, and the acquired inspection image is subjected to a binarization process to obtain a binarized image of the inspection image. The length of the black part of the binarized image was measured. Cracks were extracted from the black portion with 10 μm as a threshold. The total length was obtained for the extracted cracks. In addition, the area of the binarized image was obtained from the field of view area. The total crack length per unit area was obtained from the crack length and the area of the binarized image. Then, the average value of the total crack lengths per unit area obtained was obtained. In addition, in the semiconductor device, the electrode connection region where the electrode is connected and the electrode non-connection region where the electrode is not connected are specified in advance. The average value of the total crack length per unit area in the electrode connection area where the electrodes are connected is taken as the crack length of the electrode portion, and the average value of the total crack length per unit area in the electrode non-connection area where the electrodes are not connected is taken as Crack length of non-electrode part.

Next, the conduction reliability and insulation reliability will be described. <Wafer> A wafer with a Cu pad (wafer 1) and an interposer were prepared. Inside these, a daisy chain pattern for measuring on-resistance and a comb pattern for measuring insulation resistance are included. The insulating layer is SiN, and the step difference between the insulating layer and the Cu pad surface is shown in Example 1 to Example 12 and Comparative Example 1 to Comparative Example 3. The step difference between the insulating layer and the Cu pad surface is the amount of electrode protrusion or the amount of electrode embedding described later. For wafer 1, a wafer having a wafer size of 8 mm square and an electrode area (copper pillar) to wafer area ratio of 25% was prepared. The wafer 1 corresponds to a semiconductor wafer. The interposer includes lead wires around, so a wafer size of 10 mm square was prepared. The wafer 2 is a printed wiring board wafer including a daisy chain pattern and a comb-tooth pattern for measuring insulation resistance. <Conduction Reliability> The signal wire for resistance measurement was joined by the lead-out wiring pad soldered to the daisy-chain pattern part of the insert. A temperature cycle test was carried out on the samples prepared in the evaluation test of the electrical conductivity reliability under the condition of (-55°C/+85°C). The resistance value is measured every 500 cycles and measured to 2500 cycles. Based on the result of the resistance value, the evaluation was performed according to the evaluation criteria shown below. The evaluation results are shown in the conduction reliability column of Table 2 below. "A": The rate of change of resistance value is less than 10% "B": The rate of change of resistance value is more than 10% and less than 50% "C": The rate of change of resistance value is more than 50% and less than 100% "D": The rate of change of the resistance value is 100% or more "E": It cannot be turned on from the beginning (OPEN failure occurs)

<Insulation Reliability> The signal wire for resistance measurement was joined by the lead wire pad soldered to the comb-tooth pattern part of the insert. For the samples prepared in the evaluation test of the electrical conductivity reliability, a temperature cycle test was carried out under the condition of (-55°C/+85°C). The resistance value is measured every 500 cycles and measured to 2500 cycles. Based on the result of the change rate of the resistance value, the evaluation was performed according to the evaluation criteria shown below. The evaluation results are shown in the insulation reliability column of Table 2 below. In addition, regarding the evaluation of the insulation reliability, those who were evaluated as "D" or "E" in the conduction reliability test did not perform the subsequent insulation reliability test. "A": The rate of change of resistance value is less than 10% "B": The rate of change of resistance value is more than 10% and less than 50% "C": The rate of change of resistance value is more than 50% and less than 100% "D": The rate of change of the resistance value is more than 100% "-": the conduction reliability test is "D" or "E", and the insulation reliability test is not performed.

Hereinafter, Examples 1 to 12 and Comparative Examples 1 to 3 will be described. (Example 1) Example 1 is a semiconductor device obtained by joining a semiconductor wafer and an interposer via an anisotropic conductive member. The above-mentioned wafer 1 is used as a semiconductor wafer. Sample 1 was used for the anisotropic conductive member. With regard to the bonding conditions of the semiconductor device, the pressure was set to 5 MPa under vacuum, and after holding at a temperature of 150° C. for 5 minutes, it was held at a temperature of 250° C. for 10 minutes. Then, as post-hardening, it was held under a vacuum at a pressure of 0 MPa and a temperature of 250° C. for 30 minutes. At this time, in order to prevent the position of the wafer 1 from shifting to the Cu pad of the interposer, the alignment marks formed at the corners of the wafer are aligned and bonded. In addition, the electrode shape of the semiconductor wafer is protruding and flat (see FIG. 9 ). The flatness refers to a state where the end surface 30c (see FIG. 9) is flat. The protrusion amount of the electrode was set to 200 nm. In addition, the electrode shape of the insert is protruding and flat (see FIG. 9 ). In addition, the electrode surface roughness of the semiconductor wafer and the interposer is set to 100 nm. As for the electrode surface roughness, the surface roughness (Ra) was evaluated by measuring the unevenness of the electrode surface using an atomic force microscope (AFM). The electrode surface roughness was set to the average value of the surface roughness of 10 electrode surfaces.

(Example 2) Example 2 is the same as Example 1 except that Sample 2 is used for the anisotropic conductive member. (Example 3) Example 3 is the same as Example 1 except that the electrode shape of the insert is buried and flat (see FIG. 10 ). In addition, in Example 3, the protrusion amount of the electrode was 200 nm, and the embedding amount of the electrode was 200 nm. (Example 4) Example 4 is the same as Example 1 except that Sample 2 is used in the anisotropic conductive member and the electrode shape of the insert is buried and flat (see FIG. 10 ). In addition, in Example 4, the protrusion amount of the electrode was 200 nm, and the embedding amount of the electrode was 200 nm.

(Example 5) In Example 5, the sample 2 was used for the anisotropic conductive member, the electrode shape of the semiconductor wafer was protruding and convex (see FIG. 11), and the electrode shape of the insert was It is the same as in Example 1 except that it is protruding and concave (see FIG. 11 ). In addition, in Example 5, the protrusion amount of the convex electrode was 200 nm, and the size of the convex portion was 80% of the electrode area. In addition, the embedded amount of the concave electrode was 200 nm, and the size of the concave portion was 80% of the electrode area.

(Example 6) Example 6 is the same as Example 1 except that the electrode shape of the insert is buried and flat (see FIG. 10) and the electrode surface roughness is 10 nm. In addition, in Example 6, the protrusion amount of the electrode was 200 nm, and the embedding amount of the electrode was 200 nm. (Example 7) In Example 7, the sample 2 was used as an anisotropic conductive member, the electrode shape of the insert was buried and flat (see FIG. 10), and the electrode surface roughness was set to 10 nm. Except for the points, it is the same as in Example 1. In addition, in Example 7, the protrusion amount of the electrode was 200 nm, and the embedding amount of the electrode was 200 nm.

(Embodiment 8) Embodiment 8 except that the combination of the semiconductor wafer and the semiconductor wafer, the electrode shape of the lower semiconductor wafer is buried and flat (see FIG. 10), and any semiconductor wafer The electrode surface roughness was set to the same as Example 1 except for the point of 1 nm. In addition, the above-mentioned wafer 1 is used for all semiconductor wafers. Furthermore, in Example 8, the amount of protrusion of the electrode was 200 nm, and the amount of embedding of the electrode was 200 nm. (Example 9) Example 9 except that the combination of the semiconductor wafer and the semiconductor wafer is used, the sample 2 is used for the anisotropic conductive member, and the electrode shape of the lower semiconductor wafer is buried and flat (See FIG. 10) This point is the same as that of Example 1 except that the surface roughness of any semiconductor wafer is set to 1 nm. In addition, the above-mentioned wafer 1 is used for all semiconductor wafers. Moreover, in Example 9, the protrusion amount of the electrode was 200 nm, and the embedding amount of the electrode was 200 nm.

(Example 10) Example 10 is the same as Example 1 except that Sample 2 is used for the anisotropic conductive member and the electrode surface roughness is 250 nm. (Example 11) Example 10 is the same as Example 1 except that Sample 2 is used for the anisotropic conductive member and the electrode surface roughness is set to 10 nm. (Example 12) Example 10 except that the sample 2 was used for the anisotropic conductive member, the electrode shape of the semiconductor wafer was flat (see FIG. 8), and the electrode surface roughness was 100 nm Except this point, it is the same as that of Example 1.

(Comparative Example 1) Comparative Example 1 is the same as Example 1 except that Sample 3 is used for the anisotropic conductive member. (Comparative Example 2) Comparative Example 2 except that the combination of the interposer and the printed wiring board, the use of Sample 3 for an anisotropic conductive member, and the point of setting the electrode surface roughness to 1000 nm It is the same as Example 1. The wafer 2 is used in the printed wiring board. (Comparative Example 3) Comparative Example 3 except that the combination of the interposer and the printed wiring board, the use of Sample 2 for an anisotropic conductive member, and the point of setting the electrode surface roughness to 1000 nm It is the same as Example 1. The wafer 2 is used in the printed wiring board.

Hereinafter, the anisotropic conductive members used in Samples 1 and 2 will be described. [Anisotropic conductive member] <Fabrication of aluminum substrate> Use containing Si: 0.06% by mass, Fe: 0.30% by mass, Cu: 0.005% by mass, Mn: 0.001% by mass, Mg: 0.001% by mass, Zn: 0.001% by mass %, Ti: 0.03% by mass and the remaining part is aluminum alloy with Al and inevitable impurities to prepare molten metal. After molten metal treatment and filtration, a 500 mm thick ingot with a width of 1200 mm is produced by DC casting. Next, after the surface was cut with an average thickness of 10 mm by a face cutter, the soaking was maintained at 550°C for about 5 hours, and when the temperature was lowered to 400°C, a rolled plate with a thickness of 2.7 mm was produced using a hot rolling machine . In addition, after performing heat treatment at 500° C. using a continuous annealing machine, it was finished by cold rolling to a thickness of 1.0 mm to obtain an aluminum substrate of JIS 1050 material. After forming the aluminum substrate into a wafer shape with a diameter of 200 mm (8 inches), each process shown below was performed.

<Electrolytic polishing process> The electrolytic polishing process was performed on the aluminum substrate under the conditions of a voltage of 25 V, a liquid temperature of 65° C., and a liquid flow rate of 3.0 m/min using the electrolytic polishing liquid of the following composition. The cathode is a carbon electrode, and the power supply uses GP0110-30R (manufactured by TAKASAGO LTD.). In addition, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE Corporation). (Composition of electrolytic polishing liquid) ・85% by mass phosphoric acid (reagent manufactured by Wako Pure Chemical Industries, Ltd.) 660mL pure water 160mL sulfuric acid 150mL ethylene glycol 30mL

<Anodic Oxidation Process> Next, according to the steps described in Japanese Patent Laid-Open No. 2007-204802, the aluminum substrate after the electrolytic polishing process is subjected to anodization by its own regularization method. In an electrolytic solution of 0.50 mol/L oxalic acid, the aluminum substrate after electrolytic polishing was subjected to a pre-anodizing treatment for 5 hours under the conditions of a voltage of 40 V, a liquid temperature of 16° C., and a liquid flow rate of 3.0 m/min. Then, the aluminum substrate after the pre-anodization treatment was immersed in a mixed aqueous solution (liquid temperature: 50° C.) of 0.2 mol/L chromic anhydride and 0.6 mol/L phosphoric acid for 12 hours for film release treatment. Then, in an electrolyte of 0.50 mol/L oxalic acid, re-anodizing treatment was carried out for 3 hours and 45 minutes under the conditions of a voltage of 40 V, a liquid temperature of 16° C., and a liquid flow rate of 3.0 m/min to obtain an anodized film with a thickness of 30 μm. membrane. In addition, in the pre-anodizing treatment and the re-anodizing treatment, the cathode was set as the stainless steel electrode, and the power source used GP0110-30R (manufactured by TAKASAGO LTD.). In addition, NeoCool BD36 (manufactured by Yamato Scientific Co., Ltd.) was used for the cooling device, and a pair stirrer PS-100 (manufactured by EYELA TOKYO RIKAKIKAI CO., LTD.) was used for the stirring and heating device. In addition, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE Corporation).

<Barrier layer removal process> Next, under the same treatment liquid and processing conditions as the above anodizing treatment, an electrolytic treatment (electrolytic removal treatment) was carried out while continuously reducing the voltage from 40V to 0.2V at a voltage drop rate of 0.2V/sec. . Then, an etching treatment (etching removal treatment) immersed in 5 mass% phosphoric acid at 30° C. for 30 minutes was performed to remove the barrier layer located at the bottom of the micropores of the anodized film, and the aluminum was exposed through the micropores.

Here, the average opening diameter of the micropores existing on the anodized film after the barrier layer removal process is 60 nm. In addition, the average opening diameter was taken by FE-SEM (Field emission-Scanning Electron Microscope) field photograph (magnification: 50000 times), and it was calculated as the average value of 50-point measurement. In addition, the average thickness of the anodized film after the barrier layer removal process is 30 μm. In addition, the average thickness is FIB (Focused Ion Beam: Focused Ion Beam), the anodized film is cut with respect to the thickness, and the surface photo of the cross section is taken by FE-SEM (magnification 50000 times), calculated as 10 The measured average. In addition, the density of micropores present in the anodized film is about 100 million per mm ² . In addition, the density of the micropores was measured and calculated by the methods described in paragraphs <0168> and <0169> of Japanese Patent Laid-Open No. 2008-270158. In addition, the regularity of the micropores present in the anodized film was 92%. In addition, the surface photograph was taken by FE-SEM (magnification 20,000 times), and the degree of regularization was measured by the method described in paragraphs <0024> to <0027> of JP-A-2008-270158.

<Metal Filling Process> Next, electrolytic plating was performed using an aluminum substrate as a cathode and platinum as a positive electrode. Specifically, using a copper plating solution having the composition shown below, a constant-current electrolysis was performed to produce a metal-filled fine structure in which micropores are filled with copper. Here, in constant current electrolysis, using a plating device manufactured by YAMATOMO·MS CO., LTD. and a power supply (HZ-3000) manufactured by HOKUTO DENKO CORP., cyclic voltammetry was performed in the plating solution to confirm precipitation After the electric potential, the treatment was carried out under the conditions shown below. (Composition and conditions of copper plating solution) • Copper sulfate 100g/L • Sulfuric acid 50g/L • Hydrochloric acid 15g/L • Temperature 25℃ • Current density 10A/dm ²

<Polishing Process> Next, the surface of the metal-filled structure is subjected to CMP (Chemical Mechanical Polishing) treatment and polished by 5 μm from the surface, thereby smoothing the surface. As the CMP slurry, PNANERLITE-7000 manufactured by Fujimi Inc. was used.

Observe the surface of the anodized film after the metal is filled in the micropores with FE-SEM, thereby observing the presence or absence of sealing due to metal in 1000 micropores, and calculating the sealing ratio (number of sealed micropores/ 1000), the result is 96%. In addition, the FIB was used to cut the anodized film after filling the pores with metal in the thickness direction, and the surface of the cross section was taken by FE-SEM (magnification 50,000 times) to confirm the inside of the pores. As a result, it can be seen that the sealed micropores are completely filled with metal.

<Substrate Removal Process> Next, the aluminum substrate was dissolved and removed by immersion in a 20% by mass mercury chloride aqueous solution (mercury ascending) at 20° C. for 3 hours, thereby producing a metal-filled fine structure. <Polishing process> Next, the surface on the side where the aluminum substrate was removed, and the back surface of the metal-filled fine structure were subjected to CMP (Chemical Mechanical Polishing) treatment and polished by 5 μm, thereby making the back surface of the metal-filled fine structure Become smooth. As the CMP slurry, PNANERLITE-7000 manufactured by Fujimi Inc. was used.

<Finishing process> The metal-filled fine structure after the substrate removal process is immersed in an aqueous solution of sodium hydroxide (concentration: 5 mass%, liquid temperature: 20°C), and the immersion time is selected so that the height of the protrusion becomes 500 nm The surface of the anodized film of aluminum was dissolved in water, followed by washing with water and drying to fabricate a structure in which a cylindrical protrusion of copper as a conductive path was formed. <Process for forming the adhesive layer> An anisotropic conductive member was produced by forming the adhesive layer on the structure after the trimming process using the method shown below.

<Adhesive layer> LTC9320 is used as a commercially available product of a polyamic acid ester solution (including dimethyl sulfoxide, trialkoxyamidocarboxysilane, oxime derivative) using γ-butyrolactone as a solvent (Manufactured by FUJIFILM Electronic Materials Co., Ltd.). After applying this solution to the surface of the insulating base material with protruding vias and drying it to form a film, it was carried out in a nitrogen replacement reactor (oxygen concentration of 10 ppm or less) at 200°C for 3 hours. Chemical reaction, thereby forming a bonding layer containing a polyimide resin layer with a thickness of 500 nm. In addition, the thickness of the adhesive layer was adjusted by adding a solvent (MEK (methyl ethyl ketone)). In addition, the average thickness of the metal-filled fine structure other than the resin layer was 20 μm.

Hereinafter, the anisotropic conductive member used in Sample 3 will be described. [Anisotropic Conductive Member] The photomask and a commercially available photosensitive glass substrate (trade name: PEG3 manufactured by HOYA CORPORATION: 5 inches square, plate thickness 0.65 mm) were closely contacted and irradiated with ultraviolet rays. In addition, the irradiation condition was a wavelength of 320 nm and an exposure amount of 550 mJ/cm ² . In addition, for the mask pattern, a total of 90,000 circular patterns with a diameter of 1 μm were arranged at a pitch of 300 μm in the vertical and horizontal directions. After irradiating ultraviolet rays, heat treatment was carried out in a heating furnace at 550°C for 1 hour. Then, using abrasive grains containing Al ₂ O ₃ with a particle size of #1000, the surface and back surface of the photosensitive glass substrate are ground by a double-sided flat grinding disk, and further using cerium oxide abrasive grains and using a double-sided grinding machine Finishing polishing (finishing polishing). The thickness of the photosensitive glass substrate after fine grinding is 0.3 mm, and the combined cutting margin of the front and back surfaces is 0.35 mm.

Next, apply a photosensitive polyimide resin or epoxy resin composition to be described later so that the film thickness becomes 2 μm, and use the same mask pattern as described above in such a manner that the position of the circular pattern overlaps the above Exposure and development. Then, a mixed acid of sulfuric acid (sulfuric acid concentration: 20% by mass) in an aqueous solution of 7 vol% hydrofluoric acid was added to dissolve and remove the exposed portion of the photosensitive glass. Next, the copper electrode was brought into close contact with one surface of the glass substrate, the copper electrode was used as a cathode, and platinum was used as a positive electrode for electrolytic plating. A mixed solution of copper sulfate/sulfuric acid/hydrochloric acid=200/50/15 (g/L) was used as an electrolyte while maintaining the state at 25°C, and a constant voltage pulse electrolysis was used to produce through holes filled with copper The structure (precursor of anisotropic conductive connecting member).

Here, the constant voltage pulse electrolysis system uses a plating device manufactured by YAMATOMO·MS CO., LTD. and uses a power supply (HZ-3000) manufactured by HOKUTO DENKO CORP., and performs precipitation cyclic voltammetry in the plating solution to confirm precipitation After the potential, the potential of the copper electrode in close contact with the glass was set to -2V. In addition, the pulse waveform of constant voltage pulse electrolysis is a rectangular wave. Specifically, the total electrolysis treatment time was set to 300 seconds, a rest time of 40 seconds was set between each electrolysis treatment, and 5 times of electrolysis treatment with an electrolysis time of 60 seconds was performed.

(Polyimide resin) As the polyimide resin, a photosensitive polyimide resin (alkali-developed positive photosensitive polyimide: PIMEL AM-200 series, manufactured by ASAHI KASEI E-MATERIALS CORPORATION) was used. (Epoxy resin composition) 10 parts of a bisphenol A epoxy resin with an epoxy equivalent of 250 g/equivalent as a low epoxy equivalent epoxy resin and an epoxy equivalent of 8690 g/equivalent as an epoxy equivalent of a high epoxy equivalent epoxy resin 90 parts of bisphenol F phenoxy resin, 4,4-bis[bis(β-hydroxyethoxy)phenylsulfinyl]phenylsulfide-bis(hexafluoroantimonate) as a photoacid generator ) 9 parts were dissolved in dioxane to prepare a photosensitive epoxy resin adhesive composition with a solid content concentration of 50%.

In addition, the resin substrate of the support column of Table 1 below shows the resin substrate using FR-4 (4 type flame retardant). The low-viscosity adhesive in the adhesive component column of Table 1 below is the electronic and optical E-MASKR-50EP manufactured by Nitto Denko Corporation. The thermal peeling adhesive in the column of adhesive members in Table 2 below is a thermal peeling sheet (REVALPHA (registered trademark) No. 3198) manufactured by Nitto Denko Corporation.

[Table 1]

[Table 2]

Compared to Comparative Examples 1 to 3, Examples 1 to 12 have good conduction reliability and insulation reliability. In addition, if the crack length of the electrode portion is short and the crack length of the non-electrode portion is long as in Example 7 and Example 9, the conduction reliability is good compared to other Examples 1 to 6 and Example 8. It can be seen that, as in Example 3, Example 4, Example 6, and Example 8, if the crack length of the non-electrode portion is long, the anisotropic conductive member is physically separated and the electrical insulation becomes high, thereby ensuring reliable insulation Sex becomes good. In addition, it can be seen that if the surface roughness of the electrode is 10 nm or less as in Example 6 to Example 9 and Example 11, the crack length of the electrode portion tends to be short. Furthermore, it can be seen that if the shape of the upper electrode and the shape of the lower electrode are nested like the convex shape of the upper electrode and the concave shape of the lower electrode, as in Example 3, Example 4, and Example 6 to Example 9, then the Cracks are generated around the periphery, and the crack length of the non-electrode portion becomes longer.

10‧‧‧Semiconductor device

11‧‧‧Layered body

12, 14, 52‧‧‧‧Semiconductor chip

14a, 32a, 34a, 36a, 40a, 40b

14b‧‧‧Back

16‧‧‧Semiconductor chip

16a‧‧‧Surface

18‧‧‧Insert

20‧‧‧Anisotropic conductive member

22‧‧‧Crack

24‧‧‧Electrode connection area

26‧‧‧electrode non-connected area

30a, 30b, 31a, 31b

30c‧‧‧End

30d‧‧‧Convex

30e‧‧‧recess

32‧‧‧Semiconductor layer

34‧‧‧ Redistribution layer

36‧‧‧ Passivation layer

37‧‧‧Wiring

38‧‧‧Pad

39‧‧‧Resin layer

40‧‧‧Insulating base material

41‧‧‧through

42‧‧‧Guide

42a, 42b ‧‧‧ protruding part

44‧‧‧Resin layer

46‧‧‧Support

47‧‧‧bonded members

48‧‧‧support layer

49‧‧‧adhesive layer

50、51‧‧‧Anisotropic conductive material

54‧‧‧Sensor chip

56‧‧‧Lens

58、60‧‧‧Semiconductor wafer

58a, 60a‧‧‧surface

58b‧‧‧Back

Ds‧‧‧Layer direction

d‧‧‧Diameter

h‧‧‧thickness

p‧‧‧Distance between centers

w‧‧‧Width

x‧‧‧ direction

Z‧‧‧thickness direction

Z1‧‧‧ direction from back to front

Z2‧‧‧Front to back direction

γ‧‧‧Sag

δ‧‧‧ protrusion amount

FIG. 1 is a schematic diagram showing a first example of a semiconductor device according to an embodiment of the present invention. 2 is a plan view showing an example of the configuration of an anisotropic conductive member used in a semiconductor device according to an embodiment of the present invention. 3 is a schematic cross-sectional view showing an example of the structure of an anisotropic conductive member used in a semiconductor device according to an embodiment of the present invention. 4 is a schematic cross-sectional view showing an example of the structure of an anisotropic conductive material. 5 is a schematic diagram showing an example of an anisotropic conductive member used in a semiconductor device according to an embodiment of the present invention. 6 is a schematic diagram of another example of the anisotropic conductive member used in the semiconductor device according to the embodiment of the present invention. 7 is a schematic diagram showing a configuration example of an anisotropic conductive member used in a semiconductor device according to an embodiment of the present invention. 8 is a schematic cross-sectional view showing a first example of the configuration of an electrode of a semiconductor wafer of a semiconductor device according to an embodiment of the present invention. 9 is a schematic cross-sectional view showing a second example of the configuration of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention. 10 is a schematic cross-sectional view showing a third example of the configuration of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention. 11 is a schematic cross-sectional view showing a fourth example of the configuration of the electrode of the semiconductor wafer of the semiconductor device according to the embodiment of the present invention. 12 is a schematic cross-sectional view showing a first example of the semiconductor device according to the embodiment of the present invention. 13 is a schematic diagram showing a second example of the semiconductor device according to the embodiment of the present invention. 14 is a schematic diagram showing a third example of the semiconductor device according to the embodiment of the present invention. 15 is a schematic diagram showing a fourth example of the semiconductor device according to the embodiment of the present invention. 16 is a schematic diagram showing a manufacturing process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 17 is a schematic diagram showing a process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 18 is a schematic diagram showing a process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 19 is a schematic diagram showing a process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 20 is a schematic diagram showing a process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. 21 is a schematic diagram showing a process of the first example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. 22 is a schematic diagram showing a process of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. 23 is a schematic diagram showing a process of a modification of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. 24 is a schematic diagram showing a process of a modification of the first example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 25 is a schematic diagram showing a process of the second example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 26 is a schematic diagram showing a process of the second example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 27 is a schematic diagram showing a process of the second example of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 28 is a schematic diagram showing a process of a third example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 29 is a schematic diagram showing a process of the third example of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

Claims (16)

A semiconductor device having: an anisotropic conductive member, having an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating along the thickness direction of the insulating base material, and provided in a state of electrical insulation from each other; And at least two connected members each having an electrode; and at least one of the at least two connected members is a semiconductor element, and in the semiconductor device, the anisotropic conductive member has an electrode connection region connected to the electrode And the electrode non-connected area not connected to the electrode, the at least two connected members are electrically connected by the anisotropic conductive member, and the average value of the total crack length per unit area in the electrode connecting area It is 1 μm/mm ² or less. The semiconductor device as described in item 1 of the patent application range, wherein the average value of the total crack length per unit area in the electrode non-connection region not connected to the electrode is 0.01 μm/mm ² or more. The semiconductor device as described in item 1 of the patent application range, wherein the average value of the total crack length per unit area of the electrode connection region is less than the total cracks per unit area of the electrode non-connection region not connected to the electrode The average length. The semiconductor device according to any one of claims 1 to 3, wherein the surface of the connected member on which the electrode is provided has an insulating layer, and the electrode protrudes from the surface of the insulating layer. The semiconductor device according to any one of claims 1 to 3, wherein the at least two connected members electrically connected by the anisotropic conductive member include: electrodes having protrusions A member to be connected; and a member to be connected having an electrode having a concave portion partially recessed corresponding to the convex portion. The semiconductor device according to any one of claims 1 to 3, wherein the surface roughness of the surface of the connected member having the electrode is 10 nm or less. A laminate having: an anisotropic conductive member having an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating along the thickness direction of the insulating base material and being provided in a state of electrical insulation from each other; And at least two connected members, each having an electrode; and in the laminate, at least one of the connected members is a semiconductor element, the anisotropic conductive member has an electrode connection region connected to the electrode, and a non-connected member In the electrode non-connecting region where the electrode is connected, the at least two connected members are electrically connected by the anisotropic conductive member, and the average value of the total crack length per unit area in the electrode connecting region is 1 μm/ mm ² or less. The laminate as described in item 7 of the patent application range, wherein the average value of the total crack length per unit area in the electrode non-connected region not connected to the electrode is 0.01 μm/mm ² or more. The laminate as described in item 7 of the patent application range, wherein the average crack length per unit area of the electrode connection area is less than the total crack length per unit area of the electrode non-connection area not connected to the electrode The average length. The laminated body according to any one of claims 7 to 9, wherein the surface of the connected member on which the electrode is provided has an insulating layer, and the electrode protrudes from the surface of the insulating layer. The laminated body according to any one of claims 7 to 9, wherein the at least two connected members electrically connected by the anisotropic conductive member include: electrodes having protrusions A member to be connected; and a member to be connected having an electrode having a concave portion partially recessed corresponding to the convex portion. The laminate as described in any one of claims 7 to 9, wherein the surface roughness of the surface of the connected member having the electrode is 10 nm or less. A method for manufacturing a semiconductor device having an anisotropic conductive member, having an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating along the thickness direction of the insulating base material Insulated state setting; and at least two connected members, each having an electrode; and at least one of the at least two connected members is a semiconductor element, the semiconductor device manufacturing method has the following process: in the at least two The state where the anisotropic conductive member is arranged between the connected members, the at least two connected members are electrically connected by the anisotropic conductive member, and the surface of the connected member on which the electrode is provided With an insulating layer, the electrode protrudes relative to the surface of the insulating layer. The method of manufacturing a semiconductor device as described in item 13 of the patent application range, wherein the at least two connected members electrically connected by the anisotropic conductive member include: a connected member having an electrode having a convex portion; And a member to be connected having an electrode having a concave portion that is partially recessed corresponding to the convex portion. A method for manufacturing a laminated body having an anisotropic conductive member, an insulating base material and a plurality of conductive paths, the plurality of conductive paths penetrating along the thickness direction of the insulating base material Insulated state setting; and at least two connected members, each having an electrode; and at least one of the connected members is a semiconductor element, and the method of manufacturing the laminate has the following process: in the at least two connected members A state in which the anisotropic conductive member is disposed therebetween, the at least two connected members are electrically connected by the anisotropic conductive member, and an insulating layer is provided on the surface of the connected member on which the electrode is provided , The electrode protrudes relative to the surface of the insulating layer. The method for manufacturing a laminate as described in Item 15 of the patent application range, wherein the at least two connected members electrically connected by the anisotropic conductive member include: a connected member having an electrode having a convex portion; And a member to be connected having an electrode having a concave portion that is partially recessed corresponding to the convex portion.