TW201837489A - Method and circuit for detecting abnormal clock - Google Patents

Abstract

A method for detecting an abnormal clock is configured to detect whether an output clock of a chip is abnormal. The method includes: providing a first delay clock signal and a second delay clock signal in accordance with the output clock, in which the phases of the output clock, the first delay clock signal, and the second delay clock signal are different from each other; sampling the first delay clock signal with the second delay clock signal to detect whether the output clock is abnormal.

Description

 Abnormal clock detection method and circuit thereof  

The present disclosure relates to an abnormal clock detection method and a circuit thereof, and more particularly to an abnormal clock detection method and a circuit thereof applied to a wafer.

With the advancement of technology, electronic products continue to evolve, and the electronic products can operate normally, relying on accurate clock signals, so that the chips inside the electronic products can process the data or signals they receive in sequence. And transfer to the next level of circuitry at the correct time, or to retrieve the data correctly.

In a chip containing a high-speed clock signal, whether the clock signal is accurate or not is a test item that needs attention. The current common detection method is to use the test machine. However, because of the ability of the test machine, the pulse signal has When the transient anomaly or the clock signal is slightly distorted, it is usually not detected by the test machine.

The purpose of the present disclosure is to provide an abnormal clock detection method and circuit thereof, which are applied to an integrated circuit of a wafer, thereby enabling a user to more easily and accurately filter out wafers having abnormal clocks.

According to the above object of the present disclosure, an abnormal clock detection method is provided for detecting whether an output clock signal of a wafer is abnormal. The abnormal clock detection method includes: providing a first delayed clock signal and a second delayed clock signal according to the output clock signal, wherein the phase of the output clock signal, the first delayed clock signal and the second delayed clock signal are output Different from each other; and using the second delayed clock signal to sample the first delayed clock signal to determine whether an abnormality occurs in the output clock signal.

In some embodiments, the multi-phase generation circuit of the chip is configured to generate N delayed clock signals according to the output clock signal, wherein the phases of the N delayed clock signals and the output clock signals are different from each other, wherein The two delayed clock signals are the first delayed clock signal and the second delayed clock signal, where N is a positive integer greater than or equal to 4.

In some embodiments, the phase of the first delayed clock signal leads the phase of the second delayed clock signal, wherein the phase difference between the first delayed clock signal and the second delayed clock signal is between the output clock signal 2/N cycle to (N-2)/N cycle.

In some embodiments, the abnormal clock detection method uses the falling edge of the second delayed clock signal to sample the first delayed clock signal to detect whether the output clock signal is too slow, wherein the second delay is The falling edge of the clock signal samples the first delayed clock signal, and the low voltage level indicates that the output clock signal frequency is too slow.

In some embodiments, the abnormal clock detection method uses the rising edge of the second delayed clock signal to sample the first delayed clock signal to detect whether the output clock signal is too fast, wherein the second delay is The rising edge of the clock signal samples the first delayed clock signal as a result of the high voltage level, which means that the output clock signal frequency is too fast.

According to the above object of the present disclosure, an abnormal clock detection circuit is further provided for determining whether an abnormality occurs in an output clock signal of a chip. The abnormal clock detection circuit includes a multi-phase generation circuit and a sampling circuit. The multi-phase generating circuit is configured to provide the first delayed clock signal and the second delayed clock signal according to the output clock signal, wherein the phases of the output clock signal, the first delayed clock signal and the second delayed clock signal are not mutually the same. The sampling circuit is configured to sample the first delayed clock signal by using the second delayed clock signal to determine whether an abnormality occurs in the output clock signal.

In some embodiments, the multi-phase generating circuit is configured to generate N delayed clock signals according to the output clock signal, wherein the phases of the N delayed clock signals and the output clock signals are different from each other, wherein the N delays The two of the clock signals are the first delayed clock signal and the second delayed clock signal, where N is a positive integer greater than or equal to 4.

In some embodiments, the phase of the first delayed clock signal leads the phase of the second delayed clock signal, wherein the phase difference between the first delayed clock signal and the second delayed clock signal is between the output clock signal 2/N cycle to (N-2)/N cycle.

In some embodiments, the sampling circuit samples the first delayed clock signal by using the falling edge of the second delayed clock signal to detect whether the output clock signal is too slow, wherein the second delay clock signal The result of sampling the first delayed clock signal at the falling edge is that the low voltage level indicates that the output clock signal frequency is too slow.

In some embodiments, the sampling circuit samples the first delayed clock signal by using the rising edge of the second delayed clock signal to detect whether the output clock signal is too fast, wherein the second delay clock signal The result of sampling the first delayed clock signal by the rising edge is that the high voltage level represents that the output clock signal frequency is too fast.

The above described features and advantages of the present invention will be more apparent from the following description.

SIG‧‧‧ output clock signal

ABN‧‧‧ output

IN1‧‧‧ first input

IN2‧‧‧ second input

TSIG‧‧ cycle

TP‧‧‧ subphase

100‧‧‧Abnormal clock detection circuit

110‧‧‧Multiphase generation circuit

120‧‧‧Sampling circuit

122‧‧‧Low frequency clock detection circuit

122a, 122b, 124a, 124b‧‧‧ forward and reverse

124‧‧‧High frequency clock detection circuit

600‧‧‧ method

610, 620‧ ‧ steps

P1-P16‧‧‧Delayed clock signal

VDD‧‧‧ power supply

D‧‧‧Data input pin

CLK‧‧‧ timing pin

Q, Qb‧‧‧ output pin

A better understanding of the aspects of the present disclosure can be obtained from the following detailed description taken in conjunction with the drawings. It should be noted that, according to industry standard practices, the features are not drawn to scale. In fact, in order to make the discussion clearer, the dimensions of each feature can be arbitrarily increased or decreased.

FIG. 1 is a system block diagram of an abnormal clock detection circuit according to an embodiment of the present disclosure.

FIG. 2 is a timing diagram of an output clock signal and a delayed clock signal according to an embodiment of the present disclosure.

3 and FIG. 4 are timing diagrams showing an abnormal output clock signal and a delayed clock signal according to an embodiment of the present disclosure.

FIG. 5 is a circuit diagram of a sampling circuit according to an embodiment of the present disclosure.

FIG. 6 is a flow chart showing an abnormal clock detection method according to an embodiment of the present disclosure.

The disclosure provides many different embodiments or examples for implementing the various features disclosed herein. In order to simplify the disclosure, specific examples of components and layouts are described below. Of course, these are merely examples and are not intended to limit the disclosure. For example, if it is mentioned in the following description that the first feature is formed on the second feature, this may include an embodiment in which the first feature is in direct contact with the second feature; this may also include between the first feature and the second feature. Embodiments of other features are formed that make the first feature not in direct contact with the second feature. Moreover, the disclosure may repeat the symbols and/or text in various examples. This repetition is for the purpose of brevity and clarity, but does not in itself determine the relationship between the various embodiments and/or arrangements discussed.

Furthermore, spatially relative terms such as "lower", "lower", """"""""""" These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. These devices can also be rotated (e.g., rotated 90 degrees or rotated to other directions), and the spatially relative descriptions used herein can also be interpreted accordingly.

1 is a system block diagram of an abnormal clock detection circuit 100 in accordance with an embodiment of the present disclosure. The abnormal clock detection circuit 100 includes a multi-phase generation circuit 110 and a sampling circuit 120. In this embodiment, the abnormal clock detection circuit 100 is built in the chip, and the input end of the multi-phase generation circuit 110 receives the output clock signal SIG of the chip, and the plurality of output ends of the multi-phase generation circuit 110 respectively output. 16 delayed clock signals P1~P16. The first input terminal IN1 and the second input terminal IN2 of the sampling circuit 120 receive the delayed clock signal P1 and the delayed clock signal P13, respectively.

In this embodiment, when an abnormality occurs in the output clock signal SIG, the output terminal ABN of the sampling circuit 120 outputs an abnormal signal. Therefore, the user can easily and accurately filter out the wafer having the abnormal output clock signal SIG by monitoring the output terminal ABN of the sampling circuit 120.

2 is a timing diagram of the output clock signal SIG and the delayed clock signals P1 P P16 according to an embodiment of the present disclosure. In this embodiment, the output clock signal SIG and the delayed clock signals P1 P P16 have the same period TSIG, and the period TSIG can be equally divided into 16 sub-phases TP. In Figure 2, two adjacent clock signals are separated by a sub-phase TP. For example, the phase difference between the two adjacent output clock signals SIG and the delayed clock signal P1 is TP, and the phase difference between the two adjacent delayed clock signals P1 and the delayed clock signal P2 is TP. Similarly, there is no phase difference between the delayed clock signal P16 and the output clock signal SIG.

Referring back to FIG. 1 , the first input terminal IN1 and the second input terminal IN2 of the sampling circuit 120 respectively receive the first delayed clock signal and the second delayed clock signal. In this embodiment, the first delayed clock signal is the delayed clock signal P1, and the second delayed clock signal is the delayed clock signal P13, but the embodiment of the disclosure is not limited thereto. For the disclosure, the period of the output clock signal can be equally divided into N sub-phases, where N is a positive integer greater than or equal to 4, and the phase difference between the first delayed clock signal and the second delayed clock signal can be Outputs the 2/N cycle of the clock signal to between (N-2)/N cycles. It should be noted that, in this embodiment, the phase difference between the first delayed clock signal P1 and the second delayed clock signal P13 is 12/16 cycles of the output clock signal SIG.

In this embodiment, the sampling circuit 120 samples the first delayed clock signal P1 through the falling edge of the second delayed clock signal P13 to detect whether the output clock signal SIG is too slow. Referring to FIG. 2 again, when the output clock signal SIG is normal, the falling edge of the second delayed clock signal P13 samples the first delayed clock signal P1 as a high voltage level. 3 is a timing diagram of an abnormal output clock signal SIG and a delayed clock signal P1~P16 according to an embodiment of the present disclosure. As shown in FIG. 3, the frequency of the output clock signal SIG is too slow. Then, the falling edge of the second delayed clock signal P13 samples the first delayed clock signal P1 as a low voltage level. It is worth mentioning that the dotted line in Figure 3 represents the timing diagram when the output clock signal SIG is normal.

In this embodiment, the sampling circuit 120 samples the first delayed clock signal P1 through the rising edge of the second delayed clock signal P13 to detect whether the output clock signal SIG is too fast. Referring to FIG. 2 again, when the output clock signal SIG is normal, the rising edge of the second delayed clock signal P13 samples the first delayed clock signal P1 as a low voltage level. 4 is a timing diagram of an abnormal output clock signal SIG and a delayed clock signal P1 to P16 according to an embodiment of the present disclosure. As shown in FIG. 4, the frequency of the output clock signal SIG is too fast. Then, the rising edge of the second delayed clock signal P13 samples the first delayed clock signal P1 as a high voltage level. It is worth mentioning that the dotted line in FIG. 4 represents a timing chart when the output clock signal SIG is normal.

In summary, when the falling edge of the second delayed clock signal P13 samples the first delayed clock signal P1, the low voltage level indicates that the output clock signal SIG frequency of the chip is too slow; when the second delay clock The result of sampling the first delayed clock signal P1 at the rising edge of the signal P13 is that the high voltage level represents that the output clock signal SIG frequency of the chip is too fast. Therefore, the function of the sampling circuit 120 can be realized by applying the above-mentioned sampling result judgment to the circuit logic. The circuit architecture of the sampling circuit 120 of an embodiment of the present disclosure is described below.

FIG. 5 is a circuit diagram of a sampling circuit 120 according to an embodiment of the present disclosure. The sampling circuit 120 includes a low frequency clock detection circuit 122 and a high frequency clock detection circuit 124. The low frequency clock detection circuit 122 is configured to detect whether the output clock signal of the chip is too slow. The low frequency clock detection circuit 122 is composed of two flip-flops (Filp-Flop) 122a, 122b.

The data input pin D of the flip-flop 122b is connected to the power supply VDD (ie, the high voltage level), and the timing pin CLK of the flip-flop 122b is connected to the output pin Qb of the flip-flop 122a. Therefore, for the flip-flop 122b, the output pin Q of the flip-flop 122b outputs a high voltage only when the output signal of the output pin Qb of the flip-flop 122a rises from the low voltage level to the high voltage level. Level.

In this embodiment, the data input pin D of the flip-flop 122a receives the first delayed clock signal P1, and the timing pin CLK of the flip-flop 122a receives the inverted second delayed clock signal P13. Therefore, for the flip-flop 122a, the output pin Qb of the flip-flop 122a outputs the reverse first delay only when the second delay pulse signal P13 falls from the high voltage level to the low voltage level. Clock signal P1. The above operation corresponds to sampling the first delayed clock signal P1 through the falling edge of the second delayed clock signal P13.

Referring to FIG. 2 together, when the output clock signal SIG is normal, the falling edge of the delayed clock signal P13 samples the delayed clock signal P1 as a high voltage level, which is equivalent to the output of the flip-flop 122a. Pin Qb outputs a low voltage level. Referring to FIG. 3 together, when the output clock signal SIG frequency is too slow, the falling edge of the delayed clock signal P13 samples the delayed clock signal P1 as a low voltage level, which is equivalent to the output of the flip-flop 122a. Pin Qb outputs a high voltage level.

In summary, when the output clock signal SIG frequency is too slow, the output pin Qb of the flip-flop 122a rises from the low voltage level to the high voltage level, and the output pin Q of the flip-flop 122b outputs a high voltage level. In this way, the user can monitor whether the output clock signal SIG of the chip is abnormally slow due to the output pin Q of the flip-flop 122b. Specifically, in the present embodiment, when the output pin Q of the flip-flop 122b outputs a high voltage level, the sampling circuit 120 outputs an abnormal signal, and the user can know that the output clock signal of the chip is abnormal. .

Referring back to FIG. 5, the high frequency clock detection circuit 124 is configured to detect whether the output clock signal of the chip is too fast, and the high frequency clock detection circuit 124 is composed of two flip-flops 124a and 124b. The working principle of the high frequency clock detection circuit 124 is similar to that of the low frequency clock detection circuit 122, and therefore will not be described herein. When the output clock signal SIG frequency is too fast, the output pin Q of the flip-flop 124a rises from the low voltage level to the high voltage level, and the output pin Q of the flip-flop 124b outputs a high voltage level. In this way, the user can monitor the output pin Q of the flip-flop 124b to know whether the output pulse signal SIG of the chip has an abnormal frequency. Specifically, in the present embodiment, when the output pin Q of the flip-flop 124b outputs a high voltage level, the sampling circuit 120 outputs an abnormal signal, and the user can know that the output clock signal of the chip is abnormal. .

FIG. 6 is a flow chart of an abnormal clock detection method 600 according to an embodiment of the present disclosure. The abnormal clock detection method 600 is used to detect whether the output clock signal of the chip is abnormal. First, in step 610, the first delayed clock signal and the second delayed clock signal are provided according to the output clock signal of the chip. Referring to FIG. 1 together, in the embodiment, the multi-phase generating circuit 110 built in the chip provides the first delayed clock signal P1 and the second delayed clock signal P13 to the sampling circuit according to the output clock signal SIG of the chip. 120. Then, in step 620, the first delayed clock signal is sampled by using the second delayed clock signal to determine whether an abnormality occurs in the output clock signal of the chip. Referring to FIG. 1 together, in the embodiment, the sampling circuit 120 uses the second delayed clock signal P13 to sample the first delayed clock signal P1 to detect whether an abnormality occurs in the output clock signal SIG of the chip. When an abnormality occurs in the output clock signal SIG, the output terminal ABN of the sampling circuit 120 outputs an abnormal signal.

In summary, the present disclosure provides an abnormal clock detection method and a circuit thereof, which are applied to an integrated circuit of a chip to detect whether an abnormality occurs in the output clock signal of the chip, thereby making the user easier and The wafers with abnormal clocks are accurately screened out.

The features of several embodiments are summarized above, and those skilled in the art will be able to understand the aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures, thereby achieving the same objectives and/or achieving the same advantages as the embodiments described herein. . It should be understood by those skilled in the art that the invention may be made without departing from the spirit and scope of the disclosure.

Claims (10)

 An abnormal clock detection method for detecting whether an output clock signal of a chip is abnormal, wherein the abnormal clock detection method comprises: providing a first delayed clock signal according to the output clock signal a second delayed clock signal, wherein the output clock signal, the first delayed clock signal, and the second delayed clock signal have different phases; and the second delayed clock signal is used to The delayed clock signal is sampled to determine whether the output clock signal is abnormal.    The abnormal clock detection method of claim 1, wherein the polyphase generation circuit of the chip is configured to generate N delayed clock signals according to the output clock signal, wherein the N delay times The phase of the pulse signal is different from the phase of the output clock signal, wherein the two delayed clock signals are the first delayed clock signal and the second delayed clock signal, where N is greater than or equal to 4. A positive integer.    The abnormal clock detection method of claim 2, wherein the phase of the first delayed clock signal leads the phase of the second delayed clock signal, wherein the first delayed clock signal and the second The phase difference of the delayed clock signal is between 2/N cycles and (N-2)/N cycles of the output clock signal.    The abnormal clock detection method of claim 1, wherein the abnormal clock detection method uses the falling edge of the second delayed clock signal to sample the first delayed clock signal to detect Whether the frequency of the output clock signal is too slow, wherein when the falling edge of the second delay clock signal samples the first delayed clock signal, the low voltage level indicates that the output clock signal frequency is too slow.    The abnormal clock detection method of claim 1, wherein the abnormal clock detection method uses the rising edge of the second delayed clock signal to sample the first delayed clock signal to detect Whether the frequency of the output clock signal is too fast, and the result of sampling the first delayed clock signal when the rising edge of the second delay clock signal is a high voltage level means that the output clock signal frequency is too fast.    An abnormal clock detection circuit for determining whether an output clock signal of one of the wafers is abnormal. The abnormal clock detection circuit includes: a multi-phase generation circuit for providing a signal according to the output clock signal a first delayed clock signal and a second delayed clock signal, wherein the output clock signal, the first delayed clock signal and the second delayed clock signal have different phases; and a sampling circuit is used for The first delayed clock signal is sampled by the second delayed clock signal to determine whether the output clock signal is abnormal.    The abnormal clock detection circuit of claim 6, wherein the multi-phase generation circuit is configured to generate N delayed clock signals according to the output clock signal, wherein the N delayed clock signals are The phases of the output clock signals are different from each other, wherein the two delayed clock signals are the first delayed clock signal and the second delayed clock signal, where N is a positive integer greater than or equal to 4.    The abnormal clock detection circuit of claim 7, wherein the phase of the first delayed clock signal leads the phase of the second delayed clock signal, wherein the first delayed clock signal and the second The phase difference of the delayed clock signal is between 2/N cycles and (N-2)/N cycles of the output clock signal.    The abnormal clock detection circuit of claim 6, wherein the sampling circuit samples the first delayed clock signal by using a falling edge of the second delayed clock signal to detect the output clock. Whether the frequency of the signal is too slow, wherein when the falling edge of the second delayed clock signal samples the first delayed clock signal, the low voltage level indicates that the output clock signal frequency is too slow.    The abnormal clock detection circuit of claim 6, wherein the sampling circuit samples the first delayed clock signal by using a rising edge of the second delayed clock signal to detect the output clock. Whether the frequency of the signal is too fast, wherein when the rising edge of the second delayed clock signal samples the first delayed clock signal, the high voltage level indicates that the output clock signal frequency is too fast.