TW201836143A - Semiconductor device and display apparatus having the same - Google Patents

Abstract

Disclosed is a semiconductor device including a substrate; a coupling layer disposed on the substrate; a semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode connected to the first conductive semiconductor layer; a second electrode connected to the second conductive semiconductor layer; and an insulating layer covering the coupling layer and the semiconductor structure.

Description

 Semiconductor device and display device therewith  

Embodiments relate to a semiconductor device and a display device therewith.

A light emitting diode (LED) is a light emitting device that emits light when an electric current is applied thereto. Light-emitting diodes emit light, which is highly efficient at low voltage operation and therefore provides significant energy savings. Recently, the problem of luminosity of light-emitting diodes has been greatly reduced, and thus light-emitting diodes have been applied to various devices such as backlight units, display panels, and home appliances.

A gallium arsenide (GaAs) substrate is used in a light-emitting diode having AlGaInP as a growth substrate, but in order to manufacture a light-emitting diode as a semiconductor wafer, it must be removed to prevent light absorption. However, gallium arsenide substrates are difficult to remove using conventional laser lift-off procedures and emit a significant amount of harmful gases during removal.

Embodiments provide red semiconductor devices and semiconductor wafers in the form of vertical or horizontal wafers, including display devices therefor, and methods of fabricating the same.

The semiconductor device according to the embodiment provides red light.

Further, the embodiment provides a semiconductor device with good light extraction efficiency.

Further, embodiments provide a semiconductor laser stripping device to remove harmful gases.

Further, the embodiments provide a semiconductor device that is easy to manufacture.

Furthermore, embodiments provide a semiconductor device comprising gallium arsenide by providing laser lift.

The problems to be solved by the embodiments are not limited, and the following technical solutions and objects or effects can be understood from the embodiments.

According to an embodiment of the present invention, a semiconductor device includes: a substrate; a coupling layer disposed on the substrate; at least one semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second a conductive semiconductor layer and an active layer disposed between the first and second conductive semiconductor layers; a first electrode connected to the first conductive semiconductor layer; and a second electrode coupled to the second conductive semiconductor layer Connecting; and an insulating layer covering the coupling layer and the semiconductor structure.

The insulating layer may cover a portion of the first electrode and a portion of the second electrode.

The insulating layer may cover one side surface of the coupling layer.

The second conductive semiconductor layer may include a second main conductive semiconductor layer disposed on the active layer, and a second heavy main conductive semiconductor layer disposed on the second main conductive semiconductor layer.

The semiconductor device may further include a first cladding layer disposed between the active layer and the first conductive semiconductor layer.

The semiconductor device can further include a sacrificial layer disposed on at least one of a portion and a lower portion of the one of the coupling layers.

The semiconductor structure can include a plurality of semiconductor structures.

According to an embodiment of the present invention, a display device includes: a semiconductor wafer including a coupling layer, a semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second conductive semiconductor layer, and An active layer disposed between the first and second conductive semiconductor layers, a first electrode connected to the first conductive semiconductor layer, a second electrode connected to the second conductive semiconductor layer, and a first electrode An insulating layer covering the coupling layer and the semiconductor structure; a panel substrate disposed under the semiconductor wafer; and a driving device electrically connected to the semiconductor wafer.

According to an embodiment of the present invention, a method of fabricating a semiconductor device includes: forming a coupling layer on a substrate and forming a semiconductor structure on the coupling layer, the semiconductor structure comprising: a first conductive semiconductor layer, a first a second conductive semiconductor layer and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; forming a second substrate on the semiconductor structure; separating a first substrate from the semiconductor device; and the semiconductor Forming a coupling layer on the structure and forming a third substrate on the coupling layer; separating the second substrate from the semiconductor device; performing a first etching to reach a portion of the first conductive semiconductor layer of the semiconductor structure; Forming a first electrode on the first conductive semiconductor layer and forming a second electrode on the second conductive semiconductor layer; performing a second etching on top of the third substrate; and forming an insulating layer to cover the coupling The layer and the semiconductor structure.

Forming the coupling layer on the semiconductor structure and forming the third substrate on the coupling layer may include disposing a sacrificial layer between the coupling layer and the third substrate.

Forming the semiconductor structure may include forming the first conductive semiconductor layer on the coupling layer, forming the active layer on the first conductive semiconductor layer, and forming the second conductive semiconductor layer on the active layer.

According to an embodiment of the present invention, a method of fabricating a display device may include: emitting laser light to a semiconductor device, the semiconductor device comprising a plurality of semiconductor wafers disposed on a substrate; separating at least one semiconductor wafer from the substrate And adhering the at least one semiconductor wafer to a first adhesive layer, the first adhesive layer is disposed under a conveying device; forming the at least one semiconductor wafer on a panel substrate and adhering the at least one semiconductor wafer to the a second adhesive layer on the panel substrate; and emitting light to separate the first adhesive layer from the at least one semiconductor wafer from the substrate, and separating the first adhesive layer and the at least one semiconductor wafer Hardening is performed along with the second adhesive layer.

The semiconductor device can include: a substrate; a coupling layer disposed on the substrate; a semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second conductive semiconductor layer, and the first An active layer between the conductive semiconductor layer and the second conductive semiconductor layer; a first electrode connected to the first conductive semiconductor layer; a second electrode connected to the second conductive semiconductor layer; and an insulating layer, The coupling layer and the semiconductor structure are covered.

The adhering the at least one semiconductor wafer to a first adhesive layer may include adhering the first electrode, and the second electrode and one of the insulating layers are partially to the first adhesive layer.

The hardening the separated first adhesive layer together with the at least one semiconductor wafer together with the second adhesive layer can include separating the transport device from at least one of the semiconductor wafers.

According to an embodiment of the invention, a laser stripping device includes: a laser unit for emitting laser light; an optical unit for guiding the laser light into a target position; and a first stage for maintaining a semiconductor The device is in the target position; and a receiving unit surrounds one of the stages, wherein the receiving unit may include a first discharging unit for discharging exhaust gas discharged from the semiconductor device.

The first discharge unit may be disposed on one side surface of the receiving unit.

The laser stripping device can further include a housing surrounding the laser unit, the optical unit, the stage, and the receiving unit.

The outer casing may include a second discharge unit that is partially local to one of the outer casings.

The first discharge unit may include a plurality of discharge holes.

The stage may include a plurality of zones, and the receiving unit may include a plurality of channels formed between the zones and the discharge holes.

According to an embodiment of the present invention, a semiconductor device includes a sacrificial layer; a coupling layer is disposed on the sacrificial layer; and at least one semiconductor structure is disposed on the coupling layer and includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer disposed between the first and second conductive semiconductor layers; a first electrode connected to the first conductive semiconductor layer; and a second electrode, the second conductive semiconductor The layers are connected, wherein the sacrificial layer and the coupling layer have a thickness ratio of 1:1.5 to 1:50.

The semiconductor device can further include an insulating layer disposed on the sacrificial layer, the coupling layer, and the semiconductor structure.

The insulating layer may cover a portion of the first electrode and a portion of the second electrode.

The second conductive semiconductor layer may include a second main conductive semiconductor layer disposed on the active layer; and a second heavy main conductive semiconductor layer disposed on the second main conductive semiconductor layer.

The semiconductor device may further include a first cladding layer disposed between the active layer and the first conductive semiconductor layer.

The coupling layer may have a surface roughness of 1 nm or less.

According to an embodiment of the present invention, an electronic device includes a semiconductor device; and a housing for receiving the semiconductor device, wherein the semiconductor device includes: a sacrificial layer; a coupling layer disposed on the sacrificial layer; at least one a semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer disposed between the first and second conductive semiconductor layers; a first electrode; The first conductive semiconductor layer is connected; and a second electrode is connected to the second conductive semiconductor layer, wherein the sacrificial layer and the coupling layer have a thickness ratio of 1:1.5 to 1:50.

According to an embodiment of the present invention, a semiconductor device includes: a coupling layer; an interposer disposed on the coupling layer; a reflective layer disposed on the interposer; and a first conductive semiconductor layer disposed on the reflective layer An active layer disposed on the first conductive semiconductor layer; a second conductive semiconductor layer disposed on the active layer; a reflective layer disposed under the first conductive semiconductor layer; a first electrode Electrically connecting the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer.

The semiconductor device can further include a sacrificial layer disposed under the coupling layer.

The first conductive semiconductor layer may include indium aluminum phosphide (AlInP) and have a doping concentration of 10 ¹⁹ or higher.

The reflective layer may comprise aluminum gallium arsenide (AlGaAs).

The semiconductor device may further include an insulating layer disposed on the coupling layer, the interposer, the reflective layer, the first conductive semiconductor layer, the active layer, the second conductive semiconductor layer, the first electrode and the first a second electrode, wherein each of the first and second electrodes may have a partial portion exposed.

The second conductive semiconductor layer may include: a second main conductive semiconductor layer disposed on the active layer; and a second heavy main conductive semiconductor layer disposed on the second main conductive semiconductor layer.

The semiconductor device may further include a first cladding layer disposed between the active layer and the first conductive semiconductor layer. According to an embodiment of the invention, an electronic device includes a semiconductor device; and a housing for receiving the semiconductor device, wherein the semiconductor device includes: a coupling layer; an interposer disposed on the coupling layer; a reflection a layer disposed on the interposer; a first conductive semiconductor layer disposed on the reflective layer; an active layer disposed on the first conductive semiconductor layer; and a second conductive semiconductor layer disposed on the active layer a reflective layer disposed under the first conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer.

1‧‧‧First substrate

2‧‧‧second substrate

1‧‧‧ wafer

10‧‧‧Semiconductor wafer

10-1‧‧‧First semiconductor device

10-2‧‧‧Second semiconductor device

10-3‧‧‧ Third semiconductor device

10-4‧‧‧4th semiconductor device

110‧‧‧ third substrate

120‧‧‧ sacrificial layer

130‧‧‧Coupling layer

130’‧‧‧Coupling layer

140‧‧‧Semiconductor structure

141‧‧‧First conductive semiconductor layer

142‧‧‧ active layer

143‧‧‧Second conductive semiconductor layer

143a‧‧‧Second main conductive semiconductor layer

143b‧‧‧Second heavy conductive semiconductor layer

144‧‧‧First cladding

151‧‧‧First electrode

152‧‧‧second electrode

160‧‧‧Insulation/protective layer

170‧‧‧fourth substrate

170a‧‧‧fourth main substrate

170b‧‧‧fourth main substrate

171‧‧‧ first floor

180‧‧‧Separation layer

190‧‧‧reflective layer

191‧‧‧ first floor

192‧‧‧ second floor

210‧‧‧Conveyor

211‧‧‧First adhesive layer

212‧‧‧Transportation equipment/conveyor

300‧‧‧ Panel substrate

310‧‧‧Second adhesive layer

410‧‧‧Second panel substrate

420‧‧‧Adhesive layer

430‧‧‧flat layer

440‧‧‧gate insulation

450‧‧‧ Groove

500‧‧‧Laser stripping equipment

510‧‧‧Laser unit

520‧‧‧ optical unit

521‧‧‧ lens group

522‧‧‧Photomask

530‧‧ ‧

540‧‧‧ receiving unit

541‧‧‧First discharge unit

541a‧‧‧Drain hole

541b‧‧‧Drain hole

541c‧‧‧Drain hole

541d‧‧‧Drain hole

542‧‧‧Mobile gap

550‧‧‧ accommodating unit

551‧‧‧Second discharge unit

E1‧‧‧ first surface

E2‧‧‧ second surface

L1‧‧‧ channel

L2‧‧‧ channel

L3‧‧‧ channel

L4‧‧‧ channel

L5‧‧‧ channel

S‧‧‧body substrate

S1-12‧‧‧

S2‧‧‧

S3‧‧‧

S4‧‧‧ District

S5‧‧‧

S6‧‧‧ District

S7‧‧‧

S8‧‧‧

S9‧‧‧

S10‧‧‧

S11‧‧‧ District

S12‧‧‧

L1‧‧‧ path

L2‧‧‧ Path

L3‧‧‧ Path

L4‧‧‧ Path

P‧‧‧ side

P1‧‧‧ partition wall

P2‧‧‧ partition wall

P3‧‧‧ partition wall

P4‧‧‧ partition wall

P1‧‧‧ first width

P2‧‧‧ second width

P3‧‧‧ third width

P4‧‧‧ fourth width

I‧‧‧Ion layer

D1‧‧‧ thickness

D2‧‧‧ thickness

D3‧‧‧ thickness

D4‧‧‧ thickness

D5‧‧‧ thickness

D6‧‧‧ thickness

D7‧‧‧ thickness

D8‧‧‧ thickness

D9‧‧‧ thickness

D10‧‧‧ thickness

D11‧‧‧ thickness

D12‧‧‧ thickness

D13‧‧‧ thickness

D14‧‧‧ thickness

D15‧‧‧ thickness

D16‧‧‧ thickness

D17‧‧‧ thickness

D18‧‧‧ thickness

D19‧‧‧ thickness

D20‧‧‧ thickness

D12‧‧‧ thickness

D21‧‧‧ thickness

D22‧‧‧ thickness

D23‧‧‧ thickness

D24‧‧‧ thickness

D25‧‧‧ thickness

D26‧‧‧ thickness

D27‧‧‧ thickness

D28‧‧‧ thickness

W1‧‧‧Max width

W2‧‧‧Minimum width

W3‧‧‧Max width

W4‧‧‧ distance

W5‧‧‧Max width

W6‧‧‧Minimum width

K‧‧‧Predetermined area

K1‧‧‧ first upper surface

K2‧‧‧Second upper surface

Dw1‧‧‧ separation distance

Dw2‧‧‧ separation distance

AE‧‧ ‧ pixel electrodes

CL‧‧‧Shared power lines

CE‧‧‧Common electrode

DE‧‧‧汲 electrode

OCL‧‧ ohm contact layer

GE‧‧‧gate electrode

SCL‧‧‧ semiconductor layer

SE‧‧‧ source electrode

T2‧‧‧Driven thin film transistor

The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the embodiments of the invention. FIG. 2 is a plan view and a cross-sectional view of a semiconductor device according to the first embodiment; FIG. 3 is a plan view and a cross-sectional view of a semiconductor device according to a second embodiment; FIG. 4 is a cross-sectional view showing a modified version of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment; FIGS. 6a to 6f are diagrams according to the third A manufacturing method of the semiconductor device of the embodiment; FIGS. 7a to 7d illustrate a manufacturing method for manufacturing a display device using the semiconductor device according to the first embodiment; and FIG. 8 illustrates a laser according to an embodiment. FIG. 9 is a plan view showing one of the laser stripping devices according to an embodiment; FIG. 10 is a modified version of the laser stripping device of FIG. 9; FIG. 12 is a cross-sectional view showing a modified version of the laser stripping apparatus according to the embodiment of FIG. 11; FIG. 13 is a view showing a semiconductor device according to a fourth embodiment; A plan view and a cross-sectional view; FIGS. 14a to 14f are flowcharts showing a method of manufacturing the semiconductor device according to the fourth embodiment; and FIGS. 15a to 15e are flow charts showing the semiconductor device of the fourth embodiment. Figure 16 is a diagram showing light transmittance according to an embodiment and in accordance with the thickness of the sacrificial layer of the semiconductor device; Figure 17 is a diagram showing an embodiment according to an embodiment The light-transmitting transmittance of the coupling layer of the semiconductor device; FIG. 18 is a view showing the sacrificial layer and the coupling layer of the semiconductor device according to an embodiment; FIG. 19 is a modified version of FIG. Figure 20a is a plan view and a cross-sectional view of a semiconductor device according to a fifth embodiment; Figure 20b is an enlarged view of a portion A of Figure 20a; and Figures 21a to 21f illustrate the fabrication of the semiconductor according to the fourth embodiment. Device A flow chart of a method; FIGS. 22a and 22b illustrate a flow of transferring a plurality of semiconductor devices of a wafer to a donor substrate; and FIGS. 23a to 23c illustrate a flow chart for explaining a plurality of transfers from a wafer The flow of the semiconductor device to a donor substrate; FIG. 24 is a conceptual diagram in which a semiconductor device on a donor substrate is transferred to a panel substrate of a display device; FIGS. 25a and 25b illustrate the transfer of the semiconductor device A flowchart of a process of one of the panel substrates of the display device; FIG. 26 is a modified version of FIG. 20a; FIG. 27 is a cross-sectional view of the semiconductor device according to a sixth embodiment; FIGS. 28a to 28h show the basis A flowchart of a method for fabricating the semiconductor device of the sixth embodiment; FIG. 29 is a modified version of FIG. 27; and FIG. 30 is a diagram of a semiconductor device transferred to a display device according to an embodiment. Conceptual view.

Embodiments of the invention may be modified in other forms, or several embodiments may be combined with one another. The scope of the invention is not limited to each of the embodiments described below. Even if the content described in a particular embodiment is not described in other embodiments, the content may be understood to be related to other embodiments, unless otherwise stated or contradicted by the specific embodiments in other embodiments.

For example, when the features of component A are described in a particular embodiment and the features of component B are described in another embodiment, it should be understood that embodiments of component A and component B are within the scope of the invention and Within the spirit, even when the embodiments are not explicitly described.

As used herein, it will be understood that when an element is referred to as being "in" or "an" or "an" In addition, the terms "upper (upper)" or "lower (lower)" may encompass both orientations above and below.

In the following, embodiments of the invention will be described more fully hereinafter with reference to the accompanying drawings.

Furthermore, the semiconductor package in accordance with embodiments of the present invention can include a small semiconductor device. Here, a small semiconductor device can be referred to as a structural size of a semiconductor device. Further, a small semiconductor device may have a structural size of 1 μm to 100 μm. Further, the semiconductor device according to the embodiment may have a structural size of 30 μm to 60 μm as will be described below, but the present invention is not limited thereto. Further, the technical features or layers of the embodiments can be applied to a semiconductor device having a smaller specification.

The semiconductor device according to the embodiment of the present invention can generate red light having a peak wavelength of 530 nm to 700 nm. However, the invention is not limited to the peak wavelengths. Moreover, of the various embodiments that will be described hereinafter, any two or more embodiments may be combined.

1 is a plan view and a cross-sectional view of a semiconductor device in accordance with a first embodiment.

Referring to FIG. 1, the semiconductor device of the first embodiment includes a substrate 110, a sacrificial layer 120 disposed on the substrate 110, a coupling layer 130 disposed on the sacrificial layer 120, and a semiconductor structure 140. Disposed on the coupling layer 130 and including a first conductive semiconductor layer 141, a second heavy main conductive semiconductor layer 143b and one of the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b a layer 142; a first electrode 151 connected to the first conductive semiconductor layer 141; a second electrode 152 connected to the second main conductive semiconductor layer 143b, and an insulating layer 160 covering the coupling layer 130 And the semiconductor structure 140.

The substrate 110 can be made of a conductive material. For example, the substrate 110 can comprise a metal or a semiconductor material. The substrate 110 can be made of a metal having high electrical conductivity and/or thermal conductivity. In this case, the heat generated by the operation of the semiconductor device can be quickly released to the outside.

The substrate 110 is identical to a third substrate, which will be described hereinafter with reference to Figures 2a through 2I. The substrate 110 may comprise gallium arsenide (GaAs), sapphire (Al ₂ O ₃ ), tantalum carbide (SiC), germanium (Si), gallium nitride (GaN), zinc oxide (ZnO), gallium phosphide ( GaP), indium phosphide (InP), germanium substrate (Ge), and gallium trioxide (Ga ₂ O ₃ ).

The sacrificial layer 120 may be disposed on the substrate 110. The sacrificial layer 120 can be removed while the semiconductor device is being transferred to a display device. For example, when the semiconductor device is transferred to a display device, the sacrificial layer 120 can be detached from the semiconductor device by laser light emitted during the transfer. In this example, the sacrificial layer 120 can be detached in the wavelength of the laser light. Further, the laser light may have a wavelength of 532 nm or 1064 nm.

The sacrificial layer 120 may comprise an oxide or a nitride. However, the present invention is not limited thereto, and when the sacrificial layer 120 is a spin-on-glass (SOG) film, the sacrificial layer 120 may include silicate and silicic acid. Acid). When the sacrificial layer 120 is a spin-on-dielectric (SOD) film, the sacrificial layer 120 may comprise silicate, siloxane, polymethyl sesqui Methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MQS+HSQ, perhydrosilazane (TCPS) or polysilazane. However, the invention is not limited thereto.

The sacrificial layer 120 can be subjected to electron beam evaporation, thermal evaporation, metal-organic chemical vapor deposition (MOCVD) or sputtering, and pulsed laser deposition. , PLD) is formed, but is not limited to this.

The coupling layer 130 can be disposed over the sacrificial layer 120. However, the present invention is not limited thereto, and the coupling layer 130 may be disposed under the sacrificial layer 120. The coupling layer 130 may include any one of C, O, N, and H, and may also include a resin, but is not limited thereto.

The coupling layer 130 may have a thickness d1 of one of 1.8 μm to 2.2 μm. However, the invention is not limited thereto. Here, the thickness may be one of the lengths in the X-axis direction. Here, a first direction (an X-axis direction) is one of the thickness directions of the semiconductor structure 140 and includes a first main direction (one X1 direction) and a first main main direction (one X2 direction). The first main direction of the semiconductor structure 140 in the thickness direction is a direction from the first conductive semiconductor layer 141 toward a second conductive semiconductor layer 143. Similarly, the first major direction of the semiconductor structure 140 in the thickness direction is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141. Here, a second direction (a Y axis) may be perpendicular to the first direction (X axis). Further, the second direction (Y axis) includes a second main direction (a Y1 direction) and a second main direction (a Y2 direction).

The semiconductor structure 140 can be disposed on the coupling layer 130.

The semiconductor structure 140 may include the first conductive semiconductor layer 141, the second heavy main conductive semiconductor layer 143b, and the active layer 142 disposed between the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b. .

The first conductive semiconductor layer 141 may be disposed on the coupling layer 130. The first conductive semiconductor layer 141 may have a thickness d2 of one of 1.8 μm to 2.2 μm. However, the invention is not limited thereto.

The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first conductive semiconductor layer 141 can be electrically connected to the first electrode 151.

The first electrode 151 may be partially disposed on an upper surface of the first conductive semiconductor layer 141. The first electrode 151 may be disposed under the second electrode 152.

The first electrode 151 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Ht), but not limited to this.

The first electrode 151 can be formed by any typical electrode formation method such as sputtering, coating, and deposition.

A first cladding layer 144 may be disposed on the first conductive semiconductor layer 141. The first cladding layer 144 can be disposed between the first conductive semiconductor layer 141 and the active layer 142. The first cladding layer 144 can include a plurality of layers. The first cladding layer 144 may include an AlInGaP-based layer/AlInP-based layer.

The first cladding layer 144 has a thickness d3 of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

The active layer 142 can be disposed on the first cladding layer 144. The active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second heavy conductive semiconductor layer 143b are layered. Combine. Due to electron-hole recombination, the active layer 142 can be rotated to a lower order energy and produce ultraviolet wavelength light.

The active layer 142 can have, but is not limited to, any of the structures described below: single well structures, multi-well structures, single quantum well structures, multiple quantum well (MQW) structures, quantum dot structures, and quantum wire structures.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness d4 of one of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

Since the electrons are cooled in the first cladding layer 144, the active layer 142 can generate more radiation recombination.

The second conductive semiconductor layer 143 may be disposed on the active layer 142. The second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a and a second heavy main conductive semiconductor layer 143b.

The second main conductive semiconductor layer 143a may be disposed on the active layer 142. The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a.

The second main conductive semiconductor layer 143a may include TSBR and P-AllnP. The second main conductive semiconductor layer 143a may have a thickness d5 of one of 0.57 μm to 0.70 μm. However, the invention is not limited thereto.

The second main conductive semiconductor layer 143a may be made of a III-V compound semiconductor or a II-VI compound semiconductor. The second main conductive semiconductor layer 143a may be doped with a second dopant.

The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer.

The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

For example, the second heavy main conductive semiconductor layer 143b may be doped with magnesium (Mg) at a concentration of about 10×10 ¹⁸ , but is not limited thereto.

Furthermore, the second heavy-duty conductive semiconductor layer 143b may comprise a plurality of layers, and only some of the layers may be doped with magnesium.

The second heavy main conductive semiconductor layer 143b may have a thickness d6 of 0.9 μm to 1.1 μm. However, the invention is not limited thereto.

The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b.

The second electrode 152 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOX/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Hf), but not limited to this.

The second electrode 152 can be formed by any of the typical electrode formation methods, such as sputtering, coating, and deposition.

The insulating layer 160 may cover the coupling layer 130, the sacrificial layer 120 and the semiconductor structure 140. The insulating layer 160 may cover one side surface of the coupling layer 130, one side surface of the sacrificial layer 120, and one side surface of the semiconductor structure 140. The coupling layer 130, the sacrificial layer 120 and the semiconductor structure 140 may not be exposed.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. In addition, the insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the first electrode 151 may be partially exposed. The upper surface of the second electrode 152 may be partially exposed.

The insulating layer 160 can be made of an insulating material. The insulating material may be made of at least one selected from the group consisting of SiO ₂ , Si _x O _y , Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO _{2 ,} and AlN.

2a to 2I illustrate a method of fabricating one of the semiconductor devices according to the first embodiment.

The manufacturing method of the semiconductor device according to the first embodiment may include: forming a coupling layer 130 on a substrate and forming a semiconductor structure 140 on the coupling layer 130, the semiconductor structure 140 comprising: a first conductive a semiconductor layer 141, a second conductive semiconductor layer 143 and an active layer disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143; a second substrate 2 is formed on the semiconductor structure 140; a semiconductor device is separated from a first substrate 1; a coupling layer 130 is formed on the semiconductor structure 140; and a third substrate 110 is formed on the coupling layer 130; the second substrate 2 is separated from the semiconductor device; Sub-etching reaches a portion of the first conductive semiconductor layer 141 of the semiconductor structure 140; forming a first electrode 151 on the first conductive semiconductor layer 141 and forming a second electrode on the second conductive semiconductor layer 143 152; performing a second etching to the top of the third substrate 110; and forming an insulating layer 160 covering the coupling layer 130 and the semiconductor structure 140.

First, referring to FIG. 2a, the semiconductor device can include a first substrate 1 and a semiconductor structure 140. After the first substrate 1 is disposed, the semiconductor structure 140 can be disposed on the first substrate 1.

The semiconductor structure 140 may include a first conductive semiconductor layer 141, a first cladding layer 144 disposed on the first conductive semiconductor layer 141, and an active layer 142 disposed on the first cladding layer 144. A second main conductive semiconductor layer 143a is disposed on the active layer 142, and a second heavy main conductive semiconductor layer 143b is disposed on the second main conductive semiconductor layer 143a.

The first substrate 1 may comprise a material having excellent thermal conductivity. The first substrate 1 can be a conductive substrate or an insulating substrate. For example, the first substrate 1 may comprise any one of the following: gallium arsenide (GaAs), sapphire (Al ₂ O ₃ ), tantalum carbide (SiC), germanium (Si), gallium nitride (GaN), oxidation. Zinc (ZnO), gallium phosphide (GaP), indium phosphide (InP), germanium substrate (Ge), and gallium trioxide (Ga ₂ O ₃ ).

A concavo-convex structure may be formed on the first substrate 1, but is not limited thereto. The first substrate 1 is wet-cleaned to remove impurities on its surface.

The first conductive semiconductor layer 141 may be disposed on the first substrate 1. The first cladding layer 144 may be disposed on the first conductive semiconductor layer 141. The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The active layer 142 can be disposed on the first cladding layer 144. The second main conductive semiconductor layer 143a may be disposed on the active layer 142. The second main conductive semiconductor layer 143a may be disposed on the active layer 142. The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a.

Next, referring to FIG. 2b, a second substrate 2 may be disposed on top of the semiconductor device. The second substrate 2 may be disposed on the second heavy main conductive semiconductor layer 143b. The second substrate 2 can be a conductive substrate and/or an insulating substrate. The second substrate 2 may include a sapphire substrate, but is not limited thereto.

Referring to Figures 2c and 2d, the first substrate 1 can be detached from the semiconductor device. For example, the first substrate 1 can be removed by a process such as laser stripping.

A coupling layer 130 may be disposed on the first conductive semiconductor layer. A sacrificial layer 120 may be disposed on the coupling layer 130. A third substrate 110 may be disposed on the sacrificial layer.

The sacrificial layer 120 may comprise a material such as SiO2, SiNx, TiO2, and polyimide. The sacrificial layer 120 can be formed by a typical epitaxial film formation method such as PECVD and MOCVD or by spin coating (for polyamine). However, the invention is not limited thereto.

The coupling layer 130 may comprise a resin, but is not limited thereto.

The third substrate 110 may be disposed on the sacrificial layer 120. The third substrate 110 can serve as a support for supporting the semiconductor structure 140, the coupling layer 130 and the sacrificial layer 120. For example, the third substrate 110 may comprise a material such as a sapphire substrate and includes any of the following: Au, Ni, Al, Cu, W, Si, Se, O, and GaAs, but is not limited thereto. In addition, the third substrate 110 may be formed such that the emitted laser light passes through the third substrate 110 when it is transferred to the display device. For example, when the emitted laser light has a wavelength of 532 nm or 1064 nm, the wavelength of 532 nm or 1064 nm can be transmitted by the third substrate 110 and then absorbed by the sacrificial layer 120. Thereafter, the sacrificial layer 120 can be detached by the emitted laser light.

Referring to Figure 2e, the second substrate 2 can be removed by laser lift-off (LLO).

Referring to FIG. 2f, the first etch may begin at the top of the semiconductor structure 140 to a portion of the first conductive semiconductor layer 141.

The first etching may be a wet etching method or a dry etching method, but is not limited thereto.

Referring to FIG. 2g, a second electrode 152 can be disposed on top of the semiconductor structure 140. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b.

The first electrode 151 and the second electrode 152 can be formed by any typical electrode formation method, such as sputtering, coating, and deposition. However, the invention is not limited thereto.

The first electrode 151 and the second electrode 152 may be disposed at positions spaced apart from the third substrate 110 by different distances. The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. In this example, the second electrode 152 may be disposed above the first electrode 151. However, the invention is not limited thereto.

For example, when the first conductive semiconductor layer 141 is disposed over the second conductive semiconductor layer 143, the first electrode 151 may be disposed on the second electrode 152.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141.

Referring to FIG. 2h, a second etching may be performed to an upper surface of the third substrate 110. The second etching may be a wet etching method or a dry etching method, but is not limited thereto.

The second etch can be etched by a greater thickness than the first etch, but is not limited thereto. For example, the second etch can reach the sacrificial layer 120 or the coupling layer 130.

The semiconductor device disposed on the third substrate 110 can be isolated in the form of a plurality of wafers by the second etching.

Referring to FIG. 2i, an insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130 and side surfaces of the semiconductor structure 140. The insulating layer 160 may cover a portion up to an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed.

The insulating layer 160 may cover a portion up to an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

One of the insulating layers 160 may be partially disposed on an upper surface of the third substrate 110. One of the insulating layers 160 may be partially disposed between adjacent wafers.

3 is a plan view and a cross-sectional view of a semiconductor device in accordance with a second embodiment.

Referring to FIG. 3, the semiconductor device according to the second embodiment of the present invention includes: a substrate 110; a sacrificial layer 120 disposed on the substrate 110; a coupling layer 130 disposed on the sacrificial layer 120; The structure 140 is disposed on the coupling layer 130 and includes a first conductive semiconductor layer 141, a second heavy main conductive semiconductor layer 143b, and disposed between the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b. An active layer 142; a first electrode 151 connected to the first conductive semiconductor layer 141; a second electrode 152 connected to the second heavy-main conductive semiconductor layer 143b, and an insulating layer 160 covering the The coupling layer 130 and the semiconductor structure 140.

The description made with reference to FIG. 1 can be applied to the substrate 110, the sacrificial layer 120, and the coupling layer 130.

The semiconductor structure 140 can be disposed on the coupling layer 130.

The semiconductor structure 140 may include the first conductive semiconductor layer 141, the second heavy main conductive semiconductor layer 143b, and the active layer 142 disposed between the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b. .

The second main conductive semiconductor layer 143b may be disposed on the coupling layer 130. The second heavy main conductive semiconductor layer 143b may have a thickness d7 of 3.15 μm to 3.85 μm. However, the invention is not limited thereto.

The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143b is electrically connected to the second electrode 152.

The second electrode 152 may be formed on one side of the top of the second heavy main conductive semiconductor layer 143b. The second electrode 152 can be placed under the first electrode 151.

The second main conductive semiconductor layer 143a may be disposed over the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143a may be disposed between the second main conductive semiconductor layer 143b and the active layer 142.

The second main conductive semiconductor layer 143a may have a thickness d8 of 0.57 μm to 0.69 μm. However, the invention is not limited thereto. The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer. The second main conductive semiconductor layer 143a may include TSBR and P-AllnP.

The active layer 142 may be disposed on the second main conductive semiconductor layer 143a. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second main conductive semiconductor layer 143a are layered in this layer. Combine. Due to electron-hole recombination, the active layer 142 can be rotated to a lower order energy and produce ultraviolet wavelength light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness d9 of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

A first cladding layer 144 can be disposed on the active layer 142. The first cladding layer 144 may be disposed between the active layer 142 and the first conductive semiconductor layer 141.

The first cladding layer 144 may comprise aluminum indium gallium phosphide (AlInP). The first cladding layer 144 has a thickness d10 of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

The first conductive semiconductor layer 141 may be disposed on the first cladding layer 144. The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first conductive semiconductor layer 141 may have a thickness d11 of one of 0.45 μm to 5.5 μm. However, the invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141. The first electrode 151 can be placed over the second electrode 152.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130 and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the side surface of the semiconductor structure 140.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed.

The insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

Figure 4 is a cross-sectional view showing a modified version of the semiconductor device in accordance with the first embodiment.

Referring to FIG. 4, in the modified version, the positions of the coupling layer 130 and the sacrificial layer 120 can be interchanged. Additionally, the coupling layer 130 and the sacrificial layer 120 can exit the semiconductor device. According to this configuration, a semiconductor wafer is provided as a plate member of a display device, and the semiconductor wafer may include only the semiconductor structure 140 or include the semiconductor structure 140 and any of the coupling layer 130 and the sacrificial layer 120. layer.

5 is a cross-sectional view of a semiconductor device according to a third embodiment, and FIGS. 6a to 6f illustrate a method of fabricating one of the semiconductor devices according to the third embodiment.

Referring to FIG. 5, the semiconductor device of the third embodiment includes: a substrate 110; a sacrificial layer 120 disposed on the substrate 110; a coupling layer 130 disposed on the sacrificial layer 120; and a fourth substrate 170, disposed on the coupling layer 130; a semiconductor structure 140 disposed on the fourth substrate 170 and including a first conductive semiconductor layer 141, a second heavy conductive semiconductor layer 143b and disposed at the first An active layer 142 between the conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b; a first electrode 151 connected to the first conductive semiconductor layer 141; a second electrode 152, and the second heavy The main conductive semiconductor layers 143b are connected, and an insulating layer 160 covers the coupling layer 130 and the semiconductor structure 140.

Here, the fourth substrate 170 will be described as an intermediate layer in the drawing starting from FIG.

The description made with reference to FIG. 1 can be applied to the substrate 110, the sacrificial layer 120, the coupling layer 130, the semiconductor structure 140, the first electrode 151 and the second electrode 152. Here, the fourth substrate 170 can be a gallium arsenide substrate.

Referring to FIG. 6a, ions are implanted into the fourth substrate 170, so the fourth substrate 170 may include an ion layer I. The ions may include hydrogen (H), but are not limited thereto.

The ion layer I can be separated from a surface of the fourth substrate 170 by a predetermined distance. In this example, the fourth substrate 170 can include a fourth main substrate 170a and a fourth main substrate 170b. The ion layer I can be separated from the fourth substrate 170 by 0.4 μm to 0.6 μm. That is, the fourth main substrate 170a may have a thickness of 0.4 μm to 0.6 μm.

Referring to FIG. 6b, the sacrificial layer 120 may be disposed between the substrate 110 and the coupling layer 130 as described with reference to FIG. 2d. In addition, the fourth main substrate 170a can be disposed on the coupling layer 130, and the coupling layer 130 and the fourth main substrate 170a can be coupled to each other.

The coupling layer 130 may include SiO ₂ , and the coupling layer 130 may be coupled to the fourth main substrate 170a by an O2 plasma process.

Thus, the sacrificial layer 120 can be disposed on the substrate 110, the coupling layer 130 can be disposed on the sacrificial layer 120, the fourth main substrate 170a can be disposed on the coupling layer 130, and the ion layer I and the The fourth heavy master substrate 170b may be disposed on the fourth main substrate 170a.

Referring to FIG. 6c, the fourth substrate 170 may be disposed on the coupling layer 130. The ion layer I illustrated in FIG. 6b can be removed by liquid jetting, and the fourth heavy master substrate 170b can be separated from the fourth main substrate 170a.

The separated fourth heavy master substrate 170b can be used as a substrate. Therefore, it is expected to reduce manufacturing costs and costs.

Thus, the fourth substrate 170 disposed on the coupling layer 130 refers to the fourth main substrate 170a in FIG. 6b, but will be described below with the fourth substrate 170. Additionally, the semiconductor structure 140 can be disposed on the fourth substrate 170. An upper surface of the fourth substrate 170 (which contacts the semiconductor structure 140) may be polished to be flat. For example, the upper surface of the fourth substrate 170 may be subjected to chemical mechanical planarization, and after planarization, the semiconductor structure 140 may be disposed on the upper surface of the fourth substrate 170.

Referring to FIG. 6d, the first etching may begin at the top of the semiconductor structure 140 to a portion of the first conductive semiconductor layer 141. This example applies to the description made as shown in Figure 2f.

The first etching may be a wet etching method or a dry etching method, but is not limited thereto.

Referring to FIG. 6e, the second electrode 152 can be disposed on top of the semiconductor structure 140. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b.

The first electrode 151 and the second electrode 152 can be formed by any typical electrode formation method, such as sputtering, coating, and deposition. However, the invention is not limited thereto.

The first electrode 151 and the second electrode 152 may be disposed at positions spaced apart from the third substrate 110 by different distances. The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. In this example, the second electrode 152 may be disposed above the first electrode 151. However, the invention is not limited thereto.

For example, when the first conductive semiconductor layer 141 is disposed over the second conductive semiconductor layer 143, the first electrode 151 may be disposed on the second electrode 152.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141. This example applies to the description made in accordance with Figure 2g.

Further, a second etching may be performed to an upper surface of the third substrate 110. The second etching may be a wet etching method or a dry etching method, but is not limited thereto.

The second etching can engrave a greater thickness than the first etching, but is not limited thereto.

The semiconductor device disposed on the third substrate 110 can be isolated in the form of a plurality of wafers by the second etching. This example applies to the description made in accordance with Figure 2h.

Referring to FIG. 6f, the insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the fourth substrate 170, and the semiconductor structure 140.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the fourth substrate 170, and side surfaces of the semiconductor structure 140. The insulating layer 160 may cover a portion up to an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed.

The insulating layer 160 may cover a portion up to an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed. One of the insulating layers 160 may be partially disposed on an upper surface of the third substrate 110. One of the insulating layers 160 may be partially disposed between adjacent wafers.

7a to 7d illustrate a method of fabricating a display device using the semiconductor device according to the first embodiment.

The manufacturing method includes the steps of: separating a plurality of semiconductor wafers 10 from the substrate by selectively emitting laser light to a semiconductor device including a plurality of semiconductor wafers 10 disposed on a substrate, and The semiconductor wafer 10 is formed on a panel substrate. The gas produced in the step can be discharged.

Here, the substrate may be the third substrate 110 of the semiconductor device according to the first embodiment. In addition, the step may include: adhering at least one semiconductor wafer 10 to a first adhesive layer 211, the first adhesive layer 211 is disposed under a conveying device 210, and the semiconductor of the adhering step is separated from the substrate.

In addition, the step of forming the separated semiconductor wafer 10 on a panel substrate may include forming at least one semiconductor wafer 10 on the panel substrate, and adhering the formed semiconductor wafer 10 to the panel substrate. a second adhesive layer; emitting light, separating the first adhesive layer 211 from the at least one semiconductor wafer 10, and hardening the first adhesive layer 211 together with the second adhesive layer, the at least one semiconductor Wafer 10.

Here, the semiconductor device may include: a substrate; a coupling layer 130 disposed on the substrate; a semiconductor structure 140 disposed on the coupling layer 130 and including a first conductive semiconductor layer 141, a second conductive semiconductor a layer 143 and an active layer 142 disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143; a first electrode 151 connected to the first conductive semiconductor layer 141; a second electrode 152, The second conductive semiconductor layer 143 is connected to the second conductive semiconductor layer 143, and an insulating layer 160 covers the coupling layer 130 and the semiconductor structure 140.

In addition, in the step of separating the substrate, the first electrode 151 and the second electrode 152 and one of the insulating layer 160 are partially adhered to the first adhesive layer 211.

Furthermore, in the step of hardening together with the second adhesive layer, the transport device 210 can be isolated from the at least one semiconductor wafer 10.

The method of manufacturing the display device will be described below with reference to Figures 7a to 7d.

Referring to Fig. 7a, laser light can be emitted to the third substrate 110 of the semiconductor device according to the first embodiment.

In order to isolate the third substrate 110, laser light of a high energy source itself can be emitted via the backlight side of a transparent sapphire substrate. The laser light can be emitted to the semiconductor wafer 10 of a portion of the semiconductor device. However, the invention is not limited thereto, and the laser light can be emitted to all of the semiconductor wafers 10 of the semiconductor device.

The laser light is absorbed between the third substrate 110 and the coupling layer 130. During the absorption process, a thermo-chemical decomposition reaction may occur in the sacrificial layer 120 between the third substrate 110 and the coupling layer 130. Thereby, part of the semiconductor wafer 10 can be peeled off from the third substrate 110. In this case, the thermochemical decomposition reaction occurring in the sacrificial layer 120 can generate a harmful gas.

For example, the harmful gas may include arsenic (As) and phosphorus (P), but is not limited thereto.

Referring to Figure 8, there is shown a laser stripping apparatus in accordance with an embodiment. A laser stripping device 500, comprising: a laser unit 510 for emitting laser light, an optical unit 520 for guiding the laser light to a target position, a first stage 530, wherein the semiconductor device is disposed at the At the target position, a receiving unit 540 surrounds the stage 530 and surrounds one of the external housing units 550.

The laser unit 510 emits laser light. For example, the laser unit 510 can be a KrF excimer laser, but is not limited thereto.

A laser source can be pulse-oscillation, but is not limited thereto.

The optical unit 520 can include a photomask 522 and a lens assembly 521 for emitting the laser light in a desired mode, and the lens assembly 521 is used to amplify or form a photomask to the photomask. 522 of the beam of the laser light.

The reticle 522 can include an opening having an illuminating shape. For example, when the illumination pattern has a radial shape, the opening of the mask 522 may also have a radial shape.

The stage 530 can be a member for maintaining the position of the semiconductor device on an upper surface thereof. Here, the semiconductor device may be the above-mentioned semiconductor device according to the first embodiment. A mechanism for vacuum adsorption and maintenance of the semiconductor device may be installed in the stage 530 as needed, but is not limited thereto.

Further, the stage 530 can have various shapes. For example, the stage 530 may have a circular shape as in the semiconductor device, but is not limited thereto.

The laser light can be emitted to the semiconductor device disposed on the stage 530. In detail, the laser light can be absorbed between the third substrate 110 and the coupling layer 130. A thermochemical decomposition reaction may occur in the sacrificial layer 120 disposed between the third substrate 110 and the coupling layer 130. The semiconductor wafers 10 included in the semiconductor device can be peeled off from the third substrate 110. In this case, a harmful gas may be released due to the thermochemical decomposition reaction occurring in the sacrificial layer.

9 is a plan view of one of the laser stripping devices 500 in accordance with an embodiment, and FIG. 10 illustrates a modified version of the laser stripping device 500 of FIG.

Referring to Figures 9 and 10, the stage 530 can divide a plurality of blocks. For example, the stage 530 can be divided into four sections.

The receiving unit 540 can be disposed outside the stage 530 and surround the stage 530. The receiving unit 540 can include a first discharging unit 541 for discharging a gas discharged from the sacrificial layer of the semiconductor device.

The first discharge unit 541 may be disposed on one side surface of the receiving unit 540. Further, the first discharge unit 541 may include a plurality of discharge holes 541a, 541b, 541c, 541d.

The discharge holes 541a, 541b, 541c, 541d may have various shapes.

The receiving unit 540 may include a plurality of channels L1, L2, L3, L4 formed between the plurality of discharge holes 541a, 541b, 541c, 541d and the plurality of regions S1, S2, S3, S4.

One of the gases discharged from the zones S1, S2, S3, S4 of the stage 530 can be discharged via any of the channels L1, L2, L3, L4.

The receiving unit 540 may include a plurality of partition walls P1, P2, P3, and P4 formed between the step 530 and the discharge holes 541a, 541b, 541c, and 541d to form the channels L1, L2, L3, and L4. .

For example, a gas discharged from the first zone S1 may be discharged only through the first discharge hole 541a. However, the present invention is not limited thereto, and the above examples can be variously modified depending on the positions of the partition walls P1, P2, P3, and P4 and the shape of the receiving unit.

A mobile mechanism (not shown) may be further included for moving a target position of the laser light in the stage 530.

The accommodation unit 550 can surround the laser unit 510, the optical unit 520, the stage 530, and the receiving unit 540.

The accommodation unit 550 may have a second discharge unit 551 disposed thereon. The second discharge unit 551 can discharge a residual gas that is not discharged through the first discharge unit 541. The second discharge unit 551 may include a plurality of discharge holes, but is not limited thereto.

11 is a cross-sectional view of the laser stripping apparatus 500 in accordance with an embodiment.

Referring to Figure 11, the semiconductor device is movable and thereafter disposed on the stage 530. In this example, the semiconductor device can be transferred to the stage 530 via a mobile device (not shown) via an upper portion of the discharge aperture of the receiving unit 540. In addition, laser light can be emitted to the semiconductor device on the stage 530, and the sacrificial layer 120 can be removed by the laser light. When the sacrificial layer 120 is removed, a harmful gas can be released. The harmful gas can be discharged through a discharge hole.

Figure 12 is a cross-sectional view showing a modified version of the laser stripping device 500 in accordance with the embodiment of Figure 11;

Referring to FIG. 12, the semiconductor device can be transferred to the stage 530 via the mobile device (not shown) via a lower portion of the drain hole. A movable slit 542 may be disposed at a lower portion of the discharge hole.

When the semiconductor device is transferred to the stage 530, the movable slot 542 can be open or closed. The semiconductor device can be emitted with laser light to the stage 530, and the sacrificial layer 120 can be removed by the laser light. Further, while the sacrificial layer 120 is removed, the released harmful gas may be discharged to the discharge unit 541 disposed on the movable slit 542.

A semiconductor wafer can be separated from the third substrate 110 by moving the sacrificial layer 120. Here, the semiconductor wafer can be the semiconductor wafer described above with reference to Figure 7a. Subsequently, a first adhesive layer 211 disposed at a lower portion of the transport device 210 may be adhered to a portion of the insulating layer 160, and one of the upper surface of the first electrode 151 and the second electrode 152 Upper surface.

The delivery device 210 can include a delivery device 212 disposed on top of the first adhesive layer 211.

For example, the transporting device 212 has a concave-convex structure so that it can easily adhere the semiconductor wafer to the first adhesive layer 211.

Referring to FIG. 7b, the semiconductor wafer 10 can be separated from the third substrate 110 while the semiconductor wafer 10 is adhered to the first adhesive layer 211 of the transport device 210. Therefore, the insulating layer 160 between the adjacent semiconductor wafers 10 can be separated.

Among the semiconductor devices, some of the semiconductor wafers 10 may be disposed on the third substrate 110. That is, the semiconductor wafer 10 that is not adhered to the first adhesive layer 211 of the transport device 210 may be disposed on the third substrate 110.

Referring to Figure 7C, the semiconductor wafer 10 adhered to the transport device 210 can be delivered to a panel. The second adhesive layer 310 can be disposed on the panel.

The semiconductor wafer 10 adhered to the transport device 210 can be adhered to the second adhesive layer 310 disposed on the panel.

The second adhesive layer 310 can be adhered to the coupling layer 130 and a portion of the insulating layer 160 at a lower portion of the semiconductor wafer 10. Light can be emitted to the first adhesive layer 211 and the second adhesive layer 310 on the transport device 210.

Light can separate the semiconductor wafer 10 from the first adhesive layer 211 adhered to the semiconductor wafer 10. In another aspect, the light can cure the second adhesive layer 310. Therefore, the adhesion between the semiconductor wafer 10 and the second adhesive layer 310 can be enhanced.

Referring to FIG. 7D, the transport device 210 can be isolated from the semiconductor wafer 10. Additionally, the semiconductor wafer 10 can be disposed on the panel.

In this case, the thickness of the coupling layer 130 may be formed to form an upper surface which is the same as the upper surface of another semiconductor wafer disposed on the display device.

The display device can be fabricated by repeating the processes described above with reference to Figures 7A through 7D. Further, the process can be applied to the semiconductor devices described in FIGS. 3, 4, and 5, and the semiconductor device according to the first embodiment.

Additionally, as shown in FIG. 7b, a separation may occur between the substrate 110 and the sacrificial layer 120, and may also occur between the coupling layer 130 and the substrate 110.

13 is a plan view and a cross-sectional view of a semiconductor device in accordance with a fourth embodiment.

Referring to FIG. 13, the semiconductor device according to the fourth embodiment includes a sacrificial layer 120; a coupling layer 130 disposed on the sacrificial layer 120; an interposer 170 disposed on the coupling layer 130; a semiconductor layer 141 disposed on the interposer 170; a first cladding layer 144 disposed on the first conductive semiconductor layer 141; an active layer 142 disposed on the first cladding layer 144; a conductive semiconductor layer 143 disposed on the active layer 142; a first electrode 151 connected to the first conductive semiconductor layer 141; a second electrode 152 connected to the second conductive semiconductor layer 143, and an insulating layer The layer 160 surrounds the sacrificial layer 120, the coupling layer 130, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142 and the second conductive semiconductor layer 143.

The sacrificial layer 120 may be a layer disposed at the bottom of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be the outermost layer in a first heavy main direction (one X2 direction). The sacrificial layer 120 may be disposed on a substrate (not shown).

The maximum width W1 of the sacrificial layer 120 in the second direction (Y-axis direction) may be in the range of 30 μm to 60 μm.

Here, the first direction is a thickness direction of the semiconductor structure 140 and includes a first main direction and a first main direction. The first main direction of the semiconductor structure 140 in the thickness direction is a direction from the first conductive semiconductor layer 141 toward a second conductive semiconductor layer 143. Similarly, the first major direction of the semiconductor structure 140 in the thickness direction is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141. Here, the second direction (Y axis) may be perpendicular to the first direction (X axis). Further, the second direction (Y axis) includes a second main direction (a Y1 direction) and a second main direction (a Y2 direction).

The sacrificial layer 120 can be a layer left after the semiconductor device is moved to the display device. For example, when the semiconductor device is transferred to the display device, one of the sacrificial layers 120 can be partially detached from the semiconductor device by the laser light emitted during the transfer, and the remaining portion can be left. In this example, the sacrificial layer 120 can comprise a material that is detachable at the wavelength of the emitted laser light. Further, the wavelength of the laser light may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.

The sacrificial layer 120 may comprise an oxide or a nitride. However, the invention is not limited thereto. For example, the sacrificial layer 120 may comprise an oxide-based material that is less deformed during epitaxial growth.

The sacrificial layer 120 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO), Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium-gallium Zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold (Ni /IrOx/Au), nickel/manganese oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al), Rh, Pd, Ir, Sn, In, Ru铪 (Hf).

The sacrificial layer 120 may have a thickness d12 greater than or equal to 20 nm in the first direction (X-axis). Preferably, the sacrificial layer 120 may have a thickness d12 greater than or equal to 40 nm in the first direction (X-axis direction).

The sacrificial layer 120 can be subjected to electron beam evaporation, thermal evaporation, metal-organic chemical vapor deposition (MOCVD) or sputtering, and pulsed laser deposition. , PLD) is formed, but is not limited to this.

The coupling layer 130 may be disposed on the sacrificial layer 120. The coupling layer 130 may comprise a material such as SiO2, SiNx, TiO2, polyimide, and a resin.

The coupling layer 130 may have a thickness d13 of one of 30 nm to 1 μm. However, the invention is not limited thereto. Here, the thickness may be one length in the X axis. The coupling layer 130 may be annealed to adhere the sacrificial layer 120 to the interposer 170. In this case, hydrogen ions are discharged from the coupling layer 130, and flaking may occur. In this case, the coupling layer 130 may have a surface roughness of 1 nm or less. According to this configuration, a separation layer and a coupling layer can be easily attached to each other. The locations of the coupling layer 130 and the sacrificial layer 120 can be interchanged.

The interposer 170 can be disposed on the coupling layer 130. The interposer 170 can comprise gallium arsenide (GaAs). The interposer 170 can be coupled to the sacrificial layer 120 through the coupling layer 130.

The semiconductor structure 140 can be disposed on the interposer 170. The semiconductor structure 140 may include the first conductive semiconductor layer 141 disposed on the interposer 170, and the first cladding layer 144 disposed on the first conductive semiconductor layer 141 disposed on the first cladding layer 144. The active layer 142 on the upper and the second conductive semiconductor layer 143 disposed on the active layer 142.

The first conductive semiconductor layer 141 may be disposed on the interposer 170. The first conductive semiconductor layer 141 may have a thickness d15 of one of 1.8 μm to 2.2 μm. However, the invention is not limited thereto.

The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

A first cladding layer 144 may be disposed on the first conductive semiconductor layer 141. The first cladding layer 144 can be disposed between the first conductive semiconductor layer 141 and the active layer 142. The first cladding layer 144 can include a plurality of layers. The first cladding layer 144 may include an AlInGaP-based layer/AlInP-based layer.

The first cladding layer 144 has a thickness d16 of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

The active layer 142 can be disposed on the first cladding layer 144. The active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. The active layer 142 is a layer, and electrons (or holes) injected by the first conductive semiconductor layer 141 are combined with electrons (or holes) injected by the second conductive semiconductor layer 143 in this layer. . Due to electron-hole recombination, the active layer 142 can be rotated to a lower order energy and produce ultraviolet wavelength light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness d17 of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

Since electrons are cooled in the first cladding layer 144, the active layer 142 can generate more radiation recombination.

The second conductive semiconductor layer 143 may be disposed on the active layer 142. The second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a and a second heavy main conductive semiconductor layer 143b.

The second main conductive semiconductor layer 143a may be disposed on the active layer 142. The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a.

The second main conductive semiconductor layer 143a may include TSBR and P-AllnP. The second main conductive semiconductor layer 143a may have a thickness d18 of 0.57 μm to 0.70 μm. However, the invention is not limited thereto.

The second main conductive semiconductor layer 143a may be made of a III-V compound semiconductor or a II-VI compound semiconductor. The second main conductive semiconductor layer 143a may be doped with a second dopant.

The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer.

The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

For example, the second heavy main conductive semiconductor layer 143b may be doped with magnesium (Mg) at a concentration of about 10×10 ¹⁸ , but is not limited thereto.

Furthermore, the second heavy-duty conductive semiconductor layer 143b may comprise a plurality of layers, and only some of the layers may be doped with magnesium.

The second heavy main conductive semiconductor layer 143b may have a thickness d19 of 0.9 μm to 1.1 μm. However, the invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141.

The first electrode 151 may be disposed on a portion of an upper surface of the first conductive semiconductor layer 141, the portion being mesa-etched. Therefore, the first electrode 151 can be disposed under the second electrode 152, and the second electrode 152 is disposed on top of the second conductive semiconductor layer 143.

The insulating layer 160 is in a second major direction (a Y2 direction), and a minimum width W2 between the boundary in the second major direction (Y2 direction) and the second electrode 152 is 2.5 μm. Within the range of 3.5 μm. Similarly, the insulating layer 160 is in a second main direction (a Y1 direction), and a minimum width W6 between the boundary in the second main direction (Y1 direction) and the first electrode 151 is 2.5 μm. To the range of 3.5 μm. However, the invention is not limited thereto.

The first electrode 151 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Hf), but not limited to this.

The first electrode 151 can be formed by any typical electrode formation method such as sputtering, coating, and deposition.

As described above, the second electrode 152 may be disposed on the second heavy-main conductive semiconductor layer 143b. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b.

The second electrode 152 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Hf), but not limited to this.

The second electrode 152 can be formed by any of the typical electrode formation methods, such as sputtering, coating, and deposition.

Further, the first electrode 151 may have a width greater than the width of the second electrode 152 in the second direction (Y-axis). However, the invention is not limited thereto.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130 and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120 and side surfaces of the coupling layer 130. The insulating layer 160 may partially cover an upper surface of the first electrode 151. According to this configuration, the first electrode 151 is electrically connected to an electrode or a pad through the exposed upper surface, so that current can be injected into the first electrode 151. Similarly, the first electrode 151 and the second electrode 152 may include an upper surface exposed to the outside. The insulating layer 160 covers the sacrificial layer 120 and the coupling layer 130 such that the sacrificial layer 120 and the coupling layer 130 may not be exposed.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. In addition, the insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the first electrode 151 may be partially exposed. The upper surface of the second electrode 152 may be partially exposed.

The upper surface of the first electrode 151 and the second electrode 152 exposed to the outside may have a circular shape, but is not limited. a width between a midpoint of one of the upper surfaces to which the first electrode 151 is exposed and a midpoint of one of the upper surfaces of the second electrode 152 exposed to the second direction (Y-axis) W4 can be in the range of 20 μm to 30 μm. Here, the midpoint refers to a position at which the width of the first electrode and the second electrode are halved, and the position is exposed to the outside in the second direction (Y-axis).

a maximum width between a boundary of one of the first electrodes 151 in the second main direction (Y1 direction) and a midpoint of the first electrode 151 exposed to the outside in a second main direction (a Y1 direction) W5 can be in the range of 5.5 μm to 7.5 μm. Further, in a second heavy main direction (Y2 direction), a boundary of the second electrode 152 in the second heavy main direction (Y2 direction) and the midpoint of the second electrode 152 exposed to the outside A maximum width W6 therebetween may be in the range of 5.5 μm to 7.5 μm. However, the invention is not limited thereto.

In the semiconductor structure 140, the insulating layer 160 electrically isolates the first conductive semiconductor layer 141 from the second conductive semiconductor layer 143. The insulating layer 160 may be made of at least one selected from the group consisting of SiO ₂ , Si _x O _y , Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ and AlN are not limited thereto.

14a to 14f are flow charts showing a method of fabricating the semiconductor device in accordance with the fourth embodiment.

Referring to Figure 14a, ions can be implanted into a donor substrate S. The donor substrate S may include an ion layer I. Through the ion layer I, the donor substrate S may include an interposer 170 disposed on one of its sides and a first layer 171 disposed on the other side. As will be described below, the interposer 170 can be a layer that is disposed on the coupling layer 130 of the semiconductor device of FIG. In this example, the donor substrate S can include the interposer 170 and the first layer 171.

The ions implanted into the donor substrate S may include hydrogen ions, but are not limited thereto. The ion layer I can be separated from a surface of the donor substrate S by a predetermined distance. The predetermined distance may be 2 μm or less. For example, the ion layer I can be separated from the surface of the donor substrate S by a distance of 2 μm. That is, the interposer 170 may have a thickness of 2 μm. Preferably, the thickness of the interposer 170 is in the range of 0.4 μm to 0.6 μm.

Referring to FIG. 14b, the sacrificial layer 120 may be disposed between the substrate 110 and the coupling layer 130. In addition, a separation layer 180 may be disposed between the substrate 110 and the sacrificial layer 120.

The substrate 110 may be a transparent substrate including sapphire (alumina), glass, or the like. Therefore, the substrate 110 can transmit laser light emitted from the bottom thereof. Accordingly, the sacrificial layer can absorb the laser light when the laser is peeled off.

For example, the separation layer 180 can promote regeneration of the substrate 110, which can be, for example, a sapphire substrate. Further, the separation layer 180 facilitates the transfer performed by laser peeling, which will be described with reference to Figs. 15a to 15e. The separation layer 180 can be fabricated using a material similar to that used to fabricate the coupling layer 130. For example, the separation layer 180 may include SiO ₂ .

In this example, the substrate 110, the separation layer 180, the sacrificial layer 120, and the coupling layer 130 may be sequentially stacked. In addition, a portion of the coupling layer 130 is disposed under the interposer 170 on a surface of the donor substrate S, and the portion may be adjacent to another portion of the coupling layer 130 disposed on the sacrificial layer 120. Therefore, a portion of the coupling layer 130 (below the interposer 170) may be disposed over another portion of the coupling layer 130 (above the sacrificial layer 120), and the coupling layer 130 The two parts can also be opposite each other.

In addition, as described above, the coupling layer 130 may include SiO ₂ . A portion of the coupling layer 130 disposed over the sacrificial layer 120 may be coupled to a portion of the coupling layer 130 disposed under the interposer 170 by an O ₂ plasma processing. However, the present invention is not limited thereto, and the cutting can be performed by a material other than oxygen. For example, portions of the coupling layer 130 above the sacrificial layer 120 and below the interposer 170 may have surfaces opposite to each other. An etching process, such as polishing and annealing, can be performed on the surfaces opposite to each other.

Therefore, the interposer 170 may be disposed on the substrate 110, the sacrificial layer 120 may be disposed on the interposer 170, the coupling layer 130 may be disposed on the sacrificial layer 120, and the donor substrate S may be from the coupling layer The top of 130 is partially separated. In addition, the donor substrate S can be obtained by forming the coupling layer at the bottom, forming the interposer 170 on the coupling layer 130, and forming the ion layer I and the first layer sequentially on the interposer 170. 171.

Referring to FIG. 14c, the interposer 170 separated from the donor substrate S may be disposed on the coupling layer 130. The ion layer I in Figure 14b is removed by liquid jet such that the first layer 171 can be detached from the interposer 170.

In this example, the first layer detached from the donor substrate can be used again as a substrate. For example, the first layer of detachment can be reused as the donor substrate of Figures 14a through 14c. In this example, the detached first layer, which is a donor substrate, may be composed of a new first layer, an ionic layer, and an interposer. Therefore, it is expected to reduce manufacturing costs as well as cost.

Accordingly, the interposer 170 can be disposed on the coupling layer 130.

Additionally, the semiconductor structure 140 can be disposed over the interposer 170. The interposer 170 can be in contact with the semiconductor structure 140. Since the void generated by the ion implantation process deteriorates the roughness of the upper surface of one of the interposer 170, the interposer 170 may cause a defect during epitaxial deposition. Therefore, the upper surface of the interposer 170 can be polished or planarized. For example, chemical mechanical planarization may be performed on the upper surface of the interposer 170, and after planarization, the semiconductor structure 140 may be disposed on the upper surface of the interposer 170. According to this configuration, the electrical characteristics of the semiconductor structure 140 are expected to be enhanced.

The semiconductor structure 140 can be disposed on the interposer 170. The semiconductor structure 140 may include the first semiconductor layer 141 disposed on the interposer 170, and the first cladding layer 144 disposed on the first semiconductor layer 141 disposed on the first cladding layer 144. The active layer 142 and the second conductive semiconductor layer 143 disposed on the active layer 142. The description made with reference to FIG. 13 can be applied to the semiconductor structure 140.

Referring to Figure 14d, a first etch may begin at the top of the semiconductor structure 140 up to a portion of the first conductive semiconductor layer 141.

The first etching may be a wet etching method or a dry etching method. However, the present invention is not limited thereto, and the first etching can be performed in various ways. The second electrode 152 of FIG. 14e may be disposed on the second conductive semiconductor layer 143 before being subjected to the first etching, and then patterned as shown in FIG. 14e, however, the present invention is not limited thereto.

Referring to Figure 14e, the second electrode 152 can be disposed on the top of the semiconductor structure 140. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b. The second electrode 152 may have a lower surface that is smaller than an upper surface of the second conductive semiconductor layer 143. For example, the second electrode 152 may have a boundary that is 1 μm to 3 μm from a boundary of the second conductive semiconductor layer 143.

The first electrode 151 and the second electrode 152 can be formed by any typical electrode formation method, such as sputtering, coating, and deposition. However, the invention is not limited thereto.

Further, as described above, the second electrode 152 may be formed before the first etching, and the first electrode 151 may be disposed on top of the first conductive semiconductor layer 141 that is etched and exposed.

The first electrode 151 and the second electrode 152 may be respectively disposed at positions separated from the substrate 110 by different distances. The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The second electrode 152 may be disposed on the second conductive semiconductor layer 143. In this example, the second electrode 152 may be disposed on the first electrode 151. However, the invention is not limited thereto.

For example, when the first conductive semiconductor layer 141 is disposed on the second conductive semiconductor layer 143, the first electrode 151 may be disposed on the second electrode 152.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141 and electrically connected to the first conductive semiconductor layer 141. The description made with reference to Fig. 13 can be applied to this example.

Referring to FIG. 14f, a second etching may be performed to reach an upper surface of the third substrate 110. The second etching may be a wet etching method or a dry etching method, but is not limited thereto. In the semiconductor device, the second etching can etch away a greater thickness than the first etching.

By the second etching, the semiconductor device disposed on the substrate can be isolated in the form of a plurality of wafers. For example, referring to Fig. 14f, two semiconductor devices can be disposed on the substrate 110 by the second etching. The number of semiconductor devices can be set differently depending on the size of the substrate and the size of each semiconductor device.

In addition, the insulating layer 160 may be disposed to cover the sacrificial layer 120, the coupling layer 130, the interposer 170, and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the interposer 170, and side surfaces of the semiconductor structure 140. The insulating layer 160 may cover a portion up to an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed. The exposed upper surface of the first electrode 151 is electrically connected to an electrode pad or the like, so that current can be injected into the first electrode 151. In addition, the insulating layer 160 may cover a portion up to an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed. The upper surface of the exposed second electrode 152 is electrically connected to an electrode pad or the like so that current can be injected into the second electrode 152. Alternatively, one of the insulating layers 160 may be partially disposed on top of the surface. The insulating layer 160 disposed between adjacent semiconductor wafers may be in contact with the substrate 110.

15a to 15e show a flow chart for explaining the flow of the semiconductor device of the fourth embodiment to a display device.

Referring to FIGS. 15a to 15e, a display device manufacturing method according to an embodiment may include selectively emitting laser light to a semiconductor including a plurality of semiconductor devices disposed on the substrate 110, and separating the semiconductors from the substrate. Semiconductor devices, and the semiconductor devices are placed on a panel substrate. Here, as described with reference to FIGS. 14a to 14f, one of the semiconductor devices before the transfer may include: a separation layer disposed on the substrate 110, a sacrificial layer disposed on the separation layer, disposed on the sacrificial layer a coupling layer, a semiconductor structure disposed on the coupling layer, a first electrode, a second electrode, and an insulating layer. In addition, the semiconductor structure may include a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer disposed between the first and second conductive semiconductor layers.

First, referring to Fig. 15a, a substrate 110 can be used in the same manner as the substrate 110 described with reference to Figs. 14a to 14f. Further, as described above, the semiconductor devices may be disposed on the substrate 110. For example, the semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. However, the invention is not limited thereto, and the semiconductor devices may be of different numbers.

Referring to Fig. 15b, at least one selected from the semiconductor devices 10-1, 10-2, 10-3, and 10-4 can be transferred to a growth substrate by a transport device 210. The conveying device 210 can have a first adhesive layer 211 and a conveying device 212 disposed at a lower portion thereof. For example, the transporting device 212 can have a concave-convex structure, and thus the semiconductor device can be easily adhered to the first adhesive layer 211.

Referring to FIG. 15c, when the transport device 210 is moved upward after the laser light is emitted, the first semiconductor device 10-1 and the third semiconductor device 10-3 can be detached from the transport device 210. In addition, the second adhesive layer 310 can be coupled to the first semiconductor device 10-1 and the third semiconductor device 10-3.

In detail, the laser light is emitted to the bottom of the selected semiconductor device such that the selected semiconductor device can be detached from the substrate 110. In this example, the transport device 210 is moved upwards and the semiconductor device can move with it. For example, the laser light is emitted to the bottom of the region of the substrate 110, wherein the first semiconductor device 10-1 and the third semiconductor device 10-3 are disposed, and then the first and third semiconductor devices 10-1, 10 -3 can be detached from the substrate 110. In addition, in order to detach a semiconductor device from the substrate 110 one by one, the transport device 210 and the adhesive layer 211 can be adhered to a semiconductor device.

For example, laser stripping using a photon beam having a particular wavelength range can be applied to one of the methods of detaching the semiconductor device from the substrate 110. For example, the laser light used may have a center wavelength of 266 nm, 532 nm, or 1064 nm, but is not limited thereto.

In addition, the separation layer 180 and the coupling layer 130 disposed between the semiconductor device and the substrate 110 can prevent physical damage of the semiconductor device due to laser peeling. A sacrificial layer can be detached from the semiconductor device by laser stripping. For example, a portion of the sacrificial layer can be removed by the detachment, and the remaining portion of the sacrificial layer can be removed with the coupling layer. Therefore, the semiconductor device, the sacrificial layer, is disposed on the sacrificial layer, and the semiconductor structure, the first electrode and the second electrode are detachable from the substrate 110. According to this configuration, the separation layer 180 can remain on the substrate 110. In addition, a portion of the sacrificial layer may remain on the upper surface of one of the separation layers 180, but is not limited thereto.

Further, the plurality of semiconductor devices detached from the substrate 110 may be spaced apart from each other by a predetermined distance. As described above, the first semiconductor device 10-1 and the third semiconductor device 10-3 can be detached from the growth substrate, and the second semiconductor device 10-2 and the fourth semiconductor device 10-4 (which are the same) The distance between the first and the third semiconductor devices 10-1, 10-3 can be separated from the growth substrate in the same manner. Therefore, the semiconductor devices having the same interval can be transferred to a display panel.

Referring to Figure 15d, the selected semiconductor device can be disposed on the panel substrate. For example, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be disposed on the panel substrate. In detail, the second adhesive layer 310 can be disposed on the panel substrate 300, and the first and third semiconductor devices 10-1, 10-3 can be disposed on the second adhesive layer 310. In this example, the first and third semiconductor devices 10-1, 10-3 can be adhered to the second adhesive layer 310. According to this method, it is expected that the transfer process efficiency can be improved by arranging the semiconductor devices having the same interval on the panel substrate.

Additionally, laser light can be emitted to isolate a selected semiconductor device from the first adhesive layer 211. For example, laser light is emitted upwardly to the transport device 210 such that the first adhesive layer 211 and the selected semiconductor device are physically separated from one another.

Referring to FIG. 15e, when the transport device 210 is moved upward after the laser light is emitted, the first semiconductor device 10-1 and the third semiconductor device 10-3 can be detached from the transport device 210. In addition, the second adhesive layer 310 can be coupled to the first semiconductor device 10-1 and the third semiconductor device 10-3.

Figure 16 is a diagram showing light transmittance in accordance with an embodiment and in accordance with the thickness of the sacrificial layer of the semiconductor device. In detail, according to an embodiment, when the semiconductor device does not have a sacrificial layer (A), when the semiconductor device has a thickness (B) of 10 nm, when the semiconductor device has a thickness (C) of 20 nm, when the semiconductor The device has a thickness (D) of one of 30 nm and a transmittance measurement when the semiconductor device has a thickness (E) of 40 nm.

When the semiconductor device does not have the sacrificial layer (A), the semiconductor device can provide light transmittance of 80% or more in most wavelength ranges. Therefore, it is difficult to transmit the laser light introduced through the substrate and used for laser peeling.

Furthermore, it can be seen from the graph that, according to an embodiment, as the thickness of the sacrificial layer in the semiconductor device increases, the transmittance in the low wavelength range decreases.

When the thickness of the sacrificial layer is 10 nm (B), the semiconductor device can transmit 60% or less of the laser light in the wavelength range of 310 nm or less. According to this configuration, the semiconductor device can absorb 40% or more of the laser light, and the laser light is introduced from the substrate through the sacrificial layer. Therefore, the semiconductor device disposed on the sacrificial layer is difficult to be separated from the substrate. .

Further, when the thickness of the sacrificial layer is 20 nm (C), the semiconductor device can transmit 50% or less of the laser light in the wavelength range of 310 nm or less. When the thickness of the sacrificial layer is 10 nm (B), when the thickness of the sacrificial layer is 20 nm (C), more laser light in the wavelength range of 310 nm or less can be transmitted.

This description can be applied even when the thickness of the sacrificial layer is 30 nm (D) and when the thickness of the sacrificial layer is 40 nm (E). When the thickness of the sacrificial layer is 30 nm (D) and 40 nm (E), the semiconductor device can transmit 40% or less of the laser light in the wavelength range of 310 nm or less. That is, the sacrificial layer can absorb 60% or more of light. In this example, the semiconductor device disposed on the sacrificial layer can be easily separated from the substrate.

Thus, in accordance with an embodiment, the semiconductor device can be fabricated by transmitting 266 nm laser light having a small center wavelength. In this example, according to an embodiment, the sacrificial layer of the semiconductor device may have a thickness of 20 nm or more. According to this configuration, it is possible to easily absorb 50% or more of the laser light in the wavelength range of 310 nm or less. Preferably, according to an embodiment, the sacrificial layer of the semiconductor device may have a thickness of 40 nm or more.

The ratio of the thickness of the sacrificial layer to the thickness of the coupling layer may range from 1:1.5 to 1:50. According to this configuration, it is expected that most of the laser light in the wavelength range of 310 nm or less is absorbed and the physical separation from the substrate can be easily performed by the light transmittance of 40% or less. However, when the ratio of the thickness of the sacrificial layer to the thickness of the coupling layer is less than 1:1.5, it may be difficult to detach from the growth substrate by using laser lift-off. When the ratio of the thickness of the sacrificial layer to the thickness of the coupling layer is greater than 1:50, a severe pressure occurs due to a difference in thermal expansion coefficient between the intermediate layer and the growth substrate, and a limitation occurs, that is, the isolation layer The epitaxial growth above can become difficult.

Further, the separation layer, the sacrificial layer and the total thickness of the coupling layer may be less than or equal to 3 μm.

Figure 17 is a diagram showing the spectral transmittance of the coupling layer of the semiconductor device in accordance with an embodiment.

Referring to Figure 17, the coupling layer of the semiconductor device according to an embodiment provides high transmittance (percentage) over most of the wavelength range. For example, the semiconductor device according to an embodiment can transmit light in the range of 0 nm to 800 nm, 90% or more.

In this case, the laser light introduced through the substrate can be transferred by the separation layer and then absorbed by the sacrificial layer. Therefore, the sacrificial layer can be partially separated from the substrate by the laser light. In addition, the sacrificial layer can absorb the portion of the laser light near the separation layer and then exit the substrate. In this example, as described with reference to FIG. 13, the sacrificial layer, the coupling layer, and the semiconductor structure can be separated from the substrate to form a single semiconductor device.

Figure 18 is a diagram showing the sacrificial layer and the coupling layer of the semiconductor device in accordance with an embodiment.

Referring to Figure 18, the semiconductor device can be flipped over. The sacrificial layer 120 can be connected to the coupling layer 130, and the coupling layer 130 can be disposed between the interposer and the sacrificial layer 120. As described above, the interposer and the semiconductor structure can be placed over the coupling layer 130 and the sacrificial layer 120. Further, the sacrificial layer 120 may have a thickness of 33 nm. Further, the coupling layer 130 may have a thickness of 189 nm. In this example, about 20 nm of the total thickness of the sacrificial layer 120 can be removed by laser light removal using laser lift-off. According to this configuration, the thickness of the sacrificial layer 120 may be greater than or equal to 20 nm before being transferred. In this example, the semiconductor device may ultimately have a structure in which the sacrificial layer 120 and the coupling layer 130 may be placed under the interposer by using laser lift-off.

Figure 19 is a modified version of Figure 13.

Referring to FIG. 19, in accordance with a modified version of the present invention, a semiconductor device can include: a sacrificial layer 120; a coupling layer 130 disposed on the sacrificial layer 120; an interposer 170 disposed on the coupling layer 130 And a semiconductor structure 140 disposed on the interposer 170.

In addition, the semiconductor structure 140 can include a first conductive semiconductor layer 141, a second conductive semiconductor layer 143, and an active layer 142 disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. In addition, the second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a disposed adjacent to the active layer 142 and a second heavy main conductive semiconductor layer 143b disposed adjacent to the interposer 170. In addition, the semiconductor device can include a first electrode 151 connected to the first conductive semiconductor layer 141, a second electrode 152 connected to the second heavy-main conductive semiconductor layer 143b, and an insulating layer 160. The cover layer 130 and the semiconductor structure 140 are covered.

The sacrificial layer 120, the coupling layer 130, and the interposer 170 are applicable to the description made with reference to FIG.

Also. The second heavy main conductive semiconductor layer 143b may be disposed on the interposer 170. The second heavy main conductive semiconductor layer 143b may have a thickness of 3.15 μm to 3.85 μm. However, the invention is not limited thereto.

The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143b is electrically connected to the second electrode 152.

The second electrode 152 may be formed on one side of the top of the second heavy main conductive semiconductor layer 143b. The second electrode 152 can be placed under the first electrode 151.

The second main conductive semiconductor layer 143a may be disposed over the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143a may be disposed between the second main conductive semiconductor layer 143b and the active layer 142.

The second main conductive semiconductor layer 143a may have a thickness d8 of 0.57 μm to 0.69 μm. However, the invention is not limited thereto. The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer. The second main conductive semiconductor layer 143a may include TSBR and P-AllnP.

The active layer 142 may be disposed on the second main conductive semiconductor layer 143a. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second main conductive semiconductor layer 143a are layered in this layer. Combine. Due to electron-hole recombination, the active layer 142 can be rotated to a lower order energy and produce ultraviolet wavelength light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness d9 of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

A first cladding layer 144 can be disposed on the active layer 142. The first cladding layer 144 may be disposed between the active layer 142 and the first conductive semiconductor layer 141.

The first cladding layer 144 may comprise aluminum indium gallium phosphide (AlInP). The first cladding layer 144 has a thickness of one of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

The first conductive semiconductor layer 141 may be disposed on the first cladding layer 144. The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first conductive semiconductor layer 141 may have a thickness of one of 0.45 μm to 5.5 μm. However, the invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141. The first electrode 151 can be placed over the second electrode 152.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130 and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the side surface of the semiconductor structure 140.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed.

The insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

Figure 20a is a plan view and a cross-sectional view of a semiconductor device according to a fifth embodiment, and Figure 20b is an enlarged view of a portion A of Figure 20a. Referring to FIG. 20a, the semiconductor device according to the fifth embodiment includes: a sacrificial layer 120; a coupling layer 130 disposed on the sacrificial layer 120; and an interposer 170 disposed on the coupling layer 130; a reflective layer 190 disposed on the interposer 170; a first conductive semiconductor layer 141 disposed on the reflective layer 190; a first cladding layer 144 disposed on the first conductive semiconductor layer 141; An active layer 142 is disposed on the first cladding layer 144; a second conductive semiconductor layer 143 is disposed on the active layer 142; a first electrode 151 electrically connected to the first conductive semiconductor layer 141; a second electrode 152 electrically connected to the second conductive semiconductor layer 143, and an insulating layer 160 surrounding the sacrificial layer 120, the coupling layer 130, the first conductive semiconductor layer 141, the first package The cladding layer 144, the active layer 142 and the second conductive semiconductor layer 143.

According to the embodiment, the sacrificial layer 120 can be a layer disposed at the bottom of the semiconductor device. That is, the sacrificial layer 120 may be the outermost layer in a first heavy main direction (one X2 direction). The sacrificial layer 120 can be disposed on a substrate (not shown).

The maximum width W1 of the sacrificial layer 120 in a second direction (a Y-axis direction) may range from 30 μm to 60 μm.

Here, a first direction (an X-axis direction) is one of the thickness directions of the semiconductor structure 140 and includes a first main direction (one X1 direction) and a first main main direction (one X2 direction). The first main direction (the X1 direction) of the semiconductor structure 140 in the thickness direction is a direction from the first conductive semiconductor layer 141 toward the second conductive semiconductor layer 143. Similarly, the first major direction (the X2 direction) of the semiconductor structure 140 in the thickness direction is a direction from the second conductive semiconductor layer 143 toward the first conductive semiconductor layer 141. Here, the second direction (the Y axis) may be perpendicular to the first direction (the X axis). Further, the second direction (the Y axis) includes a second main direction (a Y1 direction) and a second main direction (a Y2 direction).

The sacrificial layer 120 can be a layer left after the semiconductor device is moved to the display device, as shown in FIG. 23c. For example, when the semiconductor device is transferred to the display device, one of the sacrificial layers 120 can be partially detached from the semiconductor device by the laser light emitted during the transfer, and the remaining portion can be left. In this example, the sacrificial layer 120 can comprise a material that is detachable at the wavelength of the emitted laser light. Further, the wavelength of the laser light may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.

The sacrificial layer 120 may comprise an oxide or a nitride. However, the invention is not limited thereto. For example, the sacrificial layer 120 may comprise an oxide-based material that is less deformed during epitaxial growth.

The sacrificial layer 120 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO), Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium-gallium Zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold (Ni /IrOx/Au), nickel/manganese oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al), Rh, Pd, Ir, Sn, In, Ru铪 (Hf).

The sacrificial layer 120 may have a thickness d20 greater than or equal to 20 nm in the first direction (X-axis direction). Preferably, the sacrificial layer 120 may have a thickness d20 greater than or equal to 40 nm in the first direction (X-axis direction).

The sacrificial layer 120 can be subjected to electron beam evaporation, thermal evaporation, metal-organic chemical vapor deposition (MOCVD) or sputtering, and pulsed laser deposition. , PLD) is formed, but is not limited to this.

The coupling layer 130 may be disposed on the sacrificial layer 120. The coupling layer 130 may comprise a material such as SiO2, SiNx, TiO2, polyimide, and a resin.

The coupling layer 130 may have a thickness d21 of one of 30 nm to 1 μm. However, the invention is not limited thereto. Here, the thickness may be one length in the X axis. The coupling layer 130 may be annealed to adhere the sacrificial layer 120 to the interposer 170. This will be described below with reference to Figures 21b and 21c. Further, during the adhesion, hydrogen ions are discharged from the coupling layer 130, and flaking may occur. In this case, the coupling layer 130 may have a surface roughness of 1 nm or less. According to this configuration, a separation layer and a coupling layer can be easily attached to each other. The locations of the coupling layer 130 and the sacrificial layer 120 can be interchanged.

The interposer 170 can be disposed on the coupling layer 130. The interposer 170 may comprise GaInP and GaAs. The interposer 170 can be coupled to the sacrificial layer 120 through the coupling layer 130. Further, the interposer 170 may be a structure in which n-GaAs and GaAs are stacked. For example, the interposer 170 can include a first layer and a second layer (not shown), the first layer comprising GaAs and the second layer comprising n-GaAs.

The reflective layer 190 can be disposed on the interposer 170. The reflective layer 190 can be in contact with the semiconductor structure 140 and the interposer 170.

Further, the reflective layer 190 may have a distributed Bragg reflector (DBR) structure and may include, for example, AlGaAs. Additionally, the reflective layer 190 can have a structure in which a plurality of materials are alternately stacked in a plurality of layers having different compositions of Al and Ga. Therefore, the reflective layer 190 can reflect light with a certain wavelength. For example, the reflective layer 190 can reflect red light. That is, by using a plurality of rather than a single distributed Bragg mirror to the reflective layer 190 to increase its stop-band bandwidth, it is expected to increase the reflectivity of light and the speed of light. Furthermore, the reflective layer 190 can be composed of a plurality of layers having different refractive indices.

The reflective layer 190 can reflect light generated by the semiconductor structure 140 upward. Therefore, the amount of light provided upward from the semiconductor structure 140 is expected to increase. Additionally, the reflective layer 190 can block light generated at the semiconductor structure 140 from being provided to the interposer 170 (underlying the reflective layer 190). Thus, the light generated at the semiconductor structure 140 is not absorbed by the interposer 170 disposed under the reflective layer 190, and most of the light generated at the semiconductor structure 140 can be provided upward. Accordingly, the optical performance of the semiconductor device according to the embodiment is expected to increase. The semiconductor structure 140 can be disposed on the reflective layer 190. The semiconductor structure 140 may include a first conductive semiconductor layer 141 disposed on the reflective layer 190, and a first cladding layer 144 disposed on the first conductive semiconductor layer 141 disposed on the first cladding layer 144. The upper active layer 142 and one of the second conductive semiconductor layers 143 disposed on the active layer 142.

The reflective layer 190 may have a thickness d22 of one of 3 μm to 4 μm.

The first conductive semiconductor layer 141 may be disposed on the reflective layer 190. The first conductive semiconductor layer 141 may have a thickness of one of 1.8 μm to 2.2 μm (d23+d24). However, the invention is not limited thereto.

The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

Further, the first conductive semiconductor layer 141 may have a doping concentration of 1.00E + ¹⁹ or more. Due to the doping concentration, the first conductive semiconductor layer 141 can be easily ohmic contact with the first electrode 151. According to this configuration, the first conductive semiconductor layer 141 can increase the injected current and thus improve the luminous efficiency.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first cladding layer 144 may be disposed on the first conductive semiconductor layer 141. The first cladding layer 144 can be disposed between the first conductive semiconductor layer 141 and the active layer 142. The first cladding layer 144 can include a plurality of layers. The first cladding layer 144 may include an AlInGaP-based layer/AlInP-based layer. However, the invention is not limited thereto.

The first cladding layer 144 has a thickness d25 of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

The active layer 142 can be disposed on the first cladding layer 144. The active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. The active layer 142 is a layer, and electrons (or holes) injected by the first conductive semiconductor layer 141 are combined with electrons (or holes) injected by the second conductive semiconductor layer 143 in this layer. . Due to electron-hole recombination, the active layer 142 can be switched to a lower order energy and produce red light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness d26 of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

Since the electrons are cooled in the first cladding layer 144, the active layer 142 can generate more radiation recombination.

The second conductive semiconductor layer 143 may be disposed on the active layer 142. The second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a and a second heavy main conductive semiconductor layer 143b.

The second main conductive semiconductor layer 143a may be disposed on the active layer 142. The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a.

The second main conductive semiconductor layer 143a may include TSBR and P-AllnP. The second main conductive semiconductor layer 143a may have a thickness d27 of one of 0.57 μm to 0.70 μm. However, the invention is not limited thereto.

The second main conductive semiconductor layer 143a may be made of a III-V compound semiconductor or a II-VI compound semiconductor. The second main conductive semiconductor layer 143a may be doped with a second dopant.

The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with the second dopant may be a p-type semiconductor layer.

The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

In addition, the second heavy main conductive semiconductor layer 143b may include a plurality of layers, and only some of the layers may be doped with magnesium, but are not limited thereto.

The second heavy main conductive semiconductor layer 143b may have a thickness d28 of 0.9 μm to 1.1 μm. However, the invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141.

The first electrode 151 may be disposed on a portion of an upper surface of the first conductive semiconductor layer 141, the portion being mesa-etched. Therefore, the first electrode 151 can be disposed under the second electrode 152, and the second electrode 152 is disposed on top of the second conductive semiconductor layer 143.

The first electrode 151 can be in ohmic contact with the first conductive semiconductor layer 141. In this example, a current can be injected into the first conductive semiconductor layer 141 through the first electrode 151.

The first electrode 151 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Hf), but not limited to this.

The first electrode 151 can be formed by any typical electrode formation method such as sputtering, coating, and deposition.

As described above, the second electrode 152 may be disposed on the second heavy-main conductive semiconductor layer 143b. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b.

The second electrode 152 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium zinc aluminum oxide (IAZO), indium gallium zinc oxide (IGZO). Indium tin oxide gallium (IGTO), zinc aluminum oxide (AZO), antimony tin oxide (ATO), zinc gallium oxide (GZO), indium zinc oxide (IZON), aluminum-gallium zinc oxide (AGZO), indium- Gallium zinc oxide (IGZO), zinc oxide (ZnO), yttrium oxide (IrOx), yttrium oxide (RuOx), nickel oxide (NiO), yttrium oxide/indium tin oxide (RuOx/ITO), nickel/yttria/gold ( Ni/IrOx/Au), nickel/yttrium oxide/indium tin oxide (Ni/IrOx/Au/ITO), Ag (silver), nickel (Ni), chromium (Cr), titanium (Ti), aluminum (Al) , rhodium (Rh), palladium (Pd), iridium (Ir), tin (Sn), indium (In), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au) And 铪 (Hf), but not limited to this.

The second electrode 152 can be formed by any of the typical electrode formation methods, such as sputtering, coating, and deposition.

Further, the first electrode 151 may have a larger width than the second electrode 152 in a second direction (a Y-axis direction). However, the invention is not limited thereto.

The insulating layer 160 may be disposed on the following layers: the sacrificial layer 120, the coupling layer 130, the interposer 170, the reflective layer 190, the first conductive semiconductor layer 141, the active layer 142, and the second conductive semiconductor. The layer 143, the first electrode 151 and the second electrode 152.

The insulating layer 160 is in a second major direction (a Y2 direction), and a minimum width W2 between the boundary in the second major direction (Y2 direction) and the second electrode 152 is 2.5 μm. Within the range of 3.5 μm. Similarly, the insulating layer 160 is in a second main direction (a Y1 direction), and a minimum width W6 between the boundary in the second main direction (Y1 direction) and the first electrode 151 is 2.5 μm. To the range of 3.5 μm. However, the invention is not limited thereto.

The insulating layer 160 may partially cover the first electrode 151 and the second electrode 152. Therefore, each of the first electrode 151 and the second electrode 152 may include a partially exposed area. In addition, the insulating layer 160 may cover the sacrificial layer 120 and the side surface of the coupling layer 130. The insulating layer 160 may partially cover an upper surface of the first electrode 151. According to this configuration, the first electrode 151 is electrically connected to an electrode or a pad through the exposed upper surface, so that current can be injected into the first electrode 151. Similarly, the first electrode 151 and the second electrode 152 may include an upper surface exposed to the outside. The insulating layer 160 covers the sacrificial layer 120 and the coupling layer 130 such that the sacrificial layer 120 and the coupling layer 130 may not be exposed.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. In addition, the insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the first electrode 151 may be partially exposed. The upper surface of the second electrode 152 may be partially exposed.

The upper surface of the first electrode 151 and the second electrode 152 exposed to the outside may have a circular shape, but is not limited. a width between a midpoint of one of the upper surfaces to which the first electrode 151 is exposed and a midpoint of one of the upper surfaces of the second electrode 152 exposed to the second direction (Y-axis) W4 can be in the range of 20 μm to 30 μm. Here, the midpoint refers to a position at which the width of the first electrode and the second electrode are halved, and the position is exposed to the outside in the second direction (Y-axis).

a maximum width between a boundary of one of the first electrodes 151 in the second main direction (Y1 direction) and a midpoint of the first electrode 151 exposed to the outside in a second main direction (a Y1 direction) W5 can be in the range of 5.5 μm to 7.5 μm. Further, in a second heavy main direction (Y2 direction), a boundary of the second electrode 152 in the second heavy main direction (Y2 direction) and the midpoint of the second electrode 152 exposed to the outside A maximum width W6 therebetween may be in the range of 5.5 μm to 7.5 μm. However, the invention is not limited thereto.

In the semiconductor structure 140, the insulating layer 160 electrically isolates the first conductive semiconductor layer 141 from the second conductive semiconductor layer 143. The insulating layer 160 may be made of at least one selected from the group consisting of SiO ₂ , Si _x O _y , Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ and AlN are not limited thereto.

Further, the reflective layer 190 may be disposed on the interposer 170. The reflective layer 190 can be in contact with the semiconductor structure 140. The reflective layer 190 can have a structure in which a plurality of materials are alternately stacked in several layers having different compositions of Al and Ga. Therefore, the reflective layer 190 can reflect light with a certain wavelength. For example, the reflective layer 190 can reflect red light. That is, by using multiple rather than a single distributed Bragg mirror to the reflective layer 190 to increase its stop-band bandwidth, it is expected to increase the reflectivity of light and the speed of light. Furthermore, the reflective layer 190 can be composed of a plurality of layers having different refractive indices.

Referring to Fig. 20b, the reflective layer 190 can include a first layer 191 having a first index of refraction and a second layer 192 having a second index of refraction that is different from one of the first indices of refraction. That is, the reflective layer 190 can have a structure in which layered interactions with different refractive indices are repeated and stacked. For example, the refractive index of the first layer 191 can be less than the refractive index of the second layer 192. However, the invention is not limited thereto.

When λ is a wavelength of light generated at the active layer 142, n is a refractive index of a medium, and m is an odd number, the reflective layer 190 may have a structure in which the first layer 191 is The second layer 192 interacts and repeats stacking to a thickness of mλ/4n, and thus provides a reflectance of 95% or higher relative to light of a particular wavelength λ. For example, the reflective layer 190 can reflect 95% or higher light having a center wavelength of 620 nm.

Accordingly, the first layer 191 and the second layer 192 can have a thickness equal to a λ/4 multiple of the same reference wavelength. In this example, each of the first layer 191 and each of the second layers 192 may have a thickness of 40 nm to 50 nm. Further, the thickness of the first layer 191 is greater than the thickness of the second layer 192.

Further, each of the first layer 191 and each of the second layers 192 forming the reflective layer 190 may be formed of Al _x Ga _y As (x + y = 1). For example, the first layer 191 can have a higher Al composition than the second layer 192. For example, the first layer 191 can be Al _0.9 Ga _0.1 As and the second layer 192 can be Al _0.5 Ga _0.5 As.

By increasing the refractive index of the medium between the first layer 191 and the second layer 192, it is expected to improve the reflectivity. Further, since the band gap energy is larger than an oscillation wavelength, the reflection layer 190 cannot absorb light completely, and thus the reflectivity of light is expected to be enhanced.

In addition, a band gap buffer layer (not shown) may be disposed on the reflective layer 190. The band gap buffer layer may comprise (Al _0.85 Ga _0.15 ) _0.5 In _0.5 P. The band gap buffer layer may have a thickness of 180 nm to 220 nm. Additionally, the bandgap buffer layer can have a larger energy band gap than the active layer 142. According to this configuration, the band gap buffer layer can transmit light generated by the active layer 142 and also contact the first conductive semiconductor layer 141 (disposed over the band gap buffer layer).

Referring again to Fig. 20, when a height difference between a first upper surface K1 and a second upper surface K2 is greater than 2 μm, the wafer is misaligned during a transfer process (Figs. 23 and 25). A transfer process refers to the process of moving a wafer from a growth substrate. That is, as the height difference increases, maintaining the horizontal state of the wafer may become difficult.

In this example, the first upper surface K1 and the second upper surface K2 have a height difference dh of 350 nm to 2.0 μm. When the height difference dh is larger than 2.0 μm, a linear deviation may occur while a semiconductor device is being transferred, and thus it is difficult to transfer the semiconductor device to a desired position. Further, when the height difference dh is less than 350 nm, the first conductive semiconductor layer 141 may not be partially exposed.

When the height difference dh between the first upper surface K1 and the second upper surface K2 is less than 1.0 μm, the upper surface of the semiconductor can become nearly flat, so that it is expected to facilitate the transfer and suppress the occurrence of cracking. For example, the height difference dh between the first upper surface K1 and the second upper surface K2 may be 0.6 μm ± 0.2 μm, but is not limited thereto.

Here, the first upper surface K1 may be defined as a surface, wherein the first conductive semiconductor layer 141 is exposed to the outside after the first etching (see FIG. 21d), and the second upper surface K2 may be defined as the first The upper surface of the second conductive semiconductor layer 143.

21a to 21f are flowcharts showing a method of manufacturing the semiconductor device according to the fourth embodiment.

Referring to Figure 21a, ions can be implanted into a donor substrate S. The donor substrate S may include an ion layer I. Through the ion layer I, the donor substrate S may include an interposer 170 disposed on one of its sides and a first layer 171 disposed on the other side. As will be described below, the interposer 170 can be a layer that is disposed on the coupling layer 130 of the semiconductor device of FIG. In this example, the donor substrate S can include the interposer 170 and the first layer 171.

The ions implanted into the donor substrate S may include hydrogen ions, but are not limited thereto. The ion layer I can be separated from a surface of the donor substrate S by a predetermined distance. The predetermined distance may be 2 μm or less. For example, the ion layer I may be separated from the surface of the donor substrate S by a distance of 2 μm or less. That is, the interposer 170 may have a thickness of 2 μm or less. Preferably, the thickness of the interposer 170 is in the range of 0.4 μm to 0.6 μm, but is not limited.

Referring to FIG. 21b, the sacrificial layer 120 may be disposed between the substrate 110 and the coupling layer 130. In addition, a separation layer 180 may be disposed between the substrate 110 and the sacrificial layer 120.

The substrate 110 may be a transparent substrate including sapphire (alumina), glass, or the like. Therefore, the substrate 110 can transmit laser light emitted from the bottom thereof. Accordingly, the sacrificial layer can absorb the laser light when the laser is peeled off, so that the sacrificial layer 120 can be detached from the substrate 110.

Additionally, the separation layer 180 can promote regeneration of the substrate 110, such as a sapphire substrate. Although the separation layer 180 is not disposed on the substrate 110, laser light emitted from the bottom of the substrate 110 toward the sacrificial layer 120 may perform laser lift-off.

Further, the separation layer 180 facilitates the transfer performed by the laser peeling, which will be described with reference to Figs. 23a to 23e. The separation layer 180 can be fabricated using a material similar to that used to fabricate the coupling layer 130. For example, the separation layer 180 may include SiO ₂ .

In this example, the substrate 110, the separation layer 180, the sacrificial layer 120, and the coupling layer 130 may be sequentially stacked. Since the coupling layer 130 is disposed on the sacrificial layer 120, a portion of the coupling layer 130 is disposed under the interposer 170 on a surface of the donor substrate S, and the portion may be adjacent to the coupling layer 130. Another portion of the coupling layer 130 is disposed over the sacrificial layer 120, and thus the two portions of the coupling layer 130 may oppose each other.

In addition, as described above, the coupling layer 130 may include SiO ₂ . A portion of the coupling layer 130 disposed over the sacrificial layer 120 may be coupled to a portion of the coupling layer 130 disposed under the interposer 170 by an O ₂ plasma processing. However, the present invention is not limited thereto, and the cutting can be performed by a material other than oxygen. For example, portions of the coupling layer 130 above the sacrificial layer 120 and below the interposer 170 may have surfaces opposite to each other. An etching process, such as polishing and annealing, can be performed on the surfaces opposite to each other.

Therefore, the interposer 170 may be disposed on the substrate 110, the sacrificial layer 120 may be disposed on the interposer 170, the coupling layer 130 may be disposed on the sacrificial layer 120, and the donor substrate S may be from the coupling layer The top of 130 is partially separated. In addition, the donor substrate S can be obtained by forming the coupling layer at the bottom, forming the interposer 170 on the coupling layer 130, and forming the ion layer I and the first layer sequentially on the interposer 170. 171.

Referring to FIG. 21c, the interposer 170 separated from the donor substrate s may be disposed on the coupling layer 130. In Fig. 21b, liquid ejection removal can be performed on the ion layer I starting from one side P of the ion layer 1. The ion layer I is removed by liquid jet such that the first layer 171 can be detached from the interposer 170.

In this example, the first layer 171 detached from the donor substrate can be used again as a substrate. For example, the detached first layer 171 can be reused as the donor substrate of Figures 21a-21c. In this example, the detached first layer 171, which is a donor substrate, may be composed of a new first layer, an ion layer, and an interposer. Therefore, it is expected to reduce manufacturing costs as well as cost.

Accordingly, the interposer 170 can be disposed on the coupling layer 130.

The interposer 170 can be in contact with the reflective layer 190. The roughness of the upper surface of one of the interposing layers 170 is deteriorated due to voids generated by the ion implantation process. Therefore, when the semiconductor structure 140 is deposited, defective epitaxial deposition may occur. In this example, the upper surface of the interposer 170 can be polished. Accordingly, the upper surface of the interposer 170 may be planarized to reduce roughness and reduce the occurrence of defects in the semiconductor structure 140. For example, chemical mechanical planarization may be performed on the upper surface of the interposer 170, and after planarization, the semiconductor structure 140 may be disposed on the upper surface of the interposer 170. According to this configuration, the electrical characteristics of the semiconductor structure 140 are expected to be enhanced.

The reflective layer 190 can be disposed on the interposer 170. The reflective layer 190 can be in contact with the semiconductor structure 140. As described above, the reflective layer 190 can have a distributed Bragg reflector (DBR) structure and can include, for example, AlGaAs. Additionally, the reflective layer 190 can have a structure in which a plurality of materials are alternately stacked in a plurality of layers having different compositions of Al and Ga. Therefore, the reflective layer 190 can reflect light with a certain wavelength. For example, the reflective layer 190 can reflect red light. That is, by using multiple rather than a single distributed Bragg mirror to the reflective layer 190 to increase its stop-band bandwidth, it is expected to increase the reflectivity of light and the speed of light. Furthermore, the reflective layer 190 can be composed of a plurality of layers having different refractive indices.

The reflective layer 190 can reflect light generated by the semiconductor structure 140 upward. Therefore, the amount of light provided upward from the semiconductor structure 140 is expected to increase. Additionally, the reflective layer 190 can block light generated at the semiconductor structure 140 from being provided to the interposer 170 (underlying the reflective layer 190). Thus, the light generated at the semiconductor structure 140 is not absorbed by the interposer 170 disposed under the reflective layer 190, and most of the light generated at the semiconductor structure 140 can be provided upward. Accordingly, the optical performance of the semiconductor device according to the embodiment is expected to increase.

The semiconductor structure 140 can be disposed on the reflective layer 190. The semiconductor structure 140 may include a first conductive semiconductor layer 141 disposed on the reflective layer 190, and a first cladding layer 144 disposed on the first conductive semiconductor layer 141 disposed on the first cladding layer 144. The upper active layer 142 and one of the second conductive semiconductor layers 143 disposed on the active layer 142. The description made with reference to Figure 20a is applicable to the semiconductor structure 140.

Referring to Figure 20d, a first etch may begin at the top of the semiconductor structure 140 up to a portion of the first conductive semiconductor layer 141.

The first etching may be a wet etching method or a dry etching method, but is not limited, and the first etching may be performed in various ways. Before the first etching, the second electrode 152 of FIG. 21e may be disposed on the second conductive semiconductor layer 143, and then patterned as shown in FIG. 21e, however, the present invention is not limited thereto.

Referring to FIG. 21e, the second electrode 152 can be disposed on top of the semiconductor structure 140. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b. The second electrode 152 may have a lower surface that is smaller than an upper surface of the second conductive semiconductor layer 143. For example, the second electrode 152 may have a boundary that is 1 μm to 3 μm from a boundary of the second conductive semiconductor layer 143.

The first electrode 151 and the second electrode 152 can be formed by any typical electrode formation method, such as sputtering, coating, and deposition. However, the invention is not limited thereto.

In addition, as described above, the second electrode 152 may be formed before the first etching, and after the first etching, the first electrode 151 may be disposed on the first conductive semiconductor layer 141 that is etched and exposed. On top of it.

The first electrode 151 and the second electrode 152 may be disposed at positions spaced apart from the third substrate 110 by different distances. The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The second electrode 152 may be disposed on the second conductive semiconductor layer 143. In this example, the second electrode 152 may be disposed above the first electrode 151. However, the invention is not limited thereto.

For example, when the first conductive semiconductor layer 141 is disposed over the second conductive semiconductor layer 143, the first electrode 151 may be disposed on the second electrode 152.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141 and electrically connected to the first conductive semiconductor layer 141. The description made with reference to Fig. 20a can be applied to this example.

Referring to FIG. 21f, a second etching may be performed to reach an upper surface of the substrate 110 or a lower surface of the sacrificial layer 120. The second etching may be a wet etching method or a dry etching method, but is not limited thereto. In the semiconductor device, the second etching can be etched by a greater thickness than the first etching.

A plurality of semiconductor devices can be disposed on the substrate by the second etching. That is, the semiconductor devices can be isolated in the form of a plurality of wafers. For example, referring to FIG. 21f, two semiconductor devices can be disposed on the substrate 110 by the second etching. The number of the semiconductor devices can be set differently depending on the size of the substrate and the size of each semiconductor device.

In addition, the insulating layer 160 can be disposed to cover the sacrificial layer 120, the coupling layer 130, the interposer 170, the reflective layer 190, and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the interposer 170, the reflective layer 190, and side surfaces of the semiconductor structure 140. The insulating layer 160 may partially cover an upper surface of the first electrode 151. For example, the upper surface of the first electrode 151 may be partially exposed. In addition, the exposed upper surface of the first electrode 151 is electrically connected to an electrode pad or the like to enable current to be injected into the first electrode 151.

Likewise, the insulating layer 160 may cover a portion of one of the upper surfaces of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed. Like the first electrode 151, the exposed upper surface of the second electrode 152 is electrically connected to an electrode pad or the like so that current can be injected into the second electrode 152. In addition, one of the insulating layers 160 may be partially disposed on top of the surface of the second electrode 152. The insulating layer 160 disposed between adjacent semiconductor wafers may be in contact with the substrate 110.

22a and 22b illustrate the flow of transferring a plurality of semiconductor devices of a wafer to a donor substrate, and FIGS. 23a and 23b illustrate a flow chart for transferring a plurality of semiconductor devices from a wafer to a donor device. The flow of the substrate.

Referring to Figures 22a and 22b, the semiconductor devices 10 as described above may be disposed on a single wafer 1. In addition, the semiconductor devices 10 on the wafer 1 can be transferred to a plurality of donor substrates for the first time.

In Fig. 22a and Fig. 22b, the wafer 1 may have a size of 6 inches, but is not limited thereto. Further, the semiconductor device 10 may have a size of 21 μm × 45 μm, but is not limited thereto.

For example, in Figure 22a, a plurality of semiconductor devices 10 can be disposed within a first width P1. Further, a plurality of semiconductor devices 10 may be disposed within a second width P2. The first width P1 may be a length in one direction in which a plurality of semiconductor devices 10 are disposed, and the second width P2 may be a length in another direction perpendicular to the direction.

The first width P1 and the second width P2 may have the same length. Each of the first width P1 and the second width P2 may be an interval, and the semiconductor devices are disposed on a panel substrate according to the interval, which will be described later. For example, each of the first width P1 and the second width P2 may be 834 μm, but may vary depending on the interval in which the semiconductor devices are disposed on the panel substrate.

Further, as described above, in FIG. 22b, the semiconductor devices 10 placed in a predetermined region K of the wafer 1 can be transferred to the donor substrate 210. The predetermined area K may have the same size as the donor substrate 210, but is not limited. Further, the semiconductor devices 10 disposed in the predetermined region K at predetermined intervals may be transferred to the donor substrate 210. The donor substrate 210 and the semiconductor devices 10 disposed on the donor substrate 210 can constitute a semiconductor module.

In addition, the number of the donor substrate 210 produced by the single wafer 1 may vary depending on the size of the wafer 1 and the donor substrate 210. For example, when the size of the wafer 1 is 6 Å, 5.4 million semiconductor devices can be disposed on the wafer 1. Further, when the size of the donor substrate 210 is 100.8 mm × 100.8 mm, 375 donor substrates 210 can be produced for each wafer 1. However, as described above, the number of the donor substrate may vary depending on the size of the wafer and the donor substrate.

Further, the donor substrate 210 may have a third length P3 which is a length in one direction and has a fourth length P4 which is a length in the other direction. Here, the third and fourth lengths P3 and P4 may have the same length. According to this configuration, when the donor substrate 210 is transferred to a panel substrate, the panel substrate can include a plurality of regions having the same wavelength pattern and the same size. In addition, in the panel substrate, a wavelength difference between a plurality of semiconductor devices of the same color may be less than or equal to a certain value at a boundary between regions of the same size. For example, a plurality of semiconductor devices for generating red light, one of a plurality of semiconductor devices for generating green light, and one of a plurality of semiconductor devices for generating blue light can transfer the semiconductor devices. Red, green, and blue light are generated to the donor substrate 210. Therefore, the semiconductor devices for generating red light, the semiconductor devices for generating green light, and the semiconductor devices for generating blue light can be repeatedly transferred to the donor substrate 210. However, the invention is not limited thereto, and any of the semiconductor devices for generating red, green, and blue light, respectively, may be disposed on a single wafer. In detail, the semiconductor devices disposed on the donor substrate 210 can provide red (R) light, green (G) light, and blue (B) light. In Figures 22a and 22b, the semiconductor devices 10 can be presented in the form of a single wafer. The red semiconductor device, the green semiconductor device, and the blue semiconductor device may constitute a single semiconductor device 10. Additionally, the semiconductor device 10 can be formed as a single wafer and can be designed to provide any of red, green, and blue.

The following description will be based on a wafer containing a plurality of semiconductor devices for generating red light. For example, the plurality of semiconductor devices 10 disposed on a wafer 1 can be transferred to the donor substrate 210 when the semiconductor devices are separated from each other by a predetermined distance in one direction. For example, as described above, of the 5.4 million semiconductor devices disposed on the wafer 1, 14,400 semiconductor devices can be transferred to the donor substrate 210. Therefore, the semiconductor devices disposed on the donor substrate 210 can be separated from each other. In addition, a spacer between the semiconductor devices disposed on the wafer 1 may be different from a spacer between the semiconductor devices disposed on the donor substrate 210. For example, the spacing between the semiconductor devices disposed on the wafer 1 may be less than the spacing between the semiconductor devices disposed on the donor substrate 210. According to this configuration, as will be described later, the semiconductor devices disposed in the same region of the wafer 1 are transferred to the panel substrate through the donor substrate 210, thereby separating the semiconductor devices from each other. In this example, the semiconductor devices that are transferred to the panel substrate can have a plurality of regions that provide wavelength-varying features of one of the semiconductor devices disposed in the same region of the wafer.

Referring to Figures 23a through 23c, a plurality of semiconductor devices disposed on a wafer and a substrate can be transferred to a donor substrate (first transfer).

First, referring to Fig. 23a, a substrate 110 can be used in the same manner as the substrate 110 described with reference to Figs. 21a to 21f. Further, as described above, a plurality of semiconductor devices 10-1 to 10-4 may be disposed on the substrate 110. For example, the semiconductor devices 10-1 to 10-4 may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. . However, the invention is not limited thereto, and the semiconductor devices may be of different numbers.

Referring to FIG. 23b, at least one selected from the semiconductor devices 10-1, 10-2, 10-3, and 10-4 can be transferred to the substrate 110 by the transport device 210. For example, as described above, the semiconductor devices separated from each other by a predetermined distance may be selected and transferred to the donor substrate 210. The donor substrate 210 can have a first adhesive layer 211 and a transport frame 212 disposed on a lower portion thereof. For example, the carriage 212 has a concave-convex structure so that it can easily adhere the semiconductor device to the first adhesive layer 211. However, the invention is not limited thereto. Referring to Figures 22a and 22b, among the semiconductors disposed on the wafer, semiconductor devices separated from each other by a certain spacer W5 can be transferred to the donor substrate 210. Furthermore, the spacers of the semiconductor devices transferred to the donor substrate can be as described above, equal to the first width P1 or the second width.

Referring to FIG. 23c, when the donor substrate 210 is moved upward after the laser light is transmitted, the first semiconductor device 10-1 and the third semiconductor device 10-3 can be detached from the donor substrate 210. In addition, the second adhesive layer 310 can be coupled to the first semiconductor device 10-1 and the third semiconductor device 10-3.

In detail, the laser light transmitted through the substrate 110 is transmitted to the bottoms of the selected semiconductor devices 10-1 and 10-3, so that the selected semiconductor devices 10-1 and 10-3 are detached from the substrate 110. In this example, the donor substrate 210 is moved upward, and the selected semiconductor devices 10-1 and 10-3 can move along with the donor substrate 210.

For example, the laser light is transmitted to the bottom region of the substrate 110 in which the first and third semiconductor devices 10-1 and 10-3 are disposed, so that the first and third semiconductor devices 10-1 and 10-3 can be The substrate 110 is detached. However, the present invention is not limited thereto, and each time a semiconductor device is detached from the substrate 110, the donor substrate 210 and the adhesive layer 211 may adhere to a semiconductor device.

For example, laser stripping using a photon beam having a particular wavelength range can be applied to one of the methods of detaching the semiconductor device from the substrate 110. For example, the laser light used may have a center wavelength of 266 nm, 532 nm, or 1064 nm, but is not limited thereto.

Further, the plurality of semiconductor devices detached from the substrate 110 may be spaced apart from each other by a predetermined distance. As described above, the first semiconductor device 10-1 and the third semiconductor device 10-3 can be detached from the substrate 110, and the second semiconductor device 10-2 and the fourth semiconductor device 10-4 (which are the same) The substrate 110 can be detached in the same manner in the distance between the first and the third semiconductor devices 10-1, 10-3. Therefore, the semiconductor devices having the same interval can be transferred to a display panel.

Figure 24 is a conceptual diagram in which a semiconductor device on a donor substrate is transferred to a panel substrate of a display device, and Figures 25a and 25b illustrate the transfer of the semiconductor device to a panel substrate of a display device. A process flow chart.

Referring to FIG. 24, a plurality of semiconductor devices 10 that are first transferred from a wafer 1 may be disposed on a donor substrate 210. In addition, a plurality of donor substrates 210 can be transferred from the wafer 1. In addition, the semiconductor devices 10 disposed on the donor substrate 210 can be transferred to a panel substrate 300. In this example, the panel substrate 300 can include a plurality of regions. Here, each region formed on the panel substrate 300 is a region in which the semiconductor device is secondly transferred from a donor substrate.

The panel substrate 300 is a panel of the display device and may be rectangular, but may have various shapes. The following description will be based on a rectangle. Further, the panel substrate 300 may include 12 zones S1 to S12. For example, the panel substrate 300 may include first to twelfth regions S1 to S12. Further, the first to twelfth regions S1 to S12 may be divided by the first to fifth straight lines L1 to L5. The first to third straight lines L1 to L3 may divide the first surface E1 of one of the panel substrates 300 into four identical portions. The fourth to fifth straight lines L4 to L5 may divide the second surface E2 of the panel substrate 300 into three identical portions. Here, each of the first and second surfaces E1 and E2 may be a boundary of the panel substrate 300. The first and second surfaces E1 and E2 may be adjacent to each other.

Further, the first to twelfth regions S1 to S12 may have the same size as the donor substrate 210. Further, each of the first to twelfth regions S1 to S12 may include a pair of bit marks. The donor substrate 210 may be disposed in the first to twelfth regions S1 to S12 in accordance with the alignment marks included in the first to twelfth regions S1 to S12. Therefore, the semiconductor device 10 disposed on the donor substrate 210 can be fabricated from the same region of the wafer 1. Moreover, during the manufacturing process, the same alignment mark can be formed for each of the donor substrate 210 and the panel substrate, and in the process, the second transfer can be performed in accordance with the alignment mark.

The plurality of semiconductor devices 10 disposed on the panel substrate 300 may have a predetermined gauge dw2. Since the semiconductor devices 10 of the donor substrate 210 are transferred to the panel substrate 300 according to the alignment mark, the plurality of semiconductor devices 10 disposed on the panel substrate 300 may have a spacer dw1. The predetermined distance dw2 between the plurality of semiconductor devices 10 disposed on the panel substrate 300 is the same as dw1. The gauge dw2 between adjacent semiconductor devices 10 on the panel substrate 300 and the gauge dw1 between adjacent semiconductor devices 10 disposed on the donor substrate 210 may be greater than a plurality of spacers disposed on the wafer 1. A gauge between the semiconductor devices 10. According to this configuration, when a plurality of semiconductor devices 10 disposed in a certain area of the wafer 1 have a certain interval therebetween, the semiconductor devices 10 can be transferred to the donor substrate 210.

Referring to Figure 25a, the semiconductor devices selected in Figure 23b can be disposed on the panel substrate. For example, the first and third semiconductor devices 10-1, 10-3 may be disposed on the panel substrate 300. In detail, the second adhesive layer 310 can be disposed on the panel substrate 300 and the first and third semiconductor devices 10-1, 10-3 can be disposed on the second adhesive layer 310. In this example, the first and third semiconductor devices 10-1, 10-3 can be adhered to the second adhesive layer 310. According to this configuration, by placing the first and third semiconductor devices having a space on the panel substrate 300, the efficiency of the transfer process is expected to be improved.

Additionally, laser light can be emitted to separate the selected semiconductor device from the first adhesive layer 211. For example, laser light can be emitted upwardly to the transport device 210 such that the first adhesive layer 211 and the selected semiconductor device can be physically separated from one another.

Referring to Fig. 25b, when the transporting device 210 is moved upward after emitting laser light, the first and third semiconductor devices 10-1, 10-3 can be detached from the transporting device 210. In addition, the second adhesive layer 310 can be coupled to the first and third semiconductor devices 10-1, 10-3. Therefore, the semiconductor devices on the donor substrate can transfer the panel substrate (second transfer).

Figure 26 is a modified version of Figure 20a. Referring to FIG. 26, in accordance with a modified version of the present invention, a semiconductor device can include: a sacrificial layer 120; a coupling layer 130 disposed on the sacrificial layer 120; and an interposer 170 disposed on the coupling layer 130. A reflective layer 190 disposed on the interposer 170; a semiconductor structure 140 disposed on the reflective layer 190; a first electrode 151; and a second electrode 152.

According to the modified version of the present invention, the semiconductor structure 140 can include a first conductive semiconductor layer 141, a second conductive semiconductor layer 143, and a first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. One of the active layers 142. In addition, the second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a disposed adjacent to the active layer 142 and a second heavy main conductive semiconductor layer 143b disposed adjacent to the interposer 170. In addition, the semiconductor device can include a first electrode 151 connected to the first conductive semiconductor layer 141, a second electrode 152 connected to the second heavy-main conductive semiconductor layer 143b, and an insulating layer 160. The cover layer 130 and the semiconductor structure 140 are covered.

The description made with reference to FIG. 20a is applicable to the sacrificial layer 120, the coupling layer 130, the interposer 170, and the reflective layer 190.

Further, the second main conductive semiconductor layer 143b may be disposed on the interposer 170. The second heavy main conductive semiconductor layer 143b may have a thickness of one of 3.15 μm to 3.85 μm. However, the invention is not limited thereto.

The second heavy main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143b is electrically connected to the second electrode 152.

The second electrode 152 may be formed on one side of the top of the second heavy main conductive semiconductor layer 143b. The second electrode 152 can be placed under the first electrode 151.

The second main conductive semiconductor layer 143a may be disposed over the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143a may be disposed between the second main conductive semiconductor layer 143b and the active layer 142.

The second main conductive semiconductor layer 143a may have a thickness of one of 0.57 μm to 0.69 μm. However, the invention is not limited thereto. The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer. The second main conductive semiconductor layer 143a may include TSBR and P-AllnP.

The active layer 142 may be disposed on the second main conductive semiconductor layer 143a. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second main conductive semiconductor layer 143a are layered in this layer. Combine. Due to electron-hole recombination, the active layer 142 can be switched to a lower order energy and produce red light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

The active layer 142 may have a thickness of one of 0.54 μm to 0.66 μm. However, the invention is not limited thereto.

A first cladding layer 144 can be disposed on the active layer 142. The first cladding layer 144 may be disposed between the active layer 142 and the first conductive semiconductor layer 141.

The first cladding layer 144 may comprise aluminum indium gallium phosphide (AlInP). The first cladding layer 144 has a thickness of one of 0.45 μm to 0.55 μm. However, the invention is not limited thereto.

A III-V compound semiconductor or a II-VI compound semiconductor is formed and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first conductive semiconductor layer 141 may have a thickness of one of 0.45 μm to 5.5 μm. However, the invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141. The first electrode 151 can be placed over the second electrode 152.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the interposer 170, the reflective layer 190, and the semiconductor structure 140. The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, the interposer 170, the reflective layer 190, and side surfaces of the semiconductor structure 140.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed.

The insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

Figure 27 is a cross-sectional view showing a semiconductor device in accordance with a sixth embodiment.

Referring to FIG. 27, the semiconductor device according to the sixth embodiment includes: an interposer 170 disposed on the coupling layer 130'; a reflective layer 190 disposed on the interposer 170; and a first conductive semiconductor layer 141. And disposed on the reflective layer 190; a first cladding layer 144 disposed on the first conductive semiconductor layer 141; an active layer 142 disposed on the first cladding layer 144; a second conductive layer a semiconductor layer 143 disposed on the active layer 142; a first electrode 151 electrically connected to the first conductive semiconductor layer 141; and a second electrode 152 electrically connected to the second conductive semiconductor layer 143; and an insulating layer 160.

Here, the above description is applicable to the interposer 170, the reflective layer 190, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, and the second conductive semiconductor layer 143, the first The electrode 151, the second electrode 152, and the insulating layer 160.

Referring to Fig. 27, as with the coupling layer 130, the coupling layer 130' may comprise a material such as SiO2, SiNx, TiO2, polyimide, and a resin. However, the present invention is not limited thereto, and the sacrificial layer 120 and the coupling layer 130 may be disposed as shown in FIG. 20a.

Additionally, the coupling layer 130' can be removed by laser stripping as described above.

28a to 28h are flowcharts showing a method of manufacturing the semiconductor device according to the sixth embodiment.

First, a first substrate P may be disposed at the bottom. The first substrate P may comprise gallium arsenide (GaAs), sapphire (Al ₂ O ₃ ), tantalum carbide (SiC), germanium (Si), gallium nitride (GaN), zinc oxide (ZnO), phosphating Any of gallium (GaP), indium phosphide (InP), germanium (Ge), and gallium trioxide (Ga ₂ O ₃ ). A concavo-convex structure may be formed on the first substrate P, but is not limited thereto. The first substrate P is wet-cleaned to remove impurities on the surface thereof.

The coupling layer 130' may be disposed on the first substrate P. The coupling layer 130' can be removed when the semiconductor device is transferred to a display device. For example, when the semiconductor device is transferred to a display device, the coupling layer 130' can be detached from the semiconductor device by the laser light emitted during the transfer. In this example, the coupling layer 130' can be detached in the wavelength of the emitted laser light. Further, the wavelength of the laser light may be 532 nm or 1064 nm, but is not limited thereto. In addition, the coupling layer 130' may remain partially under the interposer 170 during the transfer.

The coupling layer 130' may comprise any one of C, O, N and H, and may also comprise a resin, but is not limited thereto.

The coupling layer 130' may have a thickness of one of 6 μm to 8 μm. However, the invention is not limited thereto. Here, the thickness may be one length in one direction in which each layer is stacked on the semiconductor device.

The interposer 170 can be formed on the coupling layer 130'. Further, the reflective layer 190 may thus be formed on the interposer 170.

In addition, the first conductive semiconductor layer 141 may be disposed on the reflective layer 190, and the first cladding layer 144, the active layer 142 and the second conductive semiconductor layer 143 may be formed thereon.

The first conductive semiconductor layer 141 may be disposed on the reflective layer 190. The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first cladding layer 144 may be disposed on the first conductive semiconductor layer 141. The first cladding layer 144 can be disposed between the first conductive semiconductor layer 141 and the active layer 142. The first cladding layer 144 can include a plurality of layers. The first cladding layer 144 may include an AlInGaP-based layer/AlInP-based layer.

The active layer 142 can be disposed on the first cladding layer 144. The active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second heavy conductive semiconductor layer 143b. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second heavy conductive semiconductor layer 143b are layered. Combine. Due to electron-hole recombination, the active layer 142 can be switched to a lower order energy and produce red light. The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The second conductive semiconductor layer 143 may be disposed on the active layer 142. As described above, the second conductive semiconductor layer 143 may include the second main conductive semiconductor layer 143a and the second heavy main conductive semiconductor layer 143b. The second heavy main conductive semiconductor layer 143b may include a GaPlayer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

For example, the second heavy main conductive semiconductor layer 143b may be doped with magnesium (Mg) at a concentration of about 10×10 ¹⁸ , but is not limited thereto.

In addition, the second heavy main conductive semiconductor layer 143b may include a plurality of layers, and only some of the layers may be doped with magnesium, but are not limited thereto.

Next, referring to Fig. 28b, a second substrate 2 may be disposed on top of the semiconductor device. For example, the second substrate 2 may be disposed on the second heavy-main conductive semiconductor layer 143b. An adhesive layer is disposed between the second substrate 2 and the second heavy main conductive semiconductor layer 143b, so that the second substrate 2 can be combined with the second heavy main conductive semiconductor layer 143b. The second substrate 2 can be a conductive substrate and/or an insulating substrate. Further, the second substrate 2 may include a sapphire substrate, but is not limited thereto.

Referring to Figure 28c, the first substrate P can be detached from the semiconductor device. For example, the first substrate P can be removed by a laser stripping procedure.

Referring to Fig. 28d, the coupling layer 130' and the substrate 110 may be disposed over the interposer 170. The coupling layer 130' may be partially disposed over the interposer 170 and may be partially disposed under the substrate 110. Thereafter, the interposer 170 and the substrate 110 may be coupled to each other by a program such as annealing. However, the invention is not limited thereto.

Additionally, the substrate 110 can be a sapphire substrate and can transmit laser light that is emitted when transferred to a display device. For example, when the emitted laser light has a wavelength of 532 nm or 1064 nm, the laser light of 532 nm or 1064 nm can be transmitted by the substrate 110 and then absorbed by the coupling layer 130'. Additionally, the coupling layer 130' can be separated by the emitted laser light.

Referring to Figure 28e, the second substrate 2 can be removed by laser lift-off.

Referring to Fig. 28f, the first etching may be performed starting from the top of the semiconductor device to a portion of the first conductive semiconductor layer 141.

The first etching may be a wet etching method or a dry etching method, but is not limited thereto. In addition, an upper surface of the first conductive semiconductor layer 141 may be partially exposed by the first etching.

Referring to Figure 28g, the second electrode 152 can be disposed on top of the semiconductor device. The second electrode 152 is electrically connected to the second heavy main conductive semiconductor layer 143b. The first electrode 151 may be disposed on the first conductive semiconductor layer 141.

The first electrode 151 and the second electrode 152 can be formed by any typical electrode formation method, such as sputtering, coating, and deposition. However, the invention is not limited thereto.

The first electrode 151 and the second electrode 152 may be respectively disposed at positions separated from the substrate 110 by different distances. For example, the second electrode 152 may be disposed on the second conductive semiconductor layer 143. In this example, the second electrode 152 may be disposed on the first electrode 151. However, the invention is not limited thereto.

For example, as shown in FIG. 29, when the first conductive semiconductor layer 141 is disposed over the second conductive semiconductor layer 143, the first electrode may be disposed over the second electrode 152.

Referring to Figure 28h, a second etch can be performed to the upper surface of one of the substrates 110. The second etching may be a wet etching method or a dry etching method, but is not limited thereto.

The second etch can be etched by a greater thickness than the first etch, but is not limited thereto. For example, the second etch can reach the coupling layer 130. The semiconductor device disposed on the substrate 110 can be isolated in the form of a plurality of wafers by the second etching.

In addition, a protective layer 160 may be disposed on the following layers: the coupling layer 130', the interposer 170, the reflective layer 190, the first conductive semiconductor layer 141, the first cladding layer 144, and the active layer 142. And the second conductive semiconductor layer 143.

The protective layer 160 may cover the following layered side surfaces: the coupling layer 130', the interposer 170, the reflective layer 190, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, and The second conductive semiconductor layer 142. The protective layer 160 may cover a portion up to an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed. In addition, the protective layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

One of the protective layers 160 may be partially disposed on top of the substrate 110. One of the protective layers 160 may be partially disposed between adjacent semiconductor wafers. As described above, the protective layer 160 can be an insulating layer. The protective layer 160 may be made of at least one selected from the group consisting of SiO ₂ , Si _x O _y , Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO _{2 .} And AlN, but not limited by it.

Figure 29 is a modified version of Figure 27.

Referring to Fig. 29, according to the modified version, a semiconductor device can have a form in which the positions of the first and second conductive semiconductor layers of Fig. 28 are mutually replaced. In addition, the first electrode 151 may be disposed on the second electrode 152.

According to the modified version, the semiconductor device can include a coupling layer 130', an interposer 170 disposed on the coupling layer 130', a reflective layer 190 disposed on the interposer 170, and a semiconductor structure. 140, disposed on the reflective layer 190, a first electrode 151 and a second electrode 152.

The semiconductor structure 140 can include a first conductive semiconductor layer 141, a second conductive semiconductor layer 143, and an active layer 142 disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. In addition, the second conductive semiconductor layer 143 may include a second main conductive semiconductor layer 143a disposed adjacent to the active layer 142 and a second heavy main conductive semiconductor layer 143b disposed adjacent to the interposer 170. In addition, the semiconductor device can include a first electrode 151 connected to the first conductive semiconductor layer 141, a second electrode 152 connected to the second heavy-main conductive semiconductor layer 143b, and an insulating layer 160. The cover layer 130 and the semiconductor structure 140 are covered.

The description made with reference to Fig. 27 is applicable to the coupling layer 130', the interposer 170 and the reflective layer 190.

Further, the second main conductive semiconductor layer 143b may be disposed on the interposer 170. The second main conductive semiconductor layer 143b may be disposed over the second main conductive semiconductor layer 143a. The second heavy main conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second heavy main conductive semiconductor layer 143b may include a GaP layer/In _x Ga _1-x P layer (0) x 1) One of the superlattice structures.

The second electrode 152 may be disposed on the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143b is electrically connected to the second electrode 152.

The second electrode 152 may be formed on one side of the top of the second heavy main conductive semiconductor layer 143b. The second electrode 152 can be placed under the first electrode 151.

The second main conductive semiconductor layer 143a may be disposed over the second heavy main conductive semiconductor layer 143b. The second main conductive semiconductor layer 143a may be disposed between the second main conductive semiconductor layer 143b and the active layer 142.

The second main conductive semiconductor layer 143a may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1). When the second conductive semiconductor layer 143 is a p-type semiconductor layer, the second conductive semiconductor layer 143 may include magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or the like. As a p-type dopant.

The second main conductive semiconductor layer 143a doped with a second dopant may be a p-type semiconductor layer. The second main conductive semiconductor layer 143a may include TSBR and P-AllnP.

The active layer 142 may be disposed on the second main conductive semiconductor layer 143a. The active layer 142 is a layer in which electrons (or holes) injected by the first conductive semiconductor layer 141 and electrons (or holes) injected by the second main conductive semiconductor layer 143a are layered in this layer. Combine. Due to electron-hole recombination, the active layer 142 can be switched to a lower order energy and produce red light.

The active layer 142 can have any of the following structures, but is not limited thereto: a single well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure.

The active layer 142 may form, but is not limited to, one of the following ones: GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGa, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs.

A first cladding layer 144 can be disposed on the active layer 142. The first cladding layer 144 may be disposed between the active layer 142 and the first conductive semiconductor layer 141. The first cladding layer 144 may comprise aluminum indium gallium phosphide (AlInP).

The first conductive semiconductor layer 141 may be disposed on the first cladding layer 144. The first conductive semiconductor layer 141 may be made of a III-V compound semiconductor or a II-VI compound semiconductor and may be doped with a first dopant. The first conductive semiconductor layer 141 may include a semiconductor material having an experimental formula: In _x Al _y Ga _1-xy P (0) x 1,0 y 1,and 0 x+y 1) or In _x Al _y Ga _1-xy N (0 x 1,0 y 1,and 0 x+y 1).

In addition, the first dopant may be an n-type dopant such as Si (germanium), Ge (germanium), tin (Sn), selenium (Se), and tellurium (Te). When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped by the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include any one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydride vapor phase epitaxy (HVPE) or the like, but is not Limited to this.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 is electrically connected to the first conductive semiconductor layer 141. The first electrode 151 can be placed over the second electrode 152.

The insulating layer 160 may cover the coupling layer 130', the interposer 170, the reflective layer 190, and the semiconductor structure 140. The insulating layer 160 may cover the following layered side surfaces: the coupling layer 130', the interposer 170, the reflective layer 190, and the semiconductor structure 140.

The insulating layer 160 may partially cover an upper surface of the first electrode 151. The upper surface of the first electrode 151 may be partially exposed. The insulating layer 160 may partially cover an upper surface of the second electrode 152. The upper surface of the second electrode 152 may be partially exposed.

Figure 30 is a conceptual diagram of a semiconductor device being transferred to a display device in accordance with an embodiment.

Referring to FIG. 30, according to an embodiment, a display device including a semiconductor device can include a second panel substrate 410, a driven thin film transistor T2, a flat layer 430, a common electrode CE, and a pixel electrode AE. And a semiconductor device 10.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE and a drain electrode DE.

The driving thin film transistor T2 is a driving component, and the driving thin film transistor T2 can be electrically connected to the semiconductor device 10 to drive the semiconductor device 10.

The gate electrode GE can be formed by the same gate line. The gate electrode GE can be covered by a gate insulating layer 440.

The gate insulating layer 440 may be formed of an inorganic material comprises a single-layered or plural layered composition, the inorganic material comprises a silicon dioxide (the SiOx), silicon nitride (SiN _x) or the like.

The semiconductor layer SCL may be disposed on the gate insulating layer 440 in a predetermined pattern (or island) to overlap the gate electrode GE. The semiconductor layer SCL may be made of a semiconductor formed of any of amorphous silicon, polycrystalline silicon, oxide, and organic materials.

The ohmic contact layer OCL may be disposed on the semiconductor layer SCL in a predetermined pattern (or island) shape. The ohmic contact layer OCL can be used for ohmic contact between the semiconductor layer SCL and the source electrode SE and the drain electrode DE.

The source electrode SE may be formed on one side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL to overlap the other side of the semiconductor layer SCL and be spaced apart from the source electrode SE. The drain electrode DE can be formed together with the source electrode SE.

A flat layer film can be disposed to cover the second panel substrate 410. The driven thin film transistor T2 can be disposed within the flat layer film. For example, the flat layer film may comprise, but is not limited to, an organic material such as benzocyclobutene or photo acryl.

A recess 450 is a predetermined light emitting region, and the semiconductor device can be disposed on the recess 450. Here, the light-emitting area may be defined as a remaining area other than a line area in the display device.

The groove 450 may be recessed into the flat layer 430, but is not limited thereto.

The semiconductor device 10 can be disposed on the recess 450. A first electrode and a second electrode of the semiconductor device are connectable to a line (not shown) of the display device.

The semiconductor device 10 can adhere to the recess 450 through an adhesive layer 420. Here, the adhesive layer 420 may be the aforementioned second adhesive layer, but is not limited thereto.

The second electrode 152 of the semiconductor device 10 can be electrically connected to the source electrode SE of the driven thin film transistor T2 through the pixel electrode AE. In addition, the first electrode 151 of the semiconductor device 10 can be connected to a common power line through the common electrode CE.

The first electrode 151 and the second electrode 152 may have a height difference. The first electrode 151 is disposed under the second electrode 152. The first electrode 151 may be disposed on the same level as the upper surface of the flat layer 430. . However, the invention is not limited thereto.

The pixel electrode AE can electrically connect the second electrode of the semiconductor device to the source electrode SE of the driving thin film transistor T2.

The common electrode CE can electrically connect the first electrode of the semiconductor device and the common power line CL.

Each of the pixel electrodes AE and each of the common electrodes CE may include a transparent conductive material. The transparent conductive material may include, but is not limited to, one of indium oxide (ITO) or indium zinc oxide (IZO).

The display device according to an embodiment of the present invention can achieve standard image quality (SD) resolution (760×480), high image quality (HD) resolution (1180×720), and ultra high (FHD) image quality analysis. Degree (1920×1080), very high image quality (UHD) resolution (3480×2160) or ultra high quality (UHD or higher) resolution (eg 4K (K=1000), 8K, etc.). In this example, the semiconductor wafers according to an embodiment may be arranged and connected to each other according to the resolution.

In addition, the display device may be a television or a display panel having a pair of angular dimensions of 100 吋 or more, and the pixels may be implemented as a plurality of light emitting diodes (LEDs). Therefore, the display device can have low power consumption, low maintenance cost, and long service life, and can be provided as a high-brightness self-luminous display.

According to an embodiment, the display device has good color purity and color reproduction due to the use of the semiconductor device to achieve video and video.

According to an embodiment, since one of the semiconductor device packages having good straightness is used for video recording and video recording, it is expected to realize a display device capable of providing a clear picture of 100 Å or more.

. According to an embodiment, it is expected to realize a display device having a high image quality and a low cost of 100 inches or more.

The semiconductor device according to an embodiment may additionally include an optical member such as a light guide plate, a prism sheet, a diffusion sheet, and thus may function as a backlight unit. Furthermore, the semiconductor device according to an embodiment can even be applied to a display device, a lighting device and a pointing device.

In this example, the display device can include a bottom cover, a reflector, a light module, a light guide, an optical sheet, a display panel, an image signal output circuit and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate and the optical sheet can form a backlight unit.

The reflector is placed on the bottom cover, and the light emitting module emits light. The light guide plate is placed in front of the reflector to guide light emitted by the illumination module. The optical sheet includes a cymbal sheet or the like and is placed in front of the light guide plate. The display panel is placed in front of the optical sheet. The image signal output circuit provides an image signal of the display panel. The color filter is placed in front of the display panel.

The illuminating device can include a light source module, and the light source module includes a substrate and a semiconductor device, a heat dissipating unit for dispersing hot air of the light source module, and a power supply unit for Processing or converting an electrical signal from the external and providing the electrical signal to the light source module. In addition, the lighting device may comprise a light fixture, a light or a street light.

In addition, the camera flash of a mobile terminal can include a light source module including a semiconductor device in accordance with an embodiment.

The display device according to an embodiment of the present invention can achieve standard image quality (SD) resolution (760×480), high image quality (HD) resolution (1180×720), and ultra high (FHD) image quality analysis. Degree (1920×1080), very high image quality (UHD) resolution (3480×2160) or ultra high quality (UHD or higher) resolution (eg 4K (K=1000), 8K, etc.). In this example, the semiconductor wafers according to an embodiment may be arranged and connected to each other according to the resolution.

In addition, the display device may be a television or a display panel having a pair of angular dimensions of 100 吋 or more, and the pixels may be implemented as a plurality of light emitting diodes (LEDs). Therefore, the display device can have low power consumption, low maintenance cost, and long service life, and can be provided as a high-brightness self-luminous display.

According to an embodiment, the display device has good color purity and color reproduction due to the use of the semiconductor wafer for video and video.

According to an embodiment, the display device can be implemented as a display device capable of providing one of the sharp pictures of 100 Å or more by using a semiconductor device package having a good straightness to express the video and the image.

According to an embodiment, it is expected to realize a display device having a high image quality and low cost of 100 Å or more.

The semiconductor device according to an embodiment may additionally include an optical member such as a light guide plate, a prism sheet, a diffusion sheet, and thus may function as a backlight unit. Furthermore, the semiconductor device according to an embodiment can even be applied to a display device, a lighting device and a pointing device.

In this example, the display device can include a bottom cover, a reflector, a light module, a light guide, an optical sheet, a display panel, an image signal output circuit and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate and the optical sheet can form a backlight unit.

The reflector is placed on the bottom cover, and the light emitting module emits light. The light guide plate is placed in front of the reflector to guide light emitted by the illumination module. The optical sheet includes a cymbal sheet or the like and is placed in front of the light guide plate. The display panel is placed in front of the optical sheet. The image signal output circuit provides an image signal of the display panel. The color filter is placed in front of the display panel.

The illuminating device can include a light source module, and the light source module includes a substrate and a semiconductor device, a heat dissipating unit for dispersing hot air of the light source module, and a power supply unit for Processing or converting an electrical signal from the external and providing the electrical signal to the light source module. In addition, the lighting device may comprise a light fixture, a light or a street light.

In addition, the camera flash of a mobile terminal can include a light source module including a semiconductor wafer in accordance with an embodiment.

According to an embodiment, it is desirable to implement a red semiconductor device comprising one of a plurality of vertical or horizontal semiconductor wafers.

Further, it is expected to manufacture a semiconductor device having a good light extraction efficiency.

Further, it is expected that a semiconductor device including one of gallium arsenide (GaAs) can be manufactured by using laser lift-off.

In addition, it is expected to manufacture a semiconductor device having a good ohmic contact.

The various advantages and effects of the present invention are not limited by the above description, and will be more readily understood from the detailed description of the embodiments of the invention.

The present invention is not limited to the foregoing embodiments and the accompanying drawings, and various alternatives, modifications and changes can be made without departing from the spirit of the embodiments of the present invention.

Claims (10)

 A semiconductor device comprising: a substrate; a coupling layer disposed on the substrate; at least one semiconductor structure disposed on the coupling layer and including a first conductive semiconductor layer, a second conductive semiconductor layer, and a set An active layer between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode connected to the first conductive semiconductor layer; and a second electrode connected to the second conductive semiconductor layer And an insulating layer covering the coupling layer and the semiconductor structure.    The semiconductor device of claim 1, wherein the insulating layer covers a portion of the first electrode and a portion of the second electrode.    The semiconductor device of claim 1, wherein the insulating layer covers a side surface of the coupling layer.    The semiconductor device of claim 1, wherein the second conductive semiconductor layer comprises: a second main conductive semiconductor layer disposed on the active layer; and a second heavy main conductive semiconductor layer disposed on the second main On the conductive semiconductor layer.    The semiconductor device of claim 1, further comprising: a first cladding layer disposed between the active layer and the first conductive semiconductor layer.    The semiconductor device of claim 1, further comprising: a sacrificial layer disposed on at least one of a portion of the coupling layer and a lower portion of the coupling layer, wherein the sacrificial layer and the coupling layer have a 1: A thickness ratio of 1.5 to 1:50.    The semiconductor device of claim 1, wherein the semiconductor structure comprises a plurality of semiconductor structures.    The semiconductor device of claim 1, further comprising: an interposer disposed on the coupling layer; and a reflective layer disposed on the interposer, wherein the first conductive semiconductor layer is disposed on the reflective layer on.    The semiconductor device of claim 8, wherein the reflective layer comprises AlGaAs.    A display device comprising a semiconductor device, the display device comprising: a semiconductor wafer comprising: a coupling layer, a semiconductor structure disposed on the coupling layer and comprising a first conductive semiconductor layer, a second conductive a semiconductor layer and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode connected to the first conductive semiconductor layer, a second electrode, and the second conductive The semiconductor layers are connected, and an insulating layer covers the coupling layer and the semiconductor structure; a panel substrate disposed under the semiconductor wafer; and a driving device electrically connected to the semiconductor wafer.