TW201826675A - Dc-dc converters - Google Patents

Abstract

A voltage reducing circuit 102 comprises a power switch circuit portion 105 comprising a high-side 128 and low-side 130 field-effect-transistors connected at a switch node 138. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion 106 comprising an inductor 132 connected to the switch node is arranged to provide an output voltage 136. A drive circuit portion 104 receives a pulse width modulated control signal and outputs pulse width modulated (PWM) drive signals. A slew rate control circuit portion 150 comprises one or more slew rate control field-effect-transistors 1600-160n-1 arranged in parallel. A controller connected 170 is arranged to control which of the one or more slew rate control field-effect-transistors is enabled. A power field-effect transistor 162 is connected between the one or more slew rate control field-effect-transistors and the switch node.

Description

 DC-DC converter (1)  

The present invention relates to a DC-DC converter, in particular, but not exclusively, to a DC-DC voltage reducer such as a synchronous DC-DC buck converter. ).

Modern portable electronic devices typically have a power source, such as a battery pack, that acts as a direct current (DC) power supply for various electronic components within the device. Typically, however, such components will have different voltage requirements, and thus such devices conventionally use one or more DC-DC converters that will have a nominal voltage associated with the power supply. Step down to voltages suitable for different electronic components. Although this can be achieved by using a sequencer network (eg, a series of resistors) to generate several "tap" with different voltages, this is very inefficient because energy is dissipated as heat across the resistor. It was wasted.

An alternative arrangement known in the art itself is a buck converter. The buck converter circuit utilizes an inductor-capacitor (or "LC") circuit that is periodically connected to and disconnected from the power supply by the driver (eg, by The switch is intermittently opened and closed, which is typically implemented as a transistor called a "high side" transistor to step down the voltage. This can be viewed as an electronic device equivalent to a mechanical flywheel where energy is periodically input to the system to keep it output at a steady rate. The ratio of the output voltage to the input voltage can be adjusted by changing the duty cycle of the pulse width modulation (PWM) drive signal generated by the driver, the pulse width modulation drive signal being applied to the gate of the high side field effect transistor so that Make it open and closed.

The synchronous buck converter circuit replaces the so-called "idle" or "return" diodes with a second transistor, often referred to as a "low voltage side" transistor. The driver then acts on the high side of the high voltage side by applying an appropriate PWM drive signal to the high side field effect transistor and the low side field effect transistor to open and close it to intermittently couple the LC circuit to the input voltage. The low-voltage side field effect transistor is closed when the transistor is turned on, and the high-voltage side field effect transistor is closed when the low-voltage side field effect transistor is turned off. This improves the efficiency of the buck converter at the expense of increased material cost associated with the circuit.

However, such a driver must prevent both switches from being turned on at the same time, otherwise a problem called "breakdown" will occur, in which a current surge flows because both are electrically conductive high-voltage side field effect transistors. And the low side FET acts as a short circuit across the power supply. One way to avoid breakdown is to use a time delay between disconnecting the high side field effect transistor and closing the low side field effect transistor, and between disconnecting the low side field effect transistor and closing the high side field effect transistor. Take advantage of time delays. However, in order to ensure that the two transistors are not electrically conductive at the same time, this time delay will result in additional power loss and thus loss of efficiency.

The improved method known in the art itself is referred to as a "non-overlapping" operation in which the switching nodes are monitored (ie, the inductance of the high side side field effect transistor, the low side side field effect transistor and the LC circuit). The voltage at the point where the devices are connected to each other. The time delay between turning on a transistor after switching off another transistor is if the voltage at the switching node exceeds or falls below a certain threshold (where appropriate) depending on the transistor being disconnected. It is still measured at the time of p-type). Such synchronous drivers can be adapted to different types of transistors or switches without loss of efficiency, and such flexibility will be caused by a fixed non-overlap time.

Applicants have appreciated, however, that improvements can be made to further enhance the efficiency of synchronous buck converters and similar arrangements. While non-overlapping topologies ensure protection against breakdown, such converters require the driver to open and close the high side and low side field effect transistors relatively quickly in order to limit the "stagnation time" between the voltage states at the switching nodes ( Dead time)" quantity. However, the use of a sufficiently fast driver requires a relatively large peak current that introduces noise that is not readily available to the output voltage, thereby reducing the efficiency of the converter.

In addition, in the case of a positive current flowing through the buck converter, the internal diode (sometimes referred to as the bulk diode) in the low-voltage side field effect transistor is usually as high as Both low and low to high transitions are conductive, introducing further noise and degrading the efficiency of the converter. Such conventional buck converters also suffer from relatively large "undershoot" where the voltage at the switching node temporarily exceeds the intrinsic diode threshold voltage of one of the transistors (typically about 0.7V) So that the in-line diodes within the transistor are electrically conductive, which causes the body diode and substrate current to flow therethrough - a known source of noise in the converter and another source of inefficiency.

Viewed from a first aspect, the present invention provides a pressure reduction circuit including: a power switching circuit portion including a high voltage side field effect transistor arranged in series and a low voltage side field effect transistor such that the high voltage side field An effect transistor is connected to a 汲 terminal of each of the low-voltage side field effect transistors at a switching node, the power switching circuit portion having an on state and an off state, in the on state Said high voltage side field effect transistor is activated, and said low side field effect transistor is deactivated, and in said off state, said high side field effect transistor is deactivated and said low voltage side field An effect transistor is enabled; an input voltage is coupled across the high side field effect transistor to the low side field effect transistor; an energy storage circuit portion including an inductor, the energy storage circuit portion being coupled to the switching a node and arranged to provide an output voltage; a driver circuit portion arranged to receive the pulse width modulation control signal and output the first pulse width modulation drive signal and the second pulse width modulation drive signal; a rate control circuit portion comprising: one or more slew rate controlled field effect transistors arranged in parallel to form an array; a controller coupled to the one or more slew rate control field effect transistor gate terminals; and power a field effect transistor coupled between the one or more slew rate control field effect transistors and the switching node, wherein the controller is arranged to control enabling the one or more slew rate control field effect One of the crystals.

Thus, those skilled in the art will appreciate that the present invention can provide an improved decompression circuit in which the rate of conversion of the voltage at the switching node can be varied by varying the number of field effect transistors (FETs) that are controlled by the enabled slew rate. . In other words, the number of FETs can be controlled by changing the enabled slew rate to change the "pull up strength" of the circuit (ie, its ability to pull up the voltage at the switching node) to control the switching node. Voltage rise and fall time. This provides an improvement in both the noise and efficiency of the reduced voltage circuit of the preferred embodiment of the present invention when compared to conventional circuits.

Moreover, the reduced voltage circuit of the present invention can advantageously have reduced peak current consumption associated with the power switching circuit portion as compared to conventional circuits. This may cause the power switching circuit portion to operate in a zero voltage switching (ZVS) mode that allows operation at higher frequencies and higher input voltages than standard PWM operations as described above. Sacrifice efficiency.

In some embodiments, the controller includes a digital controller. In some such embodiments, the digital controller is arranged to output a digital control signal that enables selection of the one or more slew rate controlled field effect transistors. This allows the controller to "address" the array as a whole, for example by outputting a digit with a bit length equal to the number of slew rate control FETs. In such an embodiment, applying a digital "0" or "1" (ie, a logic low and a logic high, respectively) to the gate terminal of each slew rate control FET will enable or disable the FET, such that The total number of enabled FETs (and a particular series) can be controlled relatively easily. Of course, it will be appreciated that the series can control zero, some or all of the field effect transistors for the one or more slew rate.

In some embodiments, the reduced voltage circuit further includes a timer circuit portion, the timer circuit portion being arranged to determine a duration of a voltage transition at the switching node, wherein the controller is responsive to the continuation The number of slew rate control transistors to be enabled is determined by time. In some such embodiments, the controller includes a counter arranged to increment the counter value if the determined duration exceeds a threshold duration, and does not exceed the determined duration The counter value is decremented in the case of the threshold duration. In a preferred embodiment, the controller includes a up counter and a down counter, the up counter and the down counter being arranged to respectively set a duration of a positive voltage transition and a negative voltage transition with a rising threshold duration and The duration of the landing limit is compared. In such embodiments, the decompression circuit may further use a single timer circuit portion to determine the rise duration and the fall duration, or the decompression circuit may include for determining that the rise continues The rising timer circuit portion and the falling timer circuit portion of the time and the falling duration. In embodiments where the controller includes a digital controller arranged to provide a digital control signal, the digital control signal can include the counter value or can have a predetermined relationship with the counter value.

In at least a preferred embodiment, the reduced voltage circuit according to the present invention can also reduce the negative spike at the switching node and the amount of the indirect diode bias, which improves the noise performance of the converter and is improved The efficiency of the converter.

It will be appreciated that the on-state and off-state mentioned above correspond to a gate-source voltage applied to a field effect transistor (FET) that is substantially above or below a characteristic threshold voltage of the FET. Of course, in practice, the nominal threshold voltage will depend on the characteristics of the FET itself, including its semiconductor structure, doping level, oxide thickness, channel length, and so on.

Although in some embodiments, at least two slew rate control field effect transistors are the same, in other embodiments, the array may include field effect transistors having different characteristics, eg, the array may include multiple differences The channel width field effect transistor allows the controller to selectively activate a particular transistor to form a particular combination to achieve a particular pull up strength.

Although one skilled in the art will appreciate that there are several field effect transistor technologies that can be readily employed to implement the embodiments of the invention described herein, in some preferred embodiments, high side field effect transistors A p-channel metal oxide semiconductor field effect transistor is included, and the low side field effect transistor includes an n-channel metal oxide semiconductor field effect transistor.

Moreover, in some potentially overlapping embodiments, the one or more slew rate controlled field effect transistors and the power field effect transistors comprise p-channel metal oxide semiconductor field effect transistors.

Although those skilled in the art will appreciate that there are several different topologies that can be readily implemented to implement the present invention, in at least some preferred embodiments, the slew rate control circuitry is arranged such that: the conversion a 汲 terminal of the rate control transistor is coupled to a source terminal of the power transistor; a 汲 terminal of the power transistor is coupled to the switching node; and a gate terminal of the power transistor is coupled to a low voltage side field effect The gate terminal of the transistor.

It will be appreciated that there are several circuit partial arrangements known in the art per se that are suitable for generating pulse width modulated drive signals. However, in at least some embodiments, the drive circuit portion includes a latch circuit portion. In some further embodiments, the latch circuit portion includes a two input Boolean NAND gate and a two input Boolean NOR gate that are arranged such that: a first input of the inverse gate is coupled to a pulse width modulation input signal; a first input of the inverse or gate is coupled to the pulse width modulation control signal; an output of the inverse gate is coupled to the inverse Or a second input of the gate; and the output of the inverse gate is coupled to the second input of the inverse gate. In some such embodiments, the output of each gate is coupled via a buffer to a second input of another gate. These buffers increase the propagation delay to prevent the latch circuit portion from entering the disabled state of the second input of each gate to be logic low, thereby increasing the stability of the circuit portion. Of course, those skilled in the art will appreciate that the latch circuit portion can instead be implemented using a logically equivalent arrangement.

2‧‧‧"Non-overlap" synchronous DC-DC buck converter

4‧‧‧Drive circuit section

5‧‧‧Power switching circuit section

6‧‧‧ Energy storage circuit section

8‧‧‧Input voltage

10‧‧‧ Grounding

12‧‧‧ Pulse width modulation (PWM) control signal

14‧‧‧Brin anti-gate

16‧‧‧Brin anti-gate

20‧‧‧High-side driver amplifier

22‧‧‧Low-side driver amplifier

24‧‧‧Inverter

26‧‧‧Inverter

28‧‧‧High-voltage side p-channel field effect transistor (FET)

30‧‧‧n channel low-voltage side field effect transistor (FET)

32‧‧‧Inductors

34‧‧‧ Capacitors

36‧‧‧Output voltage

38‧‧‧Switch node

39‧‧‧Voltage

40‧‧‧ Pulse width modulation (PWM) drive signal / voltage

41‧‧‧Logic low value

42‧‧‧Output/Pulse Width Modulation (PWM) Drive Signal/Voltage

46a‧‧‧Total peak-to-peak voltage

46b‧‧‧peak voltage

48a‧‧‧Quantity/negative spike/peak voltage

48b‧‧‧Quantity/negative spike

102‧‧‧Relief circuit

104‧‧‧Drive circuit section

105‧‧‧Power switching circuit section

106‧‧‧ Energy storage circuit section

108‧‧‧Input voltage

110‧‧‧ Grounding

112‧‧‧ Pulse width modulation (PWM) control signal

120‧‧‧First Driver Amplifier

122‧‧‧Secondary driver amplifier

128‧‧‧High-voltage side field effect transistor

130‧‧‧Low-voltage side field effect transistor

132‧‧‧Inductors

136‧‧‧Output voltage

138‧‧‧Switch node

139‧‧‧voltage trace

139'‧‧‧Voltage trace

139"‧‧‧voltage trace

140‧‧‧First Pulse Width Modulation (PWM) Drive Signal / Bias Voltage

142‧‧‧Second Pulse Width Modulation (PWM) Drive Signal/Voltage

150‧‧‧Scaling rate control circuit section

160 ₀ ~ 160 _n-1 ‧‧‧p channel conversion rate control field effect transistor (FET)

162‧‧‧Power Field Effect Transistor (FET)

170‧‧‧Digital Control Word Signal/Controller

200‧‧‧Controller circuit section

202‧‧‧p channel field effect transistor (FET)

204‧‧‧n channel field effect transistor (FET)

206‧‧‧n channel field effect transistor (FET)

208a‧‧‧First Inverter

208b‧‧‧second inverter

210‧‧‧Latch

212‧‧‧Output signal

232‧‧‧Output signal

240‧‧‧Inverter

242‧‧‧Drop time counter

244‧‧‧Rise time counter

246‧‧‧Multiplexer

Some embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which FIG. 1 shows a conventional synchronous DC-DC buck converter for reference only.

2 shows a timing diagram illustrating a typical signal transition of the buck converter shown in FIG. 1.

3 shows a synchronous DC-DC buck converter in accordance with an embodiment of the present invention.

4 shows a timing diagram illustrating a typical signal transition of the buck converter shown in FIG.

Figure 5 shows a circuit arrangement suitable for determining if the fall time of the voltage at the switching node in Figure 3 is too large.

Figure 6 shows a graph illustrating the dependence of slew rate on load current during a negative transition.

Figure 7 shows a circuit arrangement suitable for controlling the number of enabled slew rate control FETs.

Figure 1 shows a conventional "non-overlapping" synchronous DC-DC buck converter 2. For ease of reference, the buck converter 2 shown in FIG. 1 has been divided into a drive circuit portion 4, a power switching circuit portion 5, and an energy storage circuit portion 6. The buck converter 2 is arranged to reduce the input voltage by 8 steps to the output voltage 36, wherein the ratio of the two voltages 8, 36 is proportional to the duty cycle of the pulse width modulation (PWM) control signal 12, as will be Interpretation in the text.

The driving circuit portion 4 includes a latch circuit constructed from the Brin reversal gate 14 and the Bollinger damper 16, and the output of the Bolling damper and the Bollinger NAND gate is fed to the high side driver amplifier 20, respectively. With the low side driver amplifier 22 in it. The output 40 of the high side amplifier 20, which employs the output of the inverse gate 14 as an input, is then coupled via an inverter 24 to a second input of the inverse gate 16. Similarly, the output 42 of the low side amplifier 22 (which takes the output of the inverse OR gate 16 as an input) is then coupled via another inverter 26 to the second input of the inverse gate 14. The input of each of the inverse gate 14 and the inverse gate 16 is coupled to the PWM control signal 12.

The outputs of the high side amplifier 20 and the low side amplifier 22 are then applied to the high voltage side p-channel field effect transistor (FET) 28 and the gate terminal of the n-channel low side field effect transistor (FET) 30, respectively. The high side FETs 28 and the low side FETs 30 are arranged in series with the power switching circuit portion 5 such that their respective 汲 terminals are connected at the switching node 38, and the energy storage circuit portion 6 is connected to the switching node, as will be described in further detail below. describe. The source terminal of the high side FET 28 is connected to the input voltage 8, and the source terminal of the low side FET 30 is connected to the ground 10, that is, the input voltage is connected across the power switching circuit portion 5.

The energy storage circuit portion includes an inductor-capacitor (or "LC") filter circuit that includes an inductor 32 that is coupled to the switching node 38 by one of its terminals. The other terminal of inductor 32 is then connected to one terminal of capacitor 34, which in turn connects its other terminal to ground 10. The output voltage is then obtained from output node 36 between inductor 32 and capacitor 34.

Therefore, it will be seen that the latch circuit in the driver circuit portion 4 obtains the PWM control signal 12 via the respective outputs of the high side amplifier 20 and the low side amplifier 22 and generates complementary PWM signals 40, 42. The two PWM drive signals 40, 42 are not simultaneously subjected to a transition, and thus prevent both transistors 28, 30 from being enabled simultaneously. These PWM drive signals 40, 42 intermittently (periodically if the PWM control signal 12 is periodic) cause the power switching circuit portion 5 to switch between an on state and an off state. In the on state, the high side FET 28 is enabled and the low side FET 30 is deactivated, thereby pulling up the voltage at the switching node 38 to the input voltage 8. In the off state, the high side FET 28 is deactivated and the low side FET 30 is enabled, thereby pulling the voltage at the switching node 38 down to ground 10. This intermittent switching of the power switching circuit portion 5 between the on state and the off state causes the energy storage circuit portion 6 to be intermittently coupled to and decoupled from the input voltage 8.

The operation of the buck converter 2 shown in Fig. 1 will be described with reference to the timing chart of Fig. 2.

In general, when the buck converter 2 is first turned on, the power switching circuit portion 5 starts to be in an off state, and the current in the energy storage circuit portion 6 is zero. After the initial positive transition in the PWM control signal 12, the power switching circuit portion 5 will switch to the on state and, in response, the current will increase. Inductor 32 will then generate a voltage in response to the time varying current. This voltage drop cancels the source voltage and thus reduces the voltage at output 36. Over time, the rate of change of current decreases and the voltage across inductor 32 also decreases accordingly. This increases the voltage at output 36. Throughout this process, the inductor 32 generates a magnetic field. If the power switching circuit portion 5 switches to the off state while the current is changing (decoupling the energy storage circuit portion 6 from the input voltage 8), then there will always be a voltage drop across the inductor 32, and thus the output 36 The voltage will always be less than the input voltage of 8. In fact, as will be shown below with reference to Equations 1 through 10, it is generally derived that the ratio of the output voltage 36 to the input voltage 8 is proportional to the duty cycle of the PWM control signal 12, that is, if the duty cycle is 60%, The output voltage 36 will then be 60% of the input voltage 8.

The operation of an ideal buck converter is shown below mathematically with reference to Equations 1 through 10, where: V _L is the voltage across inductor 32; V _i is input voltage 8; V _o is output voltage 36; L is inductor 32 Inductance; I _L is the current passing through the inductor 32; E is the energy stored in the inductor 32 ; t _on is the duration in which the switching circuit portion 5 is in the on state; t _off is the switching circuit portion 5 is in the off state The duration of the state; T is the total period of the voltage cycle at the switching node 38; D is the duty cycle of the voltage cycle at the switching node 38; The current change when the switching circuit portion 5 is in an on state; The current changes when the switching circuit portion 5 is in the off state.

First, since the voltage law Kish where fu (Kirchhoff's voltage law), according to Equation 1, during the on state, the voltage across the inductor V _L 32 and the input voltage must be 8 (V _i) and the output voltage 36 (V _o) The difference between them is the same: V _L = V _i - V _o Equation 1: The voltage across the inductor 32 when the switching circuit portion 5 is in the on state. The current through inductor 32 will rise linearly during this time.

Similarly, according to Equation 2, during the OFF state, the voltage across the inductor V _L 32 must be equal in magnitude to the output voltage 36 (V _o), but the opposite sign: V _L = - V _o Equation 2: Switch The voltage across the inductor 32 when the circuit portion 5 is in the off state. The current through inductor 32 will decrease during this time.

The characteristic equation for the relationship between the energy stored in the inductor 32 and the current passing through it is given below in Equation 3:

Thus, it will be seen that the energy stored in the inductor 32 increases during the on state because the current I _L passing therethrough increases. Conversely, the energy stored in inductor 32 is reduced during the off state because it is used to transfer energy to the output of buck converter 2. According to Equation 4, the rate of change through the inductor _L current I 32 is thus associated with the voltage across the inductor is V _L 32: Equation 4: Characteristic voltage-current equation for inductor 32.

Next, by integrating Equation 4 during the on state, the total change in current during the on state can be found as shown in Equation 5:

Similarly, by integrating Equation 4 during the off state, the total change in current during the off state can be found as shown in Equation 6:

Assuming that the buck converter 2 is operating in a steady state, the energy stored at the end of the period T must be equal to the energy at the beginning of the period.

Since t _on = DT and t _off = (1- D ) T according to Equations 5 and 6, these relationships can be substituted into Equation 7 to obtain Equation 8: ( V _i - V _o ) DT - V _o (1 - D ) T =0 Equation 8: Steady state condition.

Rearrangement Equation 8 further yields Equation 9 below: V _o - DV _i =0 Equation 9: Steady state conditions.

It again yields Equation 10, from which it can be seen how the ratio of the output voltage 36 ( V _o ) to the input voltage 8 ( V _i ) is proportional to the duty cycle D of the PWM control signal 12:

However, during normal operation, there are problems caused by the transition of the PWM control signal 12, as will be described with reference to FIG. Once the buck converter 2 has been operating normally for a period of time, the PWM control signal 12 undergoes a negative transition (ie, it drops from its logic high value to its logic low value 41), so that the voltage of the switching node 38 should necessarily be driven. It is in its logic low state to decouple the energy storage circuit portion 6 from the input voltage 8.

Initially, at time t ₁ , the voltage 40 applied to the gate terminal of the high side FET 28 is increased, thereby turning off the high side FET 28. After a certain amount of dead time T _dead , the voltage 42 applied to the gate terminal of the low side FET 30 then begins to rise at t ₂ . This turns on the low side FET 30, which turns the voltage at the switching node 38 down again, thereby decoupling the energy storage circuit portion 6 from the input voltage 8. However, it can be seen that, just before t _2, the voltage at the switching node experiencing an amount 38 to the negative spike 48a, which means, switching the voltage at node 38 drops to below its final value 41, at a later period of time after The final value is reached. The total peak-to-peak voltage 46a of the voltage at the switching node 38 produces switching noise associated with the buck converter 2.

Similarly, at the subsequent time t3, the PWM control signal 12 undergoes a positive transition, and the voltage 42 applied to the gate terminal of the low side FET 30 is decreased, thereby turning off the low side FET 30. After a further amount of dead time T _dead, the voltage applied to the gate terminal of the high side FET 28 and then at 40 to rise at the beginning of t _4. This turns on the high side FET 28, which in turn pulls up the voltage at the switching node 38, thereby coupling the energy storage circuit portion 6 to the input voltage 8. However, again, just after t _3, switch experiences a negative voltage at node 38 48b amount of the spike. Of course, it should be understood that, in practice, the amount of negative spike 48b associated with a positive transition and the corresponding peak-to-peak voltage 46b may be different than the negative spike 48a associated with the negative transition and the peak-to-peak voltage 48a.

3 shows a synchronous DC-DC buck converter in accordance with an embodiment of the present invention. For reference, the buck converter 102 shown in FIG. 3 has also been divided into a driver circuit portion 104, a power switching circuit portion 105, and an energy storage circuit portion 106. However, the buck converter 102 of FIG. 3 has an additional slew rate control circuit portion 150 when compared to the conventional "non-overlapping" circuit shown in FIG. As with conventional circuits, buck converter 102 is arranged to reduce input voltage 108 to output voltage 136. The ratio of these two voltages 108, 136 is proportional to the duty cycle of the pulse width modulation (PWM) control signal 112. As previously described with reference to FIG. 1, the driver circuit portion 105 generates a first PWM drive signal 140 and a second PWM drive signal 142 from the PWM control signal 112. However, as will be described below, buck converter 102 has less noise associated with it than conventional circuits such as buck converter 2 previously described with reference to FIG.

The slew rate control circuit portion 150 includes an array of p-channel slew rate control FETs 160 ₀ to 160 _n-1 arranged in parallel, each p-channel slew rate control FET having its respective source terminal connected to the input voltage 108 and causing it to be turned The terminal is connected to the source terminal of power FET 162. The gate terminals of the n slew rate control FETs 160 ₀ to 160 _n-1 are coupled to a controller circuit portion 200 (shown in FIG. 7, as described in further detail below) that uses n bits wide A digital control word signal 170 controls the array. Power FET 162 is arranged such that its Zen terminal is connected to switching node 138 and its gate terminal is connected to the gate terminal of low side FET 130.

The operation of this buck converter 102 will now be described with reference to Figure 4, which shows a timing diagram of a typical signal transition. First, the PWM control signal 112 t negative transition at time _0, the driving circuit portion 104 is set to the high logic voltage 140, move off the high pressure side FET 128, thereby decoupling the energy storage circuit portion 108 from the input voltage 106. This makes the voltage at switching node 139 138 begins to fall until it reached its final logic low ₁ 41 t. The drive circuit portion 104 sets the voltage 142 to a logic high, which turns on the low side FET 130.

By selectively enabling the appropriate number of slew rate control FETs 160 ₀ to 160 _n-1 , the slew rate of the voltage 139 at the switching node 138 can be controlled to avoid switching nodes within the conventional buck converter 2 previously described. A typical negative spike of voltage 39 at 38. This also advantageously allows for a lower or "limited" slew rate, wherein the voltage 139 in the buck converter 102 of this embodiment has a lower rate of decrease than the voltage 39 in the conventional buck converter 2, which is achieved by This is clearly seen by the gradient of the voltage 139 which is reduced compared to the voltage 39 shown in FIG. Due to the limited slew rate, voltage 139 does not experience a negative spike similar to negative peak 48a experienced by unrestricted voltage 39. The manner in which the appropriate number of slew rate control FETs 160 ₀ to 160 _{n-1 are} enabled to achieve this functionality is described in more detail below with respect to FIGS. 5-9.

On the PWM control signal 112 is changing at the time t _2, the driving circuit portion 104 is set to a logic low voltage 142, this cut-off low side FET 130. This makes the voltage 139 138 switching node begins to rise, until it soon reaches its final logical high value after t ₃ (ideally, the voltage 139 to switch 138 the node itself reaches its final logical high value at t _3, however, There is a slight delay due to the limited conversion rate of the first PWM drive signal 140 and the second PWM drive signal 142). Drive circuit portion 104 sets voltage 140 to a logic low, which turns on high side FET 128, thereby coupling energy storage circuit portion 106 to input voltage 108.

As previously mentioned, where the appropriate number of slew rate control FETs 160 ₀ to 160 _n-1 have been enabled, the slew rate of voltage 139 at switching node 138 can be controlled to avoid negative spikes. This provides a lower or "limited" slew rate in which the voltage 139 in the buck converter 102 is slower than the rise rate of the voltage 39 in the conventional buck converter 2, again by subtracting from the voltage 39. A small voltage 139 gradient is used to illustrate.

Figure 5 shows a circuit arrangement suitable for determining if the fall time of the voltage at the switching node in Figure 3 is too large. The circuit arrangement includes a push-pull pair of p-channel FETs 202 and n-channel FETs 204 connected together from respective germanium terminals. The source terminal of p-channel FET 202 is coupled to input voltage 108, while the source terminal of n-channel FET 204 is coupled to ground 110 via another n-channel FET 206. The gate terminals of the push-pull FETs 202, 204 are each coupled to the output of the second driver amplifier 122 such that a bias voltage 142 (i.e., a voltage 142 applied to the gate terminal of the low side FET 130) generated by the amplifier 122 is applied. To push-pull FETs 202,204. The gate terminal of another n-channel FET 206 is coupled to switching node 138.

The circuit arrangement further includes a set-reset (SR) latch 210 that has its set input (labeled "S" on latch 210) connected to the push via first inverter 208a The 汲 terminal of the FETs 202, 204 is pulled, and its reset input (labeled "R" on the latch 210) is coupled to the bias voltage 140 generated by the first driver amplifier 120 via the second inverter 208b. .

Figure 6 shows a graph illustrating the dependence of slew rate on load current during a negative transition. Three voltage traces 139, 139', 139" are shown in FIG. 6, which correspond to buck converter 102, respectively, arranged to provide a regular load current (as described above), light load current, and heavy load current.

Where buck converter 102 is arranged to provide a light load current, voltage 139' at switching node 138 drops relatively slowly (ie, it has a shallower gradient than voltage 139 under a regular load). . When the bias voltage 142 applied to the gate terminal of the low side FET 130 reaches the threshold voltage of the FET to turn it on, the low side FET 130 pulls down the voltage 139' at the switching node 138, as may be from time t ₅ The gradient increases as seen. In such a situation, the output signal 212 generated by the latch 210 is set to a logic high, and the controller 200 (described further below with respect to FIG. 7) is arranged to increase the slew rate control FETs 160 ₀ to 160 _{n in} response. The number of enabled transistors within the array of _-1 in order to increase the slew rate at the switching node 138.

When a heavy load current is provided, the voltage 139" at the switching node 138 drops faster than the voltage 139 at the regular load, and in this case does experience a small negative spike to the inline diode threshold. In this case, the output signal 212 generated by the latch 210 is set to a logic low, and the controller 200 is arranged to reduce the enablement within the array of slew rate control FETs 160 ₀ to 160 _n-1 in response. The number of transistors is such that the slew rate at the switching node 138 is slowed down.

Of course, it will be understood that the timing detector described above with reference to FIG. 5 and FIG. 6 is merely exemplary, and other timing detectors known in the art can be easily applied to detect the switching node. Whether the voltage rises and falls time is too large.

FIG. 7 shows controller 200 arranged to control the number of enabled slew rate control FETs 160 ₀ to 160 _n-1 . Controller 200 includes two counters (fall time counter 242 and rise time counter 244) and multiplexer 246. The fall time counter 242 takes as input an output signal 212 generated by the latch 210 (which indicates the fall time of the voltage 139 and whether the switching node 138 is currently too long). Similarly, rise time counter 244 takes as input an output signal 232 generated by latch 230 (which indicates the rise time of voltage 139 and whether switching node 138 is currently too long). Both counters 242, 244 are timed by PWM control signal 112, but rise time counter 244 obtains an inverted replica of PWM control signal 112 generated by inverter 240. Each of the counters 242, 244 is arranged to increment its counter if its respective output signal 212, 232 indicates that the falling or rising time of the voltage 139 at the switching node 138 is too long during its previous negative or positive transition, respectively. value. Conversely, if the output signals 212, 232 are not set to a logic high (ie, the falling or rising time of the voltage 139 at the switching node 138 is within an acceptable range, respectively), the counter values of the appropriate counters 242, 244 are decremented.

Thus, it will be seen that the value of the fall time counter 242 is incremented or decremented on the rising edge of the PWM control signal 112, and the value of the rise time counter 244 is incremented or decremented on the falling edge of the PWM control signal 112 such that its corresponding counter output The new value is ready and stable to enable the correct number of slew rate control FETs 160 ₀ to 160 _n-1 to control the slew rate of voltage 139 at switching node 138 during its next negative or positive transition, respectively. This provides an iterative method for discovering the number of slew rate control FETs 160 ₀ to 160 _n-1 that should be enabled to optimize the rise and fall slew rates of the voltage 139 at the switching node 138. Of course, it will be appreciated that the number of slew rate control FETs 160 ₀ to 160 _n-1 that should be enabled for a negative transition may be different than the number that should be enabled for a positive transition, as typically, a positive transition requires the activation of a larger number of slew rate control FETs. 160 ₀ to 160 _n-1 to pull up the voltage 139 at the switching node 138. Once this optimum point has been reached, the buck converter 102 can operate in a zero voltage switching (ZVS) mode. The ZVS mode allows operation at higher frequencies and higher input voltages without sacrificing efficiency compared to standard PWM operation as described above.

The outputs of the two counters 242, 244 are all input to a multiplexer 246 that switches between its two inputs in response to the value of the PWM control signal 112. The multiplexer then outputs a value generated by one of the counters 242, 244 depending on the value of the PWM control signal 112. For example, if the PWM control signal 112 is logic low, the counter value from the rise time counter 244 is output by the multiplexer 246 to enable the correct number of slew rate control FETs 160 ₀ to 160 _n-1 to control the next positive transition. The rate of conversion of voltage 139 at switching node 138 during the period. Conversely, if the PWM control signal 112 is logic high, the counter value from the fall time counter 242 is output by the multiplexer 246 to enable the correct number of slew rate control FETs 160 ₀ to 160 _n-1 to control the next negative transition. The rate of conversion of voltage 139 at switching node 138 during the period.

Accordingly, it will be seen that the DC-DC decompression circuit provided by the present invention is arranged to vary the number of enabled slew rate control field effect transistors in order to control the transition associated with switching between the on state and the off state. Rate to reduce noise and increase efficiency. It will be appreciated by those skilled in the art that the above described embodiments are illustrative only and not limiting the scope of the invention.

Claims (14)

 A pressure reducing circuit comprising: a power switching circuit portion comprising a high voltage side field effect transistor arranged in series and a low voltage side field effect transistor, wherein the high voltage side field effect transistor and the low voltage side field effect transistor The 汲 terminal of each of the terminals is connected at a switching node, the power switching circuit portion has an on state and an off state, in which the high side FET is Enabled, and the low voltage side field effect transistor is deactivated, and in the off state, the high side field effect transistor is deactivated, and the low side field effect transistor is enabled; an input a voltage across the high side FET and the low side FET; an energy storage circuit portion including an inductor, the energy storage circuit portion being coupled to the switching node and via Arranging to provide an output voltage; a driving circuit portion arranged to receive a pulse width modulation control signal and output a first pulse width modulation driving signal and a second pulse width modulation driving signal; and a slew rate control a circuit portion comprising: one or more slew rate controlled field effect transistors arranged in parallel to form an array; a controller coupled to the one or more slew rate control field effect transistor gate terminals; and power a field effect transistor coupled between the one or more slew rate controlled field effect transistors and the switching node, wherein the controller is arranged to control enabling the one or more slew rate control field effect One of the crystals.    The pressure reduction circuit of claim 1, wherein the controller comprises a digital controller.    The pressure reduction circuit of claim 2, wherein the digital controller is arranged to output a digital control signal, the digital control signal enabling one of the one or more slew rate control field effect transistors select.    A pressure reduction circuit according to any of the preceding claims, wherein the pressure reduction circuit further comprises a timer circuit portion arranged to determine a continuation of a voltage transition at the switching node Time, wherein the controller determines the number of slew rate control transistors to be enabled in response to the duration.    The pressure reduction circuit of claim 4, wherein the controller includes a counter, the counter being arranged to increment the counter value if the determined duration exceeds a threshold duration, and The counter value is decremented if the determined duration does not exceed the threshold duration.    The pressure reducing circuit of claim 4, wherein the controller includes a rising counter and a falling counter, the up counter and the down counter being arranged to respectively convert a positive voltage and The duration of the negative voltage transition is compared to the rising threshold duration and the falling threshold duration.    The reduced pressure circuit of any of the preceding claims includes at least two identical slew rate controlled field effect transistors.    The pressure reduction circuit of any of claims 1 to 6, wherein the array comprises a field effect transistor having a plurality of different channel widths.    The pressure reduction circuit according to any one of the preceding claims, wherein the high voltage side field effect transistor comprises a p-channel metal oxide semiconductor field effect transistor, and the low voltage side field effect transistor comprises a n Channel metal oxide semiconductor field effect transistor.    The reduced voltage circuit of any of the preceding claims, wherein the one or more slew rate controlled field effect transistors and the power field effect transistors comprise p-channel metal oxide semiconductor field effect transistors.    A pressure reduction circuit according to any one of the preceding claims, wherein the slew rate control circuit portion is arranged such that a thorium terminal of the slew rate control transistor is connected to a source terminal of the power transistor a 汲 terminal of the power transistor is coupled to the switching node; and a gate terminal of the power transistor is coupled to a gate terminal of the low voltage side field effect transistor.    A pressure reduction circuit according to any one of the preceding claims, wherein the drive circuit portion includes a latch circuit portion.    The decompression circuit of claim 12, wherein the latch circuit portion comprises a two-input boolean anti-gate and a two-input boolean anti-gate, which are arranged such that: a first input of the gate is coupled to the pulse width modulation input signal; a first input of the inverse or gate is coupled to the pulse width modulation control signal; an output of the inverse gate is coupled to the inverse of the gate Two inputs; and an output of the inverse or gate connected to the second input of the inverse gate.    The pressure reduction circuit of claim 13, wherein the output of each gate is connected to the second input of the other gate via a buffer.