WO2018051084A1

WO2018051084A1 - Dc-dc converters

Info

Publication number: WO2018051084A1
Application number: PCT/GB2017/052698
Authority: WO
Inventors: Samuli Antti HALLIKAINEN
Original assignee: Nordic Semiconductor Asa; Samuels, Adrian James
Priority date: 2016-09-14
Filing date: 2017-09-13
Publication date: 2018-03-22
Also published as: TW201826675A; GB2553794A; GB201615621D0

Abstract

A voltage reducing circuit (102) comprises a power switch circuit portion (105) comprising a high-side (128) and low-side (130) field-effect-transistors connected at a switch node (138). The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion (106) comprising an inductor (132) connected to the switch node is arranged to provide an output voltage (136). A drive circuit portion (104) receives a pulse width modulated control signal and outputs pulse width modulated (PWM) drive signals. A slew rate control circuit portion (150) comprises one or more slew rate control field-effect-transistors 160₀-160_n-1 arranged in parallel. A controller connected (170) is arranged to control which of the one or more slew rate control field-effect-transistors is enabled. A power field-effect transistor (162) is connected between the one or more slew rate control field-effect- transistors and the switch node.

Description

DC-DC Converters

The present invention relates to DC-DC converters, particularly although not exclusively DC-DC voltage reducers such as synchronous DC-DC buck converters.

Modern portable electronic devices are typically provided with a power source such as a battery that acts as a direct current (DC) power supply for the various electronic components within the device. However, typically these components will have different voltage requirements and so it is conventional for such devices to employ one or more DC-DC converters that step a nominal voltage associated with the power supply down to a voltage appropriate for the different electronic components. While this could be achieved by using a potential divider network (e.g. a series of resistors) to create a number of "taps" having different voltages, this is highly inefficient as energy is simply wasted as heat dissipated across the resistors.

One alternative arrangement known in the art per se is a buck converter. A buck converter circuit utilises an inductor-capacitor or "LC" circuit which is periodically connected to and disconnected from the power supply (e.g. by intermittently opening and closing a switch, typically implemented as a transistor referred to as the "high-side" transistor) by a driver in order to step down the voltage. This can be seen as an electrical equivalent to a mechanical flywheel, wherein energy is periodically input to the system to keep it outputting energy at a steady rate. The ratio of the output voltage to the input voltage can be adjusted by altering the duty cycle of a pulse width modulated (PWM) drive signal produced by the driver that is applied to the gate of the high-side transistor in order to open and close it.

A synchronous buck converter circuit replaces what is known as the "freewheeling" or "flyback" diode with a second transistor, often referred to as the "low-side" transistor. The driver then closes the low-side transistor when opening the high- side transistor and vice versa by applying appropriate PWM drive signals to the high- and low-side transistors to open and close them so as to intermittently couple the LC circuit to the input voltage. This improves the efficiency of the buck converter in exchange for increasing the bill of materials associated with the circuit. However, such a driver must prevent both switches from being turned on at the same time else an issue referred to as "shoot-through" will occur wherein a surge of current flows as the high- and low-side transistors which are both conducting act as a short circuit across the power supply. One method to avoid shoot-through is to utilise a time delay between opening the high-side transistor and closing the low-side transistor, and vice versa. However, in order to ensure that both transistors are never conducting at the same time, this time delay will result in excess power loss, and thus a loss in efficiency.

An improved method known in the art per se is known as "non-overlap" operation in which the voltage at the switch node (i.e. the point where the high-side transistor, low-side transistor and the inductor of the LC circuit are connected to one another) is monitored. The time delay between switching on one transistor after the other is switched off is measured from the point at which the voltage at the switch node exceeds, or drops below, a particular threshold as appropriate (depending on whether the transistor turning of is n-type or p-type). Such synchronous drivers can adjust to different types of transistors or switches without the loss in efficiency such flexibility would cause with a fixed non-overlap time.

However, the Applicant has appreciated that improvements can be made in order to further enhance the efficiency of synchronous buck converters and similar arrangements. While the non-overlap topologies guarantee prevention of shoot- through, such converters require the drivers that open and close the high-side and low-side transistors to be relatively fast in order to limit the amount of "dead time" between voltage states at the switch node. However, using sufficiently fast drivers requires relatively large peak currents which introduce unwanted noise into the output voltage, reducing the efficiency of the converter. Furthermore, with a positive current flowing through the buck converter, the body diode (sometimes referred to as the bulk diode) within the low-side transistor typically conducts during both high-to-low and low-to-high transitions, introducing further noise and degrading the efficiency of the converter. Such conventional buck converters also suffer from a relatively large "undershoot", in which the voltage at the switch node temporarily exceeds the body diode threshold voltage of one of the transistors (typically around 0.7 V), causing the body diode within the transistor to conduct, which causes bulk diode and substrate currents to flow therethrough - a yet further source of noise and inefficiency within conventional converters. When viewed from a first aspect, the present invention provides a voltage reducing circuit comprising:

a power switch circuit portion comprising a high-side field-effect-transistor and a low-side field-effect-transistor arranged in series such that the drain terminals of each of said high-side and low-side transistors are connected at a switch node, the power switch circuit portion having an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and an off-state wherein the high- side transistor is disabled and the low-side transistor is enabled;

an input voltage connected across said high-side and low-side transistors; an energy storage circuit portion comprising an inductor, said energy storage circuit portion being connected to the switch node and arranged to provide an output voltage;

a drive circuit portion arranged to receive a pulse width modulated control signal and output first and second pulse width modulated drive signals; and

a slew rate control circuit portion comprising: one or more slew rate control field-effect-transistors arranged in parallel so as to form an array; a controller connected to the gate terminals of said one or more slew rate control field-effect- transistors; and a power field-effect transistor connected between the one or more slew rate control field-effect-transistors and the switch node, wherein the controller is arranged to control which of the one or more slew rate control field-effect- transistors is enabled.

Thus it will be appreciated by those skilled in the art that the present invention may provide an improved voltage reducing circuit wherein the slew rate of the voltage at the switch node can be altered by varying the number of slew rate control field- effect-transistors (FETs) that are enabled. In other words, the rise and fall times of the voltage at the switch node can be controlled by varying the number of slew rate control FETs that are enabled in order to vary the "pull up strength" of the circuit (i.e. its ability to pull up the voltage at the switch node). This provides

improvements in terms of both the noise and efficiency of the voltage reducing circuit of the preferred embodiments of the present invention when compared to conventional circuits.

Furthermore, the voltage reducing circuit of the present invention may

advantageously have a reduced peak current consumption associated with the power switch circuit portion compared to conventional circuits. This can provide for operation of the power switch circuit potion in a zero voltage switching (ZVS) mode which allows for operation at a higher frequency and at higher input voltages without sacrificing efficiency compared to standard PWM operation as described hereinabove.

In some embodiments, the controller comprises a digital controller. In some such embodiments, the digital controller is arranged to output a digital control signal which enables a selection of the one or more slew rate control field-effect- transistors. This allows the controller to "address" the array as a whole, e.g. by outputting a digital word having a length in bits equal to the number of slew rate control FETs. In such embodiments, the application of a digital "0" or "1" (i.e. logic low and logic high respectively) to the gate terminal of each slew rate control FET will enable or disable said FET, such that the total number (and particular selection) of FETs that are enabled can be controlled with relative ease. It will of course be appreciated that the selection may be none, some, or all of the one or more slew rate control field-effect-transistors.

In some embodiments, the voltage reducing circuit further comprises a timer circuit portion arranged to determine a duration of a voltage transition at the switch node, wherein the controller determines a number of slew rate control transistors to be enabled in response to said duration. In some such embodiments, the controller comprises a counter arranged to increment a counter value if the determined duration exceeds a threshold duration and to decrement the counter value if the determined duration does not exceed the threshold duration. In preferred embodiments, the controller comprises a rise counter and a fall counter, arranged to compare the durations of positive and negative voltage transitions to rise and fall threshold durations respectively. In such embodiments, the voltage reducing circuit further may use a single timer circuit portion to determine said rise and fall durations, or the voltage reducing circuit may comprise a rise timer circuit portion and a fall timer circuit portion for determining said rise and fall durations

respectively. In embodiments wherein the controller comprises a digital controller arranged to provide a digital control signal, the digital control signal may comprise the counter value or may have a predetermined relationship thereto.

A voltage reducing circuit in accordance with the present invention may, at least in preferred embodiments, also reduce undershoot at the switch node and the amount of body diode biasing which improves the noise performance and in turn the efficiency of the converter.

It will be appreciated that the on- and off-states referred to hereinabove correspond to the gate-source voltage applied to the field-effect-transistor (FET) being substantially above or below the characteristic threshold voltage of the FET. Of course in practice, the nominal threshold voltage will depend on the properties of the FET itself, including its semiconductor structure, doping level, oxide thickness channel length, etc.

While in some embodiments, at least two slew rate control field-effect-transistors are identical, in other embodiments the array may comprise field-effect-transistors having different properties, for example the array may comprise field-effect- transistors with a plurality of different channel widths such that the controller may selectively enable specific transistors in order to form particular combinations for particular pull up strengths. While it will be appreciated by those skilled in the art that there are a number of field-effect-transistor technologies which could readily be used to implement embodiments of the present invention described herein, in some preferred embodiments the high-side field-effect-transistor comprises a p-channel metal- oxide-semiconductor field-effect-transistor and the low-side field-effect-transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor.

Furthermore, in some potentially overlapping embodiments, the one or more slew rate control field-effect-transistors and the power field-effect-transistor comprise p- channel metal-oxide-semiconductor field-effect-transistors. While those skilled in art will appreciate that there are a number of different topologies that could be readily used to implement the present invention, in at least some preferred embodiments the slew rate control circuit portion is arranged such that: the drain terminals of the slew rate control transistors are connected to the source terminal of the power transistor; the drain terminal of the power transistor is connected to the switch node; and the gate terminal of the power transistor is connected to the gate terminal of the low-side transistor.

It will be appreciated that there are a number of circuit portion arrangements known in the art per se suitable for generating the pulse width modulated drive signals.

However in at least some embodiments, the drive circuit portion comprises a latch circuit portion. In some further embodiments, the latch circuit portion comprises a two input Boolean NAND gate and a two input Boolean NOR gate arranged such that:

the first input of the NAND gate is connected to the pulse width modulated input signal;

the first input of the NOR gate is connected to the pulse width modulated control signal;

the output of the NAND gate is connected to the second input of the NOR gate; and the output of the NOR gate is connected to the second input of the NAND gate. In some such embodiments, the output of each gate is connected to the second input of the other gate via a buffer. These buffers increase the propagation delay to prevent the latch circuit portion from entering a forbidden state wherein the second inputs of each gate are both logic low, increasing the stability of the circuit portion. It will of course be appreciated by those skilled in the art that the latch circuit portion could instead be readily implemented using logically equivalent arrangements.

Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Fig. 1 shows a conventional synchronous DC-DC buck converter for reference purposes only;

Fig. 2 shows a timing diagram illustrating signal transitions typical of the buck converter shown in Fig. 1 ;

Fig. 3 shows a synchronous DC-DC buck converter in accordance with an embodiment of the present invention; Fig. 4 shows a timing diagram illustrating signal transitions typical of the buck converter shown in Fig. 3;

Fig. 5 shows a circuit arrangement suitable for determining whether the fall time of the voltage at the switch node in Fig. 3 is excessive;

Fig. 6 shows a graph illustrating the dependence of the slew rate on the load current during a negative transition;

Fig. 7 shows a circuit arrangement suitable for controlling the number of slew rate control FETs that are enabled. Fig. 1 shows a conventional "non-overlapped" synchronous DC-DC buck converter 2. For ease of reference, the buck converter 2 shown in Fig. 1 has been divided up into a drive circuit portion 4, a power-switch circuit portion 5 and an energy storage circuit portion 6. The buck converter 2 is arranged to step an input voltage 8 down to an output voltage 36, wherein the ratio of these two voltages 8, 36 is proportional to the duty cycle of a pulse width modulated (PWM) control signal 12 as will be explained below.

The drive circuit portion 4 includes a latch circuit constructed from a Boolean NAND gate 14 and a Boolean NOR gate 16, the outputs of which are fed into high-side and low-side driving amplifiers 20, 22 respectively. The output 40 of the high-side amplifier 20 (which takes the output of the NAND gate 14 as an input) is then coupled to the second input of the NOR gate 16 via an inverter 24. Similarly, the output 42 of the low-side amplifier 22 (which takes the output of the NOR gate 16 as an input) is then coupled to the second input of the NAND gate 14 via a further inverter 26. Each of the NAND and NOR gates 14, 16 has an input coupled to the PWM control signal 12.

The outputs of the high-side amplifier 20 and low-side amplifier 22 are then applied to the gate terminals of a high-side p-channel field-effect-transistor (FET) 28 and an n-channel low-side field-effect-transistor (FET) 30 respectively. These high- and low-side FETs 28, 30 are arranged in series as a power-switch circuit portion 5, such that their respective drain terminals are connected at a switch node 38, to which the energy storage circuit portion 6 is connected as will be described in further detail below. The source terminal of the high-side FET 28 is connected to the input voltage 8 and the source terminal of the low-side FET 30 is connected to ground 10, i.e. the input voltage is connected across the power-switch circuit portion 5.

The energy storage circuit portion comprises an inductor-capacitor or "LC" filter circuit, including an inductor 32 connected to the switch node 38 by one of its terminals. The other terminal of the inductor 32 is then connected to one terminal of a capacitor 34, which in turn has its other terminal connected to ground 10. An output voltage is then taken from an output node 36 situated between the inductor 32 and the capacitor 34.

Thus it will be seen that the latch circuit within the drive circuit portion 4 takes the PWM control signal 12 and generates complementary PWM signals 40, 42 via the outputs of the high- and low-side amplifiers 20, 22 respectively. The two PWM drive signals 40, 42 do not undergo transitions at the same time and so prevent both transistors 28, 30 being enabled at the same time. These PWM drive signals 40, 42 intermittently (periodically if the PWM control signal 12 is periodic) cause the power-switch circuit portion 5 to switch between an on-state and an off-state. In the on-state the high-side FET 28 is enabled and the low-side FET 30 is disabled, pulling the voltage at the switch node 38 up to the input voltage 8. In the off-state the high-side FET 28 is disabled and the low-side FET 30 is enabled, pulling the voltage at the switch node 38 down to ground 10. This intermittent switching between the on- and off-states of the power-switch circuit portion 5 causes the energy storage circuit portion 6 to be intermittently coupled to and decoupled from the input voltage 8.

Operation of the buck converter 2 shown in Fig. 1 will be described with reference to the timing diagram of Fig. 2.

Generally, when the buck converter 2 is first switched on, the power-switch circuit portion 5 starts in the off-state and the current in the energy storage circuit portion 6 is zero. After the first positive transition in the PWM control signal 12, the power- switch circuit portion 5 will be switched to the on-state and the current will increase in response. The inductor 32 will subsequently produce a voltage in response to the time-varying current. This voltage drop counteracts the voltage of the source and therefore reduces the voltage at the output 36. Over time, the rate of change of current decreases, and the voltage across the inductor 32 also decreases accordingly. This increases the voltage at the output 36. Throughout this process, the inductor 32 generates a magnetic field. If the power-switch circuit portion 5 is switched to the off-state (decoupling the energy storage circuit portion 6 from the input voltage 8) while the current is changing, there will necessarily always be a voltage drop across the inductor 32 and therefore the voltage at the output 36 will always be less than the input voltage 8. In fact, as will be shown below with reference to Equations 1 to 10, it typically follows that the ratio of the output voltage 36 to the input voltage 8 is directly proportional to the duty cycle of the PWM control signal 12 - i.e. if the duty cycle is 60%, the output voltage 36 will be 60% of the input voltage 8.

The operation of an ideal buck converter is shown mathematically below with reference to Equations 1 to 10, wherein:

V_L is the voltage across the inductor 32;

V_t is the input voltage 8; V₀ is the output voltage 36;

L is the inductance of the inductor 32;

I_L is the current through the inductor 32;

E is the energy stored in the inductor 32;

t_on is the duration for which the switch circuit portion 5 is in the on-state;

t₀ff is the duration for which the switch circuit portion 5 is in the off-state;

T is the total period of the voltage cycle at the switch node 38; D is the duty cycle of the voltage cycle at the switch node 38;

AI_Lon is the change in current while the switch circuit portion 5 is in the on-state; and Δ/_Ιο is the change in current while the switch circuit portion 5 is in the off-state.

Firstly, from Kirchhoff's voltage law, during the on-state the voltage V_L across the inductor 32 must be the same as the difference between the input voltage 8 (V_t) and the output voltage 36 (V₀) as per Eq. 1 :

V_L = Vt - v₀

Equation 1: Voltage across the inductor 32 while switch circuit portion 5 is in the on-state. The current through the inductor 32 will rise linearly during this time. Similarly, during the off-state the voltage V_L across the inductor 32 must be equal in magnitude to the output voltage 36 (V₀) but of the opposite sign as per Eq. 2: v_L = -v₀

Equation 2: Voltage across the inductor 32 while switch circuit portion 5 is in the off-state. The current through the inductor 32 will decrease during this time.

The characteristic equation for the relationship between energy stored in the inductor 32 and the current therethrough is given below in Eq. 3:

^E = -t

Equation 3: Energy stored in the inductor 32.

Thus it will be seen that the energy stored in the inductor 32 increases during the on-state as the current I_L therethrough increases. Conversely, the energy stored in the inductor 32 decreases during the off-state as it is used to transfer energy to the output of the buck converter 2. The rate of change of the current I_L through the inductor 32 is then related to the voltage V_L across the inductor 32 as per Eq. 4:

Equation 4: Characteristic voltage-current equation of the inductor 32. Then by integrating Eq. 4 during the on-state, the total change in current during the on-state can be found as shown in Eq. 5: ton

f VL Vi - V₀

AI_Lon = J - _{dt = (r}±—°-_)toni t_on = DT

o

Equation 5: Increase in current through the inductor during the on-state. Similarly, by integrating Eq. 4 during the off-state, the total change in current during the off-state can be found as shown in Eq. 6: ι+toff

J f V v_L, - -vV„₀

o_ff = - dt = (-^)t_off, t_off = (l - D)T

ton

Equation 6: Decrease in current through the inductor during the on-state.

Assuming that the buck converter 2 operates in the steady state, the energy stored at the end of the period T must be equal to that at the beginning of the period.

Equation 7: Steady state condition.

Since t_on = DT and t_off = (1 - D)T as per Eqs. 5 and 6, these relationships can be substituted into Eq. 7 in order to obtain Eq. 8:

(V_i - V_o)DT - V_o(l - D T = 0

Equation 8: Steady state condition.

Rearranging Eq. 8 further yields Eq. 9 below:

V₀ - DVi = 0

Equation 9: Steady state condition.

Which in turn yields Eq. 10 below, from which it can be seen how the ratio of the output voltage 36 (V₀) to the input voltage 8 (1¾ is directly proportional duty cycle D of the PWM control signal 12:

Equation 10: Relationship between input voltage and output voltage as a function of the duty cycle.

During normal operation however, there are issues caused by the transitions of the PWM control signal 12, as will be described with reference to Fig. 2. Once the buck converter 2 has been operating normally for some time, the PWM control signal 12 undergoes a negative transition - i.e. it falls from its logic high value to its logic low value 41 - which should consequentially drive the voltage at the switch node 38 to its logic low state in order to decouple the energy storage circuit portion 6 from the input voltage 8.

Initially, at time ti , the voltage 40 applied to the gate terminal of the high-side FET 28 increases, which switches off the high-side FET 28. After an amount of dead time, Tdead, the voltage 42 applied to the gate terminal of the low-side FET 30 then begins to rise at t₂. This switches the low-side FET 30 on, which in turn pulls down the voltage at the switch node 38, decoupling the energy storage circuit portion 6 from the input voltage 8. However, it can be seen that just prior to t₂, the voltage at the switch node 38 experiences an undershoot by an amount 48a - i.e. the voltage at the switch node 38 falls below its final value 41 before reaching it sometime later. The total peak-to-peak voltage 46a of the voltage at the switch node 38, generating switching noise associated with the buck converter 2.

Similarly at a subsequent time t₃, the PWM control signal 12 undergoes a positive transition and accordingly the voltage 42 applied to the gate terminal of the low-side FET 30 decreases, which switches off the low-side FET 30. After a further amount of dead time, T_dead, the voltage 40 applied to the gate terminal of the high-side FET 28 then begins to rise at t₄. This switches the high-side FET 28 on, which in turn pulls up the voltage at the switch node 38, coupling the energy storage circuit portion 6 to the input voltage 8. Once again however, just after t₃, the voltage at the switch node 38 experiences an undershoot by an amount 48b. It should of course be appreciated that in practice, the amount of undershoot 48b and the

corresponding peak-to-peak voltage 46b associated with positive transitions may be different to the undershoot 48a and peak-to-peak voltage 48a associated with negative transitions. Fig. 3 shows a synchronous DC-DC buck converter in accordance with an embodiment of the present invention. For reference, the buck converter 102 shown in Fig. 3 has also been divided up into a drive circuit portion 104, a power-switch circuit portion 105 and an energy storage circuit portion 106. However, when compared to the conventional "non-overlapping" circuit shown in Fig. 1 , the buck converter 102 of Fig. 3 has an additional slew rate control circuit portion 150. As with the conventional circuit, the buck converter 102 is arranged to step an input voltage 108 down to an output voltage 136. The ratio of these two voltages 108, 136 is proportional to the duty cycle of a pulse width modulated (PWM) control signal 112. As previously described with reference to Fig. 1 , the drive circuit portion 105 produces first and second PWM drive signals 140, 142 from the PWM control signal 112. However, as will be described below, the buck converter 102 has less noise associated with it than conventional circuits such as the buck converter 2 described previously with reference to in Fig. 1. The slew rate control circuit portion 150 comprises an array of p-channel slew rate control FETs 160₀... 160_n-i which are arranged in parallel, each having their respective source terminals connected to the input voltage 108 and their drain terminals connected to the source terminal of a power FET 162. The gate terminals of the n slew rate control FETs 160₀... 160_n-i are connected to a controller circuit portion 200 (shown in Fig. 9 as described in further detail below) which controls the array using an n-bit wide digital control word signal 170. The power FET 162 is arranged such that its drain terminal is connected to the switch node 138 and its gate terminal is connected to the gate terminal of the low-side FET 130. Operation of this buck converter 102 will now be described with reference to Fig. 4 which shows a timing diagram of typical signal transitions. Firstly with regard to a negative transition in the PWM control signal 1 12 at time t₀, the drive circuit portion 104 sets the voltage 140 to logic high, which switches off the high-side FET 128, decoupling the energy storage circuit portion 106 from the input voltage 108. This causes the voltage 139 at the switch node 138 to begin to fall until it reaches its final logic low value 41 at ti . The drive circuit portion 104 sets the voltage 142 to logic high, which switches on the low-side FET 130.

By selectively enabling the appropriate number of slew rate control FETs

160₀... Ι βθη-ι , the slew rate of the voltage 139 at the switch node 138 can be controlled so as to avoid the undershoot typical of the voltage 39 at the switch node 38 within the conventional buck converter 2 described previously. This also advantageously allows for a lower or "limited" slew rate, wherein the voltage 139 in the buck converter 102 of this embodiment falls at a slower rate than the voltage 39 in the conventional buck converter 2 - this is clearly seen by the reduced gradient of voltage 139 compared to voltage 39 shown for comparison in Fig. 4. Because of the limited slew rate, the voltage 139 does not experience an undershoot analogous to the undershoot 48a experienced by the unlimited voltage 39. The manner in which the appropriate number of slew rate control FETs 160₀... 160η._! to be enabled in order to achieve this functionality is described in greater detail below with reference to Figs. 5 to 9.

With regard to a positive transition in the PWM control signal 112 at time t₂, the drive circuit portion 104 sets the voltage 142 to logic low, which switches off the low-side FET 130. This causes the voltage 139 at the switch node 138 to begin to rise until it reaches its final logic high value shortly after t₃ (ideally the voltage 139 at the switch node 138 would reach its final logic high value at t₃ itself, however there is a slight delay due to the finite slew rate of the first and second PWM drive signals 140, 142). The drive circuit portion 104 sets the voltage 140 to logic low, which switches on the high-side FET 128, coupling the energy storage circuit portion 106 to the input voltage 108.

As before, with an appropriate number of slew rate control FETs 160₀... 160η._! having been enabled, the slew rate of the voltage 139 at the switch node 138 can be controlled so as to avoid undershoot. This provides a lower or "limited" slew rate, wherein the voltage 139 in the buck converter 102 rises at a slower rate than the voltage 39 in the conventional buck converter 2 - this is again illustrated by the reduced gradient of voltage 139 compared to voltage 39. Fig. 5 shows a circuit arrangement suitable for determining whether the fall time of the voltage at the switch node in Fig. 3 is excessive. The circuit arrangement comprises a push-pull pair made up from a p-channel FET 202 and an n-channel FET 204 having their respective drain terminals connected together. The source terminal of the p-channel FET 202 is connected to the input voltage 108, while the source terminal of the n-channel FET 204 is connected to ground 110 via a further n-channel FET 206. The gate terminals of the push-pull FETs 202, 204 are each connected to the output of the second driving amplifier 122 such that the bias voltage 142 produced by the amplifier 122 (i.e. the voltage 142 applied to the gate terminal of the low-side FET 130) is applied to the push-pull FETs 202, 204. The gate terminal of the further n-channel FET 206 is connected to the switch node 138. The circuit arrangement further comprises a set-reset (SR) latch 210 which has its set input (labelled "S" on the latch 210) connected to the drain terminals of the push-pull FETs 202, 204 via a first inverter 208a and its reset input (labelled "R" on the latch 210) connected to the bias voltage 140 produced by the first driving amplifier 120 via a second inverter 208b.

Fig. 6 shows a graph illustrating the dependence of the slew rate on the load current during a negative transition. Show in Fig. 6 are three voltage traces 139, 139', 139" which correspond to the buck converter 102 being arranged to provide a regular load current (as described hereinbefore), a light load current, and a heavy load current respectively.

In the case of the buck converter 102 being arranged to provide a light load current, the voltage 139' at the switch node 138 falls quite slowly (i.e. it has a more shallow gradient compared to the voltage 139 under a regular load). When the bias voltage 142 applied to the gate terminal of the low-side FET 130 reaches the FET's threshold voltage so as to turn it on, the low-side FET 130 pulls down the voltage 139' at the switch node 138 as can be seen from the increase in gradient at time t₅. In such circumstances, the output signal 212 produced by the latch 210 is set to logic high and the controller 200 (described in further detail below with reference to Fig. 9) is arranged to increase the number of enabled transistors within the array of slew rate control FETs 160₀... 160η._! in response, so as to increase the slew rate at the switch node 138.

When providing a heavy load current, the voltage 139" at the switch node 138 falls more quickly compared to the voltage 139 under a regular load and does in this case experience a small undershoot to the body diode threshold. In this case, the output signal 212 produced by the latch 210 is set to logic low and the controller 200 is arranged to decrease the number of enabled transistors within the array of slew rate control FETs 160₀... 160_n-i in response so as to brake the slew rate at the switch node 138.

It will of course be appreciated that the timing detector described above with reference to Figs. 5 and 6 is merely exemplary and that other timing detectors known in the art per se could be readily applied in order to detect whether the rise and fall times of the voltage at the switch node are excessive.

Fig. 7 shows a controller 200 arranged to control the number of slew rate control FETs 160₀... 160η._! that are enabled. The controller 200 comprises two counters - a fall time counter 242 and a rise time counter 244, together with a multiplexer 246. The fall time counter 242 takes the output signal 212 produced by the latch 210 (which indicates whether or not the fall time of the voltage 139 and the switch node 138 is currently too long) as an input. Similarly, the rise time counter 244 takes the output signal 232 produced by the latch 230 (which indicates whether or not the rise time of the voltage 139 and the switch node 138 is currently too long) as an input. Both counters 242, 244 are clocked by the PWM control signal 1 12, though the rise time counter 244 takes an inverted copy of the PWM control signal 112 generated by an inverter 240. Each of the counters 242, 244 is arranged to increment its counter value if their respective output signal 212, 232 indicates that the fall or rise time of the voltage 139 at the switch node 138 was too long during its previous negative or positive transition respectively. Conversely, if the output signal 212, 232 is not set to logic high (i.e. the fall or rise time of the voltage 139 at the switch node 138 was within the acceptable range respectively), the counter value of the appropriate counter 242, 244 is decremented.

Thus it will be seen that the value of the fall time counter 242 is incremented or decremented on a rising edge of the PWM control signal 1 12 and the value of the rise time counter 242 is incremented or decremented on a falling edge of the PWM control signal 1 12, such that the new values of their respective counter outputs are ready and stable in order to enable the correct number of slew rate control FETs 160₀... 160_n-i to control the slew rate of the voltage 139 at the switch node 138 during its next negative or positive transition respectively. This provides an iterative approach for finding the number of slew rate control FETs 160₀... 160_n-i that should be enabled to optimise the rise and fall slew rates of the voltage 139 at the switch node 138. it will of course be appreciated that the number of slew rate control FETs 160₀... 160_n-i that should be enabled for negative transitions may be different to the number that should be enabled for positive transitions as typically positive transitions require a greater number of the slew rate control FETs 160₀... 160η._! to be enabled in order to pull up the voltage 139 at the switch node 138. Once this optimum point has been reached, the buck converter 102 is operable in a zero voltage switching (ZVS) mode. The ZVS mode allows for operation at a higher frequency and at higher input voltages without sacrificing efficiency compared to standard PWM operation as described hereinabove.

The outputs of both counters 242, 244 are both input to the multiplexer 246, which switches between its two inputs in response to the value of the PWM control signal 112. The multiplexer then outputs the value produced by one of the counters 242, 244 depending on the value of the PWM control signal 112. For example if the PWM control signal 112 is logic low, the counter value from the rise time counter 244 is output by the multiplexer 246 in order to enable correct number of slew rate control FETs 160₀...160_n-i to control the slew rate of the voltage 139 at the switch node 138 during the next positive transition. Conversely, if the PWM control signal 112 is logic high, the counter value from the fall time counter 242 is output by the multiplexer 246 in order to enable correct number of slew rate control FETs

160₀...160η._! to control the slew rate of the voltage 139 at the switch node 138 during the next negative transition.

Thus it will be seen that the present invention provides a DC-DC voltage reducing circuit arranged to vary a number of slew rate control field-effect-transistors that are enabled so as to control the slew rates associated with switching between on- and off-states with a view to reducing noise and increasing efficiency. It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.

Claims

1. A voltage reducing circuit comprising:

2. The voltage reducing circuit as claimed in claim 1 , wherein the controller comprises a digital controller.

3. The voltage reducing circuit as claimed in claim 2, wherein the digital controller is arranged to output a digital control signal which enables a selection of the one or more slew rate control field-effect-transistors.

4. The voltage reducing circuit as claimed in any preceding claim, wherein the voltage reducing circuit further comprises a timer circuit portion arranged to determine a duration of a voltage transition at the switch node, wherein the controller determines a number of slew rate control transistors to be enabled in response to said duration.

5. The voltage reducing circuit as claimed in claim 4, wherein the controller comprises a counter arranged to increment a counter value if the determined duration exceeds a threshold duration and to decrement the counter value if the determined duration does not exceed the threshold duration.

6. The voltage reducing circuit as claimed in claim 4 or 5, wherein the controller comprises a rise counter and a fall counter, arranged to compare the durations of positive and negative voltage transitions to rise and fall threshold durations respectively.

7. The voltage reducing circuit as claimed in any preceding claim, comprising at least two identical slew rate control field-effect-transistors.

8. The voltage reducing circuit as claimed in any of claims 1 to 6, wherein the array comprises field-effect-transistors with a plurality of different channel widths.

9. The voltage reducing circuit as claimed in any preceding claim, wherein the high-side field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor and the low-side field-effect-transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor.

10. The voltage reducing circuit as claimed in any preceding claim, wherein the one or more slew rate control field-effect-transistors and the power field-effect- transistor comprise p-channel metal-oxide-semiconductor field-effect-transistors.

11. The voltage reducing circuit as claimed in any preceding claim, wherein the slew rate control circuit portion is arranged such that: the drain terminals of the slew rate control transistors are connected to the source terminal of the power transistor; the drain terminal of the power transistor is connected to the switch node; and the gate terminal of the power transistor is connected to the gate terminal of the low- side transistor.

12. The voltage reducing circuit as claimed in any preceding claim, wherein the drive circuit portion comprises a latch circuit portion.

13. The voltage reducing circuit as claimed in claim 12, wherein the latch circuit portion comprises a two input Boolean NAND gate and a two input Boolean NOR gate arranged such that:

the output of the NAND gate is connected to the second input of the NOR gate; and the output of the NOR gate is connected to the second input of the NAND gate.

14. The voltage reducing circuit as claimed in claim 13, wherein the output of each gate is connected to the second input of the other gate via a buffer.