TW201820756A - Active clamp overvoltage protection for switching power device - Google Patents

Abstract

A controller for driving a power switch incorporates a protection circuit to protect the power switch from fault conditions, such as over-voltage conditions or power surge events. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is configured to monitor the voltage across the power switch and to generate a fault detection indicator signal and the protection gate drive circuit is configured to generate a gate drive signal to turn on the power switch in response to a detected fault condition. In particular, the protection gate drive circuit generates a gate drive signal that has a slow assertion transition and is clamped at a given gate voltage value. In this manner, the protection circuit implements active clamping of the gate terminal of the power switch and safe handling of the power switch during over-voltage events.

Description

Active clamping overvoltage protection for switching power supply units

The present invention relates to a controller that drives a power switch.

Induction heating is widely used in domestic, industrial and medical fields. Induction heating refers to the technology that uses electromagnetic induction to generate a current in a closed circuit (on an object) through the fluctuation of current in another circuit that makes physical contact with an object, and heats a conductive object (such as a metal). For example, induction cookers contain an AC-powered resonant cavity that generates an AC magnetic field at the induction coil. The AC magnetic field at the induction coil generates a current in a metal cooking tank located near the induction coil. The current induced in the resistance metal cooking pot generates heat, which in turn heats the food in the cooking pot.

The common topology used in induction heating is a single-switch quasi-resonant inverter topology, which includes a separate power switch and a separate resonant capacitor to provide a variable resonant current to the induction coil. Generally, an insulated gate bipolar transistor (hereinafter referred to as IGBT) is used as a power switching device, which utilizes the high power performance and high switching frequency operation of an IGBT to configure a single-switch quasi-resonant inverter.

Overvoltage conditions such as power surges are a serious problem for single-switch quasi-resonant inverter circuits. Especially when the voltage applied to the power switching device exceeds the rated voltage, the power switching device may fail or be permanently damaged in the quasi-resonant inverter circuit. For example, when lightning occurs, there may be abnormally high surge voltage on the AC (hereinafter referred to as AC) input line. When the surge voltage exceeds the breakdown voltage of the power switching device, the power switching device may be irreversibly damaged if remedial measures are not taken for a power surge event within a short period of time (on the order of a few milliseconds).

The invention discloses a control circuit for generating a gate driving signal on an output node to drive a gate terminal of a power switch. The gate terminal controls the current flow between the first and second power terminals of the power switch. The control circuit The method includes: configuring a first gate driving circuit to receive an input control signal and generate a first output signal as a gate driving signal. According to the input control signal, the gate terminal of the driving power switch is completely turned on and off. The output signal has a first gate voltage value, and the gate terminal of the driving power switch is fully connected to the power switch; a protection circuit is configured to receive the first voltage at the first power terminal of the power switch, and generate a fault detection indication signal according to the first voltage When the voltage level exceeds a predefined level, the protection circuit takes effect and the fault detection indication signal is configured; a second gate drive circuit is configured to receive the fault detection indication signal and generate a second output signal as a gate drive signal, and drive according to the fault detection indication signal Gate end of the power switch, the second gate drive circuit includes a coupling to the output The impedance voltage dividing circuit at the point generates a second output signal with a slow effective transient. The peak voltage value is clamped at the second gate voltage value. The second gate voltage value is greater than the threshold voltage of the power switching device and is less than The first gate voltage value, wherein according to the effective fault detection instruction signal, the second gate drive circuit activates the second output signal, and at the second gate voltage value, the power switch is turned on for a predefined period of time.

The protection circuit includes a hysteresis overvoltage detection circuit having a set voltage level and a reset voltage level. The set voltage level is higher than the reset voltage level. According to the first voltage being at or above the set voltage level, the hysteresis is excessive. The voltage detection circuit activates the fault detection indication signal, and fails the fault detection indication signal according to the first voltage being at or below the reset voltage level.

Wherein, according to the lag overvoltage detection circuit to activate the fault detection instruction signal, the second gate driving circuit becomes effective to the second output signal after the first time period.

The second gate driving circuit activates the second output signal, and turns on the power switch at the second gate voltage value according to the shorter time period and the predefined fixed time period of the effective fault detection instruction signal.

Among them, according to the effective input control signal, the protection circuit is deactivated, and the power switch is turned on. After the input control signal fails, the protection circuit is enabled for the second time period to turn off the power switch.

The first gate driving circuit is disabled according to the effective fault detection instruction signal.

The first gate driving circuit includes a first transistor, a first impedance, a second impedance, a second transistor connected in series between a positive voltage source voltage and a ground voltage, and a common between the first impedance and the second impedance. Node as an output node; and the second gate driving circuit includes a third transistor, a third impedance, a fourth impedance, a fourth transistor connected in series between a positive voltage source voltage and a ground voltage, a third impedance, and a fourth impedance The common node between them is used as the output node, where the first gate driving circuit turns on the first transistor, disconnects the second transistor, takes effect on the first output signal, fully turns on the power switch, and turns off the first gate driving circuit. Turn on the first transistor, turn on the second transistor, activate the first output signal, and completely turn off the power switch; and according to the effective fault detection instruction signal, the second gate driving circuit turns on the third transistor and the fourth transistor. The transistor activates the second output signal at the second gate voltage value and turns on the power switch.

Among them, the second output signal has a slow effective transient. Therefore, after the third transistor and the fourth transistor are turned on, the third impedance and the fourth impedance constitute an impedance voltage divider.

Among them, the second output signal is clamped at the second gate voltage value. Therefore, after the third transistor and the fourth transistor are turned on, the third impedance and the fourth impedance constitute an impedance voltage divider, and the second gate voltage value The voltage that divides the positive voltage source voltage as a function of the third impedance and the fourth impedance.

Wherein, according to the effective fault detection instruction signal, the first gate driving circuit turns off the second transistor, and the second gate driving circuit turns on the third transistor and the fourth transistor.

Among them, the second gate driving circuit turns off the third transistor and the fourth transistor according to the failed fault detection indication signal or the fixed time period expires. After the third transistor is turned off, the fourth transistor is turned off for a third time. segment.

Wherein, after the fourth transistor is turned off, the first gate driving circuit turns on the second transistor, drives the first output signal to a voltage level, and keeps the power switch off.

Among them, the power switch is composed of an insulated gate bipolar transistor (IGBT) device.

The invention also discloses a method for generating a gate driving signal for driving a gate terminal of a power switch. The gate terminal controls the current flow between the first and second power terminals of the power switch. The method includes: monitoring a feedback voltage, The feedback voltage indicates the voltage between the first and second power terminals of the power switch during the off time of the power switch; it is determined that the feedback voltage exceeds the first voltage level; and according to the determination, the drive power switch is disabled during the off time Extremely common gate drive signals; enable protection gate drive signals based on the determination;

Generate a clamped gate drive signal with a clamped gate drive voltage value, and use the clamped gate drive signal to turn on the power switch; monitor the feedback voltage to determine if the feedback voltage drops below the second voltage level, the second voltage The level is lower than the first voltage level; according to the determination that the feedback voltage has fallen below the second voltage level, the clamp gate driving signal is disabled and the gate terminal of the discharge power switch is disabled; the common gate driving signal is enabled; and monitoring continues Feedback voltage, which represents the voltage between the first and second power terminals of the power switch during the off time of the power switch.

It also includes: determining that the clamp gate driving signal has been enabled for the first time period; according to the determined situation, deactivating the clamp gate driving signal and discharging the gate end of the power switch.

The invention can be implemented in a variety of ways, including as a process; a device; a system; and / or a substance composition. In this specification, these implementation manners or any other manner that the present invention may adopt may be referred to as technologies. In general, the order of the process steps can be changed within the scope of the invention.

The detailed description of the one or more embodiments of the present invention and the accompanying drawings explain the principles of the present invention. Although the present invention is proposed together with the embodiments, the scope of the present invention is not limited to any embodiment. The scope of the present invention is limited only by the claims, and the present invention includes various alternatives, modifications, and equivalents. In the following description, various specific details are provided for a comprehensive understanding of the present invention. These details are used for explanation, and the present invention can be implemented according to the claims without some or all of these details. For the sake of clarity, technical materials that are well known in the technical field related to the present invention have not been described in detail, so as to avoid unnecessary confusion on the present invention.

In the embodiment of the present invention, the controller for driving the power switch introduces a protection circuit, so as to protect the power switch when a fault such as overvoltage or power surge occurs. The protection circuit includes a fault detection circuit and a protection gate driving circuit. The purpose of configuring a fault detection circuit is to monitor the voltage on the power switch and send out a fault detection indication signal. The purpose of configuring the protection gate driving circuit is to issue a gate driving signal. When a fault condition is detected, the power switch is turned on. Specifically, the gate driving signal generated by the protection gate driving circuit has a slow effective transition, and is clamped at a specified gate voltage value. In this case, the protection circuit implements the gate terminal of the power switch effectively and safely handles the power switch in the event of an overvoltage.

In some embodiments, the protection gate driving circuit drives the power switch to turn on for a predefined period of time to consume energy in the event of a faulty over-voltage condition on the power switch. In other embodiments, the fault detection circuit includes a lagging over-voltage detection circuit, which uses the set voltage level and the voltage level reset by the fault detection, and the set voltage level is higher than the reset voltage level. When the voltage on the power switch exceeds the set voltage level, the fault detection indication signal becomes effective. When the voltage on the power switch falls below the reset voltage level, the fault detection indication signal becomes invalid. In some embodiments, the protection gate driving circuit enables the gate driving signal to take effect, and according to the effective work detection instruction signal, turns on the power switch under the embedded gate voltage. The protection gate driving circuit uses an embedded gate driving signal until the fault detection indication signal fails or after a predefined fixed time period, the fixed time period is quite short.

In the embodiment of the present invention, a controller is used to drive a power switch introduced in a single-switch quasi-resonant inverter for induction heating. Generally, an insulated gate bipolar transistor (IGBT) is used as a power switching device. A single-switch quasi-resonant inverter is configured using the high power performance and high switching frequency operation of the IGBT. The protection circuit of the present invention is configured with an active gate protection system to protect the power switch, which can effectively protect the IGBT in the quasi-resonant inverter circuit for induction heating.

Compared with the traditional protection system, the protection circuit of the present invention realizes multiple advantages of a power switching device or an IGBT. In particular, the protection circuit according to the present invention is configured with an active clamp with soft gate drive control to protect the power switching device when an overvoltage occurs. When an over-voltage situation occurs, the power switch device is turned on and the gate voltage is embedded to protect the gate end of the power switch device from the over-voltage. At the same time, turning on the power switch device one or more times in succession can consume excessive voltage and current. Soft gate drive control with soft-on and soft-off, suppresses resonance caused by voltage transients on the power switching device when turning on and off. The protection circuit according to the present invention implements effective over-voltage protection for a power switching device or an IGBT.

Figure 1 shows a circuit diagram of a single-switch quasi-resonant inverter for induction heating in some examples. Referring to FIG. 1, the single-switch quasi-resonant inverter 10 includes a surge suppressor 14, a bridge rectifier 16, a filter circuit, a resonant cavity, and a power switching device M0, which is also referred to as a power switch. The quasi-resonant inverter 10 receives an AC input voltage 12 and is coupled to a surge suppressor 14. The bridge rectifier 16 is also called a diode bridge, and converts the AC input voltage 12 into a direct current (hereinafter referred to as DC) voltage, and then filters it through a filter circuit including an input capacitor Ci, a filter inductor Lf, a filter capacitor Cf, and a resistor Rs. The filtered DC voltage is used in a resonant cavity, which is composed of an induction coil Lr and a resistance capacitor Cr. The induction coil Lr is connected to a power switch M0, and the power switch M0 is turned on and off according to the gate driving signal _Vgctrl . When the power switch M0 is turned on, no current flows through the power switch M0. Conversely, the current i _Lr circulates between the induction coil Lr and the resistance capacitor Cr. In this embodiment, the power switch M0 is an insulated gate bipolar transistor (IGBT). The controller terminal of the IGBT is connected to the induction coil Lr (node 20), and the emitter terminal of the IGBT is grounded. The gate terminal of the IGBT is driven by a gate drive signal V _gctrl .

In actual operation, when the power switch M0 (IGBT) is turned on, the AC current passes through the induction coil Lr and generates a resonant magnetic field. The resonant magnetic field induces an electric field in a metal cooking tank near the induction coil. The current flowing through the resistance metal tank will generate heat, which will heat the food in the cooking tank. When the power switch M0 is turned off, the current i _Lr circulates around the induction coil Lr and the capacitor Cr. According to the gate driving signal V _gctrl , the power switch M0 is turned on and off, and the amount of current induced in the cooking tank is controlled, thereby controlling the heat generated.

When the single-switch quasi-resonant inverter works, the power switch M0 (IGBT) is turned on and off. When the power switch is turned off, the power switch M0 can be subjected to a voltage transient at the power terminal (node 20). For example, when the IGBT is turned off, the controller voltage V _CE (node 20) can increase very quickly, for example, for an AC input voltage of 220V, it can be as high as 800-1000V. In this case, an IGBT with a typical rated voltage of 1.7kV for the emitter-collector voltage can handle normal voltage transients when switching on and off. However, the IGBT can be exposed to faulty over-voltage conditions such as power surge events. At this time, the voltage induced by the voltage surge at the induction coil Lr exceeds the rated voltage of the IGBT. For example, during lightning conditions, unusually large power surges can be introduced to the AC power line. Power surges caused by lightning can drive the IGBT's collector voltage to more than 2kV, exceeding the IGBT's rated voltage, causing damage to the IGBT. Therefore, power switches or IGBTs in single-switch quasi-resonant inverters must be protected from overvoltage events such as excessive power surges.

In addition, the power switch must be protected from power surge events, especially when the power switch is turned off and a power surge event occurs. When the power switch is turned on, the power switch can consume the surge voltage to ground through the conduction of its power terminal. For example, when an IGBT is turned on, the IGBT can conduct a voltage surge from the collector to a grounded emitter to consume the voltage surge. However, if the IGBT is turned off, the transistor cannot consume the surge voltage, and the collector terminal may experience an excessive surge voltage exceeding the rated voltage of the device, causing permanent damage to the transistor.

FIG. 2 shows a structural diagram of a controller circuit including a protection circuit in the embodiment of the present invention. The coupling protection circuit is used to drive a power switch in a single-switch quasi-resonant inverter with induction heating. Referring to FIG. 2, the single-switch quasi-resonant inverter 10 shown in FIG. 1 is driven by a control circuit 30 to turn on and off the power switch M0 and conduct alternating current through the induction coil Lr. In this embodiment, the power switch M0 is an IGBT with the gate as the control terminal, the collector and the emitter as the power terminal. In the following description, the control circuit will drive the IGBT as a power switch M0. This description is for explanation only and not for limitation. It should be understood that in addition to the IGBT, other power switching devices may be used to configure the power switch M0. The power switch or power switch device includes a control terminal or a gate terminal, receives a control signal or a gate driving signal, and conducts current through a pair of power terminals.

In the embodiment of the present invention, the control circuit 30 includes a normal gate driving circuit 34 and a protection circuit composed of a protection gate driving circuit 40 and a fault detection circuit 50. In this embodiment, the fault detection circuit 50 is configured as an overvoltage detection circuit to detect an overvoltage condition or an excessive voltage event at the collector terminal (node 20) of the IGBT, or an excessive collector-to-emitter voltage V at the IGBT _CE .

In the control circuit 30, the normal gate driving circuit 34 receives the input signal V _IN (node 32), and is used to control the on and off switching cycle of the power supply device M0 or IGBT, and obtain the required Power output. The input signal V _IN may be a PWM signal or a clock signal switched between an on period and an off period. The normal gate driving circuit 34 generates an output signal at a node 52 as a gate driving signal V _gctrl and is coupled to a gate terminal (node 22) of the IGBT. In this embodiment, the normal gate driving circuit is configured as a CMOS inverter and includes a PMOS transistor M1, which is connected in series with the NMOS transistor M2 between the positive power supply voltage Vdd (node 38) and ground. The impedance Z1 is coupled to the drain terminal (node 52) of the PMOS transistor M1, and the impedance Z2 is coupled to the drain terminal (node 52) of the NMOS transistor M2. The common node 52 between the PMOS transistor M1 and the NMOS transistor M2 is an output signal of the normal gate driving circuit 34.

The gate logic circuit 36 receives the input signal V _IN and generates a gate control signal for the PMOS transistor M1 and the NMOS transistor M2. The gate logic circuit 36 generates a gate control signal for the PMOS transistor M1 and the NMOS transistor M2, so that the PMOS transistor M1 and the NMOS transistor M2 are alternately turned on and off according to the input signal V _IN . In other words, the PMOS transistor M1 and the NMOS transistor M2 are not turned on at the same time. Therefore, when the input signal V _IN is switched between a logic high level and a logic low level, the normal gate driving circuit 34 generates a gate driving signal V _gctrl to turn the IGBT on and off for normal operation. More specifically, the NMOS transistor M2 is turned on, the gate terminal of the driving IGBT is grounded, and the IGBT is turned off under normal operation. Alternatively, the PMOS transistor M1 is turned on, the gate terminal of the IGBT is driven to the power supply voltage Vdd, and the IGBT is turned on under normal operation.

The control circuit 30 includes a protection circuit to provide over-voltage protection for the power switch M0 or IGBT at the gate driving level. The protection circuit is configured with active gate clamping and safe handling of over-voltage events at the power switch of the quasi-resonant inverter. The protection circuit includes an overvoltage detection circuit 50 and a protection gate driving circuit 40. The over-voltage detection circuit 50 detects an over-voltage fault condition during normal operation of the power switch, activates corrective measures, and protects the power switch from damage. According to the detection of the fault condition, the protection gate driving circuit 40 is activated, and an embedded gate voltage is generated as a gate driving signal to bias the power switch so as to consume a voltage surge before causing any damage to the power switch.

The overvoltage detection circuit 50 receives a feedback voltage V _FB at the input node 54, which represents the voltage from the collector to the emitter of the IGBT V _CE , or the voltage on the power supply terminal of the power switch M0. In this embodiment, the voltage divider formed by the resistors R6 and R7 is coupled to the collector terminal (node 20) of the IGBT, and divides the collector to the emitter voltage as the feedback voltage V _FB . The feedback voltage V _FB (node 20) is coupled to the over-voltage protection circuit 50 to detect an over-voltage condition. In the embodiment of the present invention, the overvoltage detection circuit 50 operates only when the IGBT is turned off. In other words, when the overvoltage detection circuit 50 is activated, the collector-emitter voltage can only be monitored during the time when the IGBT driven by the gate drive signal _Vgctrl is completely _turned off.

When the IGBT is fully turned on, the IGBT conducts current from the collector to the emitter, and the collector voltage (node 20) is maintained at the saturation voltage V _CE-SAT . Therefore, even if there is a power surge, the collector voltage at the IGBT is very low, thereby protecting the IGBT from damage. However, during the time when the IGBT is completely turned off, a power surge at the IGBT collector terminal may generate an excessively high collector voltage, thereby damaging the IGBT.

During the off-time period of the IGBT, the over-voltage detection circuit 50 compares the feedback voltage V _FB (node 20) with the over-voltage threshold voltage value to determine whether an over-voltage condition occurs at the collector terminal of the IGBT. When the feedback voltage V _FB exceeds the over-voltage threshold voltage value, the over-voltage detection circuit 50 generates a failure detection instruction signal. More specifically, according to the feedback voltage V _FB exceeding the over-voltage threshold voltage value, the over-voltage detection circuit 50 activates the fault detection instruction signal, and based on the feedback voltage V _{FB being} lower than the over-voltage threshold voltage value, the over-voltage detection circuit 50 enables the failure detection Indication signal is invalid. In some embodiments, the overvoltage detection circuit is configured as a hysteresis overvoltage detection circuit, including a set voltage level and a reset voltage level for detecting a fault overvoltage condition, the set voltage level being higher than the reset voltage Level. When the voltage on the power switch exceeds the set voltage level, the fault detection indication signal becomes effective. When the voltage on the power switch falls below the reset voltage level, the fault detection indication signal becomes invalid.

The normal gate driving circuit 34 and the protection gate driving circuit 40 are provided with a fault detection instruction signal or a signal indicating it. At the normal gate driving circuit 34, a fault detection indication signal or an equivalent signal is coupled to the gate logic circuit 36. When a fault overvoltage condition is detected, the operation disables or disconnects the NMOS transistor M2. When the overvoltage detection circuit 50 is activated, the IGBT is turned off, which means that the NMOS transistor M2 is activated or turned on in the normal gate driving circuit 34, and the gate driving signal is grounded, thereby turning off the IGBT. In order to initiate remedial measures based on whether a fault overvoltage condition is detected, the NMOS transistor M2 should be turned off or disabled, so that the protection gate driving circuit 40 can be activated to drive the gate of the IGBT. In this case, the protection gate driving circuit 40 does not need to over-drive the NMOS transistor M2. In other words, under normal operation, the transistors M1 and M2 are turned on and off alternately to drive the gate of the IGBT. However, when an overvoltage condition is detected, the transistors M1 and M2 are both turned off before or at the same time as the protective gate driving circuit 40 initiates remedial measures.

A fault detection indication signal or a signal indicating it is also provided for the protection gate driving circuit 40 to initiate remedial measures to protect the IGBT. In this embodiment, the protection gate driving circuit 40 includes a PMOS transistor M3, which is connected in series with the NMOS transistor M4 between the positive power supply voltage Vdd (node 38) and the ground. An impedance Z3 is provided at the drain terminal (node 52) of the PMOS transistor M3, and an impedance Z4 is provided at the drain terminal (node 52) of the NMOS transistor M4. The common node 52 between the PMOS transistor M3 and the NMOS transistor M4 is to protect the output signal of the gate driving circuit. The protection gate driving circuit 40 generates an output signal at the node 52 as a gate driving signal V _gctrl and is coupled to the gate terminal (node 22) of the IGBT.

The fault detection instruction signal or a signal indicating it generated by the overvoltage detection circuit 50 is coupled through the respective clock controller and the gate voltage clamping circuit to control the PMOS transistor M3 and the NMOS transistor M4. At the PMOS transistor M3, a fault detection indication signal or a signal indicating it is coupled to the clock controller 42 and the gate control circuit 44. The clock controller 42 controls the on-time of the PMOS transistor M3 according to the failure detection instruction signal. Specifically, the clock controller 42 turns on the PMOS transistor M3 until the fault detection indication signal fails or continues for a predefined fixed period of time (also referred to as "one-time duration"), which is relatively short. At the NMOS transistor M4, a fault detection indication signal is coupled to the clock controller 46 and the gate control circuit 48. The clock controller 46 controls the on-time of the NMOS transistor M4 according to the failure detection instruction signal. Specifically, the clock controller 46 delays the turn-off effective time of the NMOS transistor M4 to provide a soft turn-off of the IGBT, which will be described in detail below.

In operation, the NMOS transistor M2 in the normal gate driving circuit 34 is turned off according to the effective fault detection instruction signal. At the same time, the protection gate driving circuit 40 turns on the PMOS transistor M3 and the NMOS transistor M4. As the PMOS transistor M3 and the NMOS transistor M4 are turned on, the impedance Z3 and the impedance Z4 form a voltage divider between the positive power supply voltage and the ground. The voltage dividers of Z3 and Z4 generate an output signal, which serves as a gate driving signal and becomes a divided voltage of the positive power supply voltage Vdd at the output node 52. To be precise, the voltage value of the gate drive signal embedding is a function of the impedances Z3 and Z4, which is expressed as: Embedded voltage =

Therefore, the protection gate driving circuit 40 generates an output signal under the clamped gate voltage value, and as the gate driving signal V _gctrl , drives the gate terminal of the IGBT. Therefore, when an overvoltage condition occurs, the IGBT is turned on, and the excess charge at the collector terminal (node 20) is consumed. Through the voltage divider of Z3 and Z4, the gate of the IGBT is driven, and the gate of the IGBT is gradually turned on, so as to realize the soft switching of the clamped gate voltage. In this case, the protection gate driving circuit 40 turns on the IGBT in the protection mode to discharge the voltage overshoot.

The over-voltage detection circuit 50 continues to monitor the feedback voltage V _FB . When the collector-emitter voltage V _CE (node 20) falls below the over-voltage threshold voltage value or the reset voltage level in the hysteresis detection circuit, the over-voltage detection circuit 50 disables the fault detection instruction signal. The protection gate driving circuit 40 can then be disabled, and the IGBT can be turned off in the protection mode. In actual operation, the time controller 42 will first disable the gate control signal on the PMOS transistor M3, and release the clamped gate voltage at the output node 52. In the embodiment of the present invention, the protection circuit uses a clamp gate driving signal to turn on the IGBT under an overvoltage condition, but the on-time of the IGBT is limited to a maximum time period determined by a fixed time. In the case that the voltage overshoot is not consumed and the IGBT is turned on under the clamped gate voltage, the fault detection indication signal may remain valid for an unnecessary extended time. It is not necessary to make the IGBT turn on for too long, which may affect the reliability of the IGBT. Therefore, the time controller 42 in the protection gate driving circuit 40 can use the maximum one-time duration for the on-time of the PMOS transistor M3. When the fault detection indication signal fails or when a fixed period of time expires, whichever is shorter is selected, the time controller 42 disables the gate control signal of the PMOS transistor M3.

The PMOS transistor M3 is not available, and the output signal of the protection gate driving circuit 40 is no longer driven to the clamped gate voltage. However, the IGBT's gate terminal (node 22) must be discharged to ground to disconnect the IGBT. Therefore, when the fault detection instruction signal fails, the time controller 46 delays until the gate driving signal of the NMOS transistor M4 fails. Therefore, when the PMOS transistor M3 is turned off after an overvoltage protection event, the NMOS transistor remains on for a specified delay time to discharge the gate terminal (node 22) of the IGBT, thereby achieving a soft break of the clamped gate voltage open. After a delay time, the NMOS transistor M4 electrode is turned on and the NMOS transistor M2 in the normal gate driving circuit 34 returns to ON, and the IGBT's gate terminal is kept grounded before the IGBT returns to normal operation.

After such a configuration, the protection circuit in the control circuit 30 achieves over-protection at the gate drive level for the IGBT in the quasi-resonant inverter 10. Specifically, with the voltage divider of Z3 and Z4, the gate voltage of the IGBT can be accurately controlled between the threshold voltage and the Miller flat region level. Therefore, when the IGBT is turned on, when a fault overvoltage condition occurs, the sensing coil current i _Lr flows through the IGBT, so that the resonant capacitor voltage V _{Cr is} clamped at the required level. In this case, the protection circuit is driven by an active voltage to safely protect the power switch in the IGBT or quasi-resonant inverter from voltage overshoot or other overvoltage conditions. The protection circuit is configured with soft on and off operation, which can switch IGBT without large transients. In some embodiments, the impedances Z3 and Z4 that ensure the clamped gate voltage are used to form a protection gate drive circuit that is not affected by temperature changes.

FIG. 3 is a circuit diagram showing a control circuit structure shown in FIG. 2 in an embodiment of the present invention. Referring to FIG. 3, the control circuit 60 for driving the IGBT gate terminal (node 22) includes a common gate driving circuit 66 and a protection gate driving circuit 68. The control circuit 60 further includes a hysteresis overvoltage detection circuit 80 for contacting an overvoltage condition or an overvoltage condition at the IGBT collector terminal (node 20) or an excessive collector-to-emitter voltage V _CE at the IGBT.

In the control circuit 60, the standard gate driving circuit 66 receives an input signal V _IN (node 62) for controlling the on and off switching cycle of the IGBT to obtain the required power output at the quasi-resonant inverter. A common gate driving circuit is configured as a CMOS inverter, including a PMOS transistor M1 and an NMOS transistor M2 connected in series between a positive power supply voltage V _dd (node 64) and ground. The impedance Z1 is coupled to the drain terminal (node 76) of the PMOS transistor M1, and the impedance Z2 is coupled to the drain terminal (node 76) of the NMOS transistor M2. The common node 76 between the PMOS transistor M1 and the NMOS transistor M2 is an output signal of a commonly used gate driving circuit 34. The input signal V _IN can be a PWM signal or a clock signal that switches between on-time and off-time. The common gate driving circuit 66 generates an output signal at the node 76 as a gate driving signal V _gctrl and is coupled to the gate terminal (node 22) of the IGBT. In some embodiments, the impedance Z5 may be coupled to the output node 76 to keep the gate of the IGBT to ground so that the gate is not driven by any other circuit. The impedance Z5 is optional and can be omitted in other embodiments.

The input voltage V _{IN is} coupled to the NOR gate 72 to generate a gate control signal V _G2 for controlling the NMOS transistor M2. The input voltage V _{IN is} also coupled to the inverter 74 to generate a gate control signal V _G1 for controlling the PMOS transistor M1. The PMOS transistor M1 and the NMOS transistor M2 are essentially used as CMOS inverters for converting the logic state of the input voltage V _IN and driving the gate terminals of the transistors M1 and M2. Therefore, when the input voltage V _{IN is} at a logic high, the PMOS transistor M1 is turned on and the NMOS transistor M2 is turned off. At the same time, when the input voltage V _{IN is} at a logic low, the PMOS transistor M1 is turned off and the NMOS transistor M2 is turned on. The NMOS transistor M2 is also controlled by a gate control signal V _G4 generated by the time controller 70. The input voltage V _IN and the gate control signal V _{G4 are} coupled to the NOR gate 72. Therefore, the gate control signal V _{G2 is} valid (logic high) only when the input voltage V _IN and the gate control signal V _G4 are at a logic low. Otherwise, the gate control signal V _G2 becomes invalid (logic low). The gate control signal V _{G4 is} generated from a fault detection indication signal, which will be described in detail below.

The hysteresis overvoltage detection circuit 80 receives the feedback voltage V _FB on the input node 78, which represents the collector-to-emitter voltage V _{CE of the} IGBT. In this embodiment, the voltage divider formed by the resistors R6 and R7 is coupled to the collector terminal (node 20) of the IGBT to decompose the collector-emitter voltage as the feedback voltage V _FB . The feedback voltage V _FB (node 24) is coupled to the hysteresis overvoltage detection circuit 80 through the input impedance Z6, and serves as an overvoltage monitoring signal OV_IN to detect the overvoltage condition. The input impedance Z6 is used as an analog filter for the feedback voltage and provides ESD protection for the NMOS transistor M5. In the embodiment of the present invention, the hysteresis overvoltage detection circuit 80 operates only during the IGBT off time. Therefore, the NMOS transistor M5 is coupled to the input node 79 to enable or disable the over-voltage monitoring signal OV_IN according to the input voltage V _IN . More precisely, the input voltage V _{IN is} coupled to a time controller 88. The time controller 88 receives the input voltage signal V _IN and generates an output signal OV_Enable as an input voltage for extending the on-time T1. The OV_Enable signal is a gate control signal V _G5 and is coupled to drive the gate terminal of the NMOS transistor M5. Therefore, when the input voltage effectively turns on the IGBT, the NMOS transistor M5 turns on. As the NMOS transistor M5 is turned on, the input node 79 is shorted to ground, thereby invalidating the overvoltage monitoring signal OV_IN. The time controller 88 extends the on-time of the input voltage signal, thereby masking the high-to-low transmission of the input voltage VIN from being affected by the detection operation. That is, after the falling edge of the input voltage V _IN , the NMOS transistor M5 remains on for a short time. In other words, after the input voltage V _IN fails, the over-voltage monitoring signal OV_IN becomes effective for a short time, so that the transit time is not affected by the detection operation. In this case, the hysteresis overvoltage detection circuit 80 is activated, and only monitors the collector-to-emitter voltage V _{CE of the} IGBT for a time when the IGBT is completely _turned off by the gate drive signal V _gctrl .

In some embodiments, a hysteresis loop is used to respond quickly to form a hysteresis overvoltage detection circuit 80, and a band gap reference voltage is used to form a high gain comparator. The hysteresis overvoltage detection circuit 80 can accurately detect the overvoltage condition by monitoring the feedback voltage.

At the lagging overvoltage detection circuit 80, the overvoltage monitoring signal OV_IN is compared with the overvoltage threshold voltage value to determine whether an overvoltage condition has occurred at the collector terminal of the IGBT. Specifically, the hysteresis overvoltage detection circuit includes a set voltage level and a reset voltage level for fault overvoltage detection, and the set voltage level is higher than the reset voltage level. The over-voltage monitoring signal OV_IN is compared with the set voltage level and the reset voltage level as a threshold voltage value. The lagging overvoltage detection circuit 80 generates a failure detection instruction signal OV_OUT (node 82). When the OV_ monitoring voltage OV_IN exceeds the set voltage level, the fault detection indication signal OV_OUT is valid. When the V_ monitoring voltage OV_IN falls below the reset voltage level, the fault detection indication signal becomes invalid.

The fault detection indication signal OV_OUT (node 82) is coupled to the level shifter 84 to adjust the voltage level of the indication signal. The level adjustment work detection instruction signal V _L (node 85) is coupled to the inverter 86 to generate an inverter instruction signal V _LB (node 87). The level adjustment work detection instruction signal V _L and the inverter instruction signal V _{LB are} coupled to drive a common gate driving circuit 66 and a protection gate driving circuit 68. In this embodiment, the fault detection instruction signal OV_OUT is an active low signal. That is, the fault detection indication signal OV_OUT is usually at a logic high level (failure), and when a fault overvoltage condition is detected, the fault detection indication signal OV_OUT is transmitted to a logic low level (effective).

The protection gate driving circuit 68 includes a PMOS transistor M3, which is connected in series with the NMOS transistor M4 between the positive power supply voltage V _dd (node 64) and the ground. The impedance Z3 is located at the drain terminal (node 76) of the PMOS transistor M3, and the impedance Z4 is located at the drain terminal (node 76) of the NMOS transistor M4. The common node 76 between the PMOS transistor M3 and the NMOS transistor M4 is to protect the output signal of the gate driving circuit. The protection gate driving circuit 68 generates an output signal at the node 76 as a gate driving signal V _gctrl and is coupled to the gate terminal (node 22) of the IGBT.

The fault detection instruction signal or indication signal generated by the lagging overvoltage detection circuit 80 is coupled to the common gate driving circuit 66 and the protection gate driving circuit 68, and remedial measures are initiated according to the detected overvoltage condition. First, the inverter fault detection instruction signal V _{LB is} coupled to the time controller 70. When it fails, the inverter fault detection indication signal V _{LB is} at a logic low level, and when it is effective, it is at a logic low level. The time controller 70 transmits the inverter failure detection instruction signal V _LB to the output terminal, but maintains the extended time T2. That is, according to the inverter fault detection instruction signal V _LB , the time controller 70 validates the time control signal V _G4 . When the inverter fault detection instruction signal V _LB fails, the time controller 70 disables the gate control signal V _G4 for a period of time. The specified delay time. The gate control signal _{VG4 is} coupled to the NOR gate 72, and its output drives the NMOS transistor M2 in the commonly used gate drive circuit 66, and also drives the NMOS transistor M4 in the protection gate drive circuit 68.

As described above, the hysteresis overvoltage detection circuit 80 can operate only during the time when the IGBT is turned off. In this case, the input voltage V _IN becomes invalid (logic low), the gate control signal V _{G2 is} at a logic high level, and the NMOS transistor M2 is driven to be fully turned on. After the NMOS transistor M2 is completely turned on and the PMOS transistor M1 is completely turned off, the gate terminal (node 22) of the IGBT is discharged to the ground, and is maintained at the ground level during the off time. According to the detected overvoltage condition, the inverter fault detection indication signal V _LB becomes effective (logic high), and the gate control signal V _G4 becomes effective (logic high). Therefore, the gate control signal V _{G2 is} coupled to drive the NMOS transistor M2 to a logic low level, and the NMOS transistor M2 is unavailable or disconnected. Therefore, the common gate driving circuit 66 is unavailable and no longer drives the IGBT. At the same time, the gate control signal V _G4 becomes effective and is also coupled to the gate terminal of the NMOS transistor M4 to turn on the NMOS transistor M4.

Secondly, fault detection indication signal V _L is coupled to a timing controller 71. When it fails, the fault detection indication signal V _{L is} at a logic high level, and when it is effective, it is at a logic low level. The time controller 71 transmits the failure detection instruction signal V _L to the output terminal through a duration control. That is, according to the fault detection indication signal V _L into effect, the time controller 71 is active (logic low) time of the control signal V _G3, according to the fault detection indication signal V _L failure or fixed time period T3 expires, which occur in the first of which, the time The controller 71 has a dead time control signal V _G3 . Therefore, the maximum time period during which the gate control signal V _G3 will take effect is fixed, which is also called a one-time duration. The gate control signal V _G3 will remain in effect for a duration or less. The gate control signal V _{G3 is} coupled to drive the gate terminal of the PMOS transistor M3 in the protection gate driving circuit 68.

When an overvoltage condition is detected, the fault detection indication signal V _L becomes active (logic low), and the gate control signal V _G3 becomes active (logic low). The gate control signal V _{G3 is} coupled to the gate terminal of the PMOS transistor M3, and the PMOS transistor M3 is turned on according to the detected overvoltage condition. The PMOS transistor M3 remains on until the fault detection indication signal V _L fails or one duration T3 expires.

In actual operation, after the fault detection instruction signal OV_OUT becomes effective, the NMOS transistor M2 in the common gate driving circuit 66 is turned off. At the same time, the protection gate driving circuit 68 turns on the PMOS transistor M3 and the NMOS transistor M4. As the PMOS transistor M3 and the NMOS transistor M4 are turned on, the impedance Z3 and the impedance Z4 form a voltage divider between the positive power supply voltage and the ground terminal. The voltage dividers of Z3 and Z4 generate output signals, which are used as gate driving signals at the output node 76 to divide the voltage of the positive power supply voltage V _dd . Specifically, the voltage value embedded in the gate driving signal is a function of the impedances Z3 and Z4, and is expressed as (Z4 / (Z3 + Z4)) * V _dd . Therefore, the protection gate driving circuit 68 generates an output signal under the clamped gate voltage value, and serves as the gate driving signal V _gctrl to drive the gate terminal of the IGBT. Therefore, the IGBT is turned on under an overvoltage condition, and the excess charge at the collector terminal (node 20) is consumed. It must be noted that the gates of the IGBT are driven by the voltage dividers of Z3 and Z4, and the gates of the IGBT are gradually turned on to realize the soft turn-on control. In this case, the protection gate driving circuit 68 turns on the IGBT in the protection mode and discharges the voltage overshoot.

In some embodiments, the ratio of the impedances Z3 and Z4 is 0.55. The clamped gate voltage used by the IGBT is approximately half the voltage source voltage V _dd . Therefore, the protection circuit can quickly activate the protection gate driving circuit 68 to embed the gate voltage of the IGBT. In one example, the power supply overshoot peak of the AC input terminal can be taken as 15 μs in order to reach the collector terminal of the IGBT in the quasi-resonant inverter circuit. However, the protection circuit according to the present invention can embed the gate voltage of the IGBT for a long time before the peak value of 500ns-power supply overshoot reaches the collector terminal. In this case, when the peak overshoot voltage reaches the collector terminal, the IGBT can safely consume the power overshoot without damaging the IGBT, and the IGBT is turned on.

The hysteresis overvoltage detection circuit 80 continues to monitor the feedback voltage F _VB . When the collector-to-emitter voltage V _CE (node 20) falls below the reset voltage level, the over-voltage detection circuit 80 fails and detects the failure signal OV_OUT. Then, the protection gate driving circuit 68 can be disabled, and the IGBT is turned off in the protection mode. In actual operation, when the fault detection indication signal V _L fails (logic high) or when a fixed period of time expires, which one is pressed shorter, the time controller 71 fails the gate control signal V _{G3 of the} PMOS transistor M3. As a result, the clamped gate voltage at the output node 76 is released. At the same time, after the inverter fault detection indication signal V _{LB is} deactivated (logic low), the time controller 70 fails the gate control signal V _G4 for a lagging time period T2. After the PMOS transistor M3 is turned off, the NMOS transistor M4 remains turned on, so that the gate terminal (node 22) of the IGBT is discharged and the IGBT is turned off. After the delay period T2, the NMOS transistor M4 is turned off, and the NMOS transistor M2 in the commonly used gate drive circuit 34 is turned back on. Before the IGBT returns to normal operation, the IGBT gate terminal is kept grounded.

In the embodiment of the present invention, the protection circuit according to the present invention generates a clamped gate voltage that can be accurately controlled for the gate driving signal (node 22), thereby avoiding the voltage overshooting that is common in the traditional zener diode clamping method. Rush problem. In addition, the clamped gate voltage can be precisely controlled when the temperature and the manufacturing process change. In some embodiments, the impedances Z3 and Z4 are made using polycrystalline silicon resistors.

FIG. 4 shows a timing diagram of the operation of the control circuit shown in FIG. 3 in some examples. Referring to FIG. 4, the input signal V _IN (curve 102) is a PWM signal, and the IGBT is turned on and off through the inductor coil, and the current is alternately conducted. The time controller 88 generates a gate control signal OV_Enable (104), and drives the NMOS transistor M5 to enable or disable overvoltage monitoring. Specifically, the OV_Enable signal is prolonged for a period of time T1 and exceeds the failure of the input signal V _IN to mask the high-to-low transients of the input signal from being affected by overvoltage monitoring. During normal operation, the gate voltage V _gctrl (curve 110) of the IGBT is switched between the ground terminal and the voltage source voltage Vdd to turn the IGBT on and off. At the same time, the collector current i _C (curve 108) increases linearly during the IGBT on-time and then drops to zero during the IGBT off-time. During normal operation, the gate control signals (curves 112 and 114) of transistors M1 and M2 have a logic low level during the IGBT on-time and a logic high level during the IGBT off-time. During normal operation, the gate control signal (curve 116) of transistor M3 is at a logic high level, and the gate control signal (curve 118) of transistor M4 is at a logic low level to disable the protection gate drive circuit .

During the on-time of the IGBT, the collector-emitter voltage V _CE (curve 106) is driven to the collector-emitter saturation voltage V _CE-SAT . However, when the IGBT is turned off, the collector voltage can increase to a large voltage value, such as 600V. IGBTs usually have a rated voltage of 1.7kV. When the IGBT is operating normally, it can withstand the normal collector voltage overshoot.

The hysteresis overvoltage detection circuit monitors the collector voltage V _{CE of the} IGBT when the IGBT is turned off and after the delay time T1 that masks the input voltage V _{IN from} turning on to turning off transients. At time t1, a specific power overshoot event causes the collector voltage V _{CE to} exceed the set voltage level of the lagging overvoltage detection circuit. The hysteresis overvoltage detection circuit takes effect the failure detection indication signal. Within a very short time, such as time t1, remedial measures are initiated. The gate control signal of transistor M2 is general (logic low), and transistor M2 is turned off. The gate control signal of transistor M3 is enabled (logic low), and transistor M3 is turned on, while the gate control signal of transistor M4 is enabled (logic high), and transistor M4 is turned on. Because transistors M3 and M4 are both on, the gate voltage of the IGBT rises to the clamped gate voltage value defined by the Z3 / Z4 voltage divider. By clamping the gate voltage, the IGBT is turned on, the collector current i _{C is} conducted, and power overshoot is consumed. As a result, the collector voltage V _{CE is} reduced.

At time t2, the collector voltage V _CE falls below the reset voltage level of the hysteresis overvoltage detection circuit. In one example, the reset voltage level corresponds to a collector voltage of about 1.2 kV. Hysteresis overvoltage detection circuit failure detection signal, transistor M3 fails (logic high). Transistor M4 remains on for a period of time T2 to discharge the gate voltage of the IGBT. At time t3 and time T2 expires, transistor M4 is turned off, transistor M2 is turned on, and normal operation resumes.

Then, the IGBT is turned on again for normal operation. During the next off-time, the IGBT may experience additional power overshoot events. In this case, transistors M3 and M4 are turned on again to consume the overshoot voltage. In this example, an overshoot voltage on the IGBT collector may cause the collector voltage to switch between the set voltage level and the reset voltage level multiple times during a single off-time. Each time the collector voltage exceeds the set voltage level, the protective gate driving circuit is enabled, and each time the collector voltage falls below the reset voltage level, the protective gate driving circuit is disabled. In this case, the protective gate drive circuit can be enabled multiple times in a single off-time to overshoot with discharge power.

Figure 5 shows the collector voltage and collector current of an IGBT when a power overshoot event occurs in some examples. First, referring to FIG. 2, the purpose of the protection circuit is to consume the energy introduced in the induction coil Lr in the IGBT and embed the capacitor voltage Cr so that the collector voltage V _CE does not exceed the rated voltage of the IGBT. Returning now to Fig. 5, the collector voltage V _CE (curve 120) and the corresponding collector current i _C (curve 122) of the IGBT are shown with corresponding setting and reset voltage levels for hysteresis overvoltage Detection circuit. Note that the setting and reset voltage levels shown in FIG. 5 are the voltage levels used in the hysteresis overvoltage detection circuit. The hysteresis overvoltage detection circuit receives the falling collector voltage for detection, so the setting and reset voltage levels used in the contact circuit are corresponding falling voltage levels.

At time t1, a power overshoot occurs at the collector terminal of the IGBT, and the collector voltage increases to a set voltage level. Activate the protection gate drive circuit and turn on the IGBT at the clamped voltage level. The collector current i _C starts to increase gradually, and the clamped gate voltage is used for the IGBT. The current direction of the coil current i _Lr changes direction. The coil current i _Lr no longer circulates between the induction coil Lr and the capacitor Cr, but flows to the IGBT and is consumed by the IGBT to ground. The clamped collector voltage V _CE does not increase further. At time t2, when the current i _C is equal to the current i _Lr , the voltage V _CE starts to drop through the discharge of the capacitor Cr, and the slope of the voltage drop is determined by the collector current i _C and the capacitance of the capacitor Cr. Once the voltage V _CE reaches the reset level at t3, the protective gate driving circuit is disabled, and the collector current i _C is turned off by the soft gate control to achieve safe shutdown. The current falling time interval (t3-t4) causes the voltage V _CE to fall below the reset level. After the protection interval is completed at time t4, the IGBT returns to normal operation.

FIG. 6 shows a flowchart of a method for providing overvoltage or short-circuit protection for a power switching device in a quasi-resonant inverter circuit in an embodiment of the present invention. Referring to FIG. 6, the over-voltage protection method 200 monitors a feedback voltage, and the feedback voltage represents a voltage on the power switch during a period when the power switch (202) is turned off. The feedback voltage is compared with the overvoltage setting level OV_Set (204). When the feedback voltage is lower than the OV_Set level, the method continues to monitor the feedback voltage indicating the voltage on the power switch. On the other hand, when the feedback voltage is greater than the OV_Set level, the method 200 disables the common gate driving signal (206). For example, the method 200 turns off the NMOS transistor M2 in a common gate driving circuit, and the NMOS transistor drives the power switch in an off state. The method 200 then enables the protection gate drive signal (208). For example, the PMOS transistor M3 and the NMOS transistor M4 in the protection gate driving circuit generate a clamping gate driving signal with a clamping gate voltage value (210). The clamp gate drive signal is used to turn on the power switch. After the clamp gate driving signal is turned on, the method 200 monitors the feedback voltage to determine whether the feedback voltage has fallen below the reset voltage level OV_Reset (212). The reset voltage level OV_Reset is lower than the set voltage level OV_Set. When the feedback voltage is lower than the reset voltage level, the method 200 disables the clamp gate driving signal and discharges the power switch gate terminal (214). The method 200 enables a common gate driving circuit (216), and the method returns a monitoring feedback voltage, and the feedback voltage represents a voltage on the power switch within the time when the power switch (202) is turned off.

In some embodiments, in parallel with monitoring the feedback voltage to determine whether the feedback voltage has dropped below the reset voltage level OV_Reset (212), the method 200 also monitors the duration of the power switch on using the clamped gate drive signal. More specifically, the method 200 monitors the on-time of the power switch to determine whether the on-time is reached or the maximum duration is exceeded (220). When the maximum time expires, which is also referred to as a duration, the method 200 continues to turn off the clamp gate drive signal (214), even if the feedback voltage has fallen below the reset voltage level OV_Reset. After the common gate driving circuit (216) is enabled, the method 200 continues, and a return monitoring is performed to indicate the feedback voltage of the voltage on the power switch when the power switch (202) is turned off.

Although the embodiments have been described in detail in the above for clarity, the present invention is not limited to the above details. There are many alternatives for implementing the invention. The examples in the text are only used for explanation and are not used for limitation.

(10) ‧‧‧Quasi-Resonant Inverter

(12) ‧‧‧AC input voltage

(14) ‧‧‧Surge suppressor

(16) ‧‧‧Bridge Rectifier

(18) ‧‧‧node

(20) ‧‧‧node

(22) ‧‧‧node

(24) ‧‧‧node

(30) ‧‧‧Control circuit

(32) ‧‧‧node

(34) ‧‧‧Normal gate drive circuit

(36) ‧‧‧Gate Logic Circuit

(38) ‧‧‧node

(40) ‧‧‧Protection gate drive circuit

(42) ‧‧‧Clock Controller

(44) ‧‧‧Gate control circuit

(46) ‧‧‧Time controller

(48) ‧‧‧Gate control circuit

(50) ‧‧‧Voltage detection circuit

(52) ‧‧‧node

(54) ‧‧‧Input node

(60) ‧‧‧Control circuit

(62) ‧‧‧node

(64) ‧‧‧node

(66) ‧‧‧Common gate driving circuit

(68) ‧‧‧Protection gate drive circuit

(70) ‧‧‧Time controller

(71) ‧‧‧Time controller

(72) ‧‧‧NOR Gate

(74) ‧‧‧Inverter

(76) ‧‧‧node

(78) ‧‧‧Input node

(79) ‧‧‧Input node

(80) ‧‧‧ Hysteresis overvoltage detection circuit

(82) ‧‧‧node

(84) ‧‧‧Level shifter

(86) ‧‧‧Inverter

(87) ‧‧‧node

(88) ‧‧‧Time controller

Figure 1 shows a circuit diagram of a single-switch quasi-resonant inverter for induction heating in some examples. FIG. 2 shows a structural diagram of a controller circuit including a protection circuit in the embodiment of the present invention. The coupling protection circuit is used to drive a power switch in a single-switch quasi-resonant inverter with induction heating. FIG. 3 is a circuit diagram showing a controller circuit structure shown in FIG. 2 in an embodiment of the present invention. FIG. 4 shows a timing diagram of the operation of the controller circuit shown in FIG. 3 in some examples. Figure 5 shows the IGBT controller voltage and controller current during power surges in some examples. FIG. 6 shows a flowchart of a method for providing overvoltage or overcurrent protection for a power switching device in a quasi-resonant inverter circuit according to an embodiment of the present invention.

Claims (15)

A control circuit for generating a gate driving signal on an output node to drive a gate terminal of a power switch. The gate terminal controls the current flow between the first and second power terminals of the power switch. The control circuit includes: The first gate driving circuit receives the input control signal and generates a first output signal. As the gate driving signal, the gate terminal of the driving power switch is completely turned on and off according to the input control signal. The first output signal has a first A gate voltage value, the gate terminal of the driving power switch is fully connected to the power switch; a protection circuit is configured to receive the first voltage at the first power terminal of the power switch to generate a fault detection indication signal, and according to the first voltage exceeds a predefined Voltage level, protection circuit effective fault detection indication signal; a second gate drive circuit is configured to receive the fault detection indication signal and generate a second output signal as a gate drive signal, and drive the gate of the power switch according to the fault detection indication signal Extreme, the second gate drive circuit includes a resistor coupled to the output node The voltage dividing circuit generates a second output signal with a slow effective transient. The peak voltage value is clamped at the second gate voltage value. The second gate voltage value is greater than the threshold voltage of the power switching device and smaller than the first gate electrode. Voltage value; wherein according to the effective fault detection instruction signal, the second gate driving circuit takes effect on the second output signal, and at the second gate voltage value, the power switch is turned on for a predefined period of time. The control circuit according to item 1 of the patent application scope, wherein the protection circuit includes a hysteresis overvoltage detection circuit having a set voltage level and a reset voltage level, and the set voltage level is higher than the reset voltage level. When the voltage is at or higher than the set voltage level, the hysteresis overvoltage detection circuit takes effect on the failure detection indication signal, and according to the first voltage at or below the reset voltage level, the failure detection indication signal fails. The control circuit according to item 2 of the scope of patent application, wherein according to the lag overvoltage detection circuit, the fault detection instruction signal becomes effective, and the second gate driving circuit becomes effective the second output signal after the first time period. The control circuit according to item 1 of the scope of patent application, wherein the second gate driving circuit takes effect on the second output signal, and turns on the second according to a shorter time period and a predefined fixed time period of the effective fault detection indication signal Power switch at gate voltage. The control circuit according to item 1 of the scope of patent application, wherein according to the effective input control signal, the protection circuit is disabled, the power switch is turned on, and after the input control signal fails, the protection circuit is enabled for a second period of time to open switch. The control circuit according to item 1 of the scope of patent application, wherein the first gate driving circuit is disabled according to a valid fault detection instruction signal. The control circuit according to item 1 of the scope of patent application, wherein: the first gate driving circuit includes a first transistor, a first impedance, a second impedance, and a second circuit connected in series between a positive voltage source voltage and a ground voltage. The common node between the crystal, the first impedance, and the second impedance serves as an output node; and the second gate driving circuit includes a third transistor, a third impedance, a fourth impedance, and a series connection between the positive voltage source voltage and the ground voltage The common node between the fourth transistor, the third impedance, and the fourth impedance serves as an output node; wherein the first gate driving circuit turns on the first transistor, disconnects the second transistor, and takes effect on the first output signal. Turn on the power switch, and the first gate drive circuit turns off the first transistor, turns on the second transistor, takes effect on the first output signal, and completely turns off the power switch; and according to the effective fault detection instruction signal, the second The gate driving circuit turns on the third transistor and the fourth transistor, activates the second output signal at the second gate voltage value, and turns on the power switch. The control circuit according to item 7 of the scope of patent application, wherein the second output signal has a slow effective transient, so according to the third transistor and the fourth transistor being turned on, the third impedance and the fourth impedance constitute an impedance analysis. Press. The control circuit according to item 7 of the scope of the patent application, wherein the second output signal is clamped at the second gate voltage value, so according to the third impedance and the fourth impedance after the third transistor and the fourth transistor are turned on, An impedance voltage divider is formed, and the second gate voltage value divides the voltage of the positive voltage source voltage as a function of the third impedance and the fourth impedance. The control circuit according to item 7 of the scope of patent application, wherein the first gate driving circuit turns off the second transistor, and the second gate driving circuit turns on the third transistor and the fourth according to the effective fault detection instruction signal. Transistor. The control circuit according to item 10 of the scope of patent application, wherein the second gate driving circuit turns off the third transistor and the fourth transistor, and the third transistor is turned off according to the failed fault detection instruction signal or the fixed time period expires. After being turned on, the fourth transistor is turned off for a third period of time. The control circuit according to item 11 of the scope of patent application, wherein after the fourth transistor is turned off, the first gate driving circuit turns on the second transistor, drives the first output signal to a voltage level, and keeps the power switch off. open. The control circuit according to item 1 of the scope of patent application, wherein the power switch is composed of an insulated gate bipolar transistor (IGBT) device. A method for generating a gate driving signal for driving a gate terminal of a power switch. The gate terminal controls a current flow between first and second power terminals of the power switch. The method includes: monitoring a feedback voltage, and the feedback voltage indicates the power switch The voltage between the first and second power terminals of the power switch during the off-time; It is determined that the feedback voltage exceeds the first voltage level; According to the determination, the common gate that drives the gate of the power switch is disabled during the off-time Drive signal; enable protection gate drive signal according to the determination; generate clamp gate drive signal with clamp gate drive voltage value and use the clamp gate drive signal to turn on the power switch; monitor feedback voltage to determine feedback Whether the voltage drops below the second voltage level and the second voltage level is lower than the first voltage level; according to the determination that the feedback voltage has fallen below the second voltage level, the clamp gate driving signal is disabled, and the power switch is discharged The common gate driving signal is enabled; and continue to monitor the feedback voltage, the feedback voltage indicates the off time of the power switch, Voltage between the first terminal and the second power source switch. The control circuit according to item 14 of the scope of patent application, further includes: determining that the clamp gate driving signal has been enabled for the first time period; according to the determined condition, deactivating the clamp gate driving signal and discharging the gate terminal of the power switch.