TWI705663B - Controller circuit and method for generating gate drive signal thereof - Google Patents

Abstract

A controller for driving a power switch incorporates a hard turn-on disable circuit to prevent the power switch from turning on when the power switch is sustaining a high voltage value. The hard turn-on disable circuit includes a hard turn-on detection circuit and a protection logic circuit. The hard turn-on disable circuit is configured to block or to pass the system input signal to the normal gate drive circuit of the power switch depending on the detection indicator signal. In particular, the protection logic circuit blocks the system input signal V_IN in response to a high voltage detection so that the power switch ignores the system input signal V_IN, which may be erroneous, and the power switch is prevented from undesirable hard switching.

Description

Controller circuit and method for generating gate drive signal

The present invention relates to the field of switching power supply components, and particularly relates to hard-switching disablement for switching power supply components.

Induction heating has been widely used in domestic industry and medical fields. Induction heating refers to the technology of heating conductive objects (such as metals) through electromagnetic induction. This technology generates current in a closed circuit (object) through the fluctuation of current in a circuit physically close to the object. For example, an induction cooker includes a resonant circuit driven by alternating current, which induces an alternating magnetic field at the induction coil. The AC magnetic field at the induction coil generates an induced current in the metal cooking pot placed near the induction coil. The electric current induced in the resistance metal cooking pot generates heat, which in turn heats the food in the cooking pot.

A commonly used induction heating topology is the single-switch quasi-resonant inverter topology, which includes a single power switch and a single resonant capacitor to provide a variable resonant current for the induction coil. Due to the high power possibilities and high switching frequency operation of IGBTs, a separate switching quasi-resonant inverter usually uses insulated gate bipolar transistors (IGBTs) as power switching elements.

Overvoltage conditions, such as power surges, are a serious problem for single-switch quasi-resonant inverter circuits. Especially when the voltage exceeds the rated voltage of the power switching element, the power switching element in the quasi-resonant inverter circuit may fail or be permanently damaged. For example, when lightning occurs, extremely high surge voltages may be generated in the AC input line. When the surge voltage exceeds the power switching element During the breakdown voltage, if remedial measures are not taken within a very short time (on the order of milliseconds) after the power surge occurs, then the power switching element is irreparably damaged.

In addition, when the single-switch quasi-resonant inverter works normally, the power switch is turned on and off at a specified switching frequency (for example, 30 kHz). When the power switch is turned off, the voltage on the power switch can reach a very high peak voltage, such as 1kV. When the voltage on the switching element is still at a high voltage value, if the power switch is accidentally turned on again, the power switch will enter hard switching, which will adversely affect the efficiency and reliability of the power switch.

The present invention provides a hard switch disabling for switching power supply components. The protection logic circuit blocks system input signals based on high voltage detection, so that the power switch ignores possibly abnormal system input signals and prevents unnecessary hard switching of the power switch.

In order to achieve the above objective, the present invention is achieved through the following technical solutions:

A controller circuit for generating a gate drive signal on the output node to drive the gate terminal of the power switch, wherein the gate terminal controls the current flowing between the first power terminal and the second power terminal of the power switch. Its characteristics are , The controller circuit includes: a first gate drive circuit for receiving an input control signal and generating a first output signal as a gate drive signal to drive the gate terminal of the power switch, and turn on and Turn off the power switch, the first output signal has the first gate voltage value, drive the gate terminal of the power switch, turn on the power switch; and a hard-on disable circuit for generating input control based on the system input signal and the first voltage The first voltage represents the voltage between the first power terminal and the second power terminal of the power switch. The system input signal determines the on time and off time of the power switch. The hard-on-disable circuit generates a high-voltage indicator signal. When the first voltage exceeds the first threshold, the high-voltage indication signal becomes effective. Otherwise, the high-voltage indication signal becomes invalid. Effective high-voltage indication signal, hard turn on the disable circuit to generate the input control signal. The input control signal has the first logic state to prevent the system input signal from being provided to the first gate drive circuit, and according to the failed high-voltage indication signal, the hard-on disable The circuit generates an input control signal to mirror the system input signal to drive the first gate drive circuit.

The hard-on disable circuit includes a hysteresis detection circuit, the hysteresis detection circuit has a set voltage potential and a reset voltage potential, the set voltage potential is higher than the reset voltage potential, and the first voltage is at the set voltage potential Or when the voltage level is higher than the set voltage level, the hysteresis detection circuit activates the high voltage indication signal, and when the first voltage is at the reset voltage level or lower than the reset voltage level, the hysteresis detection circuit fails the high voltage indication signal.

The hard-on disable circuit further includes a D-flip-flop. The D-flip-flop has a data input terminal coupled to the forward voltage source voltage, a clock input terminal coupled to the system input signal, and a The set terminal is coupled to the signal representing the high-voltage indication signal and generates an output signal, wherein the D-flip-flop is placed in the reset mode according to the effective high-voltage indication signal.

The hard-on disable circuit further includes a logic AND gate for receiving the system input signal and output signal of the D-flip-flop, and the logic AND gate generates an input control signal.

The first gate drive circuit includes a first transistor, a first impedance, a second impedance, and a second transistor, which are connected in series between the forward voltage source voltage and the ground voltage, and the first impedance and the second impedance are common The node is the output node, where the first gate drive circuit turns on the first transistor and turns off the second transistor to validate the first output signal, turns on the power switch, and the first gate drive circuit turns off the first transistor, and Turn on the second transistor to disable the first output signal and turn off the power switch; and according to the effective high voltage indication signal, the first gate drive circuit turns off the first transistor and turns on the second transistor to disable the first Output signal, turn off the power switch.

The first voltage represents the voltage between the first power terminal and the second power terminal of the power switch during the off time of the power switch.

The power switch includes an insulated gate bipolar transistor (IGBT) element.

A method of generating a gate drive signal for driving the gate terminal of a power switch, wherein the gate terminal controls the current flowing between the first power terminal and the second power terminal of the power switch. The characteristic is that the method includes: monitoring display The feedback voltage of the voltage between the first power terminal and the second power terminal of the power switch; provide a high-voltage indication signal; determine that the feedback voltage exceeds the first threshold; according to the determined feedback voltage exceeds the first threshold, the high-voltage indication signal is activated; The feedback voltage is lower than the first threshold; according to the determined feedback voltage is lower than the first threshold, the high voltage indication signal is invalid; according to the failed high voltage indication signal, the system input signal is provided, and the power switch is turned on and off, and the system input signal is determined The on time and off time of the power switch; and according to the effective high-voltage indication signal, to prevent the system input signal from entering the power switch, regardless of the state of the system input signal, the power switch is turned off.

The determining that the feedback voltage exceeds the first threshold potential includes determining that the feedback voltage exceeds the set voltage potential; and determining that the feedback voltage is lower than the first threshold potential includes determining that the feedback voltage is lower than the reset voltage potential and the set voltage potential is higher than the reset voltage potential.

The method further includes: after the high voltage indication signal is activated, when the feedback voltage drops below the reset voltage potential, the high voltage indication signal is invalidated.

The monitoring means the feedback voltage of the voltage between the first power terminal and the second power terminal of the power switch, including monitoring the voltage between the first power terminal and the second power terminal of the power switch during the off time of the power switch The feedback voltage.

A controller circuit for generating a gate drive signal on an output node to drive a gate terminal of a power switch. The gate terminal controls the electricity flowing between the first power terminal and the second power terminal of the power switch Its characteristic is that the controller circuit includes: a first gate drive circuit for receiving an input control signal and generating a first output signal as a gate drive signal to drive the gate terminal of the power switch and control it according to the input Signal, turn on and off the power switch, the first output signal has the first gate voltage value, drives the gate terminal of the power switch, and turns on the power switch; the first protection circuit is used to generate input according to the system input signal and the feedback voltage Control signal, the feedback voltage represents the voltage between the first power terminal and the second power terminal of the power switch. The system input signal determines the on time and off time of the power switch. When the feedback voltage exceeds the first threshold potential, the first The protection circuit generates an input control signal to prevent the system input signal from being provided to the first gate drive circuit; and a second protection circuit for receiving the feedback voltage and generating a fault detection indication signal, according to when the feedback voltage exceeds the second threshold potential, the first The second protection circuit activates the fault detection indication signal. The second threshold potential is higher than the first threshold potential. The second protection circuit is configured to generate a second output signal as a gate drive signal. According to the valid fault detection indication signal, the second The power switch is turned on for a predefined time under the gate voltage value.

According to the feedback voltage being lower than the first threshold potential, the first protection circuit generates an input control signal mirroring system input signal to drive the first gate driving circuit.

A method of generating a gate drive signal for driving the gate terminal of a power switch, wherein the gate terminal controls the current flowing between the first power terminal and the second power terminal of the power switch. The feature is that the method includes: monitoring feedback Voltage, feedback voltage represents the voltage between the first power terminal and the second power terminal of the power switch; determine that the feedback voltage exceeds the first threshold potential; according to the determination result, prevent the system input signal from entering the power switch, the system input signal determines the power switch On time and off time, regardless of the state of the system input signal, turn off the power switch; determine that the feedback voltage exceeds the second threshold potential, and the second threshold potential is higher than the first threshold potential; according to the determination result, a clamp is generated brake The clamped gate driving signal of the pole driving voltage value is used, and the clamped gate driving signal is used to turn on the power switch; and the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch is continuously monitored.

The method further includes: determining that the feedback voltage is lower than the first threshold potential; and according to the determination result, providing a system input signal to drive the power switch to turn on and off.

10: Quasi-resonant inverter

102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174: Curve

12: AC input voltage

14: Surge suppressor

16: Bridge rectifier

18, 20, 22, 24, 32, 38, 52, 62, 64, 76, 79, 82, 85, 87, 96: nodes

200, 250, 300: method

202, 204, 206, 208, 210, 212, 214, 216, 220, 252, 254, 256, 258, 260, 302, 304, 306, 308, 310, 312, 314: steps

30, 60: control circuit

31, 61: Controller circuit

34, 66: Standard gate drive circuit

36: Gate logic circuit

40, 68: Protection gate drive circuit

42, 46, 70, 71, 88: time controller

44, 48: Gate control circuit

50: Overvoltage detection circuit

54: Input node

55, 90: Hard-on disable circuit

72: NOR gate

74, 86, 93: inverter

80: Hysteresis overvoltage detection circuit

84: Potential shifter

92: Hard-on detection circuit

94: D-Flip Flop

95: AND gate

Figure 1 shows a circuit diagram of a single-switch quasi-resonant inverter used for induction heating in some examples.

Figure 2 shows a structural diagram of a controller circuit including a protection circuit in an embodiment of the present invention. The coupled protection circuit drives the power switch in the single-switch quasi-resonant inverter for induction heating.

Fig. 3 shows a circuit diagram of the circuit configuration of the controller shown in Fig. 2 in the embodiment of the present invention.

Figure 4 shows a timing diagram of the controller circuit shown in Figure 3 in some examples.

Figure 5 shows the collector voltage and collector current of the IGBT when a power surge occurs in some examples.

Figure 6 shows a flow chart of a method for providing over-voltage or short-circuit protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention.

Figure 7 shows the configuration diagram of the controller circuit configured with a two-level protection system in an embodiment of the present invention, including coupling two protection systems to drive the power switch in a single-switch quasi-resonant inverter for induction heating.

Fig. 8 shows a circuit diagram of the circuit configuration of the controller shown in Fig. 7 in the embodiment of the present invention.

Figure 9 shows a timing diagram of the operation of the controller circuit shown in Figure 8 in some examples.

Figure 10 shows the collector voltage and collector current of the IGBT when a power surge occurs in some examples.

Figure 11 shows a flowchart of a method for providing hard-on failure protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention.

Figure 12 shows a flow chart of a method for providing two-level protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention.

The invention can be implemented in various ways, including as a manufacturing process; a component; a system; and/or a material composition. In this specification, these implementation modes or any other mode that the present invention may adopt may be referred to as technologies. Generally, the order of the process steps can be changed within the scope of the present invention.

The detailed description and drawings of one or more embodiments of the present invention explain the principle of the present invention. Although the present invention is proposed together with these embodiments, the scope of the present invention is not limited to any embodiment. The scope of the present invention is limited only by the scope of the patent application, and the present invention includes a variety of optional solutions, modifications and equivalent solutions. In the following description, various specific details are proposed for a comprehensive understanding of the present invention. These details are used for explanation, and the present invention can be implemented according to the scope of the patent application without some or all of the details. For the sake of simplicity, technical materials well-known in the relevant technical fields of the present invention are not described in detail, so as to avoid unnecessary confusion of the present invention.

In the embodiment of the present invention, the controller for driving the power switch introduces a protection circuit to protect the power switch from faults such as overvoltage or power surge. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is used to detect the voltage on the power switch and issue a fault detection indication signal. The protective gate drive circuit is used to generate the gate drive signal, and the power switch is turned on according to the detected fault condition. In particular, the protective gate drive circuit generates a gate drive signal. The gate drive signal has a slow assertion transition and is clamped at a specified gate voltage value. In this case, when an overvoltage occurs, the protection circuit is configured to effectively clamp the gate pole of the power switch, as well as the safe handling of the power switch.

In some embodiments, the protective gate drive circuit drives the power switch to turn on for a predefined period of time, and consumes a portion of energy when a fault overvoltage occurs on the power switch. In other embodiments, the fault detection circuit includes a hysteresis overvoltage detection circuit that uses the set voltage potential and the reset voltage potential for fault detection, and the set voltage potential is higher than the reset voltage potential. When the voltage on the power switch exceeds the set voltage potential, the fault detection indication signal becomes effective. When the voltage on the power switch is lower than the reset voltage potential, the fault detection indication signal becomes invalid. In some embodiments, the protective gate drive circuit activates the gate drive signal, and turns on the power switch under the clamped gate voltage according to the effective fault detection indication signal. The protective gate drive circuit uses the clamped gate drive signal until the fault detection indicates that the signal fails or a shorter predefined fixed time period.

In the embodiment of the present invention, the power switch introduced in the single-switch quasi-resonant inverter is driven by the controller for induction heating. Due to the high power performance and high switching frequency operation of IGBTs, single-switch quasi-resonant inverters usually use insulated gate bipolar transistors (IGBTs) as power switching elements. The protection circuit of the present invention is equipped with an active gate drive protection system to protect the power switch, and can be used to protect the IGBT in the quasi-resonant inverter circuit for induction heating.

The protection circuit of the present invention achieves advantages over the traditional protection system of power switching elements or IGBTs. In particular, the protection circuit configuration of the present invention has an effective clamp for soft gate drive control to protect the power switch element when an overvoltage occurs. When an overvoltage occurs, the power switching element is turned on and the gate voltage is clamped to protect the gate terminal of the power switching element from the overvoltage. At the same time, the power switching element is continuously turned on one or more times to consume excessive voltage and current. The soft gate drive control includes soft turn-on and soft-off, which suppresses the oscillation caused by the voltage transient on the power switching element when the switch is turned on and off. The protection circuit of the present invention realizes effective over-voltage protection of power switch elements or IGBTs.

In addition, in the embodiment of the present invention, the controller for driving the power switch introduces a hard-on disable circuit to prevent the power switch from turning on when the power switch is continuously at a high voltage value. The hard-on disable circuit includes a hard-on protection circuit and a protection logic circuit. Configure hard-on contact circuit, detect the voltage on the power switch, and generate a detection indicator signal. According to the state of the detection indicator signal, it indicates the high voltage on the power switch. Configure the protection logic circuit to block the system input signal or transmit to the power switch. Standard gate drive circuit. In particular, the protection logic circuit blocks the system input signal V _IN based on high voltage detection, so that the power switch ignores the system input signal V _IN . V _IN may be wrong, preventing the power switch from turning on and the power switch is driven to a high voltage potential . In this case, the hard-on disable circuit is operable to avoid excessive hard-on switching of the power switch, which can occur under abnormal system conditions, such as AC power expansion and failure control signals. In the embodiment of the present invention, a controller is used to drive a power switch in a single-switch quasi-resonant inverter for induction heating.

In addition, in the embodiment of the present invention, the controller for driving the power switch introduces a two-level protection circuit, and configures two protection systems for the power switch. In some embodiments, the protection circuit is configured with the first level of protection to prevent the power switch from being hard-switched or hard-on due to the false triggering of the system input signal. The protection circuit is equipped with secondary protection to protect the power switch in the event of overvoltage such as lightning or power surge. Especially, the secondary protection is equipped with soft start and effective clamping of the gate voltage of the power switch to prevent the power switch from exceeding its dynamic breakdown voltage and keep the power switch in a safe working area. In this way, the protection circuit enhances the immunity, efficiency and reliability of the power switch during operation. In the embodiment of the present invention, the power switch introduced in the single-switch quasi-resonant inverter is driven by the controller for induction heating.

Figure 1 shows a circuit diagram of a single-switch quasi-resonant inverter for induction heating in some examples. Referring to Figure 1, the single-switch quasi-resonant inverter 10 includes a good surge suppressor 14, a bridge rectifier 16, a filter circuit, a resonant tank, and a power switching element M0 (also called a power switch). The quasi-resonant inverter 10 receives an AC input voltage 12, and the AC input voltage 12 is coupled to a surge suppressor 14. The bridge rectifier 16 is also called a diode bridge. It converts the AC input voltage 12 into a DC voltage and then filters it through a filter circuit. The filter circuit includes an input capacitor C _i , a filter inductor L _f , a filter capacitor C _f and A resistor R _s . The filtered DC voltage V _cf (node 18) is used for the resonance circuit, which is composed of an inductance coil Lr and a resonance capacitor Cr. The inductor Lr is connected to the power switch M0, and the power switch M0 is turned on and off according to the gate drive signal V _gctrl . When the power switch M0 is turned on, the current ic flows out of the inductor Lr and is grounded through the power switch M0. When the power switch M0 is off, no current flows through the power switch M0. Conversely, the current i _Lr circulates between the inductor Lr and the resonance capacitor Cr. In this embodiment, the power switch M0 is an insulated gate bipolar transistor (IGBT). The collector terminal of the IGBT is connected to the inductor Lr (node 20), and the emitter terminal of the IGBT is grounded. The gate terminal of the IGBT is driven by the gate drive signal V _gctrl .

In operation, when the power switch M0 (IGBT) is turned on, an alternating current flows through the inductor Lr, thereby generating an oscillating magnetic field. The oscillating magnetic field induces an induced current in the metal cooking pot near the inductor coil. The current flowing in the resistance metal tank will generate heat, thereby heating the food in the cooking tank. When the power switch M0 is turned off, the current i _Lr circulates around the inductor Lr and the capacitor Cr. According to the gate drive signal V _gctrl , the power switch M0 is turned on and off to control the amount of induced current in the cooking tank, thereby controlling the heat generated.

When the single-switch quasi-resonant inverter is running, the power switch M0 (IGBT) is turned on and off. When the power switch is turned off, the power switch M0 can withstand high voltage transients at the power terminal (node 20). For example, when the IGBT is turned off, the collector voltage V _CE (node 20) can increase quickly, for example, as high as 800-1000V for an AC voltage of 220V. In this case, an IGBT with a typical collector-emitter voltage rating of 1.7kV can handle normal voltage transients during on and off operations. However, the IGBT may experience fault overvoltage conditions, such as a power surge event, that is, the induced voltage at the inductor Lr of the voltage surge exceeds the rated voltage of the IGBT. For example, when lightning occurs, extremely large power surges are induced in the AC power line. The power surge caused by flashing can drive the collector voltage of the IGBT to over 2kV, which exceeds the rated voltage of the IGBT, thereby causing damage to the IGBT. Therefore, in the event of excessive power surges and other overvoltage events, the power switch or IGBT in the single-switch quasi-resonant inverter must be protected.

In addition, especially when the power switch is turned off and a power surge occurs, the power switch must be protected from the power surge. When the power switch is turned on, the power switch can dissipate the surge voltage to the ground through the conduction of its power terminal. For example, when the IGBT is turned on, the IGBT can transmit a voltage surge from the collector to the emitter, and the emitter is grounded to dissipate the voltage surge. However, if the IGBT is turned off, the transistor cannot dissipate the surge voltage, and the collector terminal will experience an excessive surge voltage that exceeds the rated voltage of the element, causing permanent damage to the transistor.

Figure 2 shows a structural diagram of a controller circuit containing a protection circuit in an embodiment of the present invention. The coupled protection circuit drives the power switch in a single-switch quasi-resonant inverter for induction heating. Referring to Fig. 2, the single-switch quasi-resonant inverter 10 shown in Fig. 1 is driven by the control circuit 30, turns on and off the power switch M0, and conducts current alternately through the inductor Lr. In this embodiment, the power switch M0 is an IGBT with its gate as the control terminal, and the collector and emitter as the power terminal. In the following description, the control circuit will drive the IGBT as the power switch M0. This description is only used for explanation, not for limitation. It should be understood that in addition to IGBTs, other power switching elements can be used to configure the power switch M0. The power switch or power switch element includes a control terminal or a gate terminal, which receives a control signal or a gate drive signal, and a pair of power terminals conduct current.

In the embodiment of the present invention, the control circuit 30 includes a standard gate drive circuit 34 and a protection circuit. The protection circuit is composed of a protection gate drive circuit 40 and a fault detection circuit. In this embodiment, the fault detection circuit is configured as an overvoltage detection circuit for detecting overvoltage or excessive voltage at the IGBT control terminal (node 20), or excessive collector-emitter voltage V _CE at the IGBT.

In the control circuit 30, the standard gate drive circuit 34 receives the input signal V _IN (node 32) for controlling the on and off cycles of the power switch M0 or IGBT, so as to obtain the required value at the quasi-resonant inverter. Output Power. The input voltage VIN can be a PWM cycle or a clock signal, which switches between on time and off time. The standard gate drive circuit 34 generates an output signal at the node 52 as the gate drive signal V _gctrl , which is coupled to the gate terminal of the IGBT (node 22). In this embodiment, the standard gate drive circuit is configured as a CMOS transformer, which includes a PMOS transistor M1 and an NMOS transistor M2 connected in parallel between the forward voltage source Vdd (node 38) and ground. The impedance Z1 is coupled to the drain terminal (node 52) of the PMOS transistor M1, and the impedance Z2 is coupled to the drain terminal (node 52) of the NMOS transistor M2. The common node 52 between the PMOS transistor M1 and the NMOS transistor M2 is the output signal of the standard gate drive circuit 34.

The gate logic circuit 36 receives the input signal V _IN and generates gate control signals for the PMOS transistor M1 and the NMOS transistor M2. The gate logic circuit 36 generates gate control signals for the PMOS transistor M1 and the NMOS transistor M2, so that the PMOS transistor M1 and the NMOS transistor M2 are alternately turned on and off according to the input signal V _IN . That is, the PMOS transistor M1 and the NMOS transistor M2 are not turned on at the same time. Therefore, when the input signal V _IN is switched between a logic high potential and a logic low potential, the standard gate drive circuit 34 generates a gate drive signal V _gctrl to turn the IGBT on and off during normal operation. More precisely, the NMOS transistor M2 is turned on, the gate terminal of the driving IGBT is grounded, and the IGBT in normal operation is turned off. More optionally, the PMOS transistor M1 is turned on, the gate terminal of the IGBT is driven to reach the power supply voltage Vdd, and the IGBT in normal operation is turned on.

The control circuit 30 includes a protection circuit to provide overvoltage protection for the power switch M0 or the IGBT under the gate drive potential. The protection circuit is configured with active gate clamp and safely handles the overvoltage situation at the power switch of the quasi-resonant inverter. The protection circuit includes an overvoltage detection circuit 50 and a protection gate drive circuit 40. The over-voltage detection circuit 50 detects the over-voltage fault condition during the normal operation of the power switch, and initiates remedial measures to protect the power switch from damage. According to the detected fault condition, the protective gate drive circuit 40 is activated to generate a clamped gate voltage as a gate drive signal to bias the power switch to dissipate the voltage surge before the power switch is damaged.

The overvoltage detection circuit 50 receives the feedback voltage V _FB on the input node 54, which represents the collector-emitter voltage V _{CE of the} IGBT, or the power supply terminal voltage of the power switch M0. In this embodiment, a voltage divider formed by resistors R6 and R7 is coupled to the collector terminal (node 20) of the IGBT, and the collector-to-emitter voltage is decomposed as the feedback voltage V _FB . The feedback voltage V _FB (node 24) is coupled to the overvoltage detection circuit 50 to detect the overvoltage condition. In the embodiment of the present invention, the overvoltage detection circuit 50 only works during the IGBT off time. In other words, the overvoltage detection circuit 50 is activated, and the collector-to-emitter voltage is monitored only when the IGBT driven by the gate driving signal V _{gctrl is} completely disconnected.

When the IGBT is fully turned on, the IGBT conducts current from the collector to the emitter, and the collector voltage (node 20) remains at the saturation voltage V _CE-SAT voltage. Therefore, even if there is a power surge, the collector voltage at the IGBT is also very low, thereby protecting the IGBT from damage. However, when the IGBT is completely disconnected, a power surge at the collector terminal of the IGBT will cause the collector voltage to be too high, which will damage the IGBT.

When the IGBT is turned off, the over-voltage detection circuit 50 compares the feedback voltage V _FB (node 24) with the over-voltage threshold voltage to determine whether an over-voltage situation occurs at the collector terminal of the IGBT. When the feedback voltage V _FB exceeds the overvoltage threshold voltage, the overvoltage detection circuit 50 generates a fault detection signal. More specifically, when the feedback voltage V _FB exceeds the over-voltage threshold voltage, the over-voltage detection circuit 50 activates the fault detection indication signal, and when the feedback voltage V _{FB is} lower than the over-voltage threshold voltage, the over-voltage detection circuit 50 fails the fault detection indication Signal. In some embodiments, the overvoltage detection circuit is configured as a hysteresis overvoltage detection circuit, including a set voltage potential and a reset voltage potential for fault overvoltage detection, and the set voltage potential is higher than the reset voltage potential. When the feedback voltage exceeds the set voltage potential, the fault detection indication signal becomes effective, and when the feedback voltage is lower than the reset voltage potential, the fault detection indication signal becomes invalid.

The fault detection indication signal or such a signal is provided to the standard gate drive circuit 34 and the protection gate drive circuit 40. At the standard gate drive circuit 34, the fault detection indication signal or its equivalent signal is coupled to the gate logic circuit 36, and when a fault overvoltage condition is detected, the operation fails or the NMOS transistor M2 is disconnected. When the overvoltage detection circuit 50 is activated, the IGBT is turned off, which means that the NMOS transistor M2 in the standard gate drive circuit 34 is activated or turned on, and the drive gate drive signal is grounded, thereby turning off the IGBT. In order to initiate remedial measures when a fault overvoltage condition is detected, the NMOS transistor M2 should be disconnected or disabled, so that the protective gate drive circuit 40 can be activated to drive the gate of the IGBT. In this case, the protection gate driving circuit 40 does not need to overdrive the NMOS transistor M2. In other words, during normal operation, the transistors M1 and M2 are alternately turned on and off to drive the gate of the IGBT. However, when an overvoltage condition is detected, both transistors M1 and M2 are turned off before or at the same time that the protective gate drive circuit 40 takes remedial measures.

The fault detection indication signal or such a signal is also provided to the protective gate drive circuit 40 to take remedial measures to protect the IGBT. In this embodiment, the protection gate driving circuit 40 includes a PMOS transistor M3 and an NMOS transistor M4 connected in parallel between the forward voltage source (node 38) and ground. The impedance Z3 is located at the drain terminal (node 52) of the PMOS transistor M3, and the impedance Z4 is located at the drain terminal (node 52) of the NMOS transistor M4. The common node 52 between the PMOS transistor M3 and the NMOS transistor M4 is the output signal of the protection gate drive circuit. The protective gate drive circuit 40 generates an output signal on the node 52 as a gate drive signal V _gctrl , which is coupled to the gate terminal (node 22) of the IGBT.

The overvoltage detection circuit 50 generates a fault detection indication signal or indicates such a signal, couples the signal, and controls the PMOS transistor M3 and the NMOS transistor M4 through their respective time controllers and gate voltage clamping circuits. At the PMOS transistor M3, a fault detection indication signal or a signal indicating such a fault is coupled to the time controller 42 and the gate control circuit 44. According to the fault detection indication signal, the time controller 42 controls the on time of the PMOS transistor M3. In particular, the time controller 42 turns on the PMOS transistor M3 until the failure detection indication signal fails, or a shorter predefined fixed time (also referred to as "one-shot time"). At the NMOS transistor M4, the fault detection indication signal is coupled to the time controller 46 and the gate control circuit 48. According to the fault detection indication signal, the time controller 46 controls the on time of the NMOS transistor M4. In particular, the time controller 46 delays the turn-off effective time of the NMOS transistor M4 to provide a soft turn-off of the IGBT, which will be described in detail below.

During operation, the NMOS transistor M2 in the standard gate drive circuit 34 is turned off according to the effective fault detection indication signal. At the same time, the protective gate driving circuit 40 turns on the PMOS transistor M3 and the NMOS transistor M4. As the PMOS transistor M3 and the NMOS transistor M4 are turned on, the impedance Z3 and the impedance Z4 form a voltage divider between the forward voltage source and the ground. The Z3 and Z4 voltage dividers generate output signals, which are used as gate drive signals and become the divided voltages of the forward voltage source Vdd at the output node 52. Especially the gate drive signal is clamped to the voltage value of impedance Z3 and Z4 function, the clamp voltage is:

Therefore, the protective gate drive circuit 40 generates an output signal at the clamped gate voltage value as the gate drive signal V _gctrl to drive the gate terminal of the IGBT. Therefore, when an overvoltage occurs, the IGBT is turned on to dissipate the excess charge at the collector terminal (node 20). By driving the IGBT gates on the voltage divider Z3 and Z4, the gates of the IGBTs are gradually turned on to realize the soft turn-on of the clamped gate voltage. In this case, the protection gate drive circuit 40 turns on the IGBT in the protection mode to discharge the voltage surge.

The overvoltage detection circuit 50 continues to monitor the feedback voltage V _FB . When the collector-to-emitter voltage V _CE (node 20) drops below the overvoltage threshold, or when the reset voltage level in the detection circuit is lagging behind, the overvoltage detection circuit 50 fails the fault detection indication signal. Then, the gate drive circuit 40 can be fail-protected, and the IGBT in the protection mode can be turned off. During operation, the time controller 42 will first activate the gate control signal of the PMOS transistor M3 to release the clamped gate voltage at the output node 52. In the embodiment of the present invention, the protection circuit uses the clamped gate drive signal to turn on the IGBT when an overvoltage occurs, but the turn-on time of the IGBT is limited to a maximum time determined by a fixed time. When the voltage surge is not dissipated and the IGBT is turned on under the clamped gate voltage, the fault detection indication signal remains effective for an unnecessary long time. It is not necessary to turn on the IGBT for too long, because this will affect the reliability of the IGBT. Therefore, the time controller 42 in the protection gate driving circuit 40 uses the largest one shot time of the on time of the PMOS transistor M3. When the fault detection indication signal fails or when a shorter fixed time period expires, the time controller 42 disables the gate control signal of the PMOS transistor M3.

After the PMOS transistor M3 is disabled, the output signal of the protective gate drive circuit 40 no longer drives the clamped gate voltage. However, the gate terminal (node 22) of the IGBT must be discharged to ground in order to turn off the IGBT. Therefore, when the failure detection indication signal fails, the time controller 46 delays the failure of the gate drive signal of the NMOS transistor M4. Therefore, when an overvoltage protection event occurs and the PMOS transistor M3 is turned off, the NMOS transistor M4 remains on for a specified delay time to discharge the gate terminal (node 22) of the IGBT, thereby realizing the soft turn-off of the clamped gate voltage . After the delay time, the NMOS transistor M4 is turned off, The NMOS transistor M2 in the standard gate drive circuit 34 is turned on again, and the gate terminal of the IGBT is kept grounded before the IGBT returns to the normal operating state.

In this way, the protection circuit configured in the control circuit 30 realizes the over-protection of the gate drive potential of the IGBT in the quasi-resonant inverter 10. In particular, using the voltage divider of Z3 and Z4, the gate voltage of the IGBT is accurately controlled at the threshold value V _{GE_TH} and the Miller flat potential. Therefore, the IGBT is turned on and the induction coil current i _Lr flows through the IGBT. When a fault overvoltage occurs, the resonance capacitor voltage V _{Cr is} clamped at the desired potential. In this case, the protection circuit uses active gate drive to safely protect the power switch in the IGBT or quasi-resonant inverter from voltage surges or other overvoltage conditions. The protection circuit is configured with soft turn-on and turn-off operations, so that large transients will not occur when switching IGBTs. In some embodiments, impedances Z3 and Z4 are used to ensure that the clamped gate voltage is independent of temperature changes, and a protective gate drive circuit is configured.

Fig. 3 shows a circuit diagram in which the control circuit shown in Fig. 2 is arranged in an embodiment of the present invention. Referring to FIG. 3, the control circuit 60 for driving the gate terminal (node 22) of the IGBT includes a standard gate driving circuit 66 and a protective gate driving circuit 68. The control circuit 60 further includes a hysteresis overvoltage detection circuit 80 for detecting overvoltage conditions or excessive voltage at the collector terminal (node 20) of the IGBT, or excessive collector-to-emitter voltage V _CE at the IGBT.

In the control circuit 60, the standard gate drive circuit 66 receives an input signal V _IN (node 62), which is used to control the on and off switching cycle of the IGBT to obtain the required power output at the quasi-resonant inverter . The standard gate drive circuit is configured as a CMOS inverter. The standard gate drive circuit includes a PMOS transistor M1 and an NMOS transistor M2 connected in series between the forward voltage source Vdd (node 64) and ground. The impedance Z1 is coupled to the drain terminal (node 76) of the PMOS transistor M1, and the impedance Z2 is coupled to the drain terminal (node 76) of the NMOS transistor M2. The common node 76 between the PMOS transistor M1 and the NMOS transistor M2 is the output signal of the standard gate drive circuit 34. The input signal VIN can be a PWM signal, or a clock signal that switches between on time and off time. The standard gate drive circuit 66 generates an output signal at the node 76 as the gate drive signal V _gctrl , which is coupled to the gate terminal (node 22) of the IGBT. In some embodiments, the impedance Z5 may be coupled to the output node 76 to keep the gate of the IGBT grounded so that the gate is not driven by any other circuit. The impedance Z5 is optional and can be omitted in other embodiments.

The input voltage V _{IN is} coupled to the NOR gate 72 to generate a gate control signal VG2 for controlling the NMOS transistor M2. The input voltage V _{IN is} further coupled to the inverter 74 to generate a gate control signal V _G1 for controlling the PMOS transistor M1. The PMOS transistor M1 and the NMOS transistor M2 are mainly used as CMOS inverters to invert the logic state of the input voltage V _IN and drive the gate terminals of the transistors M1 and M2. Therefore, when the input voltage V _{IN is} at logic high, the PMOS transistor M1 is turned on and the NMOS transistor M2 is turned off. At the same time, when the input voltage V _{IN is} at logic low, the PMOS transistor M1 is turned off and the NMOS transistor M2 is turned on. The NMOS transistor M2 is further controlled by the gate control signal V _G4 , and the gate control signal V _G4 is generated by the time controller 70. The input voltage V _IN and the time control signal V _{G4 are} coupled to the NOR gate 72. Therefore, only when the input voltage V _IN and the gate control signal V _G4 are at logic low, the gate control signal V _G2 will take effect (logic high). Otherwise, the gate control signal V _G2 will be invalid (logic low). The gate control signal V _G4 is a fault detection indicator signal, which will be described in detail below.

The lagging overvoltage detection circuit 80 receives the feedback voltage V _FB on the input node, and the feedback voltage V _FB represents the collector-emitter voltage of the IGBT. In this embodiment, a voltage divider composed of resistors R6 and R7 is coupled to the collector terminal (node 20) of the IGBT so as to divide the collector-emitter voltage into the feedback voltage V _FB . Through the input impedance Z6, the feedback voltage V _FB (node 24) is coupled to the hysteresis overvoltage detection circuit 80 as an overvoltage monitoring signal OV_IN to monitor the overvoltage condition. The input impedance Z6 is used as an analog filter for the feedback voltage and provides ESD protection for the NMOS transistor M5. In the embodiment of the present invention, the hysteresis overvoltage detection circuit 80 operates only when the IGBT is off. Therefore, the NMOS transistor M5 is coupled to the input node 79 to enable or disable the overvoltage monitoring signal OV_IN according to the input voltage V _IN . More specifically, the input voltage V _{IN is} coupled to the time controller 88. The time controller 88 receives the input voltage signal V _IN and generates the output signal OV_Enable as the input voltage with the extended time T1. The OV_Enable signal is a gate control signal V _G5 , coupled to drive the gate terminal of the NMOS transistor M5. Therefore, when the input voltage is effective and the IGBT is turned on, the NMOS transistor M5 is turned on. As the NMOS transistor M5 is turned on, the input node 79 is shorted to ground, thereby disabling the overvoltage monitoring signal OV_IN. The time controller 88 extends the on-time of the input voltage signal to mask the detection of the high-to-low transition of the input voltage V _IN . In other words, the NMOS transistor M5 remains turned on for a short period of time after the falling edge of the input voltage V _IN . In other words, the over-voltage monitoring signal OV_IN is activated for a short period of time after the input voltage VIN fails, thereby masking the transition time to be detected. In this case, the hysteresis overvoltage detection circuit 80 is activated, and the collector-emitter voltage V _{CE of the} IGBT is monitored only when the gate drive signal V _gctrl drives the IGBT completely off.

In some embodiments, the hysteresis loop is used to respond quickly and a high gain comparator using a bandgap reference voltage is used to configure the hysteresis overvoltage detection circuit 80. By monitoring the feedback voltage, the hysteresis overvoltage detection circuit 80 can provide accurate detection of overvoltage conditions.

At the hysteresis overvoltage detection circuit 80, the overvoltage detection signal OV_IN is compared with the overvoltage threshold voltage to determine whether an overvoltage condition occurs at the collector terminal of the IGBT. Specifically, the hysteresis overvoltage detection circuit includes a set voltage potential and a reset voltage potential for detecting fault overvoltage conditions, and the set voltage potential is higher than the reset voltage potential. The overvoltage detection signal OV_IN is compared with the set voltage potential and the reset voltage potential as the threshold voltage value. The hysteresis overvoltage detection circuit 80 generates a fault detection indication signal OV_OUT (node 82). When the over voltage detection signal OV_IN exceeds the setting At the voltage level, the fault detection indication signal OV_OUT becomes effective. When the overvoltage detection signal OV_IN drops below the reset voltage level, the fault detection indication signal becomes invalid.

The fault detection indication signal OV_OUT (node 82) is coupled to the level shifter 84 to adjust the voltage level of the indication signal. The fault detection indication signal V _L (node 85) of the potential adjustment is coupled to the inverter 86 to generate the inverter indication signal V _LB (node 87). The fault detection indication signal V _L and the inverter indication signal V _{LB of the} potential adjustment are coupled to drive the standard gate drive circuit 66 and the protection gate drive circuit 68. In this embodiment, the fault detection indication signal OV_OUT is an active low signal. In other words, the fault detection indicator signal OV_OUT is usually at a logic high level (failure), and when a fault overvoltage condition is detected, the fault detection indicator signal OV_OUT transfers to a logic low level (effective).

The protection gate driving circuit 68 includes a PMOS transistor M3 and an NMOS transistor M4, which are connected in series between the forward voltage source Vdd (node 64) and the ground. The impedance Z3 is located at the drain terminal (node 76) of the PMOS transistor M3, and the impedance Z4 is located at the drain terminal (node 76) of the NMOS transistor M4. The common node 76 between the PMOS transistor M3 and the NMOS transistor M4 is the output signal of the protective gate drive circuit. The protective gate drive circuit 68 generates an output signal at the node 76 as the gate drive signal V _gctrl , which is coupled to the gate terminal (node 22) of the IGBT.

The fault detection indication signal or a signal indicating such a signal from the hysteresis overvoltage detection circuit 80 is coupled to the standard gate drive circuit 66 and the protection gate drive circuit 68, and remedial measures are initiated based on the detected overvoltage condition. First, the inverter fault detection indication signal V _{LB is} coupled to the time controller 70. When it fails, the inverter fault detection indication signal V _{LB is} at a logic low potential, and when it is effective, it is at a logic high potential. The time controller 70 transmits the inverter fault detection indication signal V _LB to the output, but with an extended turn-on time T2. In other words, when the inverter fault detection indication signal V _LB becomes effective, the time controller 70 activates the gate control signal V _G4 . When the inverter fault detection indication signal V _LB fails within a specified delay time, the time controller 70 becomes invalid Gate control signal V _G4 . The gate control signal V _{G4 is} coupled to the NOR gate 72, and its output drives the NMOS transistor M2 in the standard gate drive circuit 66, and the gate control signal VG4 is further coupled to drive the NMOS transistor M4 in the protection gate drive circuit 68.

As described above, the hysteresis overvoltage detection circuit 80 can only be allowed when the IGBT is turned off. In that case, the input voltage V _IN fails (logic low), the gate control signal V _{G2 is} at a logic high potential, and the driving NMOS transistor M2 is completely turned on. As the NMOS transistor M2 is completely turned on and the PMOS transistor M1 is completely turned off, the gate terminal (node 22) of the IGBT is discharged to the ground and remains grounded when it is turned off. According to the detected over-voltage condition, the inverter fault detection indication signal V _{LB is} effective (logic high), and the gate control signal V _G4 is also effective (logic high). Therefore, the coupled gate control signal V _G2 drives the NMOS transistor M2 to transition to a logic low level, and the NMOS transistor M2 is disabled or turned off. Therefore, the standard gate drive circuit 66 is disabled and no longer drives the IGBT. At the same time, the gate control signal V _G4 takes effect and is also coupled to the gate terminal of the NMOS transistor M4 to turn on the NMOS transistor M4.

Secondly, the failure detection signal indicative of a time controller is coupled to V _L 71. When it fails, the fault detection indication signal V _{L is} at a logic high potential, and when it is valid, it is at a logic low potential. Through one shot time control, the time controller 71 transmits the fault detection indication signal V _L to the output. That is, according to the fault detection indication signal V _L into effect, the time controller 71 is active (logic low) time control signal V _G3, according to the fault detection indication signal V _L failure or fixed time period T3 expires (which occurs first on which press) , The time controller 71 fails the gate control signal V _G3 . Therefore, the maximum time period during which the gate control signal V _G3 will be effective is a fixed time period, which is also called a shot time. The gate control signal V _G3 will be effective for one shot time or less. The gate control signal V _{G3 is} coupled to drive and protect the gate terminal of the PMOS transistor M3 in the gate drive circuit 68.

When an overvoltage condition is detected, the fault detection indication signal V _{L is} effective (logic low), and the gate control signal V _G3 is also effective (logic low). The gate control signal V _{G3 is} coupled to the gate terminal of the PMOS transistor M3, and when an overvoltage condition is detected, the PMOS transistor M3 is turned on. The PMOS transistor M3 is turned on until the failure detection indication signal V _L fails or the firing time T3 expires.

During operation, after the fault detection indication signal OV_OUT takes effect, the NMOS transistor M2 in the standard gate drive circuit 66 is turned off. At the same time, the protection gate driving circuit 68 turns on the PMOS transistor M3 and the NMOS transistor M4. After the PMOS transistor M3 and the NMOS transistor M4 are turned on, the impedances Z3 and Z4 form a voltage divider between the forward voltage source and the ground. The voltage divider of Z3 and Z4 generates an output signal as the gate drive signal on the output node 76 and becomes the divided voltage of the forward voltage source Vdd. In particular, the gate drive signal is clamped at a voltage value that is a function of impedances Z3 and Z4, and the value is (Z4/(Z3+Z4))*Vdd. Therefore, the protective gate drive circuit 68 generates an output signal under the clamped gate voltage value, which serves as the gate drive signal V _gctrl to drive the gate terminal of the IGBT. Therefore, the IGBT is turned on under an overvoltage condition, consuming the excess charge at the collector terminal (node 20). It is necessary to note that the gate of the IGBT is driven through the voltage divider of Z3 and Z4, and the gate of the IGBT is gradually turned on to achieve soft turn-on control. In this case, the protection gate drive circuit 68 turns on the IGBT in the protection mode to discharge the voltage surge.

In some embodiments, the ratio of Z3 to Z4 is 0.55. Therefore, the clamped gate voltage on the IGBT is approximately half of the voltage source voltage Vdd. In addition, the protection circuit can activate the protection gate drive circuit 68 very quickly to clamp the gate voltage of the IGBT. In an example, the peak value of the power surge at the AC input terminal can be about 15 μs so as to reach the collector terminal of the IGBT in the quasi-resonant inverter circuit. However, the protection circuit of the present invention can clamp the gate voltage of the IGBT at about 500 ns-much earlier than the peak surge at the collector end. In this case, when the peak surge reaches the collector terminal, the IGBT is turned on, and the IGBT can safely consume the power surge without damaging the IGBT.

The hysteresis overvoltage detection circuit 80 continues to monitor the feedback voltage V _FB . When the collector-to-emitter voltage V _CE (node 20) drops below the preset voltage level, the hysteresis over-voltage detection circuit 80 fails the fault detection indication signal OV_OUT. Then, the protection gate drive circuit 68 may fail, and in the protection mode, the IGBT is turned off. During operation, when the fault detection indication signal V _L fails (logic high) or when the fixed time period expires (whichever is faster, press whichever is faster), the time controller 71 disables the gate control signal V _{G3 of} the PMOS transistor M3. At the same time, the time controller 70 disables the gate control signal V _G4 , and delays a period of time T2 after the inverter fault detection indication signal V _LB fails (logic low). After the PMOS transistor M3 is turned off, the NMOS transistor M4 remains turned on to discharge the gate terminal (node 22) of the IGBT to turn off the IGBT. After the delay period T2, the NMOS transistor M4 is turned off, and the NMOS transistor M2 in the standard gate drive circuit 34 is turned on again, and the gate terminal of the IGBT is kept grounded before the IGBT returns to normal operation.

In the embodiment of the present invention, the protection circuit of the present invention generates a clamped gate voltage for the gate drive signal (node 22), which can be accurately controlled and does not appear in the traditional Zener diode clamp method often encountered The voltage overshoot problem. In addition, the clamped gate voltage can be accurately controlled without being affected by temperature and manufacturing process changes. In some embodiments, impedances Z3 and Z4 are configured using polysilicon resistors.

Figure 4 shows a timing diagram of the operation of the controller circuit shown in Figure 3 in some examples. Refer to Figure 4, the input signal V _IN (curve 102) is a PWM signal that turns on and off the IGBT, and conducts the current through the induction coil alternately. The time controller 88 generates the gate control signal OV_Enable (curve 104) to drive the NMOS transistor M5 to enable or disable the overvoltage monitoring. In particular, the OV_Enable signal prolongs the time T1 above the failure of the input signal V _IN to cover the high-to-low transition of the input signal from being affected by overvoltage monitoring. During normal operation, the gate voltage V _gctrl (curve 110) of the IGBT switches between ground and the voltage source voltage Vdd to turn the IGBT on and off. At the same time, the collector current i _C (curve 108) increases linearly during the IGBT on time and drops to zero during the IGBT off time. During normal operation, the gate control signals (curves 112, 114) of the transistors M1 and M2 have a logic low potential during the IGBT on time, and a logic high potential during the IGBT off time. During normal operation, the gate control signal (curve 116) of the transistor M3 is at a logic high potential, and the gate control signal (curve 118) of the transistor M4 is at a logic low potential to disable the protection gate drive circuit.

During the on-time of the IGBT, the collector-to-emitter voltage V _CE (curve 106) is driven to the collector-emitter saturation voltage V _CE-SAT . However, when the IGBT is turned off, the collector voltage can rise to a very high voltage value, such as 600V. IGBT usually has a rated voltage of 1.7kV, which can withstand the standard collector voltage stroke during the normal operation of the IGBT.

The hysteresis overvoltage detection circuit monitors the collector voltage V _{CE of the} IGBT within the IGBT off time and after the delay time T1 that covers the on-to-off transition of the input voltage V _IN . At t1, a specific power surge event causes the collector voltage V _{CE to} exceed the set voltage potential of the hysteresis overvoltage detection circuit. In an example, the set voltage potential corresponds to a collector voltage of about 1.4kV. The hysteresis over-voltage detection circuit activates the fault detection indication signal. In a very short time, such as t1, start the remedial measures. The gate control signal of transistor M2 is disabled (logic low), turning off transistor M2. The gate control signal of the transistor M3 is enabled (logic low), turning on the transistor M3, and the gate control signal of the transistor M4 is enabled (logic high), turning on the transistor M4. As the transistors M3 and M4 are turned on, the gate voltage of the IGBT rises to the clamped gate voltage value determined by the Z3/Z4 voltage divider. The clamped gate voltage turns on the IGBT, conducts the collector current i _C , and consumes power surges. Therefore, the collector voltage V _CE drops.

At time t2, the collector voltage V _CE drops below the reset voltage potential of the hysteresis overvoltage detection circuit. In an example, the reset voltage potential corresponds to a collector voltage of about 1.2 kV. Hysteresis overvoltage detection circuit failure failure detection indication signal, transistor M3 failure (logic high). Transistor M4 remains on for the extended time of T2 and discharges the gate voltage of the IGBT. At time t3, when the time period T2 expires, the transistor M4 is turned off, the transistor M2 is turned on, and the normal operation continues.

Then, the IGBT is turned on again and returns to normal operation. During the next off time, the IGBT will experience additional power surge events. In this case, the transistors M3 and M4 are turned on again to consume the surge voltage. In this example, a surge voltage on the IGBT collector will cause the collector voltage to switch between the set voltage potential and the reset voltage potential multiple times during a single off time. Every time the collector voltage exceeds the set voltage potential, the protection gate drive circuit is enabled, and every time the collector voltage drops below the reset voltage potential, the protection gate drive circuit is disabled. In this case, the protective gate drive circuit can be activated multiple times during a single off time to consume power surges.

Figure 5 shows the collector voltage and collector current of the IGBT when a power surge occurs in some examples. First, referring to Figure 2, the purpose of the protection circuit is to consume the energy generated in the induction coil Lr in the IGBT, and clamp the capacitor voltage Cr so that the collector voltage V _CE will not exceed the rated voltage of the IGBT. Now, referring to Figure 5, the collector voltage V _{CE of the} IGBT (curve 120) and its corresponding collector current i _C (curve 122) have the set and reset voltage potentials used in the hysteresis overvoltage detection circuit. Note that the set and reset voltage potentials shown in Figure 5 are the voltage potentials used in the hysteresis overvoltage detection circuit. The hysteresis overvoltage detection circuit receives the falling collector voltage for detection, so the setting and reset voltage potential used in the detection circuit corresponds to the falling voltage potential.

At t1, a power surge occurs at the collector end of the IGBT, and the collector voltage increases to the set voltage potential. The protective gate drive circuit is activated, and the IGBT is turned on under the clamp voltage potential. As the clamped gate voltage is applied to the IGBT, the collector current i _C begins to increase gradually. The current flow of the coil current i _Lr changes direction. The coil current i _Lr no longer circulates between the induction coil Lr and the capacitor Cr, but flows to the IGBT and is dissipated to the ground by the IGBT. Therefore, the collector voltage V _CE is clamped and no longer increases. When the current i _C is equal to the current i _Lr at time t2, the voltage V _CE begins to drop through the discharge of the capacitor Cr, and the voltage drop slope is determined by the collector current i _C and the capacitance value Cr of the capacitor. Once the voltage V _CE reaches the reset potential at t3, the protective gate drive circuit is disabled, and the collector current i _C is controlled by the soft gate to cut off, realizing soft turn-off. The current drop time interval (t3-t4) causes the voltage V _CE to drop slightly below the reset potential. Once the protection interval is completed at t4, the IGBT returns to continue operation.

Figure 6 shows a flow chart of a method for providing overvoltage or short circuit protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention. Referring to Figure 6, the over-voltage protection method 200 monitors the feedback voltage, and the feedback voltage represents the voltage on the power switch during the off time of the power switch (202). The feedback voltage is compared with the overvoltage setting potential OV_Set (204). According to the feedback voltage being less than the OV_Set potential, the method continues to monitor the feedback voltage representing the voltage on the power switch. On the other hand, when the feedback voltage is greater than the OV_Set potential, the method 200 disables the standard gate drive signal (206). For example, the method 200 turns off the NMOS transistor M2 in the standard gate drive circuit, and the standard gate drive circuit drives the power switch to turn off. Then, the method 200 enables the protection gate drive signal (208). For example, the PMOS transistor M3 and the NMOS transistor M4 in the protection gate drive circuit are both turned on to form a voltage divider with impedances Z3 and Z4. The method 200 generates a clamped gate drive signal with a clamped gate voltage value (210). Use the clamp gate drive signal to turn on the power switch. As the clamp gate drive signal turns on the power switch, the method 200 monitors the feedback voltage to determine whether the feedback voltage drops below the reset voltage level OV_Reset (212). The reset voltage potential OV_Reset is lower than the set voltage potential OV_Set. When the feedback voltage is lower than the reset voltage level, the method 200 enables the clamp gate driving signal and discharges the power switch gate terminal (214). The method 200 activates the standard gate drive circuit (216) and returns to monitor the feedback voltage. The feedback voltage represents the voltage on the power switch during the off time of the power switch (202).

In some embodiments, in parallel with monitoring the feedback voltage, it is determined whether the feedback voltage drops below the reset voltage level OV_Reset (212), and the method 200 further monitors the time when the power switch is turned on using the clamped gate driving signal. More specifically, the method 200 monitors the on time of the power switch to determine whether the on time reaches or exceeds the maximum time (220). When the maximum time expires, which is also called a shot time, the method 200 continues to disconnect the clamped gate drive signal (214), even if the feedback voltage has fallen below the reset voltage level OV_Reset. The method 200 continues to enable the standard gate drive circuit (216), and returns to monitor the feedback voltage representing the voltage on the power switch during the off time of the power switch (202).

Hard-on disable and dual-potential protection control

As mentioned above, during the normal operation of the single-switch quasi-resonant inverter, according to the gate drive signal V _gctrl , the power switch M0 (IGBT) is turned on and off alternately to control the current flow in the induction coil Lr, and the load The current induced in the tank controls the heat generated. The gate drive signal V _gctrl comes from the system input signal V _IN , which controls the on and off switching cycle of the power switch M0. Provide the system input signal V _IN to drive the power switch to turn on and off at a specified switching frequency (for example, 30kHz) to obtain the required power output at the quasi-resonant inverter. The input signal V _IN can be a PWM cycle, or a clock signal that switches between on and off time.

During the off time of the power switch M0, no current flows through the power switch M0. In contrast, the current i _Lr circulates between the induction coil Lr and the resonance capacitor Cr. However, at this time, the voltage on the power switch M0 can reach a very high peak voltage value, for example, 1kV. When the power switch M0 is an IGBT, the IGBT maintains a very high peak voltage at the collector and emitter terminals. In other words, when the IGBT is turned off, the collector-to-emitter voltage V _{CE of the} IGBT can reach 1 kV. When the IGBT is turned off, noise can be coupled back to the host system that generates the system input signal V _IN , causing the system input signal V _{IN to} trigger falsely. That is to say, the system input signal V _IN can be driven very high or very low by noise to generate a fault signal potential, causing the gate drive signal V _{gctrl to} drive above the threshold voltage. The IGBT is unintentionally driven within the assumed turn-off time. In the connection.

When the power switch is turned on by mistake during the off time, since the voltage on the power switch is at a high voltage value, the power switch will undergo hard switching or hard turning on. The hard switching of the power switch is not needed by us, which will negatively affect the efficiency and reliability of the power switch.

In the embodiment of the present invention, the controller for driving the power switch introduces a hard turn-on disable (HTOD) circuit to prevent the power switch from turning on when the power switch maintains a high voltage value. The hard-on disable circuit includes a hard-on detection circuit and a protection logic circuit. The hard-on detection circuit is used to monitor the voltage on the power switch and generate an indication signal indicating the high voltage on the power switch. According to the state of the detection indication signal, a protection logic circuit is configured to lock or transmit the system input signal V _IN to the power supply Standard gate drive circuit of the switch. In particular, the protection logic circuit blocks the system input signal V _IN according to the high voltage detection, so that the power switch M0 ignores the system input signal V _IN that may be wrong, prevents the power switch from being turned on, and drives the power switch to a high voltage potential. In this case, the hard-on-disable circuit can operate to prevent the power switch from being hard-switched under abnormal system conditions, such as AC power surges or control signal failure, which may cause false triggering of system input signals.

In the embodiment of the present invention, a controller is used to drive a power switch introduced in a single-switch quasi-resonant inverter for induction heating. After the hard-on disable circuit is introduced in the controller, when the power switch is driven to a high voltage, the power switch can be prevented from being turned on, thereby avoiding hard switching. However, in some cases, excessive abnormal voltage (such as lightning surge) may occur on the AC input line of the induction heating system. The filtered DC voltage V _Cf for the induction coil Lr can be increased by several hundred volts even if the surge absorption circuit has exceeded the excessive input voltage. The voltage on the power switch (IGBT)-the collector-to-emitter voltage V _CE- can be increased to 1.5kV or more, and the V _CE voltage may exceed the dynamic breakdown voltage of traditional IGBT components. In that case, no longer prevent the power switch from being turned on under the HTOD protection system, but refer to Figures 2 to 6 to truly and effectively use the overvoltage protection system to softly turn on the power switch and consume excess voltage.

Therefore, in some embodiments, the controller for driving the power switch is equipped with a bi-potential protection system to protect the power switch from hard switching and damage caused by power surge or overvoltage conditions. In the embodiment of the present invention, the controller for driving the power switch introduces a double-potential protection circuit, and two protection systems are configured for the power switch. In particular, the bi-potential protection circuit adopts the first potential protection and provides a hard-on disable (HTOD) protection system to prevent the power switch from being triggered by the system input signal to cause hard switching or hard switching. The bi-potential protection circuit also adopts a second potential protection, which provides an over-voltage clamp protection (OVCP) system to protect the power switch from over-voltage conditions such as lightning or power surge events. The HTOD protection system prevents the malfunction of the power switch and avoids hard switching. Prevent hard switching or hard switching of the power switch, improving the immunity and working efficiency. At the same time, referring to Figures 2 to 6, the above-mentioned OVCP protection system makes the power switch soft turn on during the off time to consume overvoltage. The OVCP protection system prevents the power switch from exceeding its dynamic breakdown voltage and keeps the power switch in a safe working area. In this way, the dual protection systems work together to improve the immunity, efficiency and reliability of the power switch.

More precisely, by detecting the voltage on the power switch during the off time of the power switch, the bi-potential protection circuit is configured with two protection systems. When the power switch is an IGBT, the double-potential protection circuit is realized by detecting the collector voltage on the IGBT or the collector-emitter voltage V _CE at the IGBT. When the power switch is off, the voltage on the power switch or the voltage indicating it will be monitored. When the voltage on the power switch rises above the first voltage potential, the hard on-disable (HTOD) protection system is activated. Regardless of the state of the system input signal V _IN , the power switch must be prevented from being turned on during the off time . However, when the voltage on the power switch continues to rise and reaches the second voltage potential, the overvoltage clamp protection (OVCP) system is activated, surpassing the HTOD protection system, causing the power switch to turn on softly to consume the overvoltage, thereby reducing The voltage on the power switch is kept within a safe working range. Especially when the OVCP system is activated, the protection circuit turns on the power switch by effectively clamping the gate voltage when the switch is off. In this case, the power surge can be dissipated from the power switch without irreparable damage to the power switch.

In one embodiment, when the voltage on the power switch exceeds 400V, the protection circuit will activate the HTOD protection system during the switch off time. In the 400-1kV voltage range, the HTOD protection system is activated to prevent the power switch from being turned on by mistake. In other words, even if the input voltage V _{IN of the} system takes effect, the HTOD protection system operates to prevent the power switch from being turned on when the voltage on the power switch is too high.

Then, if the voltage on the power switch exceeds 1kV during the off time, the protection circuit will surpass the HTOD protection system and activate the OVCP protection system, so that the power switch is softly turned on, and the gate voltage of the power switch is clamped at the specified gate. Voltage value to consume power surge. As mentioned above, referring to Figures 2 to 6, the OVCP protection system uses a gate drive circuit (transistors M3 and M4) to soft turn on the power switch instead of a standard gate drive circuit.

Figure 7 shows the configuration diagram of the controller circuit equipped with a dual-potential protection system in an embodiment of the present invention. The dual-potential protection system includes coupling two protection systems to drive the power switch in a single-switch quasi-resonant inverter , Used for induction heating. The configuration method of the controller circuit shown in FIG. 7 is the same as the configuration method of the control circuit 30 shown in FIG. 2 with the addition of a hard-on disable circuit. Similar components in Figures 2 and 7 are given similar reference numbers, and will not be repeated here. Referring to Fig. 7, the single-switch quasi-resonant inverter 10 shown in Fig. 1 is driven by a controller circuit 31 to turn on and off the power switch M0 and alternately conduct current through the induction coil Lr. In this embodiment, the power switch M0 is an IGBT, the gate of which is used as the control terminal, and the collector terminal and the emitter terminal are used as the power terminal. In the following description, the controller The road will be used as the power switch M0 to drive the IGBT. This description is only used for explanation, not for limitation. It should be understood that in addition to the IGBT, the power switch M0 can also use other power switch element configurations. The power switch or power switch element includes a control terminal or a gate terminal (receiving a control signal or a gate drive signal), and a pair of power terminals to conduct current.

In the embodiment of the present invention, the controller circuit 31 includes a standard gate drive circuit 34 and an OVCP circuit, wherein the OVCP circuit is composed of a protective gate drive circuit 40 and a fault detection circuit. In this embodiment, the fault detection circuit is configured as an overvoltage detection circuit 50 for detecting overvoltage conditions or excessive voltage events at the collector terminal (node 20) of the IGBT, or excessive collector to emitter at the IGBT Voltage V _CE . The protective gate drive circuit 40 and the fault detection circuit work together to configure the OVCP protection system in the above-mentioned manner, see Figure 2 and the following figures.

The controller circuit 31 further includes a hard turn-on disable (HTOD) circuit 55 for receiving the system input voltage V _IN (node 32) and the feedback voltage V _FB on the input node 54. The feedback voltage V _FB on the input node 54 represents The collector-to-emitter voltage V _{CE of the} IGBT, or the voltage on the power terminal of the power switch M0. The feedback voltage V _FB (node 24) is coupled to the HTOD circuit 55 to detect the high voltage condition on the power switch M0. In some embodiments, the HTOD circuit 55 can operate to detect the voltage on the power switch during the IGBT off time. The HTOD circuit 55 generates a control signal Vc as an output signal, which is coupled to drive the gate logic circuit 36 in the standard gate drive circuit 34. The control signal Vc can be operated to pass the system input signal V _IN to the standard gate drive circuit 34, or block the system input signal V _{IN to} prevent it from being transmitted to the standard gate drive circuit. That is, when the HTOD circuit 55 is not activated, the system input signal V _{IN is} transmitted to the gate logic circuit 36, the standard gate drive circuit 34 is activated, and the power switch is turned on and off according to the system input signal V _IN . On the other hand, according to the detected high voltage on the power switch, when the HTOD circuit 55 is activated, the HTOD circuit will block the system input voltage V _IN and prevent it from being passed to the gate logic circuit 36. No matter what the state of the system input signal V _IN is, the standard gate drive circuit 34 will not drive the power switch to turn on or off.

Fig. 8 shows a circuit diagram of the controller circuit shown in Fig. 7 in an embodiment of the present invention. The configuration of the controller circuit shown in Fig. 8 is the same as the configuration of the control circuit 60 shown in Fig. 3, with the addition of a hard-on disable circuit. Similar components in Figures 3 and 8 are given similar reference numbers, and will not be repeated here. Referring to FIG. 8, the controller circuit 61 for driving the IGBT gate terminal (node 22) includes a standard gate driving circuit 66 and a protective gate driving circuit 68. The controller circuit 61 further includes a hysteresis overvoltage detection circuit 80 for detecting overvoltage conditions or overvoltage conditions at the IGBT collector terminal (node 20), or excessive collector-to-emitter voltage V _CE at the IGBT. The protective gate drive circuit 68 and the hysteresis overvoltage detection circuit 80 are equipped with an OVCP protection system. According to the fault detection indication signal OV_OUT (node 82), the protective gate drive circuit 68 is activated to indicate the overvoltage condition detected at the power switch M0. The protective gate drive circuit 68 softly turns on the IGBT (power switch M0), and clamps the gate voltage of the IGBT at a specified gate voltage value. The structure and operation of the protective gate drive circuit 68 and the hysteresis overvoltage detection circuit 80 have been described in detail, and will not be repeated here.

The controller circuit 61 further includes a hard on-disable (HTOD) circuit 90 to protect the IGBT from hard switching, that is, when the voltage on the IGBT is at a high voltage potential, it prevents the IGBT from being affected by the system input voltage V _IN . The noise turns on by mistake. In the control circuit 60 shown in FIG. 3, there is no HTOD circuit, and the standard gate drive circuit 66 directly receives the system input signal V _IN (node 62) through the NOR gate 72 and the inverter 74. However, on the contrary, in the controller circuit 61 shown in FIG. 8, the system input signal V _{IN is} routed to the HTOD circuit 90. The HTOD circuit 90 generates a control signal Vc (node 96) as an output signal for driving the standard gate drive circuit 66 through the NOR gate 72 and the inverter 74. In this case, the HTOD circuit 90 thresholds the system input signal V _IN to determine whether the system input signal should or should not be passed to the standard gate drive circuit 66.

The hard-on disable circuit 90 includes a hard-on detection circuit 92 and a protection logic circuit, wherein the protection logic circuit is composed of a D-flip-flop 94 and a logic AND gate 95. The hard-on detection circuit 92 is coupled to receive the over-voltage monitoring signal OV_IN (node 79) indicating the feedback voltage V _FB . Therefore, the hard turn-on detection circuit 92 monitors the voltage V _CE on the IGBT to determine when the collector terminal (node 20) of the IGBT reaches the high voltage potential, or when the IGBT reaches the high collector-emitter voltage V _CE . In the following embodiment, the hard-on detection circuit 92 can only operate during the IGBT off time. As described above, the NMOS transistor is coupled to the node 79, and the overvoltage monitoring signal OV_IN is enabled or disabled according to the system input signal V _IN . When the system input signal is at logic high (switch on time), the OV_Enable signal VG5 is driven high to turn on the NMOS transistor M5 to the ground node 79. On the other hand, when the system input signal is at logic low (switch off time), the OV_Enable signal VG5 is driven low to turn off the NMOS transistor M5, so that the overvoltage monitoring signal OV_IN (node 79) follows the feedback voltage V _FB .

The hard-on detection circuit 92 generates a high voltage indicating signal HT as an output signal. When the overvoltage monitoring signal OV_IN exceeds the first threshold voltage level, the high voltage indication signal HT takes effect. In some embodiments, the hard turn-on detection circuit 92 is a hysteresis detection circuit containing the HTOD setting voltage potential and the HTOD reset voltage potential. When the overvoltage detection signal OV_IN exceeds the HTOD setting voltage level, the high voltage indication signal HT takes effect. When the overvoltage monitoring signal OV_IN drops below the HTOD reset voltage level, the high voltage indication signal HT becomes invalid. In addition, in some embodiments, the high voltage indicating signal HT is at a logic low level when it is disabled, and the high voltage indicating signal HT is at a logic high level when it is valid.

The high voltage indicating signal HT is coupled to the protection logic circuit. In particular, the high voltage indicating signal HT is coupled to the reset terminal RB of the D-flip-flop 94. In this embodiment, the reset terminal of the D-flip-flop 94 is an active low terminal. That is, when the reset terminal RB is driven to a logic low potential, the D-flip-flop 94 is placed in a reset state. Therefore, the high voltage indication signal HT is coupled to the inverter 93, and the inverter signal HT is provided to the reset terminal RB. In other embodiments, the reset terminal of D-flip-flop 94 is an active high side. In other cases, the inverter 93 is omitted, and the high voltage indicating signal HT can be directly coupled to the reset terminal of the D-flip-flop 94.

The D-flip-flop receives the forward voltage source voltage Vdd as the data input D, and receives the system input signal VIN as the clock input. Therefore, the data input D clock is at logic high, and according to the clock input VIN, the data input D is passed to the data output of the D-flip-flop. Both the data output Q of the D-flip-flop and the system input signal V _IN are used as input signals and are coupled to the logic AND gate 95. The output signal of the AND gate 95 is the control signal Vc (node 96). The control signal Vc is coupled to the inverter 74 and the NOR gate 72 for driving the standard gate driving circuit 66.

After the D-flip-flop 94 and the logic AND gate 95 are configured, unless the D-flip-flop 94 is in the reset mode, the control signal Vc will follow the system input signal VIN. This is because the data output Q of the D-flip-flop 94 produces the same logical output value as the system input signal VIN. However, when the D-flip-flop 94 is in the reset mode, the data output Q is at logic low, the AND gate 95 is disabled, and the system input signal VIN is blocked and cannot be transmitted to the output terminal of the AND gate 95. The control signal Vc is kept at a logic low level, and the standard gate drive circuit 66 will not be activated regardless of the state of the system input signal V _IN .

The operation of the HTOD circuit 90 is as follows. The hard-on detection circuit 92 monitors the feedback voltage V _FB , and the feedback voltage V _FB represents the collector-emitter voltage of the IGBT. In particular, the hard turn-on detection circuit 92 monitors the overvoltage monitoring signal OV_IN (node 79). The hard turn-on detection circuit 92 compares the overvoltage monitoring signal OV_IN with the first threshold voltage potential. In an example, the first threshold voltage potential corresponds to an IGBT collector-emitter voltage of about 400V. In the case that the hard-on detection circuit is a hysteresis detection circuit, the hard-on detection circuit 92 compares the overvoltage monitoring signal OV_IN with the HTOD setting voltage potential and the HTOD reset voltage potential, and the HTOD setting voltage potential is higher than the HTOD reset voltage Potential. In an example, the HTOD setting voltage potential corresponds to an IGBT collector-emitter voltage of about 400V, and the HTOD reset voltage potential corresponds to an IGBT collector-emitter voltage of about 350V. When the overvoltage monitoring signal OV_IN is lower than the HTOD setting voltage level, the HT signal is at logic low, and the reset terminal RB of the D-flip-flop 94 is not activated. Therefore, the system input signal V _{IN is} used as the control signal Vc and is transmitted through the D-flip-flop 94 and the AND gate 95. In this case, the standard gate drive circuit 66 generates a gate drive signal V _gctrl corresponding to the system input signal V _IN to turn the IGBT on and off.

When the overvoltage monitoring signal OV_IN rises above the HTOD setting voltage level, the HT signal becomes effective to a logic high level, the reset terminal RB of the D-flip-flop 94 becomes effective, and the D-flip-flop 94 is placed in the reset mode. The output signal Q of the D-flip-flop 94 remains at the reset potential-logic low. Regardless of the system input signal V _IN , the AND gate 95 is in a locked state, and the control signal Vc remains low. In this case, the standard gate drive circuit 66 keeps the IGBT off (the PMOS transistor M1 is off and the NMOS transistor M2 is on). Therefore, when the voltage on the IGBT exceeds the HTOD setting voltage level, the HTOD circuit 90 operates, and the blocking system input signal V _IN reaches the standard gate drive circuit to prevent the IGBT from being hard-on. Therefore, even if the noise coupling causes the input signal V _IN of the system to be falsely triggered, the wrong system input signal pulse will be blocked so as not to reach the power switch and cause the power switch to be turned on accidentally.

In some embodiments, the HTOD circuit 90 further includes a clock circuit for monitoring the duration of the effective high voltage indicator signal HT. When the effective time of the high voltage indication signal HT exceeds the preset fixed time period, an alarm signal or flag will be generated and transmitted to the host system, the controller circuit 61 Remedial measures can be initiated, such as turning off the power switch (IGBT) completely. In some embodiments, the preset fixed time period is a minimum of 35 μs, and is usually 70 μs.

The hard turn-on detection circuit 92 continues to monitor the overvoltage monitoring signal OV_IN. The high voltage indication signal HT remains effective until the overvoltage monitoring signal OV_IN drops below the HTOD reset voltage level. When the overvoltage monitoring signal OV_IN is lower than the HTOD reset voltage level, the high voltage indication signal HT fails to a logic low level, the reset terminal RB of the D-flip-flop 94 fails, and the D-flip-flop 94 is no longer in the reset mode . The D-flip-flop 94 operates and transmits the system input signal VIN to the data output terminal Q. The AND gate 95 receives the same signal at its two input terminals. The AND gate 95 generates a control signal Vc for monitoring the system input signal V _IN . The control signal Vc is coupled to drive the standard gate drive circuit 66. Therefore, the standard gate drive circuit 66 generates a gate drive signal V _gctrl corresponding to the system input signal V _IN , and turns on and off the IGBT during normal operation.

In this way, the controller circuit 61 configures a double-potential protection system for the power switch M0. The hard-on disable circuit 90 operates as described above to prevent the IGBT from being turned on when the collector-to-emitter voltage V _CE exceeds the first threshold voltage potential or the HTOD setting voltage potential (for example, corresponding to the IGBT collector voltage of 400V). However, when the collector-to-emitter voltage V _CE continues to increase and the overvoltage monitoring signal OV_IN transmits the overvoltage setting voltage potential (for example, corresponding to the IGBT collector voltage of 1000V), the hard-on disable circuit 90 will be overridden and the OVCP protection system Is activated, consuming voltage surge. As described above, the NMOS transistor M2 of the standard gate drive circuit 66 will be released by the NOR gate 72, so that the gate terminal of the IGBT will not be driven by the standard gate drive circuit 66. Then, the protective gate drive circuit 68 is activated. The transistors M3 and M4 in the protective gate drive circuit 68 are turned on at the same time, combined with the impedances Z3 and Z4, to generate a soft rise of the gate drive signal V _gctrl , which exceeds the threshold voltage of the IGBT. At the same time, the protection gate drive circuit 68 clamps the gate drive signal V _gctrl at the maximum voltage value, which is given by the above equation (1). In this case, turn on the IGBT, clamp the gate voltage safely, and dissipate the excess voltage to the ground at the collector terminal.

When the overvoltage monitoring signal OV_IN drops to the overvoltage reset voltage level, as the hysteresis overvoltage detection circuit 80 detects the ground, the OVCP protection system first unprotects the PMOS transistor M3 in the gate drive circuit 68, and at the same time the time controller 70 Keep the NMOS transistor M4 on for a period of time T2 to achieve soft turn off. After the time T2 expires, the NMOS transistor M2 in the standard gate drive circuit 66 is turned back on, providing a strong pull-down for the gate drive voltage node 76, and at the same time the NMOS transistor M4 is turned off.

Figure 9 shows a timing diagram of the operation of the controller circuit shown in Figure 8 in some embodiments. Referring to Figure 9, the input signal V _IN (curve 152) is a PWM signal that turns on and off the IGBT, and conducts the current through the induction coil alternately. The high voltage indication signal HT (curve 154) is generated by the HTOD protection circuit 90 to be transmitted by the blocking system input signal V _IN . When the collector voltage at the IGBT is too high, the IGBT is driven. During normal operation, the gate voltage V _gctrl (curve 160) of the IGBT switches between the ground voltage and the voltage source voltage Vdd, turning the IGBT on and off. At the same time, the collector current i _c (curve 158) increases linearly during the IGBT on time, and then decreases to zero during the IGBT off time. During normal operation, the gate control signals of the transistors M1 and M2 (curves 162 and 164) have a logic low potential during the IGBT on time and a logic high potential during the IGBT off time. During normal operation, the gate control signal of transistor M3 (curve 166) is at a logic high level, and the gate control signal of transistor M4 (curve 168) is at a logic low level to disable the protection gate drive circuit.

During the IGBT on time, the collector-emitter voltage V _CE (curve 156) is driven to the collector-emitter voltage V _CE-SAT . Then, when the IGBT is turned off, the collector voltage can be increased to a large voltage value, such as 600V. IGBT usually has a rated voltage of 1.7kV and can withstand the standard collector voltage stroke during normal operation of the IGBT.

During the IGBT off time, both the hard-on detection circuit and the hysteresis overvoltage detection circuit monitor the collector voltage V _{CE of the} IGBT. At time t1, the collector voltage V _{CE of the} IGBT exceeds the set voltage potential of HTOD. In an example, the HTOD setting voltage potential corresponds to a collector voltage of about 400V. Therefore, the high voltage indication signal HT takes effect, and the HTOD protection circuit blocks the system input signal VIN, preventing it from being transmitted to the standard gate drive circuit.

However, at t2, a specific power surge event causes the collector voltage V _{CE to} exceed the set voltage potential of the hysteresis overvoltage detection circuit. In an example, the set voltage potential corresponds to a collector voltage of about 1.4kV. The hysteresis over-voltage detection circuit activates the fault detection indication signal. In a very short period of time, remedial measures were initiated. The gate control signal of transistor M2 is disabled (logic low), turning off transistor M2. The gate control signal of the transistor M3 is enabled (logic low), turning on the transistor M3, and the gate control signal of the transistor M4 is enabled (logic high), turning on the transistor M4. Since the transistors M3 and M4 are turned on, the gate voltage of the IGBT rises to the clamped gate voltage value determined by the Z3/Z4 voltage divider. The IGBT is turned on by the clamped gate voltage and conducts the collector current ic to dissipate the power surge. Therefore, the collector voltage V _CE decreases.

At t3, the collector voltage V _CE drops below the reset voltage potential of the hysteresis overvoltage detection circuit. In an example, the reset voltage potential corresponds to a collector voltage of about 1.2 kV. Hysteresis over-voltage detection circuit failure failure detection indication signal, and transistor M3 failure (logic high). The transistor M4 remains turned on for an extended period of time T2 to discharge the gate voltage of the IGBT. At t4, after the time T2 expires, the transistor M4 is turned off, the transistor M2 is turned on, and normal operation is resumed.

At t5, the collector voltage V _CE drops below the HTOD reset voltage potential, the HTOD protection circuit fails the high voltage indicator signal HT, and normal operation resumes.

At t6, the collector voltage V _{CE of the} IGBT exceeds the HTOD setting voltage potential. Therefore, the high voltage indication signal HT takes effect, and the HTOD protection circuit blocks the system input signal V _{IN from being} transmitted to the standard gate drive circuit. At this time, noise or other system problems can cause incorrect system input signal pulses. Those signal pulses are not the system input signal noise that we expected. If the IGBT is turned on when the power switch is high collector voltage, then the IGBT will suffer hard switching. However, the HTOD protection circuit of the present invention is activated, blocking the wrong system input pulse.

At t7, the collector voltage V _CE drops below the HTOD reset voltage potential, the HTOD protection circuit fails the high voltage indicator signal HT, and normal operation is restored.

Figure 10 shows the collector voltage and collector current of the IGBT when a power surge event occurs in some examples. First, referring to Figure 7, the purpose of the HTOD protection circuit is to block unnecessary system input signals when the power switch is turned off to prevent hard switching of the power switch (IGBT). At the same time, an OVCP protection circuit is provided so that the energy induced in the resonance induced current Lr is consumed in the IGBT, and the capacitor voltage Cr is clamped so that the collector voltage V _CE will not increase above the IGBT damage potential. Now referring to Figure 10, the system input signal V _IN (curve 170) is displayed for a period of time. It represents the collector voltage V _{CE of the} IGBT (curve 172) and its corresponding collector current i _C (curve 174), using the corresponding setting and resetting voltage potentials in the hysteresis overvoltage detection circuit and the HTOD protection circuit. Note that the set and reset voltage potentials shown in Figure 10 are the corresponding voltage potentials used in the hysteresis overvoltage detection circuit and the HTOD protection circuit. The hysteresis overvoltage detection circuit and the HTOD protection circuit receive the step-down collector voltage for detection. Therefore, the setting and reset voltage potential used in the detection circuit corresponds to the step-down voltage potential.

At t1, the collector voltage V _{CE is} higher than the HTOD setting voltage potential, the HTOD protection circuit is activated, and the system input signal V _{IN is} blocked. Therefore, although the system input signal V _IN is switching, the IGBT is still disconnected.

However, at t2, a power surge occurs at the collector terminal of the IGBT, and the collector voltage increases to the OV set voltage potential. The protective gate drive circuit is activated, and the IGBT is turned on under the clamp voltage potential. The collector current i _C gradually increases, and the clamped gate voltage is applied to the IGBT. The current flowing direction of the coil current i _Lr changes. The coil current i _Lr no longer circulates between the induction coil Lr and the capacitor Cr, but flows to the IGBT and is dissipated to the ground by the IGBT. Therefore, the collector voltage V _CE is clamped and does not increase further. When the current i _C is equal to the current i _Lr at time t3, the voltage V _CE begins to drop through the discharge of the capacitor Cr, and the voltage drop slope is determined by the collector current i _C and the capacitance value of the capacitor Cr. Once the voltage V _CE reaches the OV reset voltage potential at time t4, the protective gate drive circuit is disabled, and the collector current i _C is controlled by the soft gate to cut off in order to obtain a safe shutdown. The current drop time interval (t4-t5) makes the voltage V _CE slightly lower than the OV reset voltage potential.

When the OVCP protection interval is completed at t5, the HTOD protection interval continues until the collector voltage V _CE drops below the HTOD reset voltage potential at t6. At t6, the HTOD protection circuit is touched, and the system input signal V _IN will be run through. Therefore, the IGBT resumes normal operation.

Figure 11 shows a flowchart of a method for providing hard-on/disable protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention. Referring to Figure 11, the hard-on protection method 250 monitors the feedback voltage, and the feedback voltage represents the voltage on the power switch during the off time of the power switch (252). Compare the feedback voltage with the HTOD set voltage potential (254). When the feedback voltage is lower than the HTOD setting voltage level, the method 250 continues to monitor the feedback voltage representing the voltage on the power switch. On the other hand, when the feedback voltage is higher than the HTOD setting voltage level, the method 250 blocks the system input signal from being transmitted to the standard gate drive circuit (256). For example, the control signal Vc for driving the standard gate drive circuit can be kept at a logic low level, so that the standard gate drive circuit is disabled.

The method 250 continues to monitor the feedback voltage to determine whether the feedback voltage drops below the HTOD reset voltage potential (258). The HTOD reset voltage potential is lower than the HTOD set voltage potential. When the feedback voltage is lower than the HTOD reset voltage level, the method 250 allows the system input signal to be transmitted to the standard gate drive circuit for the normal operation of the power switch (260). The method 250 resumes monitoring the feedback voltage representing the voltage on the power switch during the off time of the power switch (252).

Figure 12 shows a flowchart of a method for providing bi-potential protection for power switching elements in a quasi-resonant inverter circuit in an embodiment of the present invention. Referring to Figure 12, during the off time of the power switch (302), the bi-potential protection method 300 monitors the feedback voltage representing the voltage on the power switch. The feedback voltage is compared with the HTOD setting voltage potential and the overvoltage setting voltage potential OV_Set (304), and the HTOD setting voltage potential is lower than the overvoltage setting voltage potential. When the feedback voltage is lower than the HTOD setting voltage level, the method 300 continues to monitor the feedback voltage representing the voltage on the power switch. On the other hand, when the feedback voltage is higher than the HTOD setting voltage level, the method 300 blocks the system input signal and transmits it to the standard gate drive circuit (306). For example, the control signal Vc for driving a standard gate drive circuit can be kept at a logic low level to disable the standard gate drive circuit.

Method 300 continues to monitor the feedback voltage. When the voltage level is set according to the feedback voltage being greater than the overvoltage, the method 300 activates the overvoltage clamp protection (OVCP), softly turns on the power switch, and clamps the gate voltage of the power switch (308). In this case, the excess voltage at the power switch is dissipated.

The method 300 continues to monitor the feedback voltage (310). When the feedback voltage drops below the overvoltage reset voltage potential OV_Reset, the overvoltage clamp protection is released (312). In addition, when the feedback voltage drops below the HTOD reset voltage level, the method 300 allows the system input signal to be transmitted to a standard gate drive circuit for normal operation of the power switch (314). HTOD reset voltage potential is lower than Overvoltage reset voltage potential. During the off time of the power switch (302), the method 300 resumes monitoring the feedback voltage representing the voltage on the power switch.

Although the above content describes the embodiments in detail for the sake of clarity, the present invention is not limited to the above details. There are many alternatives for implementing the present invention. The embodiments in the text are only for explanation and not for limitation.

10: Quasi-resonant inverter

12: AC input voltage

14: Surge suppressor

16: Bridge rectifier

18, 20, 22, 24, 32, 38, 52: nodes

30: Control circuit

34: Standard gate drive circuit

36: Gate logic circuit

40: Protect gate drive circuit

42, 46: time controller

44, 48: Gate control circuit

50: Overvoltage detection circuit

54: Input node

Claims (15)

A controller circuit for generating a gate drive signal on an output node to drive a gate terminal of a power switch, the gate terminal controlling the power switch between a first power terminal and a second power terminal Flowing current, the controller circuit includes: a first gate drive circuit for receiving an input control signal and generating a first output signal as the gate drive signal to drive the gate terminal of the power switch, According to the input control signal, the power switch is turned on and off, the first output signal has a first gate voltage value, the gate terminal of the power switch is driven to turn on the power switch; and a hard-on disable A circuit for generating the input control signal according to a system input signal and a first voltage, the first voltage representing the voltage between the first power terminal and the second power terminal of the power switch, and the system input signal determines The hard-on-disable circuit generates a high-voltage indication signal for a turn-on time and a turn-off time of the power switch. When the first voltage exceeds a first threshold, the high-voltage indicator signal becomes effective; otherwise, the high-voltage indicator The signal becomes invalid; wherein, according to the effective high voltage indication signal, the hard-on disable circuit generates the input control signal, the input control signal has a first logic state, and prevents the system input signal from being provided to the first gate driver According to the failed high voltage indicator signal, the hard-on disable circuit generates an input control signal mirroring system input signal to drive the first gate drive circuit. The controller circuit described in item 1 of the scope of patent application, wherein the hard-on disable circuit includes a hysteresis detection circuit, the hysteresis detection circuit has a set voltage potential and a reset voltage potential, the set voltage potential is higher than the Reset voltage When the first voltage is at the set voltage level or higher than the set voltage level, the hysteresis detection circuit activates the high voltage indication signal, and according to the first voltage at the reset voltage level or lower than the reset voltage level At this time, the hysteresis detection circuit fails the high-voltage indication signal. The controller circuit described in item 2 of the scope of patent application, wherein the hard-on disable circuit further includes a D-flip-flop, the D-flip-flop having a data input terminal coupled to a forward voltage source voltage, The clock input terminal is coupled to the system input signal, a reset terminal is coupled to the signal representing the high voltage indicator signal, and an output signal is generated, wherein the D-flip-flop is set to a signal according to the effective high voltage indicator signal In reset mode. The controller circuit described in item 3 of the scope of patent application, wherein the hard-on disable circuit further includes a logic AND gate for receiving the system input signal and the output signal of the D-flip-flop, the logic AND gate Generate the input control signal. The controller circuit described in the first item of the scope of patent application, wherein the first gate drive circuit includes a first transistor, a first impedance, a second impedance and a second transistor, connected in series with a forward voltage source Between voltage and a ground voltage, a common node between the first impedance and the second impedance is the output node, wherein the first gate drive circuit turns on the first transistor and turns off the second transistor , To activate the first output signal, turn on the power switch, the first gate drive circuit turns off the first transistor, and turn on the second transistor, to disable the first output signal, turn off the power switch And according to the effective high voltage indication signal, the first gate driving circuit turns off the first transistor and turns on the second transistor to disable the first output signal and turn off the power switch. The controller circuit described in item 1 of the scope of patent application, wherein the first voltmeter Shows the voltage between the first power terminal and the second power terminal of the power switch during the off time of the power switch. The controller circuit described in the first item of the scope of patent application, wherein the power switch includes an insulated gate bipolar transistor element. A method of generating a gate driving signal for driving a gate terminal of a power switch, wherein the gate terminal controls the current flowing between a first power terminal and a second power terminal of the power switch, and the generating gate The method of driving the signal includes: monitoring a feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch; providing a high voltage indicator signal; determining that the feedback voltage exceeds a first threshold; according to the determined If the feedback voltage exceeds the first threshold, the high voltage indication signal is activated; it is determined that the feedback voltage is lower than the first threshold; according to the determined feedback voltage is lower than the first threshold, the high voltage indication signal is disabled; The high voltage indicator signal provides a system input signal to drive the power switch to turn on and off. The system input signal determines the on time and the off time of the power switch; and the effective high voltage indicator signal prevents The system input signal enters the power switch, and the power switch is turned off regardless of the state of the system input signal. The method for generating gate drive signals as described in item 8 of the scope of patent application, wherein Determining that the feedback voltage exceeds the first threshold potential includes the following steps: determining that the feedback voltage exceeds a set voltage potential; and determining that the feedback voltage is lower than the first threshold potential includes determining that the feedback voltage is lower than a reset voltage potential, the The set voltage potential is higher than the reset voltage potential. For example, the method for generating a gate drive signal as described in item 9 of the scope of the patent application further includes the following steps: after the high voltage indication signal is activated, the high voltage indication signal is invalidated when the feedback voltage drops below the reset voltage level . The method for generating a gate drive signal as described in item 8 of the scope of patent application, wherein monitoring the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch includes the following steps: During the off time of the switch, the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch is monitored. A controller circuit for generating a gate driving signal on an output node to drive a gate terminal of a power switch, the gate terminal controlling the flow between a first power terminal and a second power terminal of the power switch The controller circuit includes: a first gate drive circuit for receiving an input control signal and generating a first output signal as the gate drive signal to drive the gate terminal of the power switch according to The input control signal turns on and off the power switch, the first output signal has a first gate voltage value, drives the gate terminal of the power switch, and turns on the power switch; A first protection circuit for generating the input control signal according to a system input signal and a feedback voltage, the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch, the system input The signal determines an on time and an off time of the power switch. When the feedback voltage exceeds a first threshold potential, the first protection circuit generates the input control signal to prevent the system input signal from being provided to the first A gate drive circuit; and a second protection circuit for receiving the feedback voltage and generating a fault detection indication signal. When the feedback voltage exceeds a second threshold potential, the second protection circuit activates the fault detection indication signal, The second threshold potential is higher than the first threshold potential, and the second protection circuit is configured to generate a second output signal as the gate drive signal. According to the effective fault detection indication signal, a second gate The power switch is turned on for a predefined time under the voltage value. The controller circuit described in item 12 of the scope of patent application, wherein according to the feedback voltage being lower than the first threshold potential, the first protection circuit generates an input control signal mirroring system input signal to drive the first gate drive Circuit. A method of generating a gate driving signal for driving a gate terminal of a power switch, wherein the gate terminal controls the current flowing between a first power terminal and a second power terminal of the power switch, and the generating gate The method of driving the signal includes: monitoring a feedback voltage, the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch; determining that the feedback voltage exceeds a first threshold potential; According to the determination result, prevent a system input signal from entering the power switch, the system input signal determines an on time and an off time of the power switch, regardless of the state of the system input signal, turn off the power switch; confirm The feedback voltage exceeds a second threshold potential, and the second threshold potential is higher than the first threshold potential; according to the determination result, a clamp gate driving signal with a clamp gate driving voltage value is generated, and the clamp is used Bit gate drive signal to turn on the power switch; and continue to monitor the feedback voltage representing the voltage between the first power terminal and the second power terminal of the power switch. The method for generating a gate drive signal as described in item 14 of the scope of patent application further includes the following steps: determining that the feedback voltage is lower than the first threshold potential; and according to the determination result, providing the system input signal to drive the power supply The switch is on and off.

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