TWI525980B - Method for over load condition evaluation - Google Patents

Description

Circuit and method for judging load state in flyback converter

The present invention mainly relates to a power conversion system, and more specifically to detecting and calculating an output current in a voltage flyback converter applied to a power supply field, and determining whether the converter enters an overload state.

In a conventional power conversion system, a switching power supply method that performs constant voltage or constant current control is usually employed. Controlling the opening or opening of the switching element on the primary winding of the transformer in the power conversion system, periodically generating a current flowing through the switching element on the primary winding of the transformer, and transferring the energy of the primary side to the secondary side, The alternating current generated in the windings is rectified and filtered by the injected diodes and capacitors, and then converted into direct current to supply the load.

However, how to accurately budget the output current supplied to the load is a difficult problem to be solved, because this is one of the main factors for us to accurately design the topology, especially in the current continuous mode CCM and the current interrupt mode DCM. Under the premise, calculating the output current is a problem that is difficult for the prior art. Further, how to set the calculated output current or the current proportional to the output current as the basis for judging whether the flyback voltage converter enters the overload state is a problem that we need to solve.

A circuit for determining a load state in a flyback converter according to the present invention includes: a detection module that detects a primary current flowing through a sense resistor in series with the primary winding and is used to control the primary winding When a main switch that is turned on or off is turned off by a control signal, the off current value I _OFF flowing through the sense resistor is detected, and a leading edge shield signal for shielding the primary current start spike is blocked. At the instant of the end of the active state, the leading edge shielding current value I _LEB flowing through the sensing resistor is detected; a first current source providing a preset current I _SUM and a second current source providing a reference current I _REF , the preset current I _SUM includes a sum value factor obtained by adding the off current value I _OFF and the leading edge shading current value I _LEB , which can be understood as the preset current I _SUM and the sum value are set to a predetermined proportional relationship K; a first capacitor charged by the current source and a second capacitor charged by the second current source; a comparator for inputting a voltage varying from the first capacitor to the non-inverting input of the comparator and to the second The varying voltage is input to the inverting input of the comparator. When the output current of the flyback converter is transmitted to the load changes to cause the preset current I _{SUM to} change, the comparison result of the comparator output is used to detect the load state.

In the above circuit, the preset current I _SUM is equal to one-half of the sum of the sum of the off current value I _OFF and the leading edge shading current value I _LEB . In the above circuit, a switch is connected between the first current source and the first capacitor, and the switch is turned on only during the off period _TOFF of the main switch in each period T _S of the main switch, in each period The rest of the time is turned off.

In the above circuit, the capacitance value of the first capacitor is C ₁₁ and the capacitance value of the second capacitor is C ₁₂ , and whether the preset current I _SUM exceeds a set rated current value I _SUM1 to determine whether the load enters an overload state, and

In the above circuit, a switch is connected between the second current source and the second capacitor, and the switch is turned on at the time when each cycle of the main switch starts to be turned on until one-half of the time of each cycle is Turning off; and the second current source provides twice the reference current I _REF such that the total voltage charged by the second capacitor at the end of one-half of the total time of the period T _S is maintained at:

In the above circuit, the capacitance value C ₁₁ of the first capacitor is set equal to the capacitance value C _{12 of the} second capacitor.

In the above circuit, when the actual preset current I _SUM exceeds the rated current value I _SUM1 , the output of the comparator will be flipped from the low level to the high level during the off period T _OFF of the main switch in each period T _S . Or when the actual preset current I _{SUM is} lower than the rated current value I _SUM1 , the output of the comparator is maintained at a low level in each period T _S .

The above circuit further includes a monostable flip-flop that receives the output of the comparator and a counter including the one connected to the one-shot, each time the comparator flips from a low level to a rising edge of a high level, monostable The flip-flop outputs a high-level signal to the counter. When the counter receives a high-level signal from the one-shot trigger output in each of successive cycles, the counter issues a load into the heavy load state. Overload protection signal.

The above circuit, comprising a switch in parallel with the first capacitor and a switch in parallel with the second capacitor, is triggered to be turned on at the end of each cycle, thereby connecting the switch in parallel with the first capacitor and the second capacitor The switch is turned on to synchronously discharge the first and second capacitors.

The circuit further includes a sample-and-hold latch, the detection module having a first voltage-current converter for collecting a voltage sensing signal across the sensing resistor for characterizing the magnitude of the primary current, and sensing the voltage The measurement signal is converted into an intermediate current flowing through a conversion resistor connected between the current output end of the first voltage current converter and the ground; at the instant when the main switch is turned off, the detection module applies the instant to the conversion resistor The voltage applied to the voltage sensing signal corresponding to the shutdown current value I _OFF is sent to the sample-and-hold latch for storage; at the instant when the active state of the leading edge masking signal ends, the detecting module applies the instant to the switching resistor. The voltage on the upper side is converted into a voltage sensing signal corresponding to the leading edge shielding current value I _{LEB and} supplied to the sample-and-hold latch for storage.

In the above circuit, the detecting module comprises a first voltage follower, the positive input end of which is connected to the current output end of the first voltage current converter; the first storage of the first voltage follower and the first storage of the sample hold latch A first switch driven by the control signal is connected between one end of the capacitor, and the control signal is turned from the first state to the second state. When the main switch is turned off, the first switch is turned off synchronously, and the intermediate current is on the conversion resistor. The generated voltage is converted by the first voltage follower into a voltage sensing signal corresponding to the off current value I _OFF stored in the first storage capacitor.

In the above circuit, the detecting module comprises a second voltage follower whose positive input terminal is connected to the current output end of the first voltage current converter; at the output end of the second voltage follower and the second storage of the sample hold latch A second switch driven by the leading edge shielding signal is connected between one end of the capacitor. When the leading edge shielding signal is turned from the first state to the second state, the second switch is synchronously turned off, and the intermediate current is on the switching resistor. The generated voltage is converted by the second voltage follower into a voltage sensing signal corresponding to the leading edge shielding current value I _{LEB and} stored in the second storage capacitor.

The above circuit further includes a current summation unit having a second voltage current converter for recovering the voltage sensing signal corresponding to the off current value I _OFF stored by the sample holding latch to be converted from the second voltage current converter The current output terminal outputs a current equivalent to the off current value I _OFF ; the current summation unit has a third voltage current converter that stores the voltage sensing signal corresponding to the leading edge shielding current value I _LEB stored in the sample holding latch Reverting to a current equivalent to the leading edge shielding current value I _LEB flowing from the current output terminal of the third voltage current converter; the current output of each of the second and third voltage current converters is concentrated by the current output of both a sum resistance between the common node and the ground terminal at the terminal interconnection, and the current input unit has a positive input terminal of a third voltage follower connected to the common node, and the voltage V _TRS output by the third voltage follower is equal to (I _LEB + I _OFF ) is multiplied by the resistance value R _{SUM of the} sum resistance, thereby summing the sum of the off current value I _OFF and the leading edge shading current value I _LEB .

In another embodiment, the present invention also provides a method of determining a load state in a flyback converter, comprising the steps of: detecting a primary current flowing through a sense resistor in series with the primary winding, and for controlling When a main switch of the primary winding is turned on or off is turned off by a control signal, the off current value I _OFF flowing through the sense resistor is detected, and a leading edge shield for shielding the primary current start spike is masked. At the instant when the effective state of the signal ends, the leading edge shielding current value I _LEB flowing through the sensing resistor is detected; the first current source providing the preset current I _SUM is used to charge the first capacitor and the first reference current I _REF is utilized The two current sources charge the second capacitor, and the preset current I _SUM includes a sum value factor obtained by adding the off current value I _OFF and the leading edge shielding current value I _LEB , which can be understood as the preset current I _SUM and the sum value. The factor is substantially set to a predetermined proportional relationship K; the voltage that varies across the first capacitor is input to the non-inverting input of a comparator and the voltage that varies across the second capacitor is input to The inverting input of the comparator detects the load state by using the comparison result of the comparator output when the output current of the flyback converter is changed to the load causing the preset current I _{SUM to} change.

In the above method, the preset current I _SUM is set to be equal to one-half of the sum of the sum of the off current value I _OFF and the leading edge shading current value I _LEB . In the above method, a switch is connected between the first current source and the first capacitor, and the switch is turned on only during the off period _TOFF of the main switch in each period T _S of the main switch, which is the first capacitor. Charging, shutting down for the rest of each cycle.

In the above method, the capacitance value of the first capacitor is set to C ₁₁ and the capacitance value of the second capacitor is C ₁₂ , and whether the preset current I _SUM exceeds a set rated current value I _SUM1 to determine whether the load enters an overload state, and

In the above method, a switch is connected between the second current source and the second capacitor, the switch is turned on at the time when each cycle of the main switch starts to be turned on, and the second capacitor is charged until two cycles of each cycle. One of the moments is turned off; and the second current source provides twice the reference current I _REF such that the total voltage charged by the second capacitor at the end of one-half of the total time of the period T _S is maintained at:

In the above method, the capacitance value C ₁₁ of the first capacitor is set equal to the capacitance value C _{12 of the} second capacitor.

In the above method, when the actual preset current I _SUM exceeds the rated current value I _SUM1 , the output of the comparator is flipped from the low level to the high level during the off period T _OFF of the main switch in each period T _S . Or when the actual preset current I _{SUM is} lower than the rated current value I _SUM1 , the output of the comparator is maintained at a low level in each period T _S .

The above method further includes a one-shot trigger that receives the output of the comparator and a counter including the one connected to the one-shot, each time the comparator flips from a low level to a rising edge of a high level, monostable The flip-flop outputs a high-level signal to the counter. When the counter receives a high-level signal from the one-shot trigger output in each of successive cycles, the counter issues a characteristic that the load enters the heavy load state. Overload protection signal.

In the above method, a switch connected in parallel with the first capacitor and a switch connected in parallel with the second capacitor are triggered to be turned on at the end of each cycle, and the switch connected in parallel with the first capacitor and the switch connected in parallel with the second capacitor It is turned on to perform instantaneous discharge on the first and second capacitors in synchronization.

The above method provides a sample-and-hold latch, the detection module has a first voltage-current converter that collects a voltage sensing signal across the sensing resistor for characterizing the primary current magnitude, and senses the voltage The signal is converted into an intermediate current flowing through a switching resistor connected between the current output end of the first voltage current converter and the ground; at the instant when the main switch is turned off, the detecting module applies the instant to the switching resistor The voltage is converted into a voltage sensing signal corresponding to the shutdown current value I _{OFF and} sent to the sample-and-hold latch for storage; at the instant when the active state of the leading edge masking signal ends, the detecting module applies the instant to the switching resistor. The voltage is converted to a voltage sensing signal corresponding to the leading edge shielding current value I _{LEB and} supplied to the sample and hold latch for storage.

In the above method, the detecting module includes a first voltage follower whose positive input terminal is connected to the current output end of the first voltage current converter; at the output end of the first voltage follower and the first storage of the sample hold latch A first switch driven by the control signal is connected between one end of the capacitor, and the control signal is turned from the first state to the second state. When the main switch is turned off, the first switch is turned off synchronously, and the intermediate current is on the conversion resistor. The generated voltage is converted by the first voltage follower into a voltage sensing signal corresponding to the off current value I _OFF stored in the first storage capacitor.

In the above method, the detecting module includes a second voltage follower whose positive input terminal is connected to the current output end of the first voltage current converter; at the output end of the second voltage follower and the second storage of the sample hold latch A second switch driven by the leading edge shielding signal is connected between one end of the capacitor. When the leading edge shielding signal is turned from the first state to the second state, the second switch is synchronously turned off, and the intermediate current is on the switching resistor. The generated voltage is converted by the second voltage follower into a voltage sensing signal corresponding to the leading edge shielding current value I _{LEB and} stored in the second storage capacitor.

The above method provides a current summation unit having a second voltage current converter for recovering the voltage sensing signal corresponding to the off current value I _OFF stored in the sample holding latch to be converted from the second voltage current converter The current output terminal outputs a current equivalent to the off current value I _OFF ; the current summation unit has a third voltage current converter that stores the voltage sensing signal corresponding to the leading edge shielding current value I _LEB stored in the sample holding latch Reverting to a current equivalent to the leading edge shielding current value I _LEB flowing from the current output terminal of the third voltage current converter; the current output of each of the second and third voltage current converters is concentrated by the current output of both a sum resistance between the common node and the ground terminal at the terminal interconnection, and the current input unit has a positive input terminal of a third voltage follower connected to the common node, and the voltage V _TRS output by the third voltage follower is equal to (I _LEB + I _OFF ) is multiplied by the resistance value R _{SUM of the} sum resistance, thereby summing the sum of the off current value I _OFF and the leading edge shading current value I _LEB .

101, 103, 105, 106, 107, 121, 123, 124, 311, 312‧‧ ‧ nodes

102‧‧‧Main control module

110, 113, 114‧‧‧Voltage current converter

111‧‧‧First voltage follower

112‧‧‧Second voltage follower

128‧‧‧ Third voltage follower

130‧‧‧Transformers

130A‧‧‧Primary winding

130B‧‧‧Secondary winding

130C‧‧‧Auxiliary winding

201‧‧‧Detection module

202‧‧‧Sampling and holding latches

203‧‧‧ Current summation unit

271‧‧‧current source

280‧‧‧Computation circuit

301‧‧‧dipole

302‧‧‧Transconductance amplifier

315, 316‧‧‧ current source

328‧‧‧ Comparator

329‧‧‧monostable trigger

330‧‧‧ counter

350‧‧‧Overload detection circuit

SW1, SW2, SW10, SW11, SW12, SW13, SW21, SW22, SW31, SW32‧‧‧ switch

R10‧‧‧resistance

R11‧‧‧Adjustment resistance

R12‧‧‧Switching resistor

R14‧‧‧Total resistance

R23‧‧‧resistance

R _L ‧‧‧load

R _S ‧‧‧resistance resistor

QM‧‧‧ main switch

D _AUX , D _O ‧‧‧ diode

C _AUX , C _O , C ₁ ‧‧‧ capacitor

C ₂ ‧‧‧First storage capacitor

C ₃ ‧‧‧Second storage capacitor

C11‧‧‧first capacitor

C12‧‧‧second capacitor

Fig. 1 shows a schematic circuit diagram of a flyback converter of the present invention.

Figure 2A is the primary current and secondary current waveforms generated by the CCM mode control signal driving the main switch.

Figure 2B is a diagram showing the primary and secondary current waveforms generated by the DCM mode control signal driving the main switch.

Fig. 3 is a leading edge occlusion signal waveform for shielding the leading edge of the sensing signal from the moment when the main switch is turned on.

4A-4C shows a stepped current waveform corresponding to each of the primary current and the secondary current in the CCM mode.

5A-5C shows the triangular wave current waveform corresponding to the primary current and the secondary current in the DCM mode.

Figures 6A-6D are conventional calculation circuits for calculating the average output current.

Figure 7 is a calculation circuit for detecting the off current value and the leading edge shading current value and summing them.

Figure 8 is an overload detection circuit for calculating the average output current and interpreting whether it is overloaded.

Figure 9 is a waveform diagram of the second capacitor being charged throughout the cycle.

Figure 10 is a waveform diagram of the second capacitor charging in one-half cycle.

Figure 11 shows the change in output from the light load transition to the heavy duty monoflop in DCM mode.

Figure 12 shows the change in output from the light load transition to the heavy duty monoflop in CCM mode.

Figure 13 shows an example of a calculation circuit.

Referring to Fig. 1, there is shown a circuit structure of a typical flyback voltage converter according to the present invention. The electronic main switching element QM for controlling the primary side can be, for example, a power MOSFET having an input terminal such as a drain terminal. And an output having, for example, a source terminal, and a control terminal having, for example, a gate. The main switch QM receives the control signal sent by the main control module 102 on its control end and performs a corresponding open or open response action, so that the main switch QM can be turned on or off to the transformer 130 of the flyback converter. The current flowing on the primary winding 130A is controlled to be turned on or off to transfer the energy of the primary side to the secondary side. The primary winding 130A is for receiving an input DC input voltage V _IN , and the DC input voltage V _IN can be rectified by, for example, a commercial AC voltage V _AC through a rectifying element such as a bridge rectifier. The transformer 130 also has a secondary winding 130B for delivering an output voltage V _OUT , and an auxiliary winding 130C for detecting a voltage state generated on the secondary winding 130B. The auxiliary winding 130C and the secondary winding 130B have the same polarity but They are opposite in polarity to the primary winding 130A. One end of the auxiliary winding 130C is grounded and the other end is connected to the anode of a diode D _AUX , wherein the cathode of the diode D _AUX is connected to a capacitor C _AUX to rectify the AC voltage generated on the auxiliary winding 130C. C _{AUX is} charged to be used as an auxiliary power source. The voltage V _CC stored on the capacitor C _AUX is associated with the output voltage V _OUT and has a proportional relationship with V _OUT . The voltage V _CC can provide a DC voltage source for the main control module 102 alone. . A rectifying filter circuit of a diode D _O and a capacitor C _O is connected to the secondary winding 130B for generating an output voltage V _{OUT of the} flyback converter. The DC output voltage V _{OUT is} applied to the load R _L and forms an output current I _OUT flowing through the load R _L . In the feedback network of the converter, a sense resistor R _S is connected between the source terminal of the main switch QM and the ground GND, and the sense resistor R _{S is} used to sense and detect the primary current I _P flowing through the primary winding 130A and provide A feedback voltage equal to the current I _P multiplied by its resistance value R _S , that is, the sensing signal V _CS , the primary current I _P can be used as a function to characterize the secondary current I _S flowing through the secondary winding 130B. The relationship will be described in detail later. The sensing port CS of the main control module 102 detects the primary current I _P signal of the primary winding 130A by the sensing resistor R _S as a basis for determining whether the control signal needs to be adjusted to adjust the opening or closing of the main switch QM. Those skilled in the art are familiar with the topology and operation mode of the flyback converter, and the circuit parts and specific operation modes that can be omitted are not described herein.

Referring to the current continuous conduction (CCM) mode of FIG. 2A, the main switch QM is switched under the driving of a similar control signal such as a pulse width modulation signal PWM. Figure 2A plots the approximate waveform of the primary current I _P1 flowing through the primary winding 130A and the secondary current I _S1 flowing through the secondary winding 130B, and also generally shows the voltage difference V _DS1 between the drain and source of the main switch QM. . In the turn-on period T _{ON of the} main switch QM, the primary current I _P1 has a leading edge step and ramps up from the leading edge, and during the T _OFF turn-off of the main switch QM, the secondary current I _S1 is a triangular wave of superimposed attenuation on the step. When the main switch QM is ready to start conducting at the next cycle, substantially the secondary winding 130B still maintains a current, that is, at the turn-on time of the next cycle of the main switch QM, the energy stored by the transformer 130 is not completely released, still There is energy remaining.

See Figure 2B. In sharp contrast to the CCM mode of the flyback converter, the primary current I _P2 flowing through the primary winding 130A and the current discontinuous DCM (Discontinuous Conduction Mode) mode are also shown. The approximate waveform of the secondary current I _S2 flowing through the secondary winding 130B also substantially exhibits the voltage difference V _DS2 between the drain and the source of the main switch QM, and there is no step value at the leading end of the primary current I _P2 in the DCM mode. And in the off period T _{OFF of the} main switch QM, the secondary current I _S2 is an attenuated triangular wave, and has decayed to zero at the end of T _OFF before the start of the next cycle, and the main switch QM is stored in the primary winding during the on period. The energy of 130A has been transferred almost to the load by secondary winding 130B before the start of the next cycle. Note that in any one of the DCM modes, there is a great difference from the CCM mode in that the secondary current I _S2 drops to zero during the control signal turning off the main switch QM, and the secondary current I _S2 is reduced to zero. There is a Dwell dead time T _D between this time and the beginning of the next cycle (ie, the main switch QM starts to turn on again).

Referring to Fig. 3, in order to avoid unnecessary erroneous operation in the step of detecting the primary current I _P , a leading edge blanking signal LEB (Leading edge blanking) well known to those skilled in the art is introduced because of the primary current control. In the loop, it is often encountered that the primary current I _P has a pulse initial peak current phenomenon at the turn-on moment of the main switch QM, and the initial peak spike embodied is fed back to the main control module 102 at the sensing port CS. The current value at this time is sampled by the inductive resistor R _S connected in series on the primary winding and is switched and controlled as the sensing signal V _CS , which may be caused by the unexpected initial spike Spike 355 of the sensing signal V _CS in FIG. The triggering action further activates the overcurrent protection mechanism, so that the main control module 102 that generates the control signal no longer outputs the pulse width modulation signal, thereby actively inducing the action of erroneously turning off the power main switch QM without a real overcurrent abnormality. To achieve the purpose of protecting the power switch and the entire converter. The variable or fixed leading edge masking signal LEB generated by the conventional leading edge masking circuit is used to eliminate such false triggering, and the signal can be coupled to the control terminal of the main switch QM to ensure that it has a leading edge masking signal LEB. The high level period is not turned off, and after the leading edge masking signal LEB ends, the current signal is sampled on the sensing resistor R _S to capture the initial value of the more realistic and accurate sensing signal V _{CS to} realize the main switch QM. The pulse start peak of the primary current I _P is turned on for shielding. As to how to design the leading edge shielding circuit is not the focus of the present invention, the conventional power supply design instruction manual generally has a more detailed description of the leading edge shielding circuit, and can also refer to the published US patent application US 12/492,748, US 12/718,707, and the like.

Referring to Figures 4A-4C, when the flyback converter enters CCM mode, the control signal will drive the main switch QM to turn on at time t _{11 of the} beginning of a cycle. Since the energy of the transformer 130 in the previous cycle remains, the primary current I _P At the instant when the main switch QM is turned on, it rapidly jumps from zero value to a leading edge initial value I _PV , and the leading edge initial value I _PV is an initial leading edge step value greater than zero. And immediately after the period from t ₁₁ to t ₁₃ , since the control signal always drives the main switch QM to be turned on, during this time, the primary current I _P continues on the basis of the initial value I _PV of the leading edge, with a certain rising slope. Gradually rising. To note, at ₁₃ time t, the control signal is inverted from the high level to the low level state and is intended to open the main switch QM, the primary current I _P is not found to fall directly, but at time T ₁₃ to time t ₁₄ which During the segment turn-off delay time T _P , the primary current I _P overshoots to the peak current I _PP with the highest current I _P at the same rising slope as the period from t ₁₁ to t ₁₃ until the end of the delay time T _P The t ₁₄ primary current I _P quickly drops from the peak I _PP to zero. FIG. 4B ~ 4C as in the first, at the time t ₁₄ to time t ₁₅ in this period of time, the control signal will drive the main switch is turned off completely QM, 130A and starts transfer stored energy in the primary winding 130 of the transformer time t ₁₄ To the secondary winding 130B, the secondary current I _S flowing through the secondary winding 130B transitions from zero to a current peak I _SP having a maximum value at time t ₁₄ , at the same time the same end of all windings in the transformer 130 The polarity of the opposite end is reversed, so that the flyback voltage of the secondary winding 130B causes the rectifying diode D _{O of} FIG. 1 to be forward-passed, charging the output capacitor C _O while providing a load current from t ₁₄ to t ₁₅ During this time, the secondary current I _S is gradually attenuated by a falling slope. Before the end of a cycle to the time t _15, the main switch QM soon turned on again in the next cycle by cycle, the secondary current I _S at a time when a trailing end having state values I _SV, the trailing end is a state value I _SV Has an end state step value greater than zero. At time t ₁₅ immediately after the main switch QM next cycle will be switched on again, the main switch is turned on so that the secondary current I _S from the trailing end of the jump state variable I _SV value to zero. For the CCM mode, from time t ₁₁ to t ₁₅ can be regarded as a complete period T _S , and from time t ₁₁ to t _{14 is} defined as the conduction period T _ON , during which the main switch QM is considered to be on, and from time t ₁₄ To t _{15 is} defined as the off period T _OFF , during which the main switch QM is considered to be off, and the duty ratio D _{B1 of the} switch should be T _ON divided by the sum of the on period and the off period (T _ON +T _OFF ) .

The ratio of the number of turns N _{P of the} primary winding 130A to the number of turns N _{S of the} secondary winding 130B is set to N, wherein the peak current I _{SP of the} secondary winding side current I _S = N × I _PP , and the secondary winding side The final value of the trailing edge of the current I _S is I _SV =N × I _PV . In the CCM mode of the flyback converter, the output current I _O supplied to the load R _L satisfies the following functional relationship:

Referring again to Figure 4A, at the time point t _13, we intend to make the potential of the logic state of the control signal is inverted to the low level to drive the main switch QM time off, it will cause the primary current I _P synchronization with the control signal at the end of the instant A shutdown current value I _OFF , which is a transient value. It has been explained above that during the turn-off delay time T _P from time t ₁₃ to time t ₁₄ , the turn-off current value I _OFF is not the maximum value of the primary current I _P even if the control signal is at time t ₁₃ The logic state has been turned over to turn off the main switch QM, and the primary current I _P does not fall immediately. The actual situation is that the primary current I _P will still be at the off current value from the time node t ₁₃ to t ₁₄ . I _OFF on the basis continues to rise, which rise from the leading edge of the slope and initial value I is identical to _{the PV} increase the rising slope of the off current value I _OFF until the current I _P to a final increase to a peak having a maximum current I _PP As shown by the dashed vertices in Figure 4A. When the end delay time T _P enters the off time T _OFF, the main switch QM is turned off at time T _P t at the end of the instant node ₁₄ of the primary current I _P really drops from the peak current I _PP begins rapidly to zero.

Referring to Fig. 3, we sample the primary current I _P at a time node t ₁₂ at which the leading edge masking signal LEB is inverted from a high level to a low level, and the primary current I _{P is} sampled as a leading edge shielding current value I _{LEB .} , which is the transient value, the primary current I _{P is increased} from the leading edge initial value I _PV (the leading edge step value) to the rising slope of the leading edge shielding current value I _LEB and the primary current I _P is increased from the shutdown current value I _OFF to the peak current The rising slope of I _PP is exactly the same. In a complete cycle, we define the timing control signal for driving the main switch QM is turned on at time t ₁₁ to the end of the leading edge LEB inverted mask signal duration T t _LEB, and the continuation of the control signal ₁₂ occurs between the main switch to open QM is the time t _{13 is} the primary current I _P I _PP rises to a peak at time t between the delay time T _P is equal to ₁₄ continuation, i.e. T _LEB = T _P, as well as defining the peak current I _PP and the off current value I _OFF There is a difference ΔI1 between the two, and the current relationship of Fig. 4A can be calculated geometrically, and further I _PP = I _OFF + ΔI1 and I _PV = I _LEB - _ΔI1 can be obtained.

I _PP +I _PV =(I _OFF +ΔI1)+(I _LEB -△I1) (3)

I _PP +I _PV =I _OFF +I _LEB (4)

If we substitute equation (4) into equation (2), we can get the final expression of output current I _O in CCM mode, where period T _S =T _ON +T _OFF :

We do not intend to embody I _PP or I _SV in the expression of the output current I _O on the secondary side because their overshoot and overshoot peaks are actually difficult to capture or sense in the circuit, they exceed Outside the range of the grabbing capability of the circuit, it can be said to be hidden for the entire topology. The calculation of the output current I _O is almost impossible to rely on them, and the equation (5) solves this problem well in the CCM mode.

Referring to Figures 5A-5C, when the flyback converter enters DCM mode, at the beginning of a period of t ₂₁ , the control signal will drive the main switch QM to turn on. Since the energy of the transformer 130 in the previous cycle is not left, the primary current The initial value I _{PV of the} I _P at the instant when the main switch QM is turned on is almost zero, which is completely different from the initial step value of the CCM mode. And immediately after the period from t ₂₁ to t ₂₃ , the control signal always drives the main switch QM to be turned on, so during this period, the primary current I _{P is} based on the zero value of the leading edge initial value I _PV , with a certain value The rising slope gradually increases. Until the time t ₂₃ , for example, the logic high state of the control signal is released and the main switch QM is intended to be turned off, and likewise the primary current I _P does not fall directly, but the turn-off delay is from time t ₂₃ to time t _{24 .} During time T _P , the primary current I _P overshoots to the peak current I _PP with the highest current I _P at the same rising slope as the period from t ₂₁ to t ₂₃ until the primary current at time t ₂₄ at the end of the delay time T _P I _P quickly fell from the peak I _PP to zero.

Referring to Figures 5B-5C, after the end of the delay time T _P , during the period from time t ₂₄ to time t ₂₅ , the control signal will drive the main switch QM to be completely turned off, and the primary winding in the transformer 130 at time t ₂₄ 130A begins to transfer stored energy to secondary winding 130B, while secondary current I _S flowing through secondary winding 130B transitions from zero to a current peak I _SP having a maximum at time t ₂₄ , at which point transformer 130 reverse polarity dot end synonyms and end of all the windings, the secondary winding 130B causes the flyback voltage in FIG. 1 D _O rectifying diode forward conduction, to provide load current, while the output capacitance C _O gave During charging, the secondary current I _S is gradually attenuated to zero with a falling slope during the period from t ₂₄ to t ₂₅ . CCM and DCM modes of different patterns reflected in another aspect, to a time period t ₂₅ has not ended, in this case the secondary current I _S has a rear end along a state I _SV value is zero, i.e., secondary The current I _S has decayed to zero at the end of T _OFF before the start of the next cycle, and all of the energy stored in the primary winding 130A during the turn-on of the main switch QM is almost completely transferred from the secondary winding 130B to the beginning of the next cycle. load. In Fig. 5C, the secondary current I _S will fall to zero at the end of the period T _OFF at which the control signal turns off the main switch QM, and the secondary current I _S will fall to zero at the time t ₂₅ to the end of the current period. ₂₆ the time t between a period of dead time T _D, the start point is the time t ₂₆ after the end of the next cycle, the dead time T _D holding the secondary current I _S is zero at the time t down to ₂₅ And the time when the main switch QM starts to conduct again in the next cycle. For the DCM mode of the flyback converter, the time t ₂₁ to t ₂₆ can be regarded as a complete period T _S , and the time t ₂₁ to t _{24 is} defined as the conduction period T _ON , during which the main switch QM is considered to be turned on. And from time t ₂₄ to t _{25 is} defined as the off period T _OFF during which the main switch QM is considered to be off, and the time t ₂₅ to t _{26 is} defined as the dead time T _D , during which the main switch QM is also considered to be disconnected. The duty ratio D _{B2 of} the primary side switch should be T _ON divided by the sum of the conduction period and the off period and the dead period (T _ON +T _OFF +T _D ).

The ratio of the number of turns N _{P of the} primary winding 130A to the number of turns N _{S of the} secondary winding 130B is set to N, wherein the peak current I _{SP of the} secondary winding side current I _S = N × I _PP , and the secondary winding side The final state of the current I _S is I _SV =0. In the DCM mode of the flyback converter, the output current I _O supplied to the load R _L satisfies the following functional relationship:

Referring to FIG. 5A, at the time point t ₂₃ , the logic state of the control signal is turned to a low level to drive the time when the main switch QM is turned off, and the synchronization causes the primary current I _P to have a turn-off current value I at the end of the control signal. _OFF . During the turn-off delay time T _P from time t ₂₃ to time t ₂₄ , the turn-off current value I _OFF is not the maximum value of the primary current I _P , even if the logic state of the control signal has tended to flip at time t ₂₃ When the main switch QM is turned off, the primary current I _P does not drop immediately. The actual situation is that from the time node t ₂₃ to t ₂₄ , the primary current I _P will continue to rise on the basis of the off current value I _OFF , and the slope of the rise and the initial value of the leading edge I _{PV will} increase to The rising slope of the off current value I _OFF is exactly the same until the current I _P grows to the peak current I _PP which is finally the maximum value, as indicated by the apex of the broken line in Fig. 5A. Once the off time T _{OFF is} entered after the end of the delay time T _P , the main switch QM is completely turned off, and the primary current I _P is actually started from the peak current I _PP at the time node t ₂₄ at the end of the delay time T _{P .} It quickly drops to the zero value at time t ₂₅ .

Referring to FIG. 5C time, we are still at the leading edge LEB mask signal inverted from the low level to the high end of the active state of node t _22, the primary current I _P of the intermediate sampling a current sample value, referred to as the leading edge of the shielding current value I _LEB , the primary current I _{P is increased} from the leading edge initial value I _PV (zero value) to the rising slope of the leading edge shielding current value I _LEB , and the primary current I _P is increased from the shutdown current value I _{OFF to the} rise of the peak current I _PP The slope is exactly the same. In one cycle, we define the timing control signal for driving the main switch QM is turned on at time t LEB ₂₁ to the leading edge of the end of the mask signal duration T t _LEB, and the continuation of the control signal ₂₂ is reversed to open the main switch occurs QM _{23 is} a time t to the primary current I _P I _PP rises to a peak time t of between ₂₄ equal delay time T _P continuation, i.e. T _LEB = T _P, as well as defining the peak current I _PP and the off current value I _OFF of There is a difference ΔI2 between the two, which can be calculated geometrically from the current relationship of Fig. 5A, and further I _PP = I _OFF + ΔI2 and I _PV = I _LEB - ΔI2 = 0.

I _PP +I _PV =(I _OFF +ΔI2)+(I _LEB -△I2) (8)

I _PP +I _PV =I _OFF +I _LEB (9)

If we substitute equation (9) into equation (7), we can get the final expression of output current I _O in DCM mode, where period T _S =T _ON +T _OFF +T _D :

Although the overshoot and the overshoot peak of the primary side peak current I _PP or the secondary side peak current I _SV are difficult to be captured or sensed, the equation (10) can solve this problem well in DCM mode because The formula for estimating the output current I _O does not contain the peak current I _PP or I _SV . If the period T _{S is} defined in advance to express a clear meaning in the CCM and DCM modes, the formulas (5) and (10) are combined and transformed:

When we study whether the output current I _{O in} equations (5) and (10) exceeds the rated current value range due to overload over loading, divide this nominal range by a known constant value N to infer a range. So that (I _SUM ×T _OFF )/T _S in the formula (12) satisfies this range, then we only need to study whether (I _SUM ×T _OFF )/T _S conforms to the specification, among which the preset current I _SUM = (I _LEB +I _OFF )/2.

According to Equation (12) I _SUM captured we need only valid for a period of time T _OFF period T _S of the output current value, but not at other times the output of each period T _S, in order to complete execution of the I _SUM Multiply by the average current of the ratio T _OFF /T _S . Of FIG. 6A ~ 6D shows the basic scheme may be implemented to calculate mean and I _SUM, the basic idea is compared by the comparator using the I _SUM converted into a voltage and a reference value, calculate I _SUM compliance. In Fig. 6A, the current source 271 supplies a current having a current value of I _SUM , and a switch SW10 is connected between the current source 271 and the ground, and the switch SW10 is turned off only during the period T _OFF in each period T _S while in the remaining oN at all times, so that the current source 271 will be in the period T _OFF is connected to the anode current source 271, diode 301 common node 281 between the switches SW10 to provide forward conduction current, but in the remaining time period T _S is discharged to the current source 271 through the switch SW10, an average current I _SUM × T _OFF / T _S is the cathode terminal of the diode 301. 6B is substantially the same as FIG. 6A, but the switch SW11 can be used to control the voltage V1 to form a current equivalent to I _SUM in the diode 301, and the switch SW11 controls the period in which the current is formed in the diode 301 in each period is T. _OFF . Figure 6C replaces the diode of Figure 6A with a transconductance amplifier 302. In each period T _S , the switch SW12 is turned off only for the period T _{OFF and} turned on for the rest of the time, so that the current source 271 flows to resistor R23 during time period T _OFF , and node 281 at one end of resistor R23 is coupled to the positive input of transconductance amplifier 302, and the negative input of transconductance amplifier 302 is coupled to ground for use with transconductance amplifier 302 The output outputs the average current of I _SUM ×T _OFF /T _S . 6D replaces the diode in FIG. 6B with a transconductance amplifier 302. In each period T _S , the switch SW13 is turned off only for the period T _{OFF and} turned on for the rest of the time, and the voltage V2 is at the time. The segment T _{OFF is} output to the positive input of the transconductance amplifier 302, and the average current of I _SUM × T _OFF / T _S is obtained at the output of the transconductance amplifier 302. The present invention will hereinafter disclose an average current calculation method which has a more advantageous effect in place of the 6A to 6D drawings.

Referring to FIG. 7, a calculation circuit 280 for determining a load state is used to calculate an output current I _O that the secondary winding 130B supplies to the load. The calculation circuit 280 includes a detection module 201 for detecting and capturing. The primary current I _P flowing through the primary winding 130A can directly capture the sensing signal V _CS which is reflected as a voltage value across the sensing resistor R _S because it flows through the primary side of the sensing resistor R _S at different times. The current is multiplied by the resistance of the sense resistor R _S to be converted into a corresponding sense signal V _CS at different times. The detection module 201 is also essentially a current detector. It is necessary to detect the leading edge shielding current value I _LEB and the off current value I _OFF at a reasonable timing. One embodiment of computing circuit 280 is embodied in FIG.

Referring to the detection module 201 of FIG. 13, a DC power supply voltage V _DD is applied to the node 105 that supplies the operating voltage to the voltage-current converter 110 to supply power to the converter 110, and the voltage-to-current input of the voltage-current converter 110 is input. The terminal is connected to the common node 101 in FIG. 1 where the sense resistor R _S is connected to the source terminal of the main switch QM. In order to avoid confusion with the names of similar devices hereinafter, the voltage-current converter 110 is referred to as a first voltage-current converter. A conversion resistor R12 is connected between the current release terminal/output terminal of the voltage-current converter 110 and the ground terminal, so that the voltage-current converter 110 converts the voltage input to the voltage-to-current input terminal, that is, the sensing signal V _CS . The intermediate current I _M flows through the switching resistor R12, and a voltage value is generated at the node 121 of the end of the switching resistor R12 that is not grounded. As an optional rather than an optional item, a resistor R10 may be connected between the common node 101 and the voltage-to-current input terminal of the voltage-current converter 110, and the voltage-to-current input terminal and the ground terminal of the voltage-current converter 110 A capacitor C ₁ is connected between them to feed a smoother sensing signal V _CS at the voltage-to-current input of the voltage-to-current converter 110. As an optional rather than an optional item, a variable resistance adjusting resistor R11 may be directly connected to the node 121 and the ground. The adjusting resistor R11 of the detecting module 201 and the switching resistor R12 are connected in parallel between the node 121 and the ground. The total resistance between the node 121 and the ground is made adjustable by adjusting the resistor R11.

The detection module 201 further includes a first voltage follower 111 and a second voltage follower 112. The positive input terminals of the first and second voltage followers 111 and 112 are connected to the ungrounded end of the conversion resistor R12. At node 121, the negative input of the first voltage follower 111 is connected to its output, the negative input of the second voltage follower 112 is connected to its output, and the substantially identical first and second voltages follow. The switches 111, 112 output voltages to the next stage according to the voltage values drawn by the respective positive inputs. The first and second voltage followers 111, 112 serve as input buffers with high input impedance characteristics for connection to the signal source, high input impedance to isolate the interaction of the front and rear stages, and they also have lower output impedance characteristics. In order to reduce the capture time of the sensing signal V _CS . The first and second voltage followers 111, 112 are configured by an operational amplifier as a voltage follower or a unity-gain buffer. In addition, it has been explained in the foregoing that it is necessary to capture the sensing signal V _CS at a reasonable timing. Based on this, the detecting module 201 further includes a switch SW1 recorded as a first switch and a switch SW2 recorded as a second switch. SW1 is connected between the output of the first voltage follower 111 and the sample-and-hold latch 202 to be described later, and the switch SW2 is also connected between the output of the second voltage follower 112 and the sample-and-hold latch 202. . The switches SW1 and SW2 appearing in this paper and the electronic switches SW to be described later are all three-port type electronic switches. In addition to the opposite input and one output, these switches include a control input and output. There are various options for connecting or disconnecting the terminals between the terminals, such as P-type or N-type MOS transistors or bipolar transistors or junction transistors or combinations thereof.

In the CCM mode, the detection module 201 is first introduced from the node 101 at one end of the sensing resistor R _S to detect the sensing signal V _CS-LEB corresponding to the time t _{12 in} the 4Cth picture. The leading edge occlusion signal LEB additionally connects the leading edge occlusion signal LEB to the node 103 of the control terminal of the switch SW2 in addition to the initial spike Spike 355 of the sensing signal V _CS , so as long as the leading edge occlusion signal LEB has a high power phase-level logic state, the switch SW2 is turned on will always accompanied by a variation of the primary current I _P, where the primary current I _P characterization size value is completely reflected on the sensing signal V _CS 101 at the node. QM any time from the main switch is turned on the start of a period of t ₁₁ to the leading edge LEB mask signal inverted from the high level to the low level of time t _12, i.e. at the leading edge LEB mask signal is continuously phase high During the time period T _LEB , the primary current I _P corresponds to the leading edge shielding current value I _LEB from the leading edge initial value I _PV to the time t ₁₂ , during which the rising change of the sensing signal V _CS is detected by the module. 201 detects at node 101 that voltage current converter 110 again restores the current value converted by sense signal V _CS to a voltage value at node 121 of the ungrounded end of conversion resistor R12.

Specifically, although the dynamic sensing signal V _{CS is} always input to the voltage-current converter 110 during the period T _LEB , the switch SW2 is turned off once the leading edge masking signal LEB is turned to a low level, at time t _{12 .} The second voltage follower 112 cannot convert the voltage value at the node 121 into a current output until the leading edge masking signal LEB enters the high level state of its next cycle. The sensing signal V _CS-LEB corresponding to the magnitude of the leading edge shielding current value I _LEB corresponding to the time t ₁₂ is input to the voltage to current input terminal of the voltage current converter 110, which is converted into a current by the voltage current converter 110. intermediate conversion resistor R12 switching current I _M, thereby further converts the intermediate current I _M is converted into the conversion across the two ends of the voltage drop of the resistor R12, for example, equal to the voltage sense signal V _CS-LEB, and the second voltage follower 112 The voltage applied to the conversion resistor R12, that is, the voltage of the node 121 is converted into a voltage output equal to the sense signal V _CS-LEB . After the leading edge masking signal LEB is turned to a low level, the voltage value finally output by the second voltage follower 112 in one period T _S is fixed at the level of the voltage sensing signal V _CS-LEB corresponding to the time t ₁₂ . The calculation circuit 280 comprises a latch sample and hold (S / H) 202 having a second storage capacitor C ₃ receives a voltage from the second output terminal of the voltage follower 112 and charging the second storage capacitor C one end ₃ the switch SW2 is connected between the output terminal node 112 and a second voltage follower 123, the other end of the second storage capacitor C ₃ is connected directly to ground. The second storage capacitor C _{3 is} charged with a voltage equivalent to the voltage sensing signal V _CS-LEB , and the second storage capacitor C ₃ holds and stores the leading edge shielding current value I flowing through the primary winding 130A corresponding to the time t ₁₂ . _{The LEB} information, the stored information is embodied as the voltage value V _CS-LEB held at the node 123 of the second storage capacitor C ₃ .

Still in the CCM mode, the detection module 201 is further configured to detect the voltage sensing signal V _CS-OFF corresponding to the time t _{13 in} the 4Cth picture from the node 101 at one end of the sensing resistor R _S . The control signal, for example PWM, in addition to driving the control terminal of the main switch QM, additionally couples the control signal to the control terminal of the switch SW1, so that the switch SW1 is always turned on as long as the control signal has a high logic state. , whereas the switch SW1 is turned off, along with the gradual increase of the primary current I _P, the primary current I _P characterizing magnitude values situation is completely reflected on the sensing signal V _CS 101 at the node. Start time of the main switch is turned from a QM any period t ₁₁ to the control signal from the high level to the low level inversion timing t _13, the primary current I _P corresponding to the initial value I _PV from the leading edge to increase the time t ₁₃ The current value I _{OFF is} turned off, and the rising change of the sensing signal V _CS during the same period of time is detected by the detecting module 201 at the node 101, and the voltage current converter 110 is converted by the sensing signal V _CS . The current value is again restored to a voltage value at node 121 at the end of the conversion resistor R12 that is not grounded.

In the CCM mode, although the dynamic sensing signal V _{CS is} always input to the voltage-current converter 110 during the period from t ₁₁ to t ₁₃ , the switch SW1 is turned off once the control signal is turned from the high level to the low level. The first voltage follower 111 cannot convert the voltage value at the node 121 into a current output until after the time t ₁₃ until the control signal enters the high level state of its next cycle. And time t ₁₃ corresponding to the characterization voltage switch current input terminal of the off current value I _OFF magnitude sense signal V _CS-OFF is input to a voltage-current converter 110, the voltage-current converter 110 to convert it to flow through conversion The intermediate switching current I _{M of the} resistor R12, thereby converting the intermediate switching current I _M into a voltage across the switching resistor R12, for example, equal to the voltage sensing signal V _CS-OFF level, and the first voltage follower 111 will again The voltage across the conversion resistor R12, i.e., the voltage at node 121, is converted to a voltage output equal to the sense signal V _CS-OFF . The voltage value finally output by the first voltage follower 111 in one period T _S is fixed to the corresponding sensing signal V _CS-OFF level at time t ₁₃ . Sample and hold latch 202 in a first storage capacitor C ₂ 111 receives the output of voltage from the first voltage output terminal 111 of the transmission follower, one end of the first storage capacitor C ₂ as a first node 122 and the voltage follower A switch SW1 controlled by a control signal is connected between, and the other end of the first storage capacitor C ₂ is connected to the ground. Charging the first storage capacitor C ₂ with a voltage equivalent to the sense signal V _CS-OFF , the first storage capacitor C ₂ holds and stores the off current value I _OFF flowing through the primary winding 130A corresponding to the time t ₁₃ The information stored is embodied as the voltage value V _CS-OFF held at the one end node 122 of the first storage capacitor C _{2 that is} not grounded.

The detection module 201 captures the leading edge shielding current value I _LEB at time t _{12 in the} CCM mode and the off current value I _OFF at time t ₁₃ and stores it in the sample and hold latch 202 in the same manner. It is also possible to capture the leading edge shading current values I _LEB at time t _{22 in the} DCM mode and the off current value I _OFF at time t ₂₃ and store them in the sample and hold latch 202.

In the DCM mode, the detection module 201 detects the sensing signal V _CS-LEB corresponding to the time t _{22 in} the 5Cth picture from the node 101 at one end of the sensing resistor R _S as follows. The leading edge masking signal LEB is connected to the node 103 of the control terminal of the switch SW2, and the switch SW2 is turned on during the high logic state of the leading edge masking signal LEB. Start time of the main switch is turned from a QM any period t ₂₁ to the leading edge LEB mask signal inverted from the high level to the low level time t _22, i.e. in the period T _LEB, corresponding to the primary current I _P The leading edge current value I _LEB from the leading edge initial value I _{PV of} zero value to the time t ₂₂ is increased. Although the dynamic sensing signal V _{CS is} always input to the voltage-current converter 110 during the time period T _LEB , the switch SW2 is turned off once the leading edge masking signal LEB is turned to a low level, and after the time t ₂₂ to the leading edge The second voltage follower 112 is unable to convert the voltage value at node 121 into an output before the masking signal LEB enters the high state of its next cycle. And the sensing signal V _CS-LEB corresponding to the magnitude of the leading edge shielding current value I _LEB corresponding to the time t ₂₂ is input to the voltage to current input terminal of the voltage current converter 110, which is converted into a current by the voltage current converter 110. Converting the intermediate switching current I _{M of the} resistor R12, thereby further converting the intermediate switching current I _M into a voltage across the switching resistor R12, and the second voltage follower 112 will again pass the voltage across the switching resistor R12 The voltage at 121 is converted to a voltage output equivalent to the sense signal V _CS-LEB . The voltage value finally output by the second voltage follower 112 in one period T _S is fixed to the corresponding sensing signal V _CS-LEB at time t ₂₂ . Second storage capacitor C ₃ receives a voltage from the second voltage output terminal 112 and the transport follower sensing signal V _CS-LEB equivalent, a second charge storage capacitor C _3, a second storage capacitor C ₃ of the holding and storage The information corresponding to the leading edge current value I _LEB of the primary winding 130A corresponding to the time t _{22 is} stored, and the stored information is represented by the voltage value V _CS-LFB held at the one end node 123 of the second storage capacitor C _{3 that is} not grounded.

In the DCM mode, the detection module 201 detects the sensing signal V _CS-OFF corresponding to the time t _{23 in} the 5Cth diagram from the node 101 at one end of the sensing resistor RS as follows. The control signal is connected to the control terminal of the switch SW1, and the switch SW1 is turned on during the high logic state of the control signal. Start time of the main switch is turned from a QM any period t ₂₁ to the inverted control signal to the low level time t _23, corresponding to an increase of the primary current I _P from the leading edge of the initial value I _FV zero value to the time from the high level The turn-off current value of t ₂₃ is _OFF . Although the dynamic sensing signal V _{CS is} always input to the voltage-current converter 110 during the period from t ₂₁ to t ₂₃ , the switch SW1 is turned off once the control signal is turned from the high level to the low level, the time t After ₂₃ until the control signal enters the high state of its next cycle, the first voltage follower 111 cannot convert the voltage value at the node 121 to output. And the sensing signal V _CS-OFF corresponding to the magnitude of the off current value I _OFF corresponding to the time t ₂₃ is input to the voltage to current input terminal of the voltage current converter 110, which is converted into a flow by the voltage current converter 110. The intermediate conversion current I _{M of the} conversion resistor R12 further converts the intermediate conversion current I _M into a voltage across the conversion resistor R12, and the first voltage follower 111 will again cross the voltage across the conversion resistor R12, that is, at the node 121. The voltage is converted to a voltage output equivalent to the sense signal V _CS-OFF . The voltage value finally output by the first voltage follower 111 in one period T _S is fixed to the corresponding sensing signal V _CS-OFF at time t ₂₃ . Receiving a first storage capacitor C ₂ equivalent of the sensing signal V _CS-OFF of the voltage from the first voltage output terminal 111 of the transmission follower, and a first charge storage capacitor C _2, the first storage capacitor C ₂ remains stored The information of the off current value I _OFF flowing through the primary winding 130A corresponding to the time t _{23 is} stored as the voltage value V _CS-OFF held at the one end node 122 where the first storage capacitor C _{2 is} not grounded.

Referring to Fig. 7, the calculation circuit 280 includes a current summation unit 203 having a voltage current converter 113 and another voltage current converter 114, which are respectively referred to as second and third voltage current converters. A DC supply voltage V _DD is applied to the nodes 106, 107 that supply the operating voltages to the voltage-to-current converters 113, 114 to supply power to the converters 113, 114, and the current-releasing/outputs of the voltage-to-current converter 113 are connected to the ground GND. A sum resistor R14 is connected between it and has a resistance value R _SUM . Current input voltage into the voltage-current converter 113 is connected to the first storage capacitor C ₂ of the node 122 at an end, the off current value I _OFF information of the first storage capacitor C ₂ is equal to the voltage value holding V _CS-OFF manner It is supplied to a voltage-current converter 113 which converts the off current value I _OFF information at its current output terminal into a current equal to the original off current value I _OFF . The respective current outputs of the voltage to current converters 113, 114 are interconnected and commonly coupled to a common node 124 at the ungrounded end of the sum resistor R14, and the other end of the sum resistor R14 is coupled to ground. Current input voltage into the voltage-current converter 114 is connected to node 123 the second end of the storage capacitor C _3, the sample holder 202 latches the second storage capacitor C ₃ holding a leading edge of the shielding current value I _LEB information The voltage V _CS-LEB is supplied to a voltage-to-current converter 114 which converts the leading edge shading current value I _LEB information at its current output to a current equal to the original leading edge shading current value I _LEB . Thus, the total current flowing through the sum resistor R14 is equal to the sum of both the off current value _IOFF and the leading edge shading current value I _LEB , which is I _LEB +I _OFF . In addition, the current summing unit 203 further includes a third voltage follower 128, the positive input of the third voltage follower 128 is connected to the node 124 of the resistor R14 and the negative input is connected to its output terminal, and the summing resistor R14 is adjusted. The magnitude of the resistance R _SUM is such that the output voltage V _{TRS of the} third voltage follower 128 becomes adjustable, V _TRS =R _SUM ×(I _LEB +I _OFF ), and the preset current I _SUM should contain (I _LEB +I _OFF This sum value factor, for example, can set the preset current I _SUM equal to K × (I _LEB + I _OFF ), where K is a positive constant, but we are in the example of an example but not a limitation, Take the preset current I _SUM equal to 0.5 × (I _LEB +I _OFF ). In addition, the voltage V _TRS outputted by the third voltage follower 128 can be measured, and the sum value obtained by adding the off current value I _OFF and the leading edge shielding current value I _LEB included in the preset current I _SUM can be obtained by the voltage V _{TRS .} Converted out.

Referring to FIG. 8, a circuit for judging the load state is an overload detecting circuit 350. In a branch between the voltage source V _DD and the ground, a current source 315 for supplying a current value I _SUM and a switch SW21 are connected in series. A first capacitor C11, the input end of the switch SW21 is connected to the current source 315, and the output end is connected to the node 311 at one end of the first capacitor C11, and the other end of the first capacitor C11 is grounded. In another branch between the voltage source V _DD and the ground, a current source 316 providing a reference current value I _REF and a switch SW22 and a second capacitor C12 are connected in series, and the input terminal of the switch SW22 is connected to the current source. The output is connected to the node 312 at one end of the second capacitor C12, and the other end of the second capacitor C12 is grounded. In addition, the overload detection circuit 350 further includes a comparator 328 having a non-inverting input coupled to the switch SW21 and a common connection node 311 of the first capacitor C11, the inverting input of the comparator 328 being coupled to the switch SW22 and At the common connection node 312 of the second capacitor C12, the comparator 328 is mainly used to compare the voltage on the first capacitor C11 with the voltage on the second capacitor C12.

Referring to FIG. 9, the first capacitor C11 in FIG. 8 is charged by the preset current I _SUM provided by the current source 315, and the second capacitor C12 in FIG. 8 is charged by the reference current I _REF provided by the current source 316. The current provided by the current source 316 may be a single reference current I _REF or a multiple of the unit reference current I _REF . The current supplied by the current source 315 may be a single preset current I _SUM or a multiple of the unit preset current I _SUM . . The basic principle is that an excessive load output current will also cause the preset current I _{SUM to} increase synchronously, and the condition of the load can be reflected at the output of the comparator 328. There is greater flexibility in the period during which the first capacitor C11 and the second capacitor C12 are charged in each cycle, if the charging process of the second capacitor C12 continues throughout the cycle, such as the slave shown in FIG. The beginning and the end of a period T _S are always charged, and it is found that, for example, in the DCM mode, the voltage V _{312 of the} second capacitor C12 (ie, the voltage value at the node 312) and the voltage V _{311 of the} first capacitor C11 (ie, the node 311) The voltage value at the point) has an intersection point in the time period T _OFF , and the capacitor does not complete the charging at this moment, but the comparator 328 displays the comparison result. Furthermore, the timing at which the second capacitor C12 completes charging is at the end of the period T _S , which easily causes the voltage V ₃₁₂ and the voltage V _{311 to} have almost no comparison time at the end point of the period T _S , so that the comparator 328 produces the correct comparison result. . In some optional embodiments, the first capacitor C11 and the second capacitor C12 instantaneously release the stored power at the end of one cycle by using a discharge circuit not shown before charging for the next cycle. For example, a three-port type electronic switch SW31 having a control end is connected in parallel across the first capacitor C11, and a three-port type electronic switch SW32 having a control end is connected in parallel across the second capacitor C12, and each of the switches SW31 and SW32 in the overload detecting circuit 350 is controlled. The terminal synchronously receives a periodic clock signal (CLKP), and the switch SW31 and the switch SW32 are turned on by the periodic clock signal (CLKP) at the time before the start of each period Ts or at the end of each period, and the switch SW31 is connected. Between the node 311 and the ground, the switch SW32 is connected between the node 312 and the ground, so that the first and second capacitors C11 and C12 can be instantaneously discharged synchronously at the transient timing when the switch SW31 and the switch SW32 are turned on. . In other alternative embodiments, the electronic switches can be triggered by a control signal at a time when the cycle is to turn on the rising edge of the main switch QM, and the capacitor is instantaneously discharged to the ground.

Referring to FIG. 10, a spirit of the present invention that may not have been charged to the second capacitor C12, the whole cycle T _S, the drive signal supplied to the control terminal CTL2 SW22 switch only controls only in one-half the period T _S The switch SW22 is turned on and turned off at other times, and the second capacitor C12 is charged, charging is performed from the start time of each period T _S , and charging is not continued until the time point of T _S /2, but from each period The second capacitor C12 is not charged between the time nodes of T _S /2 and the time nodes ending the period T _S . In order to perform an average current calculation by multiplying the preset current I _SUM by the ratio of T _OFF /T _S , the control signal CTL1 supplied to the control terminal of the switch SW21 controls the switch SW21 to be turned on only for one off period T _OFF in the period T _S . off at other times, for charging the first capacitor C11, from the time point off period T _OFF starts charging is performed until the turn-off time period T _OFF to complete the charging end. However, the first capacitor C11 is not charged during the on period T _ON and the dead period period T _D , which is the case in the DCM mode. Similarly, if in CCM, only during the off period T _OFF period of time of the first capacitor C11 is charging, but is charged in the conduction period T _ON of the first capacitor C11 does not. Voltage waveform of the voltage V ₃₁₂ V ₃₁₁ and the node 312 at the node 311 as shown in Figure 10. It is worth noting that because the charging time of the second capacitor C12 is shortened relative to charging during the entire cycle, it is half of the original, but in order to maintain the same final charge as the entire cycle, it should be 2 The charging current of ×I _REF charges the second capacitor C12 such that the amount of charge (2 × I _REF ) × (T _S /2) charged in half cycle is still equal to the amount of charge I _REF × T _S of the entire cycle in Fig. 9. In this way, the comparator 328 concludes that the comparison timing of the voltage V ₃₁₁ and the voltage V ₃₁₂ is not limited to the time point at which one cycle ends. For example, the comparison can be performed before the end of the T _OFF , and no erroneous operation occurs.

Taking the DCM mode as an example, the reference current I _{REF is} kept constant and the actual preset current I _{SUM is} gradually increased. At the time when the off period T _OFF ends, that is, the first capacitor C11 completes T _{OFF for} such a long time of charging. When the comparator 328 starts to output the high level for the first time, it is a critical state, and the critical state occurs when the voltage V ₃₁₁ and the voltage V _{312 are} exactly equal, that is, the second capacitor C12 has the electric quantity I at the end of the time T _S /2. _REF × T _S is equal to the amount of power that the first capacitor C11 has at the end of the off period T _OFF . The critical state is also applicable to the CCM mode. The only difference from the DCM mode is that the dead time is not considered. In this case, the preset current value set at this moment has a rated current value I _{SUM1 that} satisfies the following functional relationship:

If the capacitance values of the first capacitor C11 and the second capacitor C11 are set to be the same in a particular embodiment, it can be easily calculated that the rated current value I _SUM1 is substantially equal to (I _REF × T _S ) ÷ T _OFF . I _SUM1 is a critical value as long as the actual preset current I _{SUM is} larger than I _SUM1 or the actual output current I _O ratio (N × I _REF × C ₁₁ ) ÷ C _{12 is} large, for example, the DCM of FIG. 11 mode becomes heavy load, before the end point of each of the off period T _OFF, i.e., the drive timing of each falling edge of signal CTL1 before, the comparator 328 will occur because the voltage V ₃₁₁ V ₃₁₂ is larger than the phenomenon begins The output is high until the end of a cycle. Connecting the output of the comparator 328 to the input of a one shot of the one shot in Fig. 8, the rising edge of the comparison result will be triggered every cycle before the end of the off period _TOFF The steady state flip-flop 329 sends a high level, connecting the output of the one shot 329 to a counter 330, for example, the counter 330 can receive the signal OC sent by the one shot 329 at its CLK terminal, if the counter 330 receives a high level signal OC for several consecutive cycles and the total duration of the consecutive cycles exceeds a preset time. Counter 330 can assume that the converter has entered an overload state, and counter 330 can An overload protection signal OLP is sent to shut down the entire power supply unit.

Conversely, as long as the actual preset current I _{SUM is} smaller than the nominal value I _SUM1 , or the actual output current I _O ratio is smaller than (N × I _REF × C ₁₁ ) ÷ C ₁₂ , for example, the DCM mode of FIG. 11 The medium load becomes a light load state, and the voltage V ₃₁₁ does not exceed the voltage V ₃₁₂ . In this case, the comparator 328 does not output a high level every cycle, and does not trigger the one-shot 329 to send a logic high. Flat, so the counter 330 does not send the overload protection signal OLP. Similarly, in CCM mode, there is also a rated current value I _SUM1 . The difference between this value and DCM is only whether the period T _S contains a dead time period, that is, the formula in the period T _S and CCM mode in equation (14). 5) The meaning corresponds to the meaning of formula (10) in DCM mode, and there is no difference between the other algorithms. As long as the actual preset current I _{SUM is} larger than I _SUM1 , or the output current I _{O is} larger than (N × I _REF × C ₁₁ ) ÷ C ₁₂ , for example, the load in FIG. 12 becomes heavy, in each off period T The end point of _OFF is slightly advanced, and the comparator 328 starts to output a high level because the voltage V _{311 is} larger than the voltage V ₃₁₂ until the end of one cycle, and each cycle is before each end point of the off period T _OFF . The signal OC sent by the one-shot 329 is triggered to have a high level, the output of the one-shot 329 is connected to the counter 330, and the counter 330 can receive the signal OC at its CLK terminal if the counter 330 is in several A high level signal OC is received during successive cycles and the total duration of the successive cycles continues for more than a predetermined period of time. Counter 330 can transmit an overload protection signal OLP to shut down the entire power supply unit. Conversely, in the CCM mode, as long as the actual preset current I _{SUM is} smaller than the rated value I _SUM1 , or the output current I _O ratio (N × I _REF × C ₁₁ ) ÷ C _{12 is} small, such as the load in FIG. When it becomes a light load state, the voltage V ₃₁₁ does not exceed the voltage V ₃₁₂ , so in this case, the comparator 328 does not output a high level in each cycle, and does not trigger the one-shot 329 to send a logic high. At the level, the counter 330 does not transmit the overload protection signal OLP.

The exemplary embodiments of the specific constructions of the specific embodiments have been described above by way of illustration and the accompanying drawings, which set forth the preferred embodiments. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

311, 312‧‧‧ nodes

315, 316‧‧‧ current source

328‧‧‧ Comparator

329‧‧‧monostable trigger

330‧‧‧ counter

350‧‧‧Overload detection circuit

SW21, SW22, SW31, SW32‧‧‧ switch

C11‧‧‧first capacitor

C12‧‧‧second capacitor

Claims (26)

A circuit for determining a load state in a flyback converter, comprising: a detection module that detects a primary current flowing through a sense resistor in series with a primary winding and is used to control the primary winding connection Turning on or off one of the main switches is turned off by a control signal, detecting a turn-off current value I _OFF flowing through the sense resistor, and shielding the leading edge of the primary current starting pulse At the instant when the effective state of the signal ends, a leading edge current value I _LEB flowing through the sensing resistor is detected; a first current source providing a preset current I _SUM , wherein the preset current I _{SUM is} included The turn-off current value I _OFF and the leading edge shading current value I _LEB are added to obtain a sum value factor, and a second current source providing a reference current I _REF ; a first capacitor charged by the first current source And a second capacitor charged by the second current source; a comparator, inputting the voltage of the first capacitor to the positive phase input terminal of the comparator and inputting the voltage of the second capacitor to the voltage The comparator is inverted The input terminal detects the load state by using the comparison result of the comparator output when the output current of the flyback converter is changed to cause the preset current I _{SUM to} change. A circuit for determining a load state in a flyback converter according to claim 1, wherein the preset current I _SUM is equal to a sum of the off current value I _OFF and the leading edge shading current value I _LEB One-half of the sum value. A circuit for determining a load state in a flyback converter according to claim 1, wherein a switch is connected between the first current source and the first capacitor, and the switch is in each cycle of the main switch. The T _S is turned on only during the off period T _OFF of the main switch, and is turned off during the remaining period of each period. A circuit for determining a load state in a flyback converter according to claim 3, wherein a capacitance value of the first capacitor is C ₁₁ and a capacitance value of the second capacitor is C ₁₂ , by the preset Whether the current I _SUM exceeds a set rated current value I _SUM1 to determine whether the load is in an overload state, and A circuit for determining a load state in a flyback converter according to claim 4, wherein a switch is connected between the second current source and the second capacitor, and the switch is in each cycle of the main switch. The moment when the turn-on is started is turned on until one-half of each cycle is turned off; and the second current source provides twice the reference current I _REF so that the second capacitor is in the period T _S At the end of one-half of the total time, the total voltage of charge is maintained at: A circuit for determining a load state in a flyback converter according to claim 5, wherein a capacitance value C ₁₁ of the first capacitor is set equal to a capacitance value C _{12 of} the second capacitor. A circuit for determining a load state in a flyback converter according to claim 4, wherein when the preset current I _SUM actually exceeds the rated current value I _SUM1 , the period T _S is in the During the off period T _OFF of the main switch, the output of the comparator will be flipped from a low level to a high level; or when the actual preset current I _{SUM is} lower than the rated current value I _SUM1 , in each period T The output of the comparator in _S is maintained at a low level. A circuit for determining a load state in a flyback converter according to claim 7 of the patent application, further comprising receiving one of the output of the comparator The flip-flop includes a counter connected to the one-shot, and the one-shot triggers a high-level signal every time the comparator flips from a low level to a rising edge of a high level The counter, when the counter receives the high level signal of the one-shot trigger output in each of the consecutive complex cycles, the counter issues an overload protection signal with a load entering the heavy load state. The circuit for determining a load state in a flyback converter according to claim 1, wherein the circuit further includes a switch in parallel with the first capacitor and a switch in parallel with the second capacitor in each cycle. The end time is triggered to be turned on, so that the switch connected in parallel with the first capacitor and the switch connected in parallel with the second capacitor are turned on to synchronously discharge the first and second capacitors. The circuit for determining a load state in a flyback converter according to the first aspect of the patent application, further comprising a sample and hold latch, the detection module having a first voltage current converter for collecting Characterizing the magnitude of the primary current across the sense resistor and converting the voltage sense signal into a current connection between a current output of the first voltage current converter and a ground An intermediate current of one of the conversion resistors; at the instant when the main switch is turned off, the detection module converts the voltage applied to the conversion resistor to a voltage sensing signal corresponding to the shutdown current value I _OFF The sampling holding latch is stored; when the effective state of the leading edge shielding signal ends, the detecting module converts the voltage applied to the conversion resistor to a value corresponding to the leading edge shielding current value I _LEB A voltage sensing signal is supplied to the sample hold latch for storage. The circuit for determining a load state in a flyback converter according to claim 10, wherein the detection module includes a first voltage follower, and a positive input terminal is connected to the first voltage current conversion The current output terminal of the device; a first switch driven by the control signal is connected between an output end of the first voltage follower and one end of the first storage capacitor of the sample hold latch, the control When the signal is turned from the first state to the second state, the first switch is turned off, and the first switch is synchronously turned off. At this moment, the voltage generated by the intermediate current on the conversion resistor is converted into a voltage by the first voltage follower. The voltage sensing signal corresponding to the off current value I _OFF is stored in the first storage capacitor. The circuit for determining a load state in a flyback converter according to claim 10, wherein the detection module includes a second voltage follower, and a positive input terminal is connected to the first voltage current conversion The current output terminal of the device; a second switch driven by the leading edge shielding signal is connected between an output end of the second voltage follower and one end of the second storage capacitor of the sample holding latch At a moment when the leading edge shielding signal is turned from the first state to the second state, the second switch is synchronously turned off, and the voltage generated by the intermediate current on the switching resistor is converted into the voltage by the second voltage follower. A voltage sensing signal corresponding to the leading edge shielding current value I _LEB is stored in the second storage capacitor. A circuit for determining a load state in a flyback converter according to claim 10, further comprising a current summation unit having a second voltage current converter for storing the sample hold latch a voltage sensing signal corresponding to the off current value I _OFF is restored to be converted into a current that is equivalent to the off current value I _OFF flowing from a current output terminal of the second voltage current converter; the current summation unit has a third voltage current converter resumes converting the voltage sensing signal stored in the sample holding latch corresponding to the leading edge shielding current value I _LEB into a current output terminal from one of the third voltage current converters a current equivalent to the leading edge shielding current value I _LEB ; the respective output currents of the second and third voltage current converters converge through a common node and a ground terminal at the interconnection of the current output terminals of the two One of the sum resistances, and the current summation unit has one of the third voltage followers connected to the common input terminal, and the third voltage follower output voltage V _TRS is equal to (I _LEB +I _OFF ) is multiplied by the resistance value R _{SUM of} the sum resistance, thereby summing the sum of the off current value I _OFF and the leading edge shading current value I _LEB . A method for determining a load state in a flyback converter, comprising the steps of: detecting a primary current flowing through a sense resistor in series with a primary winding, and controlling the primary winding to be turned on or off one of the main switch is turned off by a control signal the moment, one of the detected active state of the sense resistor flowing off current value I _OFF, and the primary current for shielding one of the leading edge of the shield spike start signals At the end of the detection, a leading edge shielding current value I _LEB flowing through the sensing resistor is detected; a first current source providing a predetermined current I _SUM is used to charge a first capacitor, and the preset current I _SUM includes And summing the off current value I _OFF and the leading edge shielding current value I _{LEB to} obtain a sum value factor, and charging a second capacitor by using a second current source providing a reference current I _REF ; a capacitor-varying voltage is input to one of the comparator's non-inverting input terminals and a voltage of the second capacitor is input to one of the comparator inverting inputs, when the flyback converter is transmitted to the load Output current When the change causes the preset current I _{SUM to} change, the load state is detected by the comparison result of the comparator output. A method for determining a load state in a flyback converter according to claim 14, wherein the preset current I _SUM is set equal to the turn-off current value I _OFF and the leading edge shadow current value I _LEB One-half of the sum of the sums. A method for determining a load state in a flyback converter according to claim 14, wherein a switch is connected between the first current source and the first capacitor, the switch being in each of the main switches The period T _S is turned on only during the off period T _OFF of the main switch, charging the first capacitor, and turning off during the remaining period of each period. A method for determining a load state in a flyback converter according to claim 16 wherein the capacitance value of the first capacitor is C ₁₁ and the capacitance value of the second capacitor is C ₁₂ Whether the current I _SUM exceeds a set rated current value I _SUM1 to determine whether the load enters an overload state, and A method for determining a load state in a flyback converter according to claim 17, wherein a switch is connected between the second current source and the second capacitor, the switch being in each of the main switches The time at which the cycle begins to turn on is turned on, charging the second capacitor until one-half of each cycle is turned off; and the second current source provides twice the reference current I _REF The total voltage of the second capacitor at the end of one-half of the total time of the period T _S is maintained at: A method for determining a load state in a flyback converter according to claim 18, wherein a capacitance value C ₁₁ of the first capacitor is set equal to a capacitance value C _{12 of} the second capacitor. A method for determining a load state in a flyback converter according to claim 17, wherein when the preset current I _SUM actually exceeds the rated current value I _SUM1 , the period T _S is in the During the off period T _OFF of the main switch, the output of the comparator will be flipped from a low level to a high level; or when the actual preset current I _{SUM is} lower than the rated current value I _SUM1 , in each period T The output of the comparator in _S is maintained at a low level. A method for determining a load state in a flyback converter according to claim 20, further comprising providing a one-shot trigger for receiving the output of the comparator and providing a connection with the one-shot a counter, the one-shot trigger outputs a high level signal to the counter each time the low level is flipped from a low level to a rising edge of the high level, when the counter is in a continuous complex period The high level signal of the one-shot trigger output is received in each cycle, and the counter sends an overload protection signal indicating that the load enters a heavy load state. A method for determining a load state in a flyback converter according to claim 14, wherein a switch connected in parallel with the first capacitor and a switch in parallel with the second capacitor are provided at the end of each cycle The moment is triggered to be turned on, and the switch connected in parallel with the first capacitor and the switch connected in parallel with the second capacitor are turned on to synchronously discharge the first and second capacitors. A method for determining a load state in a flyback converter according to claim 14, wherein a sample hold latch and a detection module are provided, the detection module having a first voltage current conversion Collecting a voltage sensing signal across the sensing resistor for characterizing the primary current and converting the voltage sensing signal into a current output terminal connected to the first voltage current converter and a ground One of the switching resistors is an intermediate current; when the main switch is turned off, the detecting module converts the voltage applied to the switching resistor to a voltage sense corresponding to the shutdown current value I _OFF The measurement signal is sent to the sample-and-hold latch for storage; at the instant when the effective state of the leading edge masking signal ends, the detecting module converts the voltage applied to the conversion resistor to the shielding current value of the leading edge The voltage sensing signal corresponding to the I _LEB is supplied to the sample hold latch for storage. The method for determining a load state in a flyback converter according to claim 23, wherein the detection module includes a first voltage follower, and a positive input terminal is connected to the first voltage current conversion The current output terminal of the device; a first switch driven by the control signal is connected between an output end of the first voltage follower and one end of the first storage capacitor of the sample hold latch, the control When the signal is turned from the first state to the second state, the first switch is turned off synchronously, and the voltage generated by the intermediate current on the conversion resistor is converted into a voltage by the first voltage follower. The voltage sensing signal corresponding to the off current value I _OFF is stored in the first storage capacitor. The method for determining a load state in a flyback converter according to claim 23, wherein the detection module includes a second voltage follower, and a positive input terminal is connected to the first voltage current conversion The current output terminal of the device; a second switch driven by the leading edge shielding signal is connected between an output end of the second voltage follower and one end of the second storage capacitor of the sample holding latch At a moment when the leading edge shielding signal is turned from the first state to the second state, the second switch is synchronously turned off, and the voltage generated by the intermediate current on the switching resistor is converted into the voltage by the second voltage follower. A voltage sensing signal corresponding to the leading edge shielding current value I _LEB is stored in the second storage capacitor. A method for determining a load state in a flyback converter according to claim 23, wherein a current summation unit is provided, which has a corresponding one of the second voltage current converters for storing the sample hold latch The voltage sensing signal at the off current value I _OFF is restored to be converted into a current that is equal to the off current value I _OFF flowing from one of the current output terminals of the second voltage current converter; the current summation unit has a third voltage current converter restores the voltage sensing signal stored in the sample holding latch corresponding to the leading edge shielding current value I _LEB to a current output from one of the third voltage current converters The leading edge shields the current value of the current value I _LEB ; the current output of each of the second and third voltage current converters flows between one of the common node and the ground of the current output terminal of the two One of the sum resistances, and the current summation unit has one of the third voltage followers connected to the common input terminal, and the third voltage follower output voltage V _TRS is equal to (I _LEB +I _OFF ) multiplied by the resistance value R _{SUM of} the sum resistance, thereby summing the sum of the off current value I _OFF and the leading edge shading current value I _LEB .