1320990 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種切換式電源轉換器，特別是關於一 種切換式電源轉換器的負載變動補償電路。 【先前技術】 切換式電源轉換器可以達到以較小的尺寸及較佳的 效能產生受調節的輸出電壓。具有變壓器耦合 (transformer-coupled)架構的切換式電源轉換器，例如反馳 (flyback)轉換器與順向（forward)轉換器，其功率輸出端係 藉變壓器與功率輸入端隔離，而功率開關則位於變壓器的 一次側。脈寬調變（Pulse Width Modulation; PWM)是切換 式電源轉換器用來調節輸出電壓的一種方式，其係偵測輸 出電壓與參考值之間的差值，藉以決定功率開關的責任週 期（duty cycle)。 例如，考慮圖1所示的反驰轉換器100，來自交流電 壓源101提供的交流電壓VAC經電磁干擾（Electro-Magnetic Interference; EMI)濾波器 102 及橋式 整流器 (bridge rectifier) 104濾波及整流後得到具有漣波的直流輸 入電壓Vi，輕合至變壓器TX的一次側繞組（primary winding)Lp，功率開關SW與變壓器TX的一次側繞組Lp 串聯，控制器106輸出脈寬調變信號Vpwm切換功率開關 SW，以轉換輸入電壓Vi至變壓器TX的二次側產生輸出 電壓Vo。電阻R3與變壓器TX的一次側繞組Lp串聯，用 •以谓測一次側繞組電流Ip，進而控制脈寬調變信號vpwm •的時序(timing)。為了調節輸出電壓Vo,穩壓調整器ι10 及光輕合器（optical coupler) 108從變壓器TX的二次側取 - —迫授信號Vfb給控制器106，控制器106根據迴授信號1320990 IX. Description of the Invention: [Technical Field] The present invention relates to a switching power converter, and more particularly to a load variation compensation circuit of a switching power converter. [Prior Art] A switched power converter can produce a regulated output voltage with a smaller size and better performance. Switched power converters with a transformer-coupled architecture, such as flyback converters and forward converters, whose power output is isolated from the power input by a transformer, while the power switch is Located on the primary side of the transformer. Pulse Width Modulation (PWM) is a way for a switching power converter to regulate the output voltage. It detects the difference between the output voltage and the reference value to determine the duty cycle of the power switch. ). For example, considering the flyback converter 100 shown in FIG. 1, the AC voltage VAC from the AC voltage source 101 is filtered and rectified by an Electro-Magnetic Interference (EMI) filter 102 and a bridge rectifier 104. Then, a DC input voltage Vi having a chopper is obtained, which is coupled to the primary winding Lp of the transformer TX. The power switch SW is connected in series with the primary winding Lp of the transformer TX, and the controller 106 outputs a pulse width modulation signal Vpwm. The power switch SW generates an output voltage Vo by converting the input voltage Vi to the secondary side of the transformer TX. The resistor R3 is connected in series with the primary side winding Lp of the transformer TX, and the timing of the pulse width modulation signal vpwm is controlled by the primary side winding current Ip. In order to adjust the output voltage Vo, the voltage regulator adjuster ι10 and the optical coupler 108 take the signal Vfb from the secondary side of the transformer TX to the controller 106, and the controller 106 according to the feedback signal
Vfb調節脈寬調變信號Vpwm的責任週期，因而穩定輸出 電壓V〇。 圖2顯示圖1中脈寬調變信號Vpwm、一次側繞組電 φ 流Ip及二次侧繞組電流Is的波形圖，其中波形200表示 脈寬調變信號Vpwm，波形202表示一次側繞組電流ip， 波形204表示二次側繞組電流Is❶在脈寬調變信號Vpwm 的責任期間（〇n_duty period)Ton，功率開關SW導通，一次 側繞組電流Ip從〇逐漸增加，一次側繞組Lp因此儲存能 量 • |LpxIPK2=ILp(^xTon)2=|x^xT〇n2 公式！ 其中’ Ipk為一次側繞組電流Ip的峰值(peak value)，Vi為 一次側繞組Lp上的跨壓。在脈寬調變信號Vpwm的非責 任期間（off-duty period)Toff，功率開關SW關閉，儲存在 — 一次側繞組Lp的能量傳遞到二次側繞組Ls，因此二次侧 繞組電流Is從峰值ISK逐漸減少到0。二極體D1用來整流 ’電容Co被充電產生輸出電壓Vo。在非責任期間T〇ff, 變壓器TX的二次側消耗能量 1320990Vfb adjusts the duty cycle of the pulse width modulation signal Vpwm, thereby stabilizing the output voltage V〇. 2 is a waveform diagram showing the pulse width modulation signal Vpwm, the primary side winding electric φ flow Ip, and the secondary side winding current Is of FIG. 1, wherein the waveform 200 represents the pulse width modulation signal Vpwm, and the waveform 202 represents the primary side winding current ip. The waveform 204 indicates that the secondary side winding current Is ❶ is in the duty period (〇n_duty period) Ton of the pulse width modulation signal Vpwm, the power switch SW is turned on, the primary side winding current Ip is gradually increased from 〇, and the primary side winding Lp thus stores energy. |LpxIPK2=ILp(^xTon)2=|x^xT〇n2 Formula! Where ' Ipk is the peak value of the primary winding current Ip and Vi is the crossover voltage on the primary winding Lp. In the off-duty period Toff of the pulse width modulation signal Vpwm, the power switch SW is turned off, and the energy stored in the primary side winding Lp is transferred to the secondary side winding Ls, so the secondary side winding current Is is peaked. ISK is gradually reduced to zero. The diode D1 is used for rectification. The capacitor Co is charged to generate an output voltage Vo. During the non-responsibility period T〇ff, the secondary side of the transformer TX consumes energy 1320990
VoxIoxToff+Io2xRoxToff+IsxVfxToff 公式 2 其中，Io為輸出電流，大小等於二次側繞組電流Is的平均 值，Ro為二次側的輸出阻抗，Vf為二極體D1的順向偏壓 (forward voltage)。在公式2中，VoxIoxToff為負載得到的 能量，其餘則為二次側的耗損能量。 變壓器 TX的一次側另有輔助繞組（auxiliary winding)Laux，用來產生直流電壓VCC當作控制器106的 電源。實際上一次側繞組Lp儲存的能量係傳遞給二次側 繞組Ls及一次側的輔助繞組Laux，但是輔助繞組Laux 消耗的能量非常小，故可以忽略不計。讓公式1等於公式 2再除以Toff可得 公式3VoxIoxToff+Io2xRoxToff+IsxVfxToff Equation 2 where Io is the output current, the magnitude is equal to the average value of the secondary winding current Is, Ro is the output impedance of the secondary side, and Vf is the forward voltage of the diode D1. . In Equation 2, VoxIoxToff is the energy obtained by the load, and the rest is the energy of the secondary side. The primary side of the transformer TX has an auxiliary winding Laux for generating the DC voltage VCC as the power source for the controller 106. Actually, the energy stored in the primary side winding Lp is transmitted to the secondary side winding Ls and the primary side auxiliary winding Laux, but the energy consumed by the auxiliary winding Laux is very small and can be ignored. Let Equation 1 equal Equation 2 and divide by Toff. Equation 3
又因為二次側繞組Ls上的跨壓 公式4 V2=Vo+I〇xRo+Vf 且電流1〇為電流Is的平均值，故可將電流1〇視為電流Is ，因此根據公式3及公式4可得 7 1320990 1 VI2 Torf 1 V2=Vo+I〇xRo+Vf=r-x1rrfY〇 公式 5 由公式5可知，當負載電流I〇因為負載增加而增加時，二 次側繞組Ls上的跨壓V2及輸出電壓Vo都將下降，反之 則上升。 在反驰轉換器100中，從變壓器TX的二次側取得輸 出電壓反饋信號（output voltage feedback signal)可以提供 * 精準的輸出電壓調節，卻必定增加控制系統的複雜度和成 本。改用一次側迴授電路取得輸出電壓反饋信號可以減少 控制系統的複雜度和成本，但是必定造成精準調節的困難 度提兩。美國專利公開號第2003/0128018號、第 2004/0052095號及第2〇〇6/〇〇5〇539號使用複雜的運算在 一次側迴授系統中’來達成精準的輸出電壓調節。但是這 技術〶要較大且較複雜的電路，會增加電路尺寸及成本 擊’對於許多精準度要求不高的應用*言並不合適。 【發明内容】 本發明的目的之―，在於提出一種切換式電源轉換器 .的負載變動補償電路’其具有低成本的優勢。 ’ 換式電源轉換器的負載變動補償電路，用 來孤視誤差化號’在該誤差信號達到該一臨界值時，調 整輸出電壓反饋信號對一輸出電塵偵測信號的比例，該 誤差㈣及一脈寬調變信號因而改變，使該電源轉換器之 8 1320990 輸出電壓能穩定在預定之變動範圍内。 【實施方式】 圖3顯示應用本發明的第一實施例，在反馳轉換器300 中，來自交流電壓源302提供的交流電壓VAC經EMI濾波 器304及橋式整流器306產生具有漣波的直流輸入電壓Vi ，耦合至變壓器TX的一次側繞組Lp，功率開關SW與變 壓器TX的一次側繞組Lp串聯，PWM產生器314產生脈 寬調變信號Vpwm切換功率開關SW，將輸入電壓Vi轉換 為輸出電壓Vo。 輔助繞組Laux在變壓器TX的一次側用來偵測二次側 的輸出電壓Vo，其繞組電流Iaux經二極體D2整流，對電 容C1充電產生偵測信號VD。如前所述，使用一次側的輔 助繞組Laux來偵測輸出電壓Vo是習知技術。輔助繞組 Laux上的跨壓 V3=Vf2+VD 公式 6 其中，電壓Vf2為二極體D2的順向偏壓。假設繞組Lp、 Ls及Laux的匝數比為nl : n2 : n3，則二次側繞組電壓 V2=(n2/n3)xV3=NxV3 公式 7 其中，N為二次侧繞組Ls對輔助繞組Laux的匝數比。電 9 1320990 .阻R1及R2組成的分壓器對偵測信號VD分壓產生輸出電 壓反饋信號 VEl=VDx[R2/(Rl+R2)] 公式 8 ' 誤差放大器312的反相輸入端耦合輸出電壓反饋信號VE1 ，非反相輸入端耦合參考信號VREF1，誤差放大器312放 大二者的差值產生誤差信號COMP。電阻R6與一次側繞 ® 組Lp串聯，偵測一次側繞組電流Ip產生電流偵測信號CS ，PWM產生器314根據電流偵測信號CS及誤差信號 COMP決定脈寬調變信號Vpwm的時序與責任週期。使用 PWM產生器314根據電流偵測信號CS及誤差信號COMP 產生脈寬調變信號Vpwm也是習知技術。 負載變動補償電路310監視誤差信號COMP以調整該 輸出電壓反饋信號VE1對該偵測信號VD的比例。在負載 φ 變動補償電路310中，電阻R3及電晶體3104串聯在誤差 放大器312的反相輸入端VE1及接地GND之間，電阻R5 及電晶體3106串聯在比較器3102的反相輸入端及接地 GND之間，電阻R4耦合在電壓VR2與比較器3102的反 • 相輸入端之間，比較器3102的非反相輸入端耦合誤差信 - 號COMP，比較器3102藉由比較誤差信號COMP及其反 相輸入端上的臨界信號VREF2以導通或關閉電晶體3104 及 3106 。 公式8可改寫為 1320990 VD=VElx[l+(Rl/R2)] 公式 9 由於經負迴授穩定後，輸出電壓反饋信號VE1將等於參考 信號VREF1，因此可得 VD=VREF1X [ 1 +(R 1 /R2)] 公式 10 * 圖4顯示圖3中轉換器300的負載電流Ιο變化時輸出 電壓Vo及誤差信號COMP的波形圖，其中波形402表示 輸出電壓Vo，波形404表示誤差信號COMP。當負載上升 時，負載電流1〇上升，輸出電壓Vo下降，如波形402所 示，而電壓V2、偵測信號VD及輸出電壓反饋信號VE1 也都隨之下降，因而使得誤差信號COMP上升，如波形 404所示。在誤差信號COMP尚未高於臨界信號VREF2 φ 時，電晶體3104及3106為關閉狀態，此時臨界信號 VREF2=VR2 公式 11 • 當負載電流1〇上升至1〇2時，誤差信號COMP超越臨界 - 信號VREF2，比較器3102因輸出端轉態而導通電晶體 3104及3106，造成電阻R3與電阻R2並聯，因此輸出電 壓反饋信號變成 11 1320990 VE1 = VD x [(R2//R3 )/(R 1 +(R2//R3))] 公式 12 其中，R2//R3表示電阻R2及R3並聯的等效電阻值。因 此，在電晶體3104導通後，造成輸出電壓反饋信號VE1 短暫性微小降低，進而導致誤差信號COMP微小升高，如 波形404所示，脈寬調變產生器314偵測該誤差信號COMP 微小升高後，則提高該脈寬調變信號Vpwm的責任週期， 二次側繞組電壓V2隨即提升，根據公式5，輸出電壓Vo 也因而提升。 從另一方面來看，經負迴授穩定後，輸出電壓反饋信號 VE1將回到VREF1的準位，此時公式10變成 VD = VREFlx[l+(Rl/(R2//R3))] 公式 13 從公式13可知，偵測信號VD也因電阻R2及R3的並聯 φ 而上升至較高的值。假設二極體D1及D2具有相同的順向 偏壓，即Vf=Vf2，根據公式5、公式6及公式7可得And because the over-voltage formula 4 V2=Vo+I〇xRo+Vf on the secondary winding Ls and the current 1〇 is the average value of the current Is, the current 1〇 can be regarded as the current Is, so according to the formula 3 and the formula 4 Available 7 1320990 1 VI2 Torf 1 V2=Vo+I〇xRo+Vf=r-x1rrfY〇 Equation 5 It can be seen from Equation 5 that when the load current I〇 increases due to the load increase, the cross on the secondary winding Ls Both the voltage V2 and the output voltage Vo will decrease, and vice versa. In the flyback converter 100, obtaining an output voltage feedback signal from the secondary side of the transformer TX provides * accurate output voltage regulation, but necessarily increases the complexity and cost of the control system. Switching to the primary feedback circuit to obtain the output voltage feedback signal can reduce the complexity and cost of the control system, but it must be difficult to achieve precise adjustment. U.S. Patent Publication Nos. 2003/0128018, 2004/0052095, and 2, 6/5, 5, 539 use sophisticated calculations in a primary feedback system to achieve accurate output voltage regulation. However, this technique requires a larger and more complex circuit, which increases the circuit size and cost. It is not suitable for many applications where accuracy is not high. SUMMARY OF THE INVENTION An object of the present invention is to provide a load variation compensation circuit of a switching power converter which has the advantage of low cost. The load variation compensation circuit of the switching power converter is used for the orphan error correction number to adjust the ratio of the output voltage feedback signal to an output dust detection signal when the error signal reaches the threshold value, the error (4) And a pulse width modulation signal is thus changed, so that the 8 1320990 output voltage of the power converter can be stabilized within a predetermined variation range. [Embodiment] FIG. 3 shows a first embodiment to which the present invention is applied. In the flyback converter 300, an AC voltage VAC supplied from an AC voltage source 302 generates a DC having a chopper via an EMI filter 304 and a bridge rectifier 306. The input voltage Vi is coupled to the primary side winding Lp of the transformer TX, the power switch SW is connected in series with the primary side winding Lp of the transformer TX, and the PWM generator 314 generates a pulse width modulation signal Vpwm to switch the power switch SW to convert the input voltage Vi into an output. Voltage Vo. The auxiliary winding Laux is used to detect the output voltage Vo of the secondary side on the primary side of the transformer TX, and the winding current Iaux is rectified by the diode D2 to charge the capacitor C1 to generate the detection signal VD. As described above, it is a conventional technique to use the primary side auxiliary winding Laux to detect the output voltage Vo. The voltage across the auxiliary winding Laux V3 = Vf2 + VD Equation 6 where voltage Vf2 is the forward bias of diode D2. Assuming that the turns ratio of the windings Lp, Ls and Laux is nl : n2 : n3, the secondary winding voltage V2 = (n2 / n3) x V3 = NxV3 Equation 7 where N is the secondary winding Ls to the auxiliary winding Laux Turn ratio. Electricity 9 1320990. The voltage divider composed of resistors R1 and R2 divides the detection signal VD to produce an output voltage feedback signal VEl=VDx[R2/(Rl+R2)] Equation 8 'Inverting input coupling output of error amplifier 312 The voltage feedback signal VE1, the non-inverting input is coupled to the reference signal VREF1, and the error amplifier 312 amplifies the difference between the two to generate an error signal COMP. The resistor R6 is connected in series with the primary side winding group Lp, and detects the primary side winding current Ip to generate a current detection signal CS. The PWM generator 314 determines the timing and responsibility of the pulse width modulation signal Vpwm according to the current detection signal CS and the error signal COMP. cycle. It is also a conventional technique to generate the pulse width modulation signal Vpwm based on the current detection signal CS and the error signal COMP using the PWM generator 314. The load variation compensation circuit 310 monitors the error signal COMP to adjust the ratio of the output voltage feedback signal VE1 to the detection signal VD. In the load φ variation compensation circuit 310, the resistor R3 and the transistor 3104 are connected in series between the inverting input terminal VE1 of the error amplifier 312 and the ground GND, and the resistor R5 and the transistor 3106 are connected in series at the inverting input terminal of the comparator 3102 and grounded. Between GND, resistor R4 is coupled between voltage VR2 and the inverse input of comparator 3102, the non-inverting input of comparator 3102 is coupled with error signal -COMP, and comparator 3102 compares error signal COMP and The critical signal VREF2 on the inverting input turns on or off the transistors 3104 and 3106. Equation 8 can be rewritten as 1320990 VD=VElx[l+(Rl/R2)] Equation 9 Since the output voltage feedback signal VE1 will be equal to the reference signal VREF1 after being stabilized by the negative feedback, VD=VREF1X [ 1 +(R 1 /R2)] Formula 10 * FIG. 4 is a waveform diagram showing the output voltage Vo and the error signal COMP when the load current Ιο of the converter 300 of FIG. 3 is changed, wherein the waveform 402 represents the output voltage Vo, and the waveform 404 represents the error signal COMP. When the load rises, the load current increases by 1〇, and the output voltage Vo decreases. As shown by the waveform 402, the voltage V2, the detection signal VD, and the output voltage feedback signal VE1 also decrease, thereby causing the error signal COMP to rise, such as Waveform 404 is shown. When the error signal COMP is not higher than the critical signal VREF2 φ, the transistors 3104 and 3106 are in a closed state, and the critical signal VREF2=VR2 at this time. Equation 11 • When the load current 1〇 rises to 1〇2, the error signal COMP exceeds the criticality - The signal VREF2, the comparator 3102 conducts the crystals 3104 and 3106 due to the output state transition, causing the resistor R3 to be connected in parallel with the resistor R2, so the output voltage feedback signal becomes 11 1320990 VE1 = VD x [(R2//R3)/(R 1 +(R2//R3))] Equation 12 where R2//R3 represents the equivalent resistance value of the resistors R2 and R3 in parallel. Therefore, after the transistor 3104 is turned on, the output voltage feedback signal VE1 is temporarily reduced slightly, and the error signal COMP is slightly increased. As shown by the waveform 404, the pulse width modulation generator 314 detects the error signal COMP. After the high, the duty cycle of the pulse width modulation signal Vpwm is increased, and the secondary side winding voltage V2 is then increased. According to Equation 5, the output voltage Vo is also increased. On the other hand, after the negative feedback is stabilized, the output voltage feedback signal VE1 will return to the level of VREF1, and the formula 10 becomes VD = VREFlx[l+(Rl/(R2//R3))] Equation 13 As can be seen from Equation 13, the detection signal VD also rises to a higher value due to the parallel φ of the resistors R2 and R3. Assume that the diodes D1 and D2 have the same forward bias voltage, that is, Vf=Vf2, which can be obtained according to Equation 5, Equation 6, and Equation 7.
Vo=VDxN+(N-l)Vf-I〇xRo 公式 14 - 由公式14可知，當負載電流1〇增加時輸出電壓Vo將減 小。參照圖4，當負載電流1〇由1〇0上升至1〇2時，輸出 電壓Vo下降AV，如上所述，因電阻R2及R3並聯，V2 提升，而讓偵測信號VD也上升，導致輸出電壓Vo上升ΔΥ 12 1320990 抵消因負載電流I〇增加所造成的下降。將公式13減去公 式10可得偵測信號VD的變化量 △VD=VREFlx(Rl/R3) 公式 15 由公式15得知，偵測信號VD的變化量AVD與電阻R1 及R3以及參考信號VREF1有關，因此可以藉由選取適當 的電阻R1及R3以及參考信號VREF1使公式16中的 VDxN完全抵消IoxRo造成的衰減，使該電源轉換器之輸 出電壓Vo能穩定在預定之變動範圍Δν之内。 當負載電流1〇減少時，例如由1〇3降至Ιο 1，由於先 前已導通電晶體3106，故此時比較器3102的反相輸入端 的臨界信號 VREF2=VR2 x [R5/(R4+R5)] 公式 16 小於先前的臨界值VR2。當負載電流Ιο降至1〇2時，比較 器3102的輸出並沒有轉態，而要等負載電流1〇再下降至 1〇1時，誤差信號COMP才會小於臨界信號VREF2，造成 比較器3102的輸出再轉態使電晶體3104及3106關閉， 因而導致誤差信號COMP及輸出電壓Vo微小下降，自此 ，臨界信號VREF2又回復為VR2 .，而偵測信號VD也回 復如公式12所示。此磁滯（hysteresis)設計可以避免雜訊干 擾，進一步優化性能。 13 在此實施例中，為了方便爷 載補償單元，實際上，負載：：月及理解’只顯示-個負 多個負载補補償電路训可以包括更 大器^ 母貞制償 大器312的反相輸入端VE卜且自耦合至誤差放 信號具有不同的臨界值，例如，第㈤、補償單^的臨界 考電壓為VR2H個㈣ 負_償單元的參 ，如此，如同圖4的波形4:=早:二參 到第一個負制償單元的參考電4^號 COMP精微拉高，在誤差信號c〇Mp ' 單元的參考電壓VR3時，誤差Μ 個負載_ 南，依此類推’每當誤差信號C0MP相―個負載補償單 兀的臨界值時，都將使誤差信號C0MP稍微拉高。反之， 在誤差信號COMP減小的過財，也是依序觸發不同的負 載補償單元，而稍微拉低誤差信號COMP。 圖5顯示本發明的第二實施例，在反馳轉換器5〇〇中 ，除了負載變動補償電路510以外，其他元件與圖3所示 相同，不再贅述。負載變動補償電路51〇監視誤差信號 COMP以調整該輸出電壓反饋信號VE1對該债測信號vD 的比例。在負載變動補償電路510中，電晶體5104及電 阻R3串聯在誤差放大器512的反相輸入端VE1及接地 GND之間，電阻R4與齊納二極體D3串聯在誤差放大器 512的輸出COMP及接地GND之間’運算放大器5102的 非反相輸入端耦合齊納二極體D3的陽極，其反相輸入端 耦合電阻R3，其輸出端產生控制信號給電晶體5104的閘 1320990 極。齊納.二極體D3在此作為一偏壓元件，本發明之偏壓 元件並不偈限為齊納二極體。 圖6顯示圖5中輸出電壓Vo及誤差信號COMP的波 形圖，其中波形602表示誤差信號COMP，波形604表示 輸出電壓Vo。當負載上升時，負載電流1〇上升，輸出電 壓Vo下降，如波形604所示，二次側繞組Ls上的跨壓 V2、偵測信號VD及輸出電壓反饋信號VE1也都隨之下降 ，因而使得誤差信號COMP上升，如波形602所示。當誤 差信號COMP大於齊納二極體D3的崩潰電壓VZ時，運 算放大器5102的非反相輸入端之電壓Vl=COMP-VZ，運 算放大器5102因而導通電晶體5104，根據負迴授之虛短 路(virtual short)原理，運算放大器5102的反相輸入端之電 壓將等於VI之電壓，因此流經電阻R3之電流IR3為 IR3=(COMP-VZ)/R3 公式 17 由於崩潰電壓VZ為定值，因此電流IR3的變化量正比於 誤差信號COMP的變化量。如同第一實施例之推導，本實 施例之偵測信號VD在電晶體5104關閉時可表示為如公式 9所示，偵測信號VD在電晶體5104導通時可表示為 VD=VE1 X [ 1 +(R 1 /R2)]+IR3 x R1 公式 18 將公式17代入公式18後，可得 15 1320990 VD=VElx[l+(Rl/R2)]+[(COMP-VZ)/R3]xRl 公式 19 將公式19減去公式9可得偵測信號VD在電晶體5104導 通前後的變化量 ΔVD=(R 1 /R3)X(COMP-VZ) 公式 20 從公式20可知，偵測信號VD的變化量AVD與誤差信號 ® COMP成正比。再根據公式14，偵測信號VD的增加可以 抵消輸出電壓Vo因負載電流1〇所造成的衰減，又因誤差 信號COMP正比於負載電流1〇，因此，適當地選取電阻 R1及R3可以使輸出電壓Vo保持在一穩定值，如波形604 所示。 在本發明的第二實施例中，當電晶體5104導通後， 該偵測信號VD對該輸出電壓反饋信號VE1的比例可由公 φ 式19進一步推導為 [l+(Rl/R2)]+[(COMP-VZ)/R3]x[Rl/VREFl]，因誤差信號 COMP正比於負載電流1〇，因此該輸出電壓反饋信號VE1 對該偵測信號VD的比例係一變動值，若負載電流1〇持續 • 增加’適當地選取電阻R1及R3可以使輸出電壓Vo保持 -+ 在一穩定值。 如以上的實施例所揭示的，本發明的負載變動補償電 路及方法只運用了少數的元件及簡單的電路，在誤差信號 COMP達到臨界值時調整該輸出電壓反饋信號VE1對該偵 16 1320990Vo=VDxN+(N-l)Vf-I〇xRo Equation 14 - As can be seen from Equation 14, the output voltage Vo will decrease as the load current 1〇 increases. Referring to FIG. 4, when the load current 1〇 rises from 1〇0 to 1〇2, the output voltage Vo falls AV. As described above, since the resistors R2 and R3 are connected in parallel, V2 is boosted, and the detection signal VD is also raised, resulting in an increase in the detection signal VD. The output voltage Vo rises by ΔΥ 12 1320990 to offset the drop due to the increase in load current I〇. Subtracting Equation 13 from Equation 10 gives the amount of change in the detection signal VD ΔVD=VREFlx (Rl/R3) Equation 15 It is known from Equation 15 that the amount of change AVD of the detection signal VD and the resistors R1 and R3 and the reference signal VREF1 Accordingly, the VDxN in Equation 16 can be completely offset by the attenuation caused by IoxRo by selecting appropriate resistors R1 and R3 and the reference signal VREF1, so that the output voltage Vo of the power converter can be stabilized within a predetermined variation range Δν. When the load current 1〇 decreases, for example, from 1〇3 to Ιο1, since the crystal 3106 has been previously energized, the critical signal of the inverting input of the comparator 3102 is VREF2=VR2 x [R5/(R4+R5) Equation 16 is smaller than the previous threshold VR2. When the load current Ιο falls to 1〇2, the output of the comparator 3102 does not change state, and when the load current 1〇 falls to 1〇1, the error signal COMP is less than the critical signal VREF2, resulting in the comparator 3102. The output re-transition causes the transistors 3104 and 3106 to be turned off, thereby causing the error signal COMP and the output voltage Vo to drop slightly. Since then, the threshold signal VREF2 is restored to VR2. The detection signal VD also returns as shown in Equation 12. This hysteresis design avoids noise interference and further optimizes performance. 13 In this embodiment, in order to facilitate the load compensation unit, in fact, the load:: month and understand that 'only display-negative multiple load compensation circuit training can include a larger device ^ mother-made compensation device 312 The inverting input terminal VE and the self-coupling to the error discharge signal have different critical values. For example, the threshold voltage of the (5)th, compensation matrix is VR2H (four) negative compensation unit parameters, thus, like the waveform 4 of FIG. := Early: The reference to the first negative compensation unit of the second reference COM4 is slightly high, when the error signal c〇Mp 'unit reference voltage VR3, the error Μ load _ south, and so on' Whenever the error signal C0MP phase-a load compensation unit 临界 threshold value, the error signal C0MP will be slightly pulled high. Conversely, when the error signal COMP is reduced, the different load compensation units are sequentially triggered, and the error signal COMP is slightly pulled down. Fig. 5 shows a second embodiment of the present invention. In the flyback converter 5, except for the load variation compensation circuit 510, the other elements are the same as those shown in Fig. 3 and will not be described again. The load variation compensation circuit 51 monitors the error signal COMP to adjust the ratio of the output voltage feedback signal VE1 to the debt measurement signal vD. In the load variation compensation circuit 510, the transistor 5104 and the resistor R3 are connected in series between the inverting input terminal VE1 of the error amplifier 512 and the ground GND, and the resistor R4 is connected in series with the Zener diode D3 at the output COMP of the error amplifier 512 and ground. Between GND's non-inverting input of operational amplifier 5102 is coupled to the anode of Zener diode D3, its inverting input is coupled to resistor R3, and its output produces a control signal to gate 1320990 of transistor 5104. The Zener diode D3 is here a biasing element, and the biasing element of the present invention is not limited to a Zener diode. Figure 6 shows a waveform diagram of the output voltage Vo and the error signal COMP of Figure 5, wherein waveform 602 represents the error signal COMP and waveform 604 represents the output voltage Vo. When the load rises, the load current increases and the output voltage Vo decreases. As shown by the waveform 604, the voltage across the secondary winding Ls, the detection signal VD, and the output voltage feedback signal VE1 also decrease. The error signal COMP is caused to rise as shown by waveform 602. When the error signal COMP is greater than the breakdown voltage VZ of the Zener diode D3, the voltage Vl=COMP-VZ of the non-inverting input terminal of the operational amplifier 5102, the operational amplifier 5102 thus conducts the crystal 5104, and the virtual short circuit according to the negative feedback (virtual short) principle, the voltage of the inverting input terminal of the operational amplifier 5102 will be equal to the voltage of VI, so the current IR3 flowing through the resistor R3 is IR3=(COMP-VZ)/R3 Equation 17 Since the breakdown voltage VZ is constant, Therefore, the amount of change in the current IR3 is proportional to the amount of change in the error signal COMP. As the derivation of the first embodiment, the detection signal VD of the present embodiment can be expressed as shown in Equation 9 when the transistor 5104 is turned off, and the detection signal VD can be expressed as VD=VE1 X when the transistor 5104 is turned on. +(R 1 /R2)]+IR3 x R1 Equation 18 After substituting the formula 17 into the formula 18, 15 1320990 VD=VElx[l+(Rl/R2)]+[(COMP-VZ)/R3]xRl Equation 19 Subtracting Equation 9 from Equation 9 gives the amount of change ΔVD=(R 1 /R3)X(COMP-VZ) of the detection signal VD before and after the transistor 5104 is turned on. Equation 20 From Equation 20, the amount of change in the detection signal VD is known. The AVD is proportional to the error signal ® COMP. According to the formula 14, the increase of the detection signal VD can offset the attenuation caused by the load current 1〇 by the output voltage Vo, and the error signal COMP is proportional to the load current 1〇. Therefore, appropriately selecting the resistors R1 and R3 can make the output The voltage Vo is maintained at a stable value as shown by waveform 604. In the second embodiment of the present invention, when the transistor 5104 is turned on, the ratio of the detection signal VD to the output voltage feedback signal VE1 can be further derived from the common φ equation 19 as [l+(Rl/R2)]+[( COMP-VZ)/R3]x[Rl/VREFl], because the error signal COMP is proportional to the load current 1〇, the ratio of the output voltage feedback signal VE1 to the detection signal VD is a variable value, if the load current is 1〇 Continue • Increase 'Appropriately select resistors R1 and R3 to keep the output voltage Vo -+ at a stable value. As disclosed in the above embodiments, the load variation compensation circuit and method of the present invention uses only a few components and a simple circuit, and adjusts the output voltage feedback signal VE1 to the detect when the error signal COMP reaches a critical value.
測信號VD的比例，該誤差信號COMP因而改變，該PWM 產生器314再根據該誤差信號COMP之變化調整該脈寬調 變信號Vpwm，使該電源轉換器之輸出電壓Vo能穩定在預 定之變動範圍之内。 17 1320990 【圖式簡單說明】 圖1係習知的反驰轉換器； 圖2顯示圖1中脈寬調變信號、一次側繞組電流及二 次侧繞組電流的波形圖， 圖3顯示應用本發明的第一實施例； 圖4顯示圖3中的轉換器在負載變化時，負載電流、 輸出電壓及誤差信號的波形圖； 圖5顯示應用本發明的第二實施例；以及 圖6顯示圖5中的轉換器在負載變化時，負載電流、 輸出電壓及誤差信號的波形圖。 【主要元件符號說明】 100 反驰轉換器 101 交流電壓源 102 EMI濾波器 104 橋式整流器 106 控制器 108 光耦合器 110 穩壓調整器 200 脈寬調變信號的波形 202 一次側繞組電流的波形 204 二次側繞組電流的波形 300 反馳轉換器 302 交流電壓源 18 1320990 304 EMI濾波器 306 橋式整流器 310 負載變動補償電路 3102 比較器 3104 電晶體 3106 電晶體 312 誤差放大器 314 PWM產生器The ratio of the signal VD is measured, the error signal COMP is thus changed, and the PWM generator 314 adjusts the pulse width modulation signal Vpwm according to the change of the error signal COMP, so that the output voltage Vo of the power converter can be stabilized at a predetermined variation. Within the scope. 17 1320990 [Simple diagram of the diagram] Figure 1 is a conventional flyback converter; Figure 2 shows the waveform of the pulse width modulation signal, the primary winding current and the secondary winding current of Figure 1, Figure 3 shows the application A first embodiment of the invention; FIG. 4 is a waveform diagram showing load current, output voltage and error signals of the converter of FIG. 3 when the load changes; FIG. 5 shows a second embodiment to which the present invention is applied; The waveform of the load current, output voltage and error signal of the converter in 5 when the load changes. [Main component symbol description] 100 Reverse converter 101 AC voltage source 102 EMI filter 104 Bridge rectifier 106 Controller 108 Photocoupler 110 Regulator adjuster 200 Pulse width modulation signal waveform 202 Primary side winding current waveform 204 Secondary winding current waveform 300 Reverse converter 302 AC voltage source 18 1320990 304 EMI filter 306 Bridge rectifier 310 Load variation compensation circuit 3102 Comparator 3104 Transistor 3106 Transistor 312 Error amplifier 314 PWM generator
402 輸出電壓的波形 404 誤差信號的波形 500 反馳轉換器 510 負載變動補償電路 5102 運算放大器 5104 電晶體 602 誤差信號的波形402 Output voltage waveform 404 Error signal waveform 500 Reverse converter 510 Load variation compensation circuit 5102 Operational amplifier 5104 Transistor 602 Error signal waveform
604 輸出電壓的波形604 output voltage waveform