TW201817165A - Clocked commands timing adjustments in synchronous semiconductor integrated circuits - Google Patents

Abstract

A clock timing adjust circuit is incorporated in a clocked integrated circuit to detect an input clock frequency and to adjust the timing latency of an internal control signal for accessing a memory element in the clocked integrated circuit. The clock timing adjust circuit introduces an adjustable timing latency to an internal control signal derived from the command signal. The clock timing adjust circuit operates to adjust the timing latency of the control signal to cause clock based operations to either be advanced or delayed by one or more clock cycles in response to the clock frequency detection. In one embodiment, the clock timing adjust circuit includes a clock frequency detect circuit and a latency adjust circuit. The clock timing adjust circuit can operate at both high and low clock frequencies to ensure that undesired data collision events are obviated without introducing unnecessary delays.

Description

Clock command time adjustment in synchronous semiconductor integrated circuit

Synchronous or clocked semiconductor integrated circuits have circuits driven by a clock signal. Generally, an input clock is provided to a synchronous semiconductor integrated circuit, and the internal circuit of the integrated circuit is driven by the input clock or a derivative of one of the input clocks. In the clock control integrated circuit, a major concern during operation is the sequencing and acquisition of various internal time signals. Internal time signals are generated from both synchronous and asynchronous events. Synchronous events are clocked and timed from the rising or falling edge of the input clock. Asynchronous events are based on gate delay and / or based on The interconnection delay of the interconnecting wires and capacitors of integrated circuits is called the RC delay. The internal time signals of the first group (generated from synchronization events and in which the stem is mainly based on clock gating) have minimal or no temperature, wafer manufacturing process, or voltage dependence on their time. However, the internal time signal of the first group will directly depend on the clock frequency. The second group of internal time signals (signs generated from asynchronous events and whose time axis is mainly based on the gate delay and RC delay) will have the time, manufacturing process and voltage that they shift or change within the allowable range of different temperatures Operating conditions. In some cases, the internal time signal can enter a collision domain. A time conflict occurs when the arrival of a data signal does not match the acquisition signal intended to capture and store that data signal. In one example, one of the output buffers in the clock product circuit is implemented as a first-in-first-out (FIFO) register. The first-in-first-out register is derived from an input clock or an output of one of the input clocks. The clock. A collision domain event may occur when data from a subsequent memory read operation (a major asynchronous event) rewrites the latched data before the data latched in an output buffer is read by the receiving system. . In another example, such as during high-speed operation, the RC delay may cause data from a read operation to reach the output buffer later than requested, and thus the clock product circuit sends invalid data.

The invention can be implemented in numerous ways, including as a process, a device, a system, and / or a substance. In this specification, these embodiments or any other form that the invention may take may be referred to as technology. Generally, the order of the steps of the disclosed processes may be changed within the scope of the present invention. The following provides a detailed description of one or more embodiments of the invention, together with the accompanying drawings, which illustrate the principles of the invention. The present invention is described in conjunction with these embodiments, but the present invention is not limited to any embodiment. The scope of the invention is limited only by the scope of the patent application and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the present invention. These details are provided for the purpose of example, and the invention may be practiced according to the scope of the patent without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail, so the invention is not unnecessarily obscured. According to an embodiment of the present invention, a clock time adjustment circuit is incorporated in a clock product circuit to detect an input frequency or an operating frequency range of an input clock of the clock product circuit and adjust an internal control. The time delay of the signal is used to access a memory element in the clock product circuit. The clock product circuit receives a command signal to access the memory elements in the clock product circuit. The command signal is used to generate an internal control signal, and the generated internal control signal is routed to the memory element of the clock product circuit to access the memory element. The clock time adjustment circuit introduces an adjustable time delay to the internal control signal derived from the command signal. In an embodiment of the present invention, the clock time adjustment circuit operates in response to the frequency detection to shift or adjust the time delay of the internal control signal during operation, so that the clock-based operation is advanced or delayed by one or more hours. Pulse cycle. The clock timing adjustment circuit of the present invention enables the clock product circuit to operate over a wide frequency range, while ensuring that unwanted data conflict events are avoided without introducing unnecessary delays. The clock time adjustment circuit can be implemented without using a mode register setting command or other non-conventional operating procedures. Instead, the clock time adjustment circuit can be operated in real time during normal circuit operation or "on the fly" to adjust the internal time signal to avoid data conflicts. The clock timing adjustment circuit of the present invention can be advantageously applied to memory circuits such as dynamic random access memory (DRAM), NAND flash memory, static random access memory (SRAM), or other types of volatile Memory or non-volatile memory. The clock timing adjustment circuit of the present invention can also be advantageously applied to a logic circuit, such as a microprocessor integrated circuit. Generally, the clock timing adjustment circuit of the present invention can be applied to any clock integrated circuit or synchronous integrated circuit including a memory element such as a memory on a chip. The clock timing adjustment circuit can be advantageously used to adjust the timing of the internal memory access control signals to avoid conflict events that may occur during memory access operations such as read operations and write operations of memory elements. More specifically, in the embodiment of the present invention, the clock time adjustment circuit detects that the input clock of the clock product circuit is running slowly (at a low frequency) or running fast (at a high frequency). Frequency). The clock time adjustment circuit generates an internal control signal based on a command signal received by the clock product circuit and uses a predetermined adjustable time delay amount. The clock time adjustment circuit adjusts the time delay of the internal control signal based on the detected frequency of the input clock and according to the command signal. In one example, in response to detecting that the input clock is at a low frequency, the clock time adjustment circuit uses a predetermined time delay to generate an internal control signal. However, in response to detecting that the input clock is at a high frequency, the clock time adjustment circuit generates an internal control signal that is advanced or delayed by one or more clock cycles relative to a predetermined time delay. In another example, in response to detecting that the input clock is at a high frequency, the clock time adjustment circuit uses a predetermined time delay to generate an internal control signal. At the same time, in response to detecting that the input clock is at a low frequency, the clock time adjustment circuit generates an internal control signal that is advanced or delayed by one or more clock cycles relative to a predetermined time delay. In particular, the clock timing adjustment circuit may generate an internal control signal that is one or more clock cycles in advance by removing one or more clock cycles based on a predetermined time delay. Advancing a control signal by one or more clock cycles will introduce one or more additional clock cycles to provide time margin for downstream data operations. In a clock memory circuit, advancing a control signal in advance results in advance of reading data for a particular data reading operation, as will be explained in more detail below. On the other hand, the clock time adjustment circuit may generate an internal control signal delayed by one or more clock cycles by adding one or more clock cycles based on a predetermined time delay. Delaying a control signal by one or more clock cycles will introduce one or more additional clock cycles into the internal signal path of a clock product circuit. In a clock memory circuit, delaying a control signal causes a data delay for a specific data write operation, as described in more detail below. In an embodiment of the present invention, the clock timing adjustment circuit of the present invention can be advantageously applied to a memory circuit (such as a dynamic random access memory (DRAM), a NAND flash memory) or a logic circuit (such as a microcomputer). processor). In the following description, the application of the clock timing adjustment circuit of the present invention in a memory device and a microprocessor device will be described with specific implementation details provided for the synchronous memory circuit. However, those skilled in the art will understand that the clock time adjustment circuit of the present invention can be applied to any clock integrated circuit or synchronous integrated circuit to adjust the clock time, thereby avoiding conflicts due to time signal delay on the chip . In particular, the clock time adjustment circuit of the present invention can be applied to any clock integrated circuit or synchronous integrated circuit having a memory element on a chip to adjust the clock time of the control signal to access the memory on the chip. Body components. The on-chip memory element may be an on-chip memory array or a register or a register bank. In this description, a clock integrated circuit or a clock controlled integrated circuit refers to a semiconductor integrated circuit having a circuit driven by a clock signal. The clock integrated circuit is sometimes called a synchronous integrated circuit. An input clock is provided to the synchronous semiconductor integrated circuit, and the internal circuit of the integrated circuit is driven by an input clock or an output derived from one of the input clocks. Examples of the clock product circuit include a clock synchronous memory device and a clock microprocessor device or a synchronous microprocessor device. A clock product circuit is typically coupled to a clock-based (or clock cycle-based) external system that accesses the clock product circuit synchronously. In addition, in this description, a command signal is provided to an integrated circuit so that the integrated circuit performs a function supported by the integrated circuit. In this description, a command signal is different from a bit address signal, and the address signal specifies the position of the function to be applied in the integrated circuit. A command signal is also different from a data signal that provides a data value for a function to be applied. The integrated circuit receives the command signal to generate an internal control signal to control the integrated circuit circuit. In an embodiment of the present invention, the clock product circuit receives a command signal to access a memory element of the clock product circuit. In addition, in some embodiments, the command signal may include a read command signal and a write command signal. FIG. 1 is a block diagram of a synchronous memory device in which a clock timing adjustment circuit can be incorporated in an exemplary embodiment of the present invention. A generalized architecture of a synchronous memory device 10 is shown in FIG. 1 to illustrate the use of the clock timing adjustment circuit of the present invention in a memory circuit. The synchronous memory device 10 may include additional components not shown in FIG. 1 to complete the memory circuit. In addition, the memory architecture shown in FIG. 1 is merely illustrative, and it will be understood that the clock timing adjustment circuits and methods described herein can be used in other memory architectures. In some examples, the synchronous memory device 10 may be configured as a DRAM, SRAM, flash memory, or other types of volatile or non-volatile memory. Referring to FIG. 1, the synchronous memory device 10 includes a two-dimensional array 12 of memory cells 14. The memory cells 14 in the array 12 are accessed by word lines (columns) and bit lines (rows). A row of decoders 18 and a row of decoders 20 address the cell array 12 to selectively access the memory cells 14 in the array 12 for read operations and write operations. Specifically, a bit address ADDR is received at a control circuit 16 and the received address is decoded by a column decoder 18 that selects the word lines of the memory array 12 and a row decoder 20 that selects the bit lines. The column decoder 18 selectively activates a word line and the row decoder selectively activates a bit line to allow access to a memory cell 14 at the intersection of the selected word line and the selected bit line. The synchronous memory device 10 also receives a command signal to control the operation of the memory device. The command signal is received by the control circuit 16, and then one or more control signals are generated based on the command signal. The command signal may include a read command signal for reading data from the memory array or a write command signal for writing data to the memory array. The synchronous memory device 10 may also receive other command signals to support the operation of the memory device. As a synchronous or clock device, the synchronous memory device 10 also receives an input clock signal CLK having a given clock frequency at the control circuit. The control circuit generates an internal clock signal based on the input clock signal CLK to control the operation of the memory circuit. To read data from the clock memory circuit, the sense amplifier 24 senses the read data from the selected memory cell of the memory array 12 and the I / O gate circuit 22 connects the selected positioning element line to the storage. One of the read data reads the FIFO 26. As a clock memory device, the read FIFO 26 is controlled by a clock signal CLK2 _R Control, CLK2 _R It is the same as or derived from the input clock signal CLK. In response to the clock signal CLK2 _R The read data is provided to an output buffer 28 to provide the output data DOUT as one of the circuits and systems external to the synchronous memory device 10. To write data into the clock memory circuit, it is received by the synchronous memory device 10 and more specifically an input buffer 30 receives the written data DIN from external circuits and systems. Then, the written data DIN is transmitted to the clock signal CLK2. _W One of the controls is written to the FIFO 32. In response to the clock signal CLK2 _W , The written data is latched into the write FIFO 32 from the input buffer 30 and the written data is read from the write FIFO 32 again. The write data is supplied from the write FIFO 32 to the write driver circuit. The write driver circuit drives the write data to the selected positioning element line through the I / O gate control circuit 22 so that the data is stored in the selected memory unit 14. According to an embodiment of the present invention, a clock time adjustment circuit 80 is incorporated in the synchronous memory device 10 to generate a time-adjusted control signal to access the memory array. Specifically, the clock time adjustment circuit 80 receives an input clock signal CLK from the control circuit 16 and also receives command signals such as a read command and a write command from the control circuit 16. The clock time adjustment circuit 80 generates a time adjustment internal control signal based on the detected input clock frequency, such as L-Read for a read command and L-Write for a write command, as described in more detail below. The time-adjusted control signals L-Read and L-Write are coupled to the memory array 12 to control read and write operations to the memory array 12. In some embodiments, the clock timing adjustment circuit 80 may be formed as a part of the control circuit 16. The exact configuration of the clock time adjustment circuit 80 in the synchronous memory device 10 is not important to the practice of the present invention. The only necessary clock timing adjustment circuit 80 generates a time-adjusted control signal to operate the memory array with the desired time adjustment. FIG. 2 is a block diagram of a microprocessor device in which a clock timing adjustment circuit can be incorporated in an exemplary embodiment of the present invention. Referring to FIG. 2, a microprocessor device or a microprocessor integrated circuit 50 includes various functional blocks 52 such as an arithmetic logic unit (ALU), a random access memory (RAM), a shift register, and a first order Storage device (L1 cache). The functional block 52 is sometimes called a macro block. Many of the macro blocks 52 are clock circuits, and the clock circuit needs to transmit data back and forth through the silicon of the integrated circuit over a large distance. Propagation delays in the data signal path can cause data to reach the destination macro block outside the expected clock cycle. Therefore, in some embodiments, a clock timing adjustment circuit 80 of the present invention is incorporated into the microprocessor device 50 to adjust the timing of control signals used to transfer data between functional blocks or macro blocks. . For example, the clock timing adjustment circuit 80 receives an input clock signal CLK from the microprocessor device 50 and also receives a command signal. The clock time adjustment circuit 80 generates a time-adjusted control signal L-command, which can be used to control the macro block 1 and / or the macro block 2 to promote data in the macro block of the microprocessor device. Time to time. In some examples, the command signal is used to access a memory element in the macro block 52 and the command signal may be a read command signal or a write command signal. The clock timing adjustment circuit of the present invention can be incorporated into other logic circuits than a microprocessor integrated circuit. The microprocessor integrated circuit of FIG. 2 is merely illustrative and is not intended to be limiting. FIG. 3 (a) is a block diagram of a clock timing adjustment circuit in some embodiments of the present invention. Referring to FIG. 3 (a), a clock time adjustment circuit 80 includes a clock frequency detection circuit 82 and a delay adjustment circuit 86. The clock frequency detection circuit 82 receives an input clock signal CLK of the clock product circuit and generates a clock detection output signal FASTCLK. The clock frequency detection circuit 82 detects the clock frequency of the input clock signal CLK to determine whether the input clock signal CLK is higher than a predetermined frequency threshold or lower than a predetermined frequency threshold. In this description, a frequency above a frequency threshold is referred to as a high-frequency clock, and a frequency below a frequency threshold is referred to as a low-frequency clock. For example, in an application, a high frequency clock is considered to be greater than 500 MHz. Therefore, in one embodiment, the frequency threshold is 500 MHz. An input clock frequency of 500 MHz or higher is considered as a high clock frequency, and an input clock frequency below 500 MHz is considered as a low clock frequency. When the input clock frequency is equal to or greater than the frequency threshold, the clock frequency detection circuit 82 confirms the FASTCLK output signal to indicate a high clock frequency. Otherwise, deassert the FASTCLK output signal to indicate a low clock frequency. The delay adjustment circuit 86 receives the FASTCLK signal from the clock frequency detection circuit 82 and also receives the command signal received by the clock product circuit and also receives the input clock signal CLK. The delay adjustment circuit 86 generates an internal control signal L-Command based on the command signal and in response to the FASTCLK signal. In operation, the delay adjustment circuit 86 is configured to add a given amount of time delay to the command signal to generate a control signal L-Command. The time delay amount is given as the number of clock cycles or clock cycles of the input clock signal, and can represent the time delay of the internal control signal expected in the low frequency operation mode or the high frequency operation mode. That is, the predetermined time delay amount introduced by the delay adjustment circuit 86 may have a delay value suitable for operating the clock product circuit at a low clock frequency. Alternatively, the predetermined time delay amount introduced by the delay adjustment circuit 86 may have a delay value suitable for operating the clock product circuit at a high clock frequency. Then, depending on the state of the FASTCLK signal, the delay adjustment circuit 86 adjusts the time delay by adding a clock cycle or removing the clock cycle from a predetermined time delay, thereby delaying or advancing the internal control signal L-Command. In one example, the delay adjustment circuit 86 does not apply time adjustment when the FASTCLK signal is deasserted. Therefore, the control signal L-Command is generated with a predetermined time delay for low-frequency operation. On the other hand, the delay adjustment circuit 86 applies a time adjustment when the FASTCLK signal is verified. Therefore, the control signal L-Command generates an adjusted time delay for high frequency operation. Time adjustment may involve advancing the control signal by one or more clock cycles with respect to low frequency operation. Time adjustment may also involve delaying the control signal by one or more clock cycles with respect to low frequency operation. Then, the time-adjusted control signal is used to access the memory elements of the clock product circuit. Because of this configuration, the time-adjusted control signal ensures that the data signals transmitted in the clock product circuit are captured at the correct time and collision events are avoided. In other examples, the delay adjustment circuit 86 may be configured to operate in the opposite way: that is, no time adjustment is applied when the FASTCLK signal is asserted, and time adjustment is applied when the FASTCLK signal is deasserted. A clock product circuit typically receives multiple command signals that will need to be time adjusted based on the input clock frequency to ensure proper circuit operation without conflict events. For example, in a clock product circuit including a memory element, the clock product circuit may receive a read command to read data from the memory element and write data to the memory element. One write command. Therefore, the clock product circuit may include a separate instance of the clock time adjustment circuit 80 for each command signal. That is, the clock timing adjustment circuit 80 can be repeated for each command signal. In an alternative embodiment, the clock timing adjustment circuit may be configured to detect a plurality of command signals of the circuit using a common clock frequency. FIG. 3 (b) is a block diagram of a clock timing adjustment circuit in an alternative embodiment of the present invention. Referring to FIG. 3 (b), a clock time adjustment circuit 90 is configured to generate internal control signals for two command signals (Command 1 and Command 2) received by the integrated circuit. The clock timing adjustment circuit 90 is configured to generate a single clock frequency detection circuit 82 of a FASTCLK signal to indicate a low clock frequency or a high clock frequency. The clock time adjustment circuit 90 is configured with two examples of the delay adjustment circuits 86-1 and 86-2. Each delay adjustment circuit instance receives a FASTCLK signal, an input clock signal CLK, and a respective command signal. The delay adjustment circuit 86-1 generates a time-adjusted control signal L-Command1, and the delay adjustment circuit 86-2 generates a time-adjusted control signal L-Command2. In the case of multiple command signals, when the same frequency threshold can be applied to two command signals, the configuration of the clock time adjustment circuit 90 of FIG. 3 (b) provides the advantage of simplifying the circuit. In this case, a single clock frequency detection circuit 82 is required to generate the FASTCLK signal to adjust the delay time of multiple command signals. Each delay adjustment circuit 86 can have the same or different time delay amount, and can be configured to add or remove clock cycles according to the command signal. In other examples, the clock product circuit can be configured with multiple examples of the clock time adjustment circuit 80 of FIG. 3 (a) for multiple command signals. In this way, it is possible to apply different frequency thresholds to different command signals. For example, a read command signal may be processed using a frequency threshold of 500 MHz, and a write command signal may be processed using a frequency threshold of 600 MHz. In this case, separate instances of the clock time adjustment circuit 80 are used for read commands and write command signals, and the clock frequency detection circuit 82 in each instance of the clock time adjustment circuit 80 is configured to Used for desired frequency threshold. The clock timing adjustment circuit of the present invention realizes many advantages over the conventional collision avoidance method used in the clock product circuit. First, the clock timing adjustment circuit of the present invention can be advantageously applied to a clock or synchronous integrated circuit designed to operate over a wide range of input clock frequencies. The clock time adjustment circuit operates to adjust internal control signals based on the input clock frequency to avoid conflict events and ensure effective operation over the entire input clock frequency range. Second, the use of the clock timing adjustment circuit of the present invention in a clock product circuit avoids the need to use extra depth FIFO / output buffer circuit blocks to handle the need to read data. The use of the clock time adjustment circuit of the present invention in a clock product circuit can also avoid the need to use an extra depth FIFO / input register in the memory array to process written data. It is not advisable to use the extra depth FIFO as an output buffer or an input register because it requires additional silicon area and increases the size of the integrated circuit, thereby increasing the cost of the integrated circuit. The clock timing adjustment circuit of the present invention can be incorporated into a clock product circuit to reduce costs and improve speed performance while reducing power consumption. FIG. 4 illustrates a block diagram of a read path and a write path of a synchronous memory device incorporated in a clock time adjustment circuit in an embodiment of the present invention. Referring to FIG. 4, a synchronous memory device 100 includes a first example 80a of a clock time adjustment circuit in a read path for a read command, and a clock time adjustment in a write path for a write command. One of the second examples of the circuit is 80b. In this embodiment, separate examples of the clock time adjustment circuit are used for the read command signal and the write command signal. In this way, the same or different frequency thresholds can be used in each instance of the clock time adjustment circuit. In other embodiments, the clock timing adjustment circuit 90 of FIG. 3 (b) may be used, wherein the read signal path and the write signal path may share the same clock frequency detection circuit. Referring to FIG. 4, in the read path, the clock time adjustment circuit 80 a receives an input clock signal CLK, and the input clock signal CLK is provided to the input clock or system clock of the synchronous memory device 100. The clock time adjustment circuit 80a also receives a read command provided to the synchronous memory device 100 when a read operation is expected. The input clock signal CLK is provided to the clock frequency detection circuit 110a, and the clock frequency detection circuit 110a generates a FASTCLK signal. Then, the FASTCLK signal and the read command are provided to the delay adjustment circuit 120a to generate the time-adjusted control signal L-Read. Then, the time-adjusted control signal L-Read is used to access the memory array 130 in a read operation. It is assumed that the memory device 100 has received a bit address signal ADDR to select a memory location in the memory array 130 for reading data. Under the control of the time-adjusted control signal L-Read, the memory array 130 provides read data from a selected memory unit and the read data is provided to a FIFO / output buffer containing a read FIFO Circuit 140. The FIFO / output buffer circuit 140 provides the read data DOUT as an output signal of the synchronous memory device 100. The read FIFO in the FIFO / output buffer circuit 140 consists of a clock signal CLK2. _R Control, clock signal CLK2 _R It is derived from the input clock signal CLK or derived from the input clock signal CLK. In the embodiment of the present invention, the clock time adjustment circuit 80a is used to advance the time-adjusted control signal L-Read by one or more clock cycles in response to the input clock signal CLK having a high clock frequency. In some embodiments, when the input clock signal CLK has a clock frequency higher than a predetermined frequency threshold, the clock frequency detection circuit 110a determines that the input clock signal CLK has a high clock frequency and Verify the FASTCLK signal. When the input clock frequency is determined to be a high clock frequency, the delay adjustment circuit 120a adjusts the control signal L by removing one or more clock cycles so that the control signal L-Read is advanced by one or more clock cycles. -Read time delay. In this way, the control memory array 130 provides read data one or more clock cycles earlier in high-frequency operation, so that the read data can reach the FIFO / output buffer 140 early enough to use the clock signal CLK2 _R The desired read delay is latched into the read FIFO, which is typically specified by a system coupled to the memory device to access data stored on the memory device. On the other hand, when the input clock has a low clock frequency (that is, a clock frequency below one of the frequency thresholds), the clock frequency detection circuit 110a does not verify the FASTCLK signal and the delay adjustment circuit 120a does not adjust the time In the case of delay, the control signal L-Read is generated. In this way, the read data will arrive at the FIFO / output buffer 140 at the desired time and be clocked by the clock signal CLK2 at the desired read delay time. _R It is latched into the read FIFO and sent out to the output data pad. In the write path, the clock time adjustment circuit 80b receives the input clock signal CLK and also receives a write command provided to the synchronous memory device 100 when a write operation is expected. The input clock signal CLK is provided to the clock frequency detection circuit 110b, which generates the FASTCLK signal in the same manner as explained above with reference to the clock time adjustment circuit 80a. Then, the FASTCLK signal and the write command are provided to the delay adjustment circuit 120b to generate a time-adjusted control signal L-Write. Then, the time-adjusted control signal L-Write is used to control the memory array 130 in a write operation. For example, the time-adjusted control signal L-Write is used to control a bank to write to the data buffer 135. In particular, the memory array 130 is generally divided into a plurality of memory cell banks and each memory cell bank may have been associated with a bank write data buffer for storing write data for its memory bank. In this illustration, the control signal L-Write is coupled to control the bank write data buffer 135 to provide the write data to the memory array 130 to be written to the selected memory unit. It is assumed that the memory device 100 has received an address signal ADDR for selecting a memory location in the memory array 130 for writing data. It is also assumed that the memory device 100 has received the input data DIN to be written to the memory location specified by the address signal. In a write operation, the synchronous memory device 100 receives input data DIN to be written to data in a memory location specified by the address signal ADDR. The input data DIN is stored in an input buffer / FIFO circuit 145 containing a write FIFO. The write FIFO in the input buffer / FIFO circuit 145 receives a clock signal CLK2. _W Control, clock signal CLK2 _W It can be derived from the input clock signal CLK or derived from the input clock signal CLK. In response to the clock signal CLK2 _W The input data stored in the write FIFO is unlocked from the FIFO and provided to the library write data buffer 135. Under the control of the time-adjusted control signal L-Write, the write data stored in the bank write data buffer 135 is written into the selected memory unit. In the embodiment of the present invention, the clock timing adjustment circuit 80b is configured to delay the time-adjusted control signal L-Write by one or more clock cycles in response to the input clock signal CLK having a high clock frequency. In some embodiments, when the input clock signal CLK has a clock frequency higher than a predetermined frequency threshold, the clock frequency detection circuit 110b determines that the input clock signal CLK has a high clock frequency and Verify the FASTCLK signal. When the input clock frequency is determined to be a high clock frequency, the delay adjustment circuit 120b adjusts the control signal L by adding one or more clock cycles so that the control signal L-Write is delayed by one or more clock cycles. -Write time. In this way, the control signal L-Write is delayed during a high clock frequency, so that written data has time to reach the bank write data buffer 135 before the control L-Write is verified. On the other hand, when the input clock has a low clock frequency (that is, a clock frequency below one of the predetermined frequency thresholds), the clock frequency detection circuit 110b does not verify the FASTCLK signal and the delay adjustment circuit 120b is not adjusting. In the case of time delay, the control signal L-Write is generated. At a low clock frequency, the written data arrives at the library write data buffer 135 at a time that matches the control signal L-Write, so that the correctly written data is written into the memory array 130. FIG. 5 is a block diagram illustrating a clock frequency detection circuit of a clock time adjustment circuit according to an embodiment of the present invention. Referring to FIG. 5, a clock frequency detection circuit 110 includes: a low-pass filter 121 configured to receive an input clock signal CLK; and one or more clock flip-flop circuits 122 configured to Generate the output signal FASTCLK. The clock flip-flop circuit 122 is controlled by an input clock signal CLK. The clock frequency detection circuit 110 may further include one or more inverters 123 as a buffer or a driver of the output signal FASTCLK. In other embodiments of the clock frequency detection circuit, the inverter 123 may be omitted. In the embodiment of the present invention, the clock frequency detection circuit 110 uses a low-pass filter 121 to detect a clock speed or a clock frequency. The low-pass filter 121 is configured to allow low-speed clock frequency signals to pass through while blocking or filtering high-speed clock frequency signals. Then, the clock flip-flop stage 122 captures or latches the low-pass filtered clock signal. The clock flip-flop circuit 122 generates an output signal FASTCLK having a logic high value in response to a detected high clock frequency, or generates an output signal having a logic low value in response to a detected low clock frequency. FASTCLK. In some embodiments, the low-pass filter 121 is configured to have a predetermined frequency value as one of the frequency detection thresholds. The low-pass filter 121 can detect a clock signal higher than a predetermined frequency threshold to have a high clock frequency or a high clock speed. The low-pass filter 121 can detect a clock signal below a predetermined frequency threshold to have a low clock frequency or a low clock speed. In some embodiments, the low-pass filter circuit 121 is implemented as an RC low-pass filter circuit. FIG. 6 is a circuit diagram illustrating an RC low-pass filter circuit in a clock frequency detection circuit of a clock timing adjustment circuit that can be incorporated in an embodiment of the present invention. Referring to FIG. 6, the low-pass filter 121 is implemented as an RC circuit including a resistor R connected between the input terminal IN and the output terminal OUT and a capacitor C connected from the output terminal OUT to the ground. In some embodiments, the resistor R may not only be implemented in the form of a resistor element but also use other available devices (such as an NMOS transistor whose gate is constrained to be higher than the NMOS threshold value) that gives an effective resistance Voltage). Similarly, the capacitor C may be implemented with a device other than a capacitor element, such as a MIM (metal-insulator-metal) capacitor or a MOS (metal-oxide-silicon) capacitor. An input clock signal CLK is provided to the input terminal IN, and a common node between the resistor R and the capacitor C provides a low-pass filtered output signal. Therefore, the resistance and capacitance of the resistor and capacitor of the RC circuit determine the threshold frequency of the low-pass filter 121. The resistance or capacitance of the RC circuit can be adjusted to set a desired frequency threshold for frequency detection in the clock frequency detection circuit 110. Specifically, the frequency threshold of the RC low-pass filter 121 determines the frequency at which the output signal FASTCLK will be verified (logic high). In this embodiment, the input clock signal having one of the clock frequencies higher than a threshold frequency is filtered by the low-pass filter 121. Then, the clock flip-flop circuit 122 will latch a logic high signal and will generate an output signal FASTCLK with a logic high value, thereby indicating a high clock frequency. On the other hand, an input clock signal having one of the clock frequencies below one of the threshold frequencies will pass through the low-pass filter 121. The clock flip-flop circuit 122 will latch a logic low signal and will generate an output signal FASTCLK with a logic low value, thereby indicating a low clock frequency. FIG. 7 is a circuit diagram illustrating a clock flip-flop circuit that can be incorporated in a clock time adjustment circuit in an embodiment of the present invention. In the embodiment of the present invention, the clock flip-flop circuit 122 may be incorporated in the clock frequency detection circuit 110 and the delay adjustment circuit 120. Referring to FIG. 7, a clocked flip-flop circuit 122 has: an input terminal IN that receives an input data to be latched; and a clocked input terminal that receives a clock signal. The clock flip-flop circuit 122 includes an input stage formed of transistors M0 to M3, inverters I0 to I4, and an output stage formed of transistors M4 to M7. In operation, when the input clock is at a logic low, the clock flip-flop circuit 122 passes the input data to the first pair of back-to-back inverters I1 and I2 via the input terminal IN. Then, when the input clock transitions to a logic high, the data latched and stored in the inverters I1 and I2 are passed to the second pair of back-to-back inverters I3 and I4 and provided as output data OUT. It should be understood that the driving strength of the inverters I2 and I4 is generally weaker than that of the transistors M0 to M7, so that the input stage and the output stage can drive the inverter latches. The clocked flip-flop circuit 122 shown in FIG. 7 is merely illustrative, and those skilled in the art will understand other circuit implementations in which a clocked flip-flop circuit may be used. The exact construction of the clocked flip-flop circuit is not important to the practice of the invention. FIG. 8 is a circuit diagram illustrating one of the delay adjustment circuits of the clock time adjustment circuit in the embodiment of the present invention. Referring to FIG. 8, the delay adjustment circuit 120 receives a command signal (such as a read command or a write command for a memory device), and continuously shifts the command signal through a series of clock stages or delay stages. . In this embodiment, the clock stage is implemented as a clock flip-flop circuit 122, which is clocked by a clock signal, such as an input clock signal CLK. The number of clock levels in the link determines the desired time delay for the command signal. The desired time delay can be selected for high clock frequency operation or for low clock frequency operation. The command signal is shifted by the clock stage 122 to generate a time-adjusted control signal L-Command, such as L-Read or L-Write. In this embodiment, the clock stage 122 is implemented using the clock flip-flop circuit of FIG. 7. In other embodiments, other clock delay circuits may be used to implement the clock stage. In one example, the number of clock stages provides one of the time delays required during low clock frequency operation. In another example, the number of clock stages provides a time delay required during high clock frequency operation. For example, an external system coupled to a clock product circuit may specify a read from the issuance of a read command to a read of the read data by the external system at the output of the clock product circuit Delay time. Then, the delay adjustment circuit 120 may be configured with a chain of clock stages, and the clock stage is selected to meet the read delay requirement under low clock frequency operation. In another example, an external system coupled to a clock product circuit may specify a write delay time from the time a write command is issued to providing write data at an input pad of the clock product circuit. Then, the delay adjustment circuit 120 can be configured with a chain of clock stages, and the clock stage is selected to meet the write delay time under low clock frequency operation. In this embodiment, the number of clock stages used corresponds to the delay required for low frequency operation of the clock product circuit. The delay adjustment circuit 120 also receives the FASTCLK signal from the clock frequency detection circuit 110. The FASTCLK signal is provided to a stage skip circuit 124 as an enable-skip ENSKIP signal. A stage skip circuit 124 is inserted into a series of clock stages 122. In this embodiment, the stage skip circuit 124 is inserted to be able to skip a clock stage. In other embodiments, the delay adjustment circuit 120 may be configured to be able to skip two or more clock stages, as will be explained in more detail below. The circuit configuration of the delay adjustment circuit 120 of FIG. 8 is merely illustrative and is not intended to be limiting. In operation, when the FASTCLK signal is asserted or at a logic high level, the stage skip circuit 124 is enabled to bypass a clock flip-flop circuit 122. In this way, the command signal shifted through a series of clock flip-flop circuits 122 has bypassed a clock cycle delay. Therefore, the command signal is advanced by one clock cycle. The clock-adjusted control signal L-Command will be confirmed one clock cycle earlier than in low-frequency operation. In an example of a memory read operation, providing a time-adjusted control signal L-Read one clock cycle earlier for a high clock frequency results in providing read data at the correct time for latching into the read FIFO. The read FIFO stores the read data to be buffered and driven to the outside of the synchronous memory circuit in an appropriate order. At a high clock frequency, the internal control signal L-Read cannot arrive in time to access the memory array. However, when a high clock frequency is detected by the clock frequency detection circuit 110, the delay adjustment circuit 120 of the present invention advances the L-Read control signal so that the read data can be accessed from the memory array earlier, and The read data can then reach the read FIFO for latching at the desired time. On the other hand, when the FASTCLK signal is deasserted or at a logic low level, the stage skip circuit 124 is not enabled and the clock flip-flop circuit 122 is not bypassed. In this manner, the control signal L-Read is not advanced but undergoes all the delays in a series of clock flip-flop circuits 122. In low frequency operation, the control signal L-Read is asserted at a specified time. As explained above, in other embodiments of the delay adjustment circuit 120, the stage skip circuit 124 may be configured to bypass one or more clock stages 122 to provide a desired timing adjustment. In one example, the stage skip circuit 124 may be configured to bypass the two clock stages 122 by placing the stage skip circuit 124 behind the two clock flip-flop circuits 122. In another embodiment, a multi-bit FASTCLK signal (such as FASTCLK <n: 0>) can be generated by a clock frequency detection circuit 110. For example, the clock frequency detection circuit 110 can be implemented as multiple instances of the clock frequency detection circuit, wherein the low-pass filter of each instance is configured for a different frequency detection threshold. In one example, a set of slow frequency thresholds, medium frequency thresholds, fast frequency thresholds, and very fast frequency thresholds may be used. Each instance of the clock frequency detection circuit generates a respective FASTCLK signal, and all the FASTCLK signals of this instance form a FASTCLK <n: 0> signal together. Each bit of FASTCLK <n: 0> will then be associated with a different number of clock levels to be skipped. For example, multiple instances of the stage skip circuit 124 may be used, each of which is driven by a respective FASTCLK <n: 0> signal. In the embodiment set forth above, the delay adjustment circuit 120 is illustrated as being implemented to skip one or more clock stages. That is, the stage skip circuit 124 is generally disabled, so that a full series of clock stages in the delay adjustment circuit 120 is used in low-frequency operation. When the FASTCLK signal is asserted, stage skip circuit 124 is enabled to skip or remove one or more clock stages from a series of clock stages in the delay adjustment circuit. In this embodiment, the FASTCLK signal is provided to the enable skip ENSKIP input signal of the stage skip circuit 124. In other embodiments of the present invention, the delay adjustment circuit 120 may be configured to add one or more clock levels, so that the time-adjusted command signal L-Command is delayed due to low-frequency operation. Therefore, the delay adjustment circuit 120 is configured with an additional clock stage that is usually bypassed by the stage skip circuit 124. That is, in an alternative embodiment, the stage skip circuit 124 is typically enabled in low frequency operation to bypass or skip additional clock stages so that the delay adjustment circuit 120 is operated with the remaining clock stages. However, when the FASTCLK signal is asserted, disabling the stage skip circuit 124 causes additional clock stages to be inserted into a series of clock stages. In this way, the time-adjusted control signal L-Command will pass the extra clock stage, thereby delaying the control signal L-Command by an extra clock cycle. In one embodiment, the delay adjustment circuit 120 may be configured to add one or more clock stages by inverting one of the FASTCLK signals to control the enabling of the stage skip circuit 124 to skip the ENSKIP input signal. In other embodiments, the number of clock stages used may correspond to the delay required for high frequency operation of the clock product circuit, and the stage skip circuit 124 may be configured to skip or insert clock stages that are low Clock frequency operation. FIG. 9 is a circuit diagram illustrating one stage skip circuit of a delay array access enable circuit in an embodiment of the present invention. Referring to FIG. 9, the stage skip circuit receives: the enable skip input signal ENSKIP; and an IN_SKIP signal connected to an input of a clock stage to be bypassed; and an IN_NORMAL signal connected to a time to be bypassed Pulse-level output. The enable skip input signal ENSKIP is configured to direct the signal IN_SKIP or the signal IN_NORMAL to the output terminal of the stage skip circuit 124. In the event that the signal FASTCLK is provided as the enable skip input signal ENSKIP, the stage skip circuit 124 selects the IN_SKIP signal to remove a clock stage when the signal FASTCLK is verified, and the stage skip circuit when the signal FASTCLK is deasserted 124 Select the IN_NORMAL signal to use the full range of clock levels in normal operation. In the event that the inversion of the signal FASTCLK is provided as the enable skip input signal ENSKIP, when the signal FASTCLK is instructed, the time skip circuit 124 selects the IN_NORMAL signal to add an additional clock level to the clock level series, and when FASTCLK is deasserted. The timing skip circuit 124 selects the IN_SKIP signal to remove additional clock stages, so that only the full series of clock stages are used in normal operation. In the embodiment illustrated in FIG. 8, the delay adjustment circuit is configured to skip the first clock stage in the clock stage chain. In other embodiments, the delay adjustment circuit may be configured to skip any clock stage in the clock stage chain. Alternatively, the delay adjustment circuit can be configured to add a clock stage at any position along the clock stage chain. Figures 8 and 9 above illustrate an exemplary embodiment of a delay adjustment circuit in which a clock level chain or a delay level chain is used to introduce time delay to a command signal and by adding or removing one or more clocks Level to adjust the time delay. The use of a chain of clock stages or a delay stage to introduce an adjustable time delay into a delay adjustment circuit is merely illustrative and is not intended to be limiting. In other embodiments, the delay adjustment circuit may use a counter circuit to count the number of clock cycles, and use a selection circuit that generates a selection signal in response to the FASTCLK signal to select the desired number of clock cycles. The command signal is then shifted by selecting the number of clock cycles. FIG. 10 is a timing diagram illustrating a read operation of a synchronous memory device according to an embodiment of the present invention. The timing diagram of FIG. 10 illustrates a case where a read operation is performed at a low input clock frequency. In a read operation, the synchronous memory device receives a read command signal at clock cycle 0 and is expected to be valid at a given number of clock cycles (called a read delay or RL clock cycle) later. Read data. In the example of the present invention, the clock time adjustment circuit shifts the read command through the clock chain, so that the control signal L-Read is verified at the RL-4 clock cycle. It is worth noting that although the control signal of the synchronous memory device is generated based on the input clock, the memory array operates as an analog circuit and generates an output signal with RC delay or propagation delay. The output signal generated is not based on the input The clock clock cycle. In addition, the RC delay or propagation delay does not change with the clock frequency. That is, as the clock frequency increases, the RC delay or propagation delay can remain unchanged and therefore become a larger part or a larger number of high frequency clock cycles, leading to possible conflicting events . In the example shown in FIG. 10, the memory array is accessed to read data at a selected memory location with the control signal L-Read asserted. The delay from the confirmation of the control signal L-Read to the read data from the memory array is an analog propagation delay that is not necessarily dominated by the clock cycle. After a certain propagation delay, the read data is transferred to the read FIFO. Then the clock signal CLK2 _R Under the control, the read data is read from the FIFO to the output data pad as the output data DOUT. In this case, in the case where the input clock operates at a low clock frequency, the read data is available at the RL clock cycle and the valid data is read out. 11 is a timing diagram illustrating a read operation of a synchronous memory device at a high clock frequency and without a time delay adjustment in some examples. The memory read operation is performed in the same manner as explained above with reference to FIG. 10. However, as the read command signal is propagated through the delayed clock chain, there is an inherent delay from the rising edge of the clock signal RL-4 to the rising edge of the control signal L-Read, which is shown in FIG. 11 as "delay". This inherent delay is negligible when the clock frequency is low. However, when the clock frequency is high, this inherent delay becomes a large part of the clock period. Therefore, under the condition that the control signal L-Read is confirmed to be delayed, the read data from the memory array is also delayed, so that the read data cannot reach the read FIFO in time for latching and cycle RL during the read delay clock. Read out everywhere. In this illustration, valid read data will arrive at a clock cycle after the RL clock cycle. However, since a receiving system expects to read data from the memory device at the clock cycle RL, invalid data is read as output data. 12 is a timing diagram illustrating a read operation of a synchronous memory device at a high clock frequency and a time delay adjustment is applied in an embodiment of the present invention. In the memory read operation shown in FIG. 12, the clock time adjustment circuit detects a high input clock frequency and configures a delay adjustment circuit to skip one or more clock cycles of the read command. As shown in FIG. 12, the time-adjusted control signal L-Read is generated by skipping a clock cycle (for example, +3 clock cycle) so that at the time of the RL-5 clock cycle (at RL-4 Before the clock cycle) confirm the control signal L-Read. Even with the confirmation delay of the L-Read signal edge, it is still possible to retrieve the read data from the memory array, provide the read data to the read FIFO, and then read it at the expected clock cycle RL to As output data DOUT. Therefore, by adjusting the time delay of the control signal L-Read, valid data can be read even at a high input clock frequency. 13 is a timing diagram illustrating a write operation of a synchronous memory device in an embodiment of the present invention. The timing chart of FIG. 13 illustrates a case where a write operation is performed at a low input clock frequency. In a write operation, the synchronous memory device receives a write command signal at a clock cycle 0 and then provides a valid write at a given number of clock cycles (called a write delay or WL clock cycle). Into the information. The written data is retrieved at the input buffer and then transferred to the memory array for writing to the selected memory cell. However, there is an analogous propagation delay between the time at which the written data is fetched at the input buffer and the time at which the written data is propagated to the memory array. This propagation delay is not based on the clock cycle and does not vary with the clock frequency. In the example of the present invention, the clock time adjustment circuit shifts the write command through the clock chain, so that the control signal L-Write is verified at the clock cycle t1. At a low input clock frequency, the control signal L-Write arrives at the same time as the written data and retrieves valid written data at the memory array. FIG. 14 is a timing diagram illustrating a write operation of a synchronous memory device at a high clock frequency and without a time delay adjustment in an example. The memory read operation is performed in the same manner as explained above with reference to FIG. 13. However, due to the propagation delay of the written data, when the control signal L-Write is confirmed at the clock cycle t1, the valid written data has not reached the memory array. Therefore, the effective write data is not captured by the control signal L-Write. Therefore, instead of expecting to write data, invalid data is written to the memory array. 15 is a timing diagram illustrating a write operation of a synchronous memory device at a high clock frequency and a time delay adjustment is applied in an embodiment of the present invention. In the memory write operation shown in FIG. 15, the clock time adjustment circuit detects a high input clock frequency and configures a delay adjustment circuit to add one or more clock cycles of a write command. Therefore, the control signal L-Write is delayed by one clock cycle and is not confirmed until the clock cycle t2. In this way, extra time is provided to allow written data to reach the memory array. At clock cycle t2, when the valid write data has reached the memory array, the control signal L-Write is verified and a valid write operation is performed. In the embodiment described above, the clock time adjustment circuit is configured to remove or skip clock stages in a synchronous memory device for high frequency read operations, and is configured to write to high frequency The operation adds a clock level to a synchronous memory device. The operation of the clock timing adjustment circuit in a synchronous memory device described above is merely illustrative and is not intended to be limiting. In other embodiments, the clock timing adjustment circuit can be configured to remove or add clock levels in a synchronous memory device for low or high frequency read operations. In addition, in other embodiments, the clock timing adjustment circuit can be configured to remove or add clock levels in a synchronous memory device for low or high frequency write operations. Although the foregoing embodiments have been set forth in certain details for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.

10‧‧‧Sync Memory Device

12‧‧‧ 2D array / array / cell array / memory array

14‧‧‧Memory Unit

16‧‧‧Control circuit

18‧‧‧column decoder

20‧‧‧line decoder

22‧‧‧I / O gate control circuit

24‧‧‧Sense Amplifier

26‧‧‧Read FIFO

28‧‧‧ output buffer

30‧‧‧ input buffer

32‧‧‧Write FIFO

50‧‧‧Microprocessor integrated circuit / microprocessor device

52‧‧‧Function Block / Macro Block

80‧‧‧Clock time adjustment circuit

80a‧‧‧First example / Clock time adjustment circuit

80b‧‧‧Second example / Clock time adjustment circuit

82‧‧‧Clock frequency detection circuit

86‧‧‧Delay adjustment circuit

86-1‧‧‧Delay adjustment circuit

86-2‧‧‧Delay adjustment circuit

90‧‧‧Clock time adjustment circuit

100‧‧‧Clock time adjustment circuit

110‧‧‧clock frequency detection circuit

110a‧‧‧clock frequency detection circuit

110b‧‧‧Clock frequency detection circuit

120‧‧‧ Delay adjustment circuit

120a‧‧‧Delay adjustment circuit

120b‧‧‧Delay adjustment circuit

121‧‧‧ Low Pass Filter / Low Pass Filter Circuit / Wire Interconnect Low Pass Filter

122‧‧‧Frequency converter circuit / Frequency converter circuit / Clock level / Clock level

123‧‧‧Inverter

124‧‧‧level skip circuit

130‧‧‧Memory Array

135‧‧‧bank write data buffer

140‧‧‧ FIFO / Output Buffer Circuit

145‧‧‧input buffer / first-in-first-out circuit

Addr‧‧‧ address / address signal

C‧‧‧Capacitor

CLK‧‧‧ Input clock signal

CLK2 _R ‧‧‧ clock signal

CLK2 _W ‧‧‧ clock signal

DIN‧‧‧Write data / input data

DOUT‧‧‧Output data / read data

ENSKIP‧‧‧Input signal

FASTCLK‧‧‧Clock detection output signal / output signal / signal

I0‧‧‧ Inverter

I1‧‧‧ Inverter

I2‧‧‧ Inverter

I3‧‧‧ Inverter

I4‧‧‧ Inverter

IN‧‧‧Input terminal

IN_Normal‧‧‧Signal

IN_SKIP‧‧‧Signal

L-Command‧‧‧Time-adjusted control signal / Internal control signal / Control signal / Time-adjusted command signal

L-Command1‧‧‧Time-adjusted control signal

L-Command2‧‧‧time-adjusted control signal

L-Read‧‧‧Time-adjusted control signal / control signal / internal control signal

L-Write‧‧‧Time-adjusted control signal / control signal

M0-M7‧‧‧Transistor

OUT‧‧‧output terminal

R‧‧‧ resistor

RL‧‧‧Cycle Cycle

t0‧‧‧clock cycle

t1‧‧‧clock cycle

t2‧‧‧clock cycle

t3‧‧‧clock cycle

WL‧‧‧Cycle Cycle

Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings. FIG. 1 is a block diagram of a synchronous memory device in which a clock timing adjustment circuit can be incorporated in an exemplary embodiment of the present invention. FIG. 2 is a block diagram of a microprocessor device in which a clock timing adjustment circuit can be incorporated in an exemplary embodiment of the present invention. FIG. 3 (a) is a block diagram of a clock timing adjustment circuit in some embodiments of the present invention. FIG. 3 (b) is a block diagram of a clock timing adjustment circuit in an alternative embodiment of the present invention. FIG. 4 illustrates a block diagram of a read path and a write path of a synchronous memory device incorporated in a clock time adjustment circuit in an embodiment of the present invention. FIG. 5 is a block diagram illustrating a clock frequency detection circuit of a clock time adjustment circuit according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an RC low-pass filter circuit in a clock frequency detection circuit of a clock timing adjustment circuit that can be incorporated in an embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a clock flip-flop circuit that can be incorporated in a clock time adjustment circuit in an embodiment of the present invention. FIG. 8 is a circuit diagram illustrating one of the delay adjustment circuits of the clock time adjustment circuit in the embodiment of the present invention. FIG. 9 is a circuit diagram illustrating one stage skip circuit of a delay array access enable circuit in an embodiment of the present invention. FIG. 10 is a timing diagram illustrating a read operation of a synchronous memory device according to an embodiment of the present invention. 11 is a timing diagram illustrating a read operation of a synchronous memory device at a high clock frequency and without a time delay adjustment in some examples. 12 is a timing diagram illustrating a read operation of a synchronous memory device at a high clock frequency and a time delay adjustment is applied in an embodiment of the present invention. 13 is a timing diagram illustrating a write operation of a synchronous memory device in an embodiment of the present invention. FIG. 14 is a timing diagram illustrating a write operation of a synchronous memory device at a high clock frequency and without a time delay adjustment in an example. 15 is a timing diagram illustrating a write operation of a synchronous memory device at a high clock frequency and a time delay adjustment is applied in an embodiment of the present invention.

Claims (34)

A clock product circuit receives an input clock signal having a clock frequency and a command signal for accessing a memory element in the clock product circuit. The clock product circuit includes: The pulse frequency detection circuit receives the input clock signal and generates a clock detection output signal. The clock detection output signal has a first logic state in response to the clock frequency being lower than a frequency threshold and A second logic state in response to the clock frequency being at or above a frequency threshold; and a delay adjustment circuit that receives the input clock signal, the command signal, and the clock detection output signal, the The delay adjustment circuit generates a time-adjusted control signal. The time-adjusted control signal is delayed by the command signal for a first time delay. The first time delay includes one or more clock cycles of the input clock signal. The delay adjustment circuit adjusts the first time delay in response to the clock detection output signal. For example, the clock product circuit of item 1, wherein the delay adjustment circuit generates the time-adjusted command signal delayed by the first time delay in response to the clock detection output signal having the first logic state. A control signal; and in response to the clock detection output signal having the second logic state, the delay adjustment circuit generates the time-adjusted control signal of the command signal delayed by a second time delay, the second time delay It is derived from the first time delay adjustment. For example, the clock product circuit of claim 2, wherein in response to the clock detection output signal having the second logic state, the delay adjustment circuit adds one or more clock periods to the first time delay. For example, the clock product circuit of claim 2, wherein in response to the clock detection output signal having the second logic state, the delay adjustment circuit removes one or more clock cycles from the first time delay. For example, if the clock product circuit of item 1 is provided, in response to the clock detection output signal having the second logic state, the delay adjustment circuit generates the time-adjusted command signal delayed by the first time delay. A control signal; and in response to the clock detection output signal having the first logic state, the delay adjustment circuit generates the time-adjusted control signal of the command signal delayed by a second time delay, the second time delay It is derived from the first time delay adjustment. For example, the clock product circuit of claim 5, wherein in response to the clock detection output signal having the first logic state, the delay adjustment circuit adds one or more clock cycles to the first time delay. For example, the clock product circuit of claim 5, wherein in response to the clock detection output signal having the first logic state, the delay adjustment circuit removes one or more clock cycles from the first time delay. For example, the clock product circuit of claim 1, wherein the delay adjustment circuit includes a plurality of clock stages connected in series and timed by the input clock signal, and the plurality of clock stages determine the first time delay, the command signal The plurality of clock levels are shifted to generate the time-adjusted control signal having the first time delay. For example, the clock product circuit of claim 8, wherein the delay adjustment circuit further includes a stage skip circuit configured to adjust the plurality of clock stages in response to the clock detection output signal. The number of clock stages, the stage skip circuit removes one or more clock stages from the plurality of clock stages. For example, the clock product circuit of claim 8, wherein the delay adjustment circuit further includes a stage skip circuit configured to adjust the plurality of clock stages in response to the clock detection output signal. The number of clock stages, the stage skip circuit adds one or more clock stages to the plurality of clock stages. For example, the clock product circuit of claim 8, wherein the plurality of clock stages includes a plurality of clock flip-flop stages connected in series. For example, the clock product circuit of item 1, wherein the delay adjustment circuit includes: a counter circuit that is timed by the input clock signal and generates a counter value; and a selection circuit that is configured to respond to the time The pulse detection output signal generates a selection signal. The selection signal selects a counter value from the counter circuit. The counter value is selected to adjust the time delay of the time-adjusted control signal. For example, the clock product circuit of item 1, wherein the clock frequency detection circuit includes: a low-pass filter circuit configured to receive the input clock signal and generate a low frequency at the frequency threshold. One of the pass filters is a low-pass filtered output signal; and a plurality of clock stages are clocked by the input clock signal, and the low-pass filtered output signal is shifted through the plurality of clock stages to generate the clock detection output signal. For example, the clock product circuit of item 2, wherein the clock product circuit includes a clock memory circuit, and the command signal includes a read command signal for reading data from the clock memory circuit, and In response to the clock detection output signal having the second logic state, the delay adjustment circuit generates a time-adjusted read control signal that is one of the read command signals delayed by the second time delay, and the time-adjusted read The control signal is advanced by the one or more clock cycles compared to the first time delay. For example, the clock product circuit of claim 2, wherein the clock product circuit includes a clock memory circuit, and the command signal includes a write command signal for writing input data to one of the clock memory circuits. And in response to the clock detection output signal having the second logic state, the delay adjustment circuit generates a time-adjusted write control signal that is one of the write command signals delayed by the second time delay, the time-adjusted The write control signal is delayed by the one or more clock cycles compared to the first time delay. For example, the clock product circuit of claim 2, wherein the clock product circuit includes a microprocessor circuit, and the command signal includes a memory element from a macro block of the microprocessor circuit. A read command signal of one of the read data, and in response to the clock detection output signal having the second logic state, the delay adjustment circuit generates a time-adjusted one of the read command signal delayed by the second time delay. The read control signal is advanced by the one or more clock cycles compared to the first time delay. For example, the clock product circuit of item 2, wherein the clock product circuit includes a microprocessor circuit, and the command signal includes data for writing data into a macro block of the microprocessor circuit. A write command signal of one of the memory elements, and in response to the clock detection output signal having the second logic state, the delay adjustment circuit generates the write command signal delayed by a second time delay of the microprocessor. Once the time-adjusted write control signal is delayed by the one or more clock cycles compared to the first time delay. For example, the clock product circuit of item 1, wherein the clock frequency detection circuit includes a plurality of clock frequency detection circuit instances, and each clock frequency detection circuit instance is associated with a respective frequency threshold. The clock frequency is coupled to each clock frequency detection circuit instance to be detected against the respective frequency threshold. The clock frequency detection circuit generates an indication of one of the frequency ranges of the clock frequency. The bit clock detection output signal, and the delay adjustment circuit adjusts the first time delay in response to the multi-bit clock detection output signal. A method performed in a clock product circuit, the clock product circuit receives an input clock signal having a clock frequency and a command signal for accessing a memory element in the clock product circuit The method includes: detecting whether the input clock signal has a clock frequency higher than a frequency threshold or lower than the frequency threshold; in response to the clock frequency being lower than the frequency threshold, having A clock detection output signal in one of the first logic states; generating the clock detection output signal with a second logic state in response to the clock frequency being higher than the frequency threshold; delaying the command signal by a first A time delay to generate a time-adjusted control signal, the first time delay is one or more clock cycles of the input clock signal; and the first time delay is adjusted in response to the clock detection output signal. The method of claim 19, further comprising: in response to the clock detection output signal having the first logic state, delaying the command signal by the first time delay to generate the command delayed by the first time delay The time-adjusted control signal of the signal; adjusting the first time delay to a second time delay in response to the clock detection output signal having the second logic state; and in response to the clock detection output signal having The second logic state delays the command signal by the second time delay to generate the time-adjusted control signal. The method of claim 20, wherein adjusting the first time delay to a second time delay in response to the clock detection output signal having the second logic state includes: adding one or more clock cycles to The first time delay generates the second time delay. The method of claim 20, wherein adjusting the first time delay to a second time delay in response to the clock detection output signal having the second logic state includes: removing one or more from the first time delay Clock cycles to generate the second time delay. The method of claim 19, further comprising: in response to the clock detection output signal having the second logic state, delaying the command signal by the first time delay to generate the command delayed by the first time delay The time-adjusted control signal of the signal; adjusting the first time delay to a second time delay in response to the clock detection output signal having the first logic state; and in response to the clock detection output signal having The first logic state delays the command signal by the second time delay to generate the time-adjusted control signal. The method of claim 23, wherein adjusting the first time delay to a second time delay in response to the clock detection output signal having the first logic state includes: adding one or more clock cycles to The first time delay generates the second time delay. The method of claim 23, wherein adjusting the first time delay to a second time delay in response to the clock detection output signal having the first logic state includes: removing one or more from the first time delay Clock cycles to generate the second time delay. The method of claim 23, wherein: delaying the command signal by a first time delay to generate a time-adjusted control signal includes: delaying the command signal through a plurality of clock stages to generate the time-adjusted control signal, the complex number Each clock level determines the first time delay; and adjusting the first time delay in response to the clock detection output signal includes adjusting the number of clock levels in the plurality of clock levels. The method of claim 26, wherein adjusting the number of clock levels in the plurality of clock levels includes removing one or more clock levels from the plurality of clock levels. The method of claim 26, wherein adjusting the number of clock levels in the plurality of clock levels includes: adding one or more clock levels to the plurality of clock levels. The method of claim 19, wherein detecting whether the input clock signal has a clock frequency higher than a frequency threshold or lower than the frequency threshold includes: inputting the input clock at the frequency threshold The signal is low-pass filtered. The method of claim 19, wherein: detecting whether the input clock signal has a clock frequency higher than a frequency threshold or lower than the frequency threshold includes detecting the input by comparing a plurality of frequency thresholds Clock signal; generating the clock detection output signal includes generating a multi-bit clock detection output signal indicating a frequency range of the clock frequency; and adjusting the first in response to the clock detection output signal The time delay includes adjusting the first time delay in response to the multi-bit clock detection output signal. The method of claim 20, wherein the clock product circuit includes a clock memory circuit, and the command signal includes a read command signal for reading data from the clock memory circuit. The method includes: responding The clock detection output signal has the second logic state, and the first time delay is adjusted to the first time delay by one or more clock cycles compared to the first time delay. Two time delays; and in response to the clock detection output signal having the second logic state, delaying the command signal by the second time delay to generate the time-adjusted control signal. The method of claim 20, wherein the clock product circuit includes a clock memory circuit, and the command signal includes a write command signal for writing data to one of the clock memory circuits. The method includes: In response to the clock detection output signal having the second logic state, the first time delay is adjusted to the second time delay by delaying the second time delay from the first time delay by one or more clock cycles. A second time delay; and in response to the clock detection output signal having the second logic state, delaying the command signal by the second time delay to generate the time-adjusted control signal. The method of claim 20, wherein the clock product circuit includes a microprocessor circuit, and the command signal includes data for reading data from a memory element in a macro block of the microprocessor circuit. A read command signal, the method includes: in response to the clock detection output signal having the second logic state, by making the second time delay earlier than the first time delay by one or more clock cycles And adjusting the first time delay to the second time delay; and in response to the clock detection output signal having the second logic state, delaying the command signal by the second time delay to generate the time-adjusted control signal . The method of claim 20, wherein the clock product circuit includes a microprocessor circuit, and the command signal includes a memory element for writing data to a macro block of the microprocessor circuit One of the write command signals, the method comprising: in response to the clock detection output signal having the second logic state, delaying the second time delay by one or more clocks compared to the first time delay Periodically adjusting the first time delay to the second time delay; and in response to the clock detection output signal having the second logic state, delaying the command signal by the second time delay to generate the time-adjusted control signal.