TW201816879A - Dummy fin etch to form recesses in substrate - Google Patents

Dummy fin etch to form recesses in substrate Download PDF

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Publication number
TW201816879A
TW201816879A TW106115429A TW106115429A TW201816879A TW 201816879 A TW201816879 A TW 201816879A TW 106115429 A TW106115429 A TW 106115429A TW 106115429 A TW106115429 A TW 106115429A TW 201816879 A TW201816879 A TW 201816879A
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Taiwan
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groove
semiconductor
semiconductors
long
integrated circuit
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TW106115429A
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Chinese (zh)
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TWI649802B (en
Inventor
官琬純
廖志騰
邱意為
翁子展
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台灣積體電路製造股份有限公司
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

Description

積體電路結構與其製造方法    Integrated circuit structure and manufacturing method thereof   

本揭露係有關一種積體電路結構與其製造方法，且特別有關於一種於半導體基板中形成凹槽之結構及其製造方法。 This disclosure relates to an integrated circuit structure and a manufacturing method thereof, and more particularly to a structure for forming a groove in a semiconductor substrate and a manufacturing method thereof.

在鰭式場效電晶體(FinFETs)的形成中，通常開始時半導體基板會先被蝕刻，以在半導體基板中形成複數凹槽。在凹槽之間的半導體基板部分為複數長條半導體，鰭式場效電晶體於此之上形成。為了降低圖案負載效應(pattern-loading effect)，複數虛置長條半導體於形成長條半導體時同時形成。虛置長條半導體之殘餘部分通常於去除虛置鰭式半導體後殘留下來。 In the formation of fin-type field effect transistors (FinFETs), the semiconductor substrate is usually etched at the beginning to form a plurality of grooves in the semiconductor substrate. The semiconductor substrate portion between the grooves is a plurality of long semiconductors, and a fin-type field effect transistor is formed thereon. In order to reduce the pattern-loading effect, a plurality of dummy long semiconductors are formed simultaneously when forming the long semiconductors. Residual portions of the dummy long semiconductor usually remain after removing the dummy fin semiconductor.

本發明包括一種積體電路結構，包括半導體基板，具有複數長條半導體；第一凹槽，沿著長條半導體之中兩相鄰之長條半導體之間形成；第二凹槽，形成於第一凹槽之中；隔離區域，位於第一凹槽及第二凹槽之間，第二凹槽具有低於第一凹槽之深度。 The present invention includes an integrated circuit structure including a semiconductor substrate having a plurality of long semiconductors; a first groove formed along two adjacent long semiconductors among the long semiconductors; and a second groove formed at the first A groove; an isolation region is located between the first groove and the second groove, and the second groove has a depth lower than the first groove.

本發明亦包括一種積體電路結構，包括半導體基 板；複數隔離區域，延伸至半導體基板之中；第一及第二長條半導體，位於半導體基板之中。第一長條半導體為冠狀長條半導體，包括底座，位於隔離區域；複數鰭式半導體，直接位於底座之上；第二長條半導體為單鰭式長條半導體；第一凹槽，位於兩相鄰第一長條半導體之間；第二凹槽，形成於第一凹槽之中；第二凹槽延伸自兩相鄰之第一長條半導體之底部至半導體基板之較低部分；隔離區域包括延伸進入第二凹槽之第一部分；第二凹槽及第一長條半導體之底座具有大抵上相同之寬度；第三凹槽，位於兩相鄰第二長條半導體之間；第四凹槽，形成於第三凹槽之中；第四凹槽延伸自兩相鄰之第二長條半導體之底部至半導體基板之較低部分；隔離區域包括延伸進入第四凹槽之第二部分，且第四凹槽及第二長條半導體具有大抵上相同之寬度。 The present invention also includes an integrated circuit structure including a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; and first and second long semiconductors located in the semiconductor substrate. The first long semiconductor is a crown-shaped long semiconductor including a base and is located in an isolation region; the plurality of fin semiconductors is directly above the base; the second long semiconductor is a single-fin semiconductor; the first groove is located in two phases Adjacent to the first long semiconductor; a second groove formed in the first groove; the second groove extending from the bottom of two adjacent first long semiconductors to a lower portion of the semiconductor substrate; an isolation region The first groove includes a first portion extending into the second groove; the second groove and the base of the first elongated semiconductor have substantially the same width; the third groove is located between two adjacent second elongated semiconductors; the fourth concave A groove formed in the third groove; a fourth groove extending from the bottom of two adjacent second long semiconductors to a lower portion of the semiconductor substrate; an isolation region including a second portion extending into the fourth groove, And the fourth groove and the second long semiconductor have substantially the same width.

本發明亦包括一種積體電路結構的製造方法，包括自一半導體基板形成第一長條半導體及第二長條半導體；蝕刻第一長條半導體；蝕刻一部分半導體基板，部分直接位於蝕刻後之第一條狀半導體之下以形成一凹槽。 The invention also includes a method for manufacturing an integrated circuit structure, which includes forming a first elongated semiconductor and a second elongated semiconductor from a semiconductor substrate; etching the first elongated semiconductor; etching a part of the semiconductor substrate, and a portion of the semiconductor substrate directly located after the etching. A strip of semiconductor is formed below to form a groove.

20‧‧‧基板 20‧‧‧ substrate

22‧‧‧墊氧化層 22‧‧‧pad oxide layer

24‧‧‧硬罩幕 24‧‧‧ hard screen

26‧‧‧溝槽 26‧‧‧Trench

28、128A、128B、228A、228B‧‧‧長條半導體 28, 128A, 128B, 228A, 228B

34‧‧‧犧牲間隔層 34‧‧‧ sacrificial spacer

36‧‧‧底層 36‧‧‧ ground floor

36’‧‧‧殘留部分 36’‧‧‧ residue

38‧‧‧中間層 38‧‧‧ middle layer

40‧‧‧上層 40‧‧‧ Upper floor

42‧‧‧三層結構 42‧‧‧three-story structure

44‧‧‧開口 44‧‧‧ opening

46、48‧‧‧凹槽 46, 48‧‧‧ groove

47、49、49’‧‧‧虛線 47, 49, 49’‧‧‧ dashed line

52‧‧‧介電區域/材料 52‧‧‧Dielectric area / material

54‧‧‧襯氧化物 54‧‧‧lining oxide

56‧‧‧介電材料 56‧‧‧ Dielectric materials

58‧‧‧淺溝槽隔離區 58‧‧‧Shallow trench isolation area

60‧‧‧閘極堆疊 60‧‧‧Gate stack

62‧‧‧虛置閘極堆疊 62‧‧‧Virtual Gate Stack

64‧‧‧閘極介電質 64‧‧‧Gate dielectric

66‧‧‧虛置閘極電極 66‧‧‧Virtual gate electrode

68‧‧‧閘極間隔物 68‧‧‧Gate spacer

70‧‧‧置換閘極 70‧‧‧Replacement gate

72‧‧‧閘極介電層 72‧‧‧Gate dielectric layer

74‧‧‧閘極電極 74‧‧‧Gate electrode

76‧‧‧源極/汲極矽化物區域 76‧‧‧Source / Drain Silicide Area

78‧‧‧源極/汲極接觸栓塞 78‧‧‧Source / Drain Contact Embolism

82‧‧‧層間介電質 82‧‧‧Interlayer dielectric

100‧‧‧晶圓 100‧‧‧ wafer

130A、130B‧‧‧底座 130A, 130B‧‧‧base

130A’、130B’‧‧‧上表面 130A ’, 130B’‧‧‧upper surface

132A、132B、232A、232B‧‧‧鰭式半導體 132A, 132B, 232A, 232B‧‧‧fin semiconductor

168、268‧‧‧磊晶區 168, 268‧‧‧Epicenter

180、280‧‧‧鰭式場效電晶體 180, 280‧‧‧ Fin Field Effect Transistors

200‧‧‧流程圖 200‧‧‧flow chart

202、204、206、208、210、212、214、216、218、220、222、224‧‧‧流程圖步驟 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224‧‧‧ flow chart steps

W1、W1’、W2、W2’‧‧‧寬度 W1, W1 ’, W2, W2’‧‧‧Width

D2、D3‧‧‧深度 D2, D3‧‧‧ depth

以下將配合所附圖式詳述本發明之實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明的特徵。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the features of the present invention.

第1-9、10A-10B、11-13圖為根據一些實施例形成隔離區域及鰭式場效電晶體之中間階段之剖面圖。 1-9, 10A-10B, and 11-13 are cross-sectional views of an intermediate stage of forming an isolation region and a fin-type field effect transistor according to some embodiments.

第14圖係根據一些實施例繪示出隔離區域及鰭式場效電晶體之形成方法之流程圖。 FIG. 14 is a flowchart illustrating a method of forming an isolation region and a fin-type field effect transistor according to some embodiments.

以下公開許多不同的實施方法或是例子來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明。當然這些實施例僅用以例示，且不該以此限定本發明的範圍。例如，在說明書中提到第一特徵形成於第二特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明，不代表所討論的不同實施例及/或結構之間有特定的關係。 A number of different implementation methods or examples are disclosed below to implement the different features of the provided subject matter, and specific embodiments and arrangements thereof are described below to illustrate the present invention. Of course, these embodiments are only for illustration, and the scope of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repetitive numbers or signs may be used in different embodiments, and these repetitions are merely for a simple and clear description of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

此外，其中可能用到與空間相關用詞，例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。 In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, and The described orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used in it will also be interpreted in terms of the orientation after turning.

根據各種示例性實施例，本發明提供隔離區域、鰭式場效電晶體及其形成方法。形成隔離區域及鰭式場效電晶體之中間階段被繪示於此揭露。在此並討論一些實施例的變 型。在各種圖示及示意性實施例中，相似的參考編號被用於代表相似的元件。 According to various exemplary embodiments, the present invention provides an isolation region, a fin-type field effect transistor, and a method of forming the same. The intermediate stage of forming the isolation region and the fin-type field effect transistor is shown here and disclosed. Variations of some embodiments are discussed herein. In the various illustrations and illustrative embodiments, similar reference numbers are used to represent similar elements.

根據一些實施例，第1圖至第13圖繪示形成鰭式場效電晶體中間階段之剖面圖。如第1圖至第13圖所示之步驟被示意性地繪示於圖14中之流程圖200中。 According to some embodiments, FIGS. 1 to 13 are cross-sectional views of an intermediate stage of forming a fin-type field effect transistor. The steps shown in FIGS. 1 to 13 are schematically illustrated in the flowchart 200 in FIG. 14.

第1圖繪示基板20之剖面圖，基板為晶圓100之一部份。基板20可為塊體基板或絕緣體上之半導體基板。根據本發明之一些實施例，基板20由半導體材料所形成，包括但不限於矽鍺(Silicon germanium)、碳化矽(Silicon carbon)、鍺(germanium)，以及III-V族半導體化合物如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或相近之化合物。基板20可被淡摻雜p型或n型雜質。 FIG. 1 illustrates a cross-sectional view of a substrate 20, which is a part of the wafer 100. The substrate 20 may be a bulk substrate or a semiconductor substrate on an insulator. According to some embodiments of the present invention, the substrate 20 is formed of a semiconductor material, including, but not limited to, silicon germanium, silicon carbon, germanium, and III-V semiconductor compounds such as GaAsP, AlInAs , AlGaAs, GaInAs, GaInP, GaInAsP or similar compounds. The substrate 20 may be lightly doped with p-type or n-type impurities.

墊氧化層22和硬罩幕24形成於半導體基板20之上。相應之步驟被繪示於第14圖中流程圖之步驟202中。根據本發明之一些實施例，墊氧化層22由氧化矽(silicon oxide)所形成，其可藉由氧化半導體基板20之表面層所形成。硬罩幕24可由氮化矽、氮氧化矽、碳化矽、碳氮化矽或相近之化合物所形成。根據本發明之一些實施例，硬罩幕24由氮化矽所形成，例如以低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition，簡稱LPCVD)製成。根據本發明之其他實施例，罩幕層24由矽之熱氮化處理、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，簡稱PECVD)、或陽極電漿氮化所形成。 A pad oxide layer 22 and a hard mask 24 are formed on the semiconductor substrate 20. The corresponding steps are illustrated in step 202 of the flowchart in FIG. 14. According to some embodiments of the present invention, the pad oxide layer 22 is formed of silicon oxide, which may be formed by oxidizing a surface layer of the semiconductor substrate 20. The hard mask 24 may be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or similar compounds. According to some embodiments of the present invention, the hard mask 24 is formed of silicon nitride, for example, made of Low-Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the present invention, the mask layer 24 is formed by thermal nitridation of silicon, Plasma Enhanced Chemical Vapor Deposition (PECVD), or anode plasma nitridation.

請參照第2圖，圖案化硬罩幕24、墊氧化層22及基 板20以形成溝槽26。因此形成長條半導體128A、128B、228A和228B。相應之步驟被繪示於第14圖中流程圖之步驟204中。在本描述中，長條半導體128A、128B、228A和228B被統稱為長條半導體28。溝槽26延伸至半導體基板20之中且隔開長條半導體128A、128B、228A和228B。在晶圓100之俯視圖之中，溝槽26有於縱向相互平行之延伸部分。此外，在晶圓100之俯視圖之中，每一或其中一些長條半導體128A、128B、228A和228B可被對應之溝槽26包圍。根據本發明之一些實施例，溝槽26之深度D1介於大約100奈米與大約150奈米之間。應當理解的是在本說明書中所揭露之數值僅為例子，在不改變本發明之原則下也可採用不同之數值。 Referring to FIG. 2, the hard mask 24, the pad oxide layer 22 and the substrate 20 are patterned to form a trench 26. Thus, long semiconductors 128A, 128B, 228A, and 228B are formed. The corresponding steps are illustrated in step 204 of the flowchart in FIG. In this description, the long semiconductors 128A, 128B, 228A, and 228B are collectively referred to as the long semiconductors 28. The trench 26 extends into the semiconductor substrate 20 and separates the long semiconductors 128A, 128B, 228A, and 228B. In the top view of the wafer 100, the trenches 26 have extending portions parallel to each other in the longitudinal direction. In addition, in the top view of the wafer 100, each or some of the long semiconductors 128A, 128B, 228A, and 228B may be surrounded by corresponding trenches 26. According to some embodiments of the present invention, the depth D1 of the trench 26 is between about 100 nanometers and about 150 nanometers. It should be understood that the numerical values disclosed in this specification are merely examples, and different numerical values may be adopted without changing the principles of the present invention.

根據本發明之一些實施例，長條半導體128A及128B被稱為冠狀長條半導體。長條半導體128A包括底座130A及底座130A之上之長條半導體132A。長條半導體128B包括底座130B及底座130B之上之長條半導體132B。雖然第2圖中繪示兩條長條半導體132A(或132B)於底座130A(或130B)之上，於對應之底座130A或130B之上之長條半導體132A或132B之數量可為任何整數，如1、2、3、4、5或更多，其數量取決於設計之鰭式場效電晶體之驅動電流。底座130A之上表面130A’和底座130B之上表面130B’大抵上可為平面或微凹陷之曲面。 According to some embodiments of the present invention, the strip semiconductors 128A and 128B are referred to as crown strip semiconductors. The long semiconductor 128A includes a base 130A and a long semiconductor 132A on the base 130A. The long semiconductor 128B includes a base 130B and a long semiconductor 132B on the base 130B. Although FIG. 2 shows that two long semiconductors 132A (or 132B) are above the base 130A (or 130B), the number of long semiconductors 132A or 132B above the corresponding base 130A or 130B may be any integer, Such as 1, 2, 3, 4, 5 or more, the number of which depends on the driving current of the designed fin-type field effect transistor. The upper surface 130A 'of the base 130A and the upper surface 130B' of the base 130B may be substantially flat or slightly concave curved surfaces.

根據本發明之一些實施例，長條半導體228A和228B為單鰭式長條半導體，其中長條半導體228A和228B之側壁大抵上是直的且連續地從上往下延伸，且無底座形成。 According to some embodiments of the present invention, the long semiconductors 228A and 228B are single-fin long semiconductors, wherein the side walls of the long semiconductors 228A and 228B are substantially straight and continuously extend from top to bottom, and there is no base formed.

根據本發明之一些實施例，長條半導體128A、 128B、228A和228B之形成包括蝕刻半導體基板20以形成長條半導體132A及132B，形成犧牲間隔層34以覆蓋長條半導體132A及132B之側壁及底部，且利用犧牲間隔層34及硬罩幕24之組合形成蝕刻幕罩以進一步蝕刻基板20。因此形成底座130A和130B。長條半導體228A和228B無形成於其側壁上之犧牲間隔層34，因此無半導體底座形成於其下。相反地，長條半導體228A和228B之上部可與長條半導體132A和132B同時形成，長條半導體228A和228B之底部於形成半導體底座130A和130B時形成。長條半導體228A和228B之底部從而可大抵上與底座130A和130B之底部同平面。隨後去除犧牲間隔層34。 According to some embodiments of the present invention, the formation of the long semiconductors 128A, 128B, 228A, and 228B includes etching the semiconductor substrate 20 to form the long semiconductors 132A and 132B, and forming the sacrificial spacer layer 34 to cover the sidewalls of the long semiconductors 132A and 132B and The substrate 20 is further etched by using a combination of the sacrificial spacer layer 34 and the hard mask 24 to form an etching mask. The bases 130A and 130B are thus formed. The long semiconductors 228A and 228B have no sacrificial spacer layer 34 formed on the sidewalls thereof, and thus no semiconductor base is formed thereunder. Conversely, the upper portions of the long semiconductors 228A and 228B may be formed simultaneously with the long semiconductors 132A and 132B, and the bottoms of the long semiconductors 228A and 228B are formed when the semiconductor bases 130A and 130B are formed. The bottoms of the elongated semiconductors 228A and 228B can thus be substantially flat with the bottoms of the bases 130A and 130B. The sacrificial spacer layer 34 is subsequently removed.

可分配長條半導體132A、132B、228A和228B及其組合以形成複數有著均勻節距之細長長條，因此可降低形成長條半導體28中之負載效應。此外，根據本發明之一些實施例，長條半導體132A、132B、228A和228B可被設計為有同樣之寬度W1。長條半導體128A和228A為主動區域，鰭式場效電晶體於此之上形成。長條半導體128B和228B為虛置圖案，不會被用於形成鰭式場效電晶體。因此，於隨後之步驟，虛置長條半導體128B和228B被去除。 The strip semiconductors 132A, 132B, 228A, and 228B and combinations thereof can be assigned to form a plurality of elongated strips having a uniform pitch, thereby reducing the load effect in forming the strip semiconductors 28. In addition, according to some embodiments of the present invention, the strip semiconductors 132A, 132B, 228A, and 228B may be designed to have the same width W1. The long semiconductors 128A and 228A are active regions on which fin-type field effect transistors are formed. The long semiconductors 128B and 228B are dummy patterns and will not be used to form fin-type field effect transistors. Therefore, in the subsequent steps, the dummy long semiconductors 128B and 228B are removed.

應注意的是，雖然長條半導體128A、128B、228A和228B在此被繪示為靠近彼此，但它們在一些實施例中可用任意組合位於晶粒上不同之區域。舉例來說，半導體區域128A和128B可位於第一元件區域，且半導體區域228A和228B可位於與第一元件區域分離之第二元件區域。根據本發明之其他實施例，長條半導體128A、128B、228A和228B可如圖所示排列。 It should be noted that, although the long semiconductors 128A, 128B, 228A, and 228B are illustrated here as being close to each other, they may be located in different regions on the die in any combination in some embodiments. For example, the semiconductor regions 128A and 128B may be located in a first element region, and the semiconductor regions 228A and 228B may be located in a second element region separate from the first element region. According to other embodiments of the present invention, the strip semiconductors 128A, 128B, 228A, and 228B may be arranged as shown in the figure.

請參照第3圖，形成圖案化之微影罩幕。相應之步驟被繪示於第14圖中流程圖之步驟206中。根據本發明之一些實施例，圖案化之微影罩幕包括三層結構42，結構包括底層36，底層36之上之中間層38及中間層38之上之上層40。根據本發明之一些實施例，底層36和上層40由光阻所形成。中間層38可由無機材料所形成，其可為碳化物(如碳氮化矽)、氮化物(如氮化矽)、氮氧化物(如氮氧化矽)、氧化物(如氧化矽)或相近之化合物。上層40被圖案化以形成開口44，開口垂直地對準於欲去除之虛置圖案。 Please refer to Figure 3 to form a patterned lithographic mask. The corresponding steps are illustrated in step 206 of the flowchart in FIG. 14. According to some embodiments of the present invention, the patterned lithographic mask includes a three-layer structure 42 including a bottom layer 36, an intermediate layer 38 above the bottom layer 36, and an upper layer 40 above the intermediate layer 38. According to some embodiments of the present invention, the bottom layer 36 and the upper layer 40 are formed of a photoresist. The intermediate layer 38 may be formed of an inorganic material, which may be a carbide (such as silicon carbonitride), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or similar Of compounds. The upper layer 40 is patterned to form an opening 44 that is vertically aligned with the dummy pattern to be removed.

接下來，進行非等向性蝕刻。以圖案化之上層40(如第3圖所示)為蝕刻罩幕蝕刻中層38，因此上層40之圖案被轉移至中層38中。在中層38之圖案化過程中，上層40至少部分地或完全地被消耗。在蝕穿中層38之後，非等向地圖案化底層36，其中中層38被用於做為蝕刻罩幕。上層40也完全消耗於下層36之圖案化過程中，若其未被完全消耗於中層38之圖案化過程中。 Next, anisotropic etching is performed. The middle layer 38 is etched by using the patterned upper layer 40 (as shown in FIG. 3) as an etching mask, so the pattern of the upper layer 40 is transferred to the middle layer 38. During the patterning of the middle layer 38, the upper layer 40 is at least partially or completely consumed. After etching through the middle layer 38, the bottom layer 36 is patterned anisotropically, wherein the middle layer 38 is used as an etching mask. The upper layer 40 is also completely consumed in the patterning process of the lower layer 36, if it is not completely consumed in the patterning process of the middle layer 38.

在蝕刻過程中，硬罩幕24與墊氧化層22於特定時間被暴露，隨後被蝕刻以暴露其下之虛置長條半導體132B和228B。得到之結構如第4圖所示。暴露之虛置長條半導體132B和228B隨後被蝕刻。相應之步驟被繪示於第14圖中流程圖之步驟208中。此外，隨著底層36之消耗以及長條半導體132B之完全去除，半導體底座130B也被暴露。半導體底座130B和虛置長條半導體128B隨後被以非等向性蝕刻製程蝕刻直到其被完全去除。 During the etching process, the hard mask 24 and the pad oxide layer 22 are exposed at a specific time, and then are etched to expose the dummy long semiconductors 132B and 228B below it. The resulting structure is shown in Figure 4. The exposed dummy long semiconductors 132B and 228B are subsequently etched. The corresponding steps are illustrated in step 208 of the flowchart in FIG. 14. In addition, as the bottom layer 36 is consumed and the long semiconductor 132B is completely removed, the semiconductor base 130B is also exposed. The semiconductor base 130B and the dummy long semiconductor 128B are subsequently etched by an anisotropic etching process until they are completely removed.

根據本發明之一些實施例，在完全去除虛置長條半導體128B及228B後蝕刻仍在繼續，因此形成凹槽46和48，如第5圖所示。相應之步驟被繪示於第14圖中流程圖之步驟210中。根據本發明之一些實施例，在形成凹槽46和48之後且當蝕刻結束時，下層36仍然有殘留部分36’未被完全消耗。此可由調整蝕刻配方所達成。殘留部分36’有著保持凹槽46及48之寬度為對應之虛置長條半導體128B和228B之寬度的功能。此外，可選擇層36、38及40等等之厚度以具有適當之數值進而確保殘留部分36’存在。 According to some embodiments of the present invention, the etching continues after the dummy long semiconductors 128B and 228B are completely removed, so that the grooves 46 and 48 are formed, as shown in FIG. 5. The corresponding steps are illustrated in step 210 of the flowchart in FIG. According to some embodiments of the present invention, after the grooves 46 and 48 are formed and when the etching is finished, the remaining portion 36 'of the lower layer 36 still has not been completely consumed. This can be achieved by adjusting the etching recipe. The remaining portion 36 'has a function of keeping the widths of the grooves 46 and 48 to the widths of the corresponding dummy long semiconductors 128B and 228B. In addition, the thicknesses of the layers 36, 38, 40, etc. may be selected to have appropriate values to ensure that the residual portion 36 'is present.

隨後去除下層36之殘留部分，例如於灰化製程中去除。其得到之結構如第6圖所示。此製程被控制，以使完全去除虛置長條半導體128B和228B之後，蝕刻繼續進行以進一步蝕刻其下之半導體基板20。在得到的結構中，凹槽46和48自長條半導體128A和228A之底層進一步向下延伸至基板20內。根據本發明之一些實施例，形成凹槽46且有V型剖面，形成凹槽48且有U型剖面。應當理解的是，於實際製程中，V型及U型可略為圓化，且示意之直側壁及底部可略為彎曲。舉例來說，凹槽46可有如同虛線47之所示之形狀，其中凹槽46之側邊及底部略為彎曲而非全直。此外，隨著凹槽46之進一步彎曲，凹槽46之形狀可接近於半圓形(碗狀)。凹槽48之U型也可有如同虛線49之所示之形狀，其中底部有2、3個或更多凹陷區。凹陷區是由在底層36(如第4圖)及長條半導體132B和130B中不同之蝕刻速率所造成，且凹陷區通過條狀半導體132B和130B中比底層36更快之蝕刻速率產生。因此，凹陷區直接產生於被蝕刻之長 條半導體132B之下且與之對準(如第4圖)。此外，凹陷區之數目與長條半導體132B之數目相同。 Then, the remaining portion of the lower layer 36 is removed, for example, in an ashing process. The resulting structure is shown in Figure 6. This process is controlled so that after the dummy long semiconductors 128B and 228B are completely removed, etching is continued to further etch the semiconductor substrate 20 below. In the resulting structure, the grooves 46 and 48 extend further downward from the bottom layers of the long semiconductors 128A and 228A into the substrate 20. According to some embodiments of the present invention, the groove 46 is formed with a V-shaped cross section, and the groove 48 is formed with a U-shaped cross section. It should be understood that, in the actual manufacturing process, the V-shape and the U-shape may be slightly rounded, and the straight side walls and the bottom may be slightly curved. For example, the groove 46 may have a shape as shown by the dashed line 47, wherein the sides and bottom of the groove 46 are slightly curved rather than completely straight. In addition, as the groove 46 is further bent, the shape of the groove 46 may be close to a semi-circular shape (bowl shape). The U-shape of the groove 48 may also have a shape as shown by the dotted line 49, in which the bottom portion has 2, 3 or more recessed areas. The recessed area is caused by different etching rates in the bottom layer 36 (as shown in FIG. 4) and the strip semiconductors 132B and 130B, and the recessed area is generated by a faster etching rate in the strip semiconductors 132B and 130B than the bottom layer 36. Therefore, the recessed area is directly under and aligned with the etched long semiconductor 132B (as shown in FIG. 4). In addition, the number of the recessed regions is the same as that of the long semiconductor 132B.

根據本發明之一些實施例，利用調整蝕刻配方和層36、38和40之厚度，凹陷部可反過來變成突出部，如同虛線49’所示。因此，突出直接產生於長條半導體132B之下且與之垂直對準(如第4圖)，其中突出部之數量與長條半導體132B之數目相同。根據其他實施例，藉由調整蝕刻配方及調整層36、38及40之厚度，凹槽48之底部大抵上共平面且無凹陷及突出。 According to some embodiments of the present invention, by adjusting the etching recipe and the thickness of the layers 36, 38, and 40, the recessed portion can be turned into a protruding portion, as shown by the dotted line 49 '. Therefore, the protrusions are directly under the vertical semiconductor 132B and vertically aligned therewith (as shown in FIG. 4), wherein the number of the protruding portions is the same as that of the vertical semiconductor 132B. According to other embodiments, by adjusting the etching recipe and adjusting the thicknesses of the layers 36, 38, and 40, the bottom of the groove 48 is substantially coplanar without dents and protrusions.

根據本發明之一些實施例，長條半導體228A之寬度W1大抵上與凹槽46之寬度W1’相同，舉例來說，有小於百分之二十或百分之十之W1之寬度差異。相似地，長條半導體128A之寬度W2大抵上與凹槽48之寬度W2’相同，舉例來說，有小於百分之二十或百分之十之W2之寬度差異。 According to some embodiments of the present invention, the width W1 of the long semiconductor 228A is substantially the same as the width W1 'of the groove 46, for example, there is a width difference of W1 less than 20% or 10%. Similarly, the width W2 of the long semiconductor 128A is substantially the same as the width W2 'of the groove 48. For example, there is a width difference of W2 less than 20% or 10%.

凹槽46及48之形成有利地幫助釋放晶圓100之中之應力，因此凹槽46及48之形成改善了鰭式場效電晶體之效能。為了有顯著的元件效能改善，凹槽46之深度D2及凹槽48之深度D3被製作成大於大約2奈米。據例來說，深度D2可介於大約4奈米及大約5奈米之間，深度D3可介於大約8奈米及大約10奈米之間。凹槽46之深度D2可比凹槽48之深度D3小。根據本發明之一些實施例，比例D3/D2介於大約1.5及大約3之間。 The formation of the grooves 46 and 48 is beneficial to help release the stress in the wafer 100. Therefore, the formation of the grooves 46 and 48 improves the performance of the fin-type field effect transistor. In order to have a significant improvement in device performance, the depth D2 of the groove 46 and the depth D3 of the groove 48 are made greater than about 2 nm. For example, the depth D2 may be between approximately 4 nanometers and approximately 5 nanometers, and the depth D3 may be between approximately 8 nanometers and approximately 10 nanometers. The depth D2 of the groove 46 may be smaller than the depth D3 of the groove 48. According to some embodiments of the invention, the ratio D3 / D2 is between about 1.5 and about 3.

請參照第7圖，形成介電區域/材料52以填補第6圖中所示的溝槽26及凹槽46和48。相應之步驟被繪示於第14圖中流程圖之步驟212中。根據本發明之一些實施例，介電區域52包括襯氧化物54及於襯氧化物54之上之介電材料56。襯氧化物 54可形成保形層，其水平部分及垂直部分有著相近之厚度。襯氧化物54之厚度可介於大約10Å及大約50Å之間。根據本發明之一些實施例，襯氧化物54藉由於含氧環境中氧化晶圓100所形成，例如利用矽之局部氧化法(Local Oxidation of Silicon，簡稱LOCOS)，其中氧氣(O2)可被包括於相對應之製程氣體中。根據本發明之其他實施例，襯氧化物54藉由臨場蒸氣產生技術(In-Situ Steam Generation，簡稱ISSG)所形成，舉例來說，藉由水蒸氣或氫氣(H2)及氧氣(O2)之組合氣體以氧化暴露之半導體基板20及長條半導體128A和228A。ISSG氧化法可於高溫下執行。根據其他實施例，襯氧化物54以沉積技術形成，如次大氣壓化學氣相沉積法(Sub Atmospheric Chemical Vapor Deposition，簡稱SACVD)。 Referring to FIG. 7, a dielectric region / material 52 is formed to fill the trenches 26 and the grooves 46 and 48 shown in FIG. 6. The corresponding steps are illustrated in step 212 of the flowchart in FIG. 14. According to some embodiments of the invention, the dielectric region 52 includes a lining oxide 54 and a dielectric material 56 over the lining oxide 54. The lining oxide 54 can form a conformal layer, and the horizontal portion and the vertical portion have similar thicknesses. The thickness of the lining oxide 54 may be between about 10 Å and about 50 Å. According to some embodiments of the present invention, the lining oxide 54 is formed by oxidizing the wafer 100 in an oxygen-containing environment, for example, by using the Local Oxidation of Silicon (LOCOS) method, wherein oxygen (O 2 ) can be Included in the corresponding process gas. According to other embodiments of the present invention, the lining oxide 54 is formed by in-situ steam generation (ISSG), for example, water vapor or hydrogen (H 2 ) and oxygen (O 2 The combined gas) oxidizes the exposed semiconductor substrate 20 and the long semiconductors 128A and 228A. ISSG oxidation can be performed at high temperatures. According to other embodiments, the liner oxide 54 is formed by a deposition technique, such as Sub Atmospheric Chemical Vapor Deposition (SACVD).

介電材料56隨後被形成以填補溝槽26及凹槽46和48剩下之部分，其得到之結構如第7圖所示。介電材料56可由氧化矽、碳化矽、氮化矽或由其多層所形成。形成介電材料56之方法可從可流動式化學氣相沉積(Flowable Chemical Vapor Deposition，簡稱FCVD)、旋轉塗佈、化學氣相沉積(Chemical Vapor Deposition，簡稱CVD)、原子層沉積(Atomic Layer Deposition，簡稱ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，簡稱HDPCVD)及LPCVD之中所選擇。 A dielectric material 56 is then formed to fill the remaining portions of the trenches 26 and grooves 46 and 48, and the resulting structure is shown in FIG. The dielectric material 56 may be formed of silicon oxide, silicon carbide, silicon nitride, or multiple layers thereof. The method of forming the dielectric material 56 may include Flowable Chemical Vapor Deposition (FCVD), spin coating, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (Abbreviated as ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD) and LPCVD.

根據本發明一些使用FCVD之實施例，含有矽及氮之前驅物(舉例來說，三甲矽烷基胺(trisilylamine，簡稱TSA)或二甲矽烷基胺(disilylamine，簡稱DSA)被使用，因此形成之 介電材料56為可流動的(如果凍狀)。根據本發明之一些實施例，可流動之介電材料56使用以烷胺基矽烷(alkylamino silane)為主之前驅物形成。在沉積過程中，電漿被開啟以活化氣相前驅物進而形成可流動的氧化物。在介電材料56形成後，進行退火/固化步驟，其將可流動的介電材料56轉化為固態介電材料。 According to some embodiments of the present invention using FCVD, a precursor containing silicon and nitrogen (for example, trisilylamine (TSA) or disilylamine (DSA) is used, and thus formed The dielectric material 56 is flowable (if frozen). According to some embodiments of the present invention, the flowable dielectric material 56 is formed using an alkylamino silane-based precursor. During the deposition process The plasma is turned on to activate the gas phase precursor to form a flowable oxide. After the dielectric material 56 is formed, an annealing / curing step is performed, which converts the flowable dielectric material 56 into a solid dielectric material.

隨後執行平坦化如化學機械研磨(Chemical Mechanical Polish，簡稱CMP)，如第8圖所示。相應之步驟被繪示於第14圖中流程圖之步驟214中。隔離區域52剩下之部分被稱為淺溝槽隔離(Shallow Trench Isolation，簡稱STI)區58。罩幕層24可被用作CMP停止層，因此罩幕層24之上表面大抵上和STI區域58之上表面共平面。在第8圖及隨後之圖中，襯氧化物54和介電層56(見第7圖)仍存在，雖然它們可能不被單獨表示。襯氧化物54和介電層56之間之介面可因不同之材料特性，如不同之材料和/或不同之密度而被區分，或無法被區分。 Subsequently, planarization such as chemical mechanical polishing (CMP) is performed, as shown in FIG. 8. The corresponding steps are illustrated in step 214 of the flowchart in FIG. 14. The remaining portion of the isolation region 52 is referred to as a Shallow Trench Isolation (STI) region 58. The mask layer 24 can be used as a CMP stop layer, so the upper surface of the mask layer 24 is substantially coplanar with the upper surface of the STI region 58. In FIG. 8 and subsequent figures, the lining oxide 54 and the dielectric layer 56 (see FIG. 7) still exist, although they may not be shown separately. The interface between the lining oxide 54 and the dielectric layer 56 may be distinguished or cannot be distinguished due to different material characteristics, such as different materials and / or different densities.

隨後去除罩幕層24。罩幕層24若由氮化矽所形成，可用使用熱磷酸(H3PO4)作為蝕刻劑之濕製程去除。接下來，凹蝕STI區58，襯墊層22可被以同樣之製程去除。因此產生鰭式半導體132A及232A。其得到之結構如第9圖所示。STI區58之凹蝕被繪示於第14圖中流程圖之步驟216中。STI區58之凹蝕可用等向蝕刻製程進行，其可為乾蝕刻製程或濕蝕刻製程。根據本發明之一些實施例，STI區58之凹蝕使用乾蝕刻製程進行，使用包括氨氣(NH3)和三氟化氮(NF3)之製程氣體。根據本發明之替代實施例，STI區58之凹蝕以濕蝕刻方式進行，其中蝕刻劑溶液為稀釋之氟化氫(HF)溶液，其HF濃度可低於大 約百分之一。 The cover curtain layer 24 is subsequently removed. If the mask layer 24 is formed of silicon nitride, it can be removed by a wet process using hot phosphoric acid (H 3 PO 4 ) as an etchant. Next, the STI region 58 is etched back, and the pad layer 22 can be removed by the same process. As a result, fin semiconductors 132A and 232A are produced. The resulting structure is shown in Figure 9. The etchback of the STI region 58 is shown in step 216 of the flowchart in FIG. 14. The etchback of the STI region 58 may be performed by an isotropic etching process, which may be a dry etching process or a wet etching process. According to some embodiments of the present invention, the etchback of the STI region 58 is performed using a dry etching process using a process gas including ammonia (NH 3 ) and nitrogen trifluoride (NF 3 ). According to an alternative embodiment of the present invention, the etchback of the STI region 58 is performed by wet etching, wherein the etchant solution is a diluted hydrogen fluoride (HF) solution, and its HF concentration may be less than about one percent.

STI區58之凹蝕造成鰭式半導體132A和232A突出至STI區58之上表面之上。根據本發明之一些實施例，STI區58直接位於底座130A之上之部分被去除，剩下之STI區58上表面大抵上共平面於或略低於底座130A之上表面。根據本發明之一些實施例，直接位於底座130A之上之STI區58的部分有一些部分殘留，因此剩下之STI區58之上表面高於底座130A之上表面。 The etchback of the STI region 58 causes the fin semiconductors 132A and 232A to protrude above the upper surface of the STI region 58. According to some embodiments of the present invention, a portion of the STI region 58 directly above the base 130A is removed, and the upper surface of the remaining STI regions 58 is substantially coplanar with or slightly lower than the upper surface of the base 130A. According to some embodiments of the present invention, some portions of the STI region 58 directly above the base 130A remain, so the upper surface of the remaining STI region 58 is higher than the upper surface of the base 130A.

根據本發明之一些實施例，第10A圖說明虛置閘極堆疊62的形成。相應之步驟被繪示於第14圖中流程圖之步驟218中。虛置閘極堆疊62可包括虛置閘極介電質64及虛置閘極介電質64之上之虛置閘極電極66。虛置閘極介電質64可由氧化矽所形成。根據一些實施例，虛置閘極電極66可由多晶矽所形成。第10B圖示意於第10A圖顯示之構造之剖面圖，其中剖面圖可從包括第10A圖中任一10B-10B線之垂直面獲得。請參照第10A圖及第10B圖，虛置閘極堆疊62形成在各個鰭式半導體132A或232A之中間部分的側壁及上表面，鰭式半導體132A和232A的末端則被露出。閘極間隔物68形成在虛置閘極堆疊62之側壁上。 FIG. 10A illustrates the formation of the dummy gate stack 62 according to some embodiments of the present invention. The corresponding steps are illustrated in step 218 of the flowchart in FIG. 14. The dummy gate stack 62 may include a dummy gate dielectric 64 and a dummy gate electrode 66 on the dummy gate dielectric 64. The dummy gate dielectric 64 may be formed of silicon oxide. According to some embodiments, the dummy gate electrode 66 may be formed of polycrystalline silicon. FIG. 10B is a cross-sectional view of the structure shown in FIG. 10A, where the cross-sectional view can be obtained from a vertical plane including any 10B-10B line in FIG. 10A. 10A and 10B, the dummy gate stack 62 is formed on the side wall and the upper surface of the middle portion of each fin semiconductor 132A or 232A, and the ends of the fin semiconductor 132A and 232A are exposed. A gate spacer 68 is formed on a side wall of the dummy gate stack 62.

接著，如第11圖中所示，以蝕刻製程去除鰭式半導體132A和232A之末端暴露部分，其中被去除的鰭式半導體132A和232A部分以虛線表示。相應之步驟被繪示於第14圖中流程圖之步驟220中。第11圖中所示之剖面圖也可從和第10B圖中所示之同樣的垂直面交叉線11-11(其經過鰭式半導體132A/232A之未被覆蓋部分)取得。在蝕刻之後，直接位於虛置 閘極堆疊62之下的鰭式半導體132A和232A部分仍殘留。由於未被蝕刻之鰭式半導體132A和232A部分並不在示意之平面中，它們在第11圖之中以虛線表示。 Next, as shown in FIG. 11, the exposed portions of the end portions of the fin semiconductors 132A and 232A are removed by an etching process, and the removed fin semiconductors 132A and 232A portions are indicated by dashed lines. The corresponding steps are illustrated in step 220 of the flowchart in FIG. 14. The cross-sectional view shown in FIG. 11 can also be obtained from the same vertical plane crossing line 11-11 (which passes through the uncovered portion of the fin semiconductor 132A / 232A) as shown in FIG. 10B. After the etching, portions of the fin semiconductors 132A and 232A directly under the dummy gate stack 62 remain. Since the unetched fin semiconductors 132A and 232A are not in the schematic plane, they are indicated by dashed lines in FIG. 11.

請參照第12圖，執行磊晶被以再生長磊晶區168及268。磊晶區168從底座130A之上表面生長。磊晶區268從剩餘之條狀半導體228A之上表面生長。磊晶區168及268形成鰭式場效電晶體之源極/汲極區。磊晶步驟被繪示於第14圖中流程圖之步驟222中。根據本發明之一些實施例，當所欲之鰭式場效電晶體之導電性為p型鰭式場效電晶體，磊晶區168及268可由矽鍺摻雜p型雜質(如硼)所構成。當所欲之鰭式場效電晶體之導電性為n型鰭式場效電晶體，磊晶區168及268可由矽磷所構成。根據一些實施例，磊晶區168及268可有向上晶面和向下晶面或其他形狀。 Referring to FIG. 12, the epitaxy is performed to grow the epitaxy regions 168 and 268. The epitaxial region 168 grows from the upper surface of the base 130A. The epitaxial region 268 grows from the upper surface of the remaining stripe semiconductor 228A. The epitaxial regions 168 and 268 form a source / drain region of a fin-type field effect transistor. The epitaxial step is shown in step 222 of the flowchart in FIG. 14. According to some embodiments of the present invention, when the conductivity of the desired fin-type field-effect transistor is a p-type fin-type field-effect transistor, the epitaxial regions 168 and 268 may be composed of silicon germanium doped with p-type impurities (such as boron). When the conductivity of the desired fin-type field effect transistor is an n-type fin-type field effect transistor, the epitaxial regions 168 and 268 may be composed of silicon phosphorus. According to some embodiments, the epitaxial regions 168 and 268 may have upward and downward crystal planes or other shapes.

隨後進行複數製程步驟以完成鰭式場效電晶體180和280的形成，其中鰭式場效電晶體180代表從冠狀主動區域128A形成之鰭式場效電晶體，鰭式場效電晶體280代表從單鰭式主動區域228A形成之鰭式場效電晶體。示例性之鰭式場效電晶體被繪示於第13圖，其以180/280標記代表鰭式場效電晶體180及280可有相似之剖面。第10A圖所示之虛置閘極堆疊60被置換閘極70所取代，置換閘極70之一被繪示於第13圖。相應之步驟被繪示於第14圖中流程圖之步驟224中。每一置換閘極70包括位於鰭式半導體132A或232A上表面和側壁之上之閘極介電層72，以及位於閘極介電層72之上之閘極電極74。閘極介電層72可由熱氧化所形成，因此可包括熱氧化矽。閘極介電層 72之形成也可包括一或複數沉積步驟，形成之閘極介電層72可包括高介電常數介電材料或非高介電常數介電材料。閘極電極74隨後形成於閘極介電層72之上，其可由金屬堆疊所形成。形成元件之製程不予贅述。源極/汲極矽化物區域76形成在源極/汲極區域168/268表面之上。源極/汲極接觸栓塞78形成在層間介電質(Inter-Layer Dielectric，簡稱ILD)82中且與源極/汲極矽化物區域76電連結。 Subsequently, a plurality of process steps are performed to complete the formation of fin-type field effect transistors 180 and 280. The fin-type field effect transistor 180 represents a fin-type field effect transistor formed from the crown active region 128A, and the fin-type field effect transistor 280 represents a single-fin type Fin-type field effect transistor formed by the active region 228A. Exemplary fin-type field-effect transistors are shown in FIG. 13, which are labeled with 180/280 to indicate that the fin-type field-effect transistors 180 and 280 may have similar cross sections. The dummy gate stack 60 shown in FIG. 10A is replaced by a replacement gate 70, and one of the replacement gates 70 is shown in FIG. 13. The corresponding steps are illustrated in step 224 of the flowchart in FIG. 14. Each replacement gate 70 includes a gate dielectric layer 72 on the upper surface and sidewalls of the fin semiconductor 132A or 232A, and a gate electrode 74 on the gate dielectric layer 72. The gate dielectric layer 72 may be formed by thermal oxidation, and thus may include thermal silicon oxide. The formation of the gate dielectric layer 72 may also include one or more deposition steps. The formed gate dielectric layer 72 may include a high-k dielectric material or a non-high-k dielectric material. The gate electrode 74 is then formed over the gate dielectric layer 72, which may be formed from a metal stack. The process of forming the components will not be described in detail. A source / drain silicide region 76 is formed over the surface of the source / drain regions 168/268. The source / drain contact plug 78 is formed in an inter-layer dielectric (ILD) 82 and is electrically connected to the source / drain silicide region 76.

請回頭參照第12圖，凹槽46和48被繪示形成於相同之晶圓100及相同晶粒之中，晶粒可由單粒化晶圓100得到。根據本發明之替代實施例，凹槽46可被形成於不含凹槽48之晶片或晶圓之上，凹槽48可被形成於不含凹槽46之晶片或晶圓之上。當凹槽46和凹槽48在不同之晶片上形成時，凹槽46和48的深度可獨自地被調整以達成最佳降低應力之結果。 Please refer back to FIG. 12. The grooves 46 and 48 are formed in the same wafer 100 and the same die. The die can be obtained from the single wafer 100. According to an alternative embodiment of the present invention, the groove 46 may be formed on a wafer or wafer without the groove 48, and the groove 48 may be formed on a wafer or wafer without the groove 46. When the grooves 46 and 48 are formed on different wafers, the depths of the grooves 46 and 48 can be adjusted independently to achieve the best stress reduction results.

本發明之一些實施例有一些有利的特徵。藉由在半導體晶圓和晶片中形成凹槽，可降低晶圓和晶片之應力，改善形成於晶圓和晶片之鰭式場效電晶體之元件效能。最佳化之凹槽深度和製程可從進行於樣品晶圓上之實驗決定，因此當本發明之實施例在實施時，將無額外之晶圓製造成本。 Some embodiments of the invention have some advantageous features. By forming grooves in semiconductor wafers and wafers, the stress on the wafers and wafers can be reduced, and the device performance of fin-type field effect transistors formed on the wafers and wafers can be improved. The optimized groove depth and process can be determined from experiments performed on the sample wafer, so when the embodiment of the present invention is implemented, there will be no additional wafer manufacturing costs.

根據本發明之一些實施例，積體電路結構，包括半導體基板，具有複數長條半導體；第一凹槽，沿著長條半導體之中兩相鄰之長條半導體之間形成；第二凹槽，形成於第一凹槽之中；隔離區域，位於第一凹槽及第二凹槽之間，第二凹槽具有低於第一凹槽之深度。 According to some embodiments of the present invention, the integrated circuit structure includes a semiconductor substrate having a plurality of long semiconductors; a first groove formed along two adjacent long semiconductors among the long semiconductors; and a second groove Is formed in the first groove; the isolation region is located between the first groove and the second groove, and the second groove has a depth lower than that of the first groove.

根據本發明之一些實施例，一種積體電路結構， 包括半導體基板；複數隔離區域，延伸至半導體基板之中；第一及第二長條半導體，位於半導體基板之中。第一長條半導體為冠狀長條半導體，包括底座，位於隔離區域；複數鰭式半導體，直接位於底座之上；第二長條半導體為單鰭式長條半導體；第一凹槽，位於兩相鄰第一長條半導體之間；第二凹槽，形成於第一凹槽之中；第二凹槽延伸自兩相鄰之第一長條半導體之底部至半導體基板之較低部分；隔離區域包括延伸進入第二凹槽之第一部分；第二凹槽及第一長條半導體之底座具有大抵上相同之寬度；第三凹槽，位於兩相鄰第二長條半導體之間；第四凹槽，形成於第三凹槽之中；第四凹槽延伸自兩相鄰之第二長條半導體之底部至半導體基板之較低部分；隔離區域包括延伸進入第四凹槽之第二部分，且第四凹槽及第二長條半導體具有大抵上相同之寬度。 According to some embodiments of the present invention, an integrated circuit structure includes a semiconductor substrate; a plurality of isolation regions extend into the semiconductor substrate; and first and second long semiconductors are located in the semiconductor substrate. The first long semiconductor is a crown-shaped long semiconductor including a base and is located in an isolation region; the plurality of fin semiconductors is directly above the base; the second long semiconductor is a single-fin semiconductor; the first groove is located in two phases Adjacent to the first long semiconductor; a second groove formed in the first groove; the second groove extending from the bottom of two adjacent first long semiconductors to a lower portion of the semiconductor substrate; an isolation region The first groove includes a first portion extending into the second groove; the second groove and the base of the first elongated semiconductor have substantially the same width; the third groove is located between two adjacent second elongated semiconductors; the fourth concave A groove formed in the third groove; a fourth groove extending from the bottom of two adjacent second long semiconductors to a lower portion of the semiconductor substrate; an isolation region including a second portion extending into the fourth groove, And the fourth groove and the second long semiconductor have substantially the same width.

根據本發明之一些實施例，一種積體電路結構的製造方法包括自一半導體基板形成第一長條半導體及第二長條半導體；蝕刻第一長條半導體；蝕刻一部分半導體基板，部分直接位於蝕刻後之第一條狀半導體之下以形成一凹槽。 According to some embodiments of the present invention, a method for manufacturing an integrated circuit structure includes forming a first strip semiconductor and a second strip semiconductor from a semiconductor substrate; etching the first strip semiconductor; A groove is formed below the first strip-shaped semiconductor.

上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明為基礎，設計或修改其他製程及結構，以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本發明之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明的精神及 範圍。 The foregoing outlines the features of many embodiments, so that those with ordinary knowledge in the relevant technical field may better understand the aspects of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention. Such an equivalent creation does not exceed the spirit and scope of the present invention.

Claims (16)

一種積體電路結構，包括：一半導體基板，具有複數長條半導體；一第一凹槽，沿著該些長條半導體之中兩相鄰之長條半導體之間形成；一第二凹槽，形成於該第一凹槽之中；以及一隔離區域，位於該第一凹槽及該第二凹槽之間，該第二凹槽具有一低於該第一凹槽之深度。     An integrated circuit structure includes: a semiconductor substrate having a plurality of long semiconductors; a first groove formed along two adjacent long semiconductors among the long semiconductors; and a second groove, Formed in the first groove; and an isolation region between the first groove and the second groove, the second groove has a depth lower than the first groove.     如申請專利範圍第1項所述之積體電路結構，其中該第二凹槽有一U型(U-shaped)底部，該些長條半導體凹槽之一包括：一底座，其中該第一凹槽自該底座之底部向下延伸至該半導體基板；以及複數鰭式半導體，該些鰭式半導體直接位於且連接至該底座之上。     According to the integrated circuit structure described in item 1 of the patent application scope, wherein the second groove has a U-shaped bottom, one of the long semiconductor grooves includes: a base, wherein the first concave The groove extends downward from the bottom of the base to the semiconductor substrate; and a plurality of fin semiconductors, the fin semiconductors are directly located on and connected to the base.     如申請專利範圍第2項所述之積體電路結構，其中該底座及該第二凹槽大抵上具有相同之寬度。     According to the integrated circuit structure described in item 2 of the scope of patent application, wherein the base and the second groove have substantially the same width.     如申請專利範圍第2或3項所述之積體電路結構，其中該第二凹槽之U型底部有複數凹陷。     The integrated circuit structure according to item 2 or 3 of the scope of the patent application, wherein the U-shaped bottom of the second groove has a plurality of depressions.     如申請專利範圍第2或3項所述之積體電路結構，其中該些長條半導體更包括複數單鰭式長條半導體，其中該第二凹槽、該些單鰭式長條半導體及於該底座之上之該些鰭式半導體相互平行且具有一均勻節距。     According to the integrated circuit structure described in item 2 or 3 of the scope of patent application, the strip semiconductors further include a plurality of single-fin strip semiconductors, wherein the second groove, the single-fin strip semiconductors, and the The fin semiconductors on the base are parallel to each other and have a uniform pitch.     如申請專利範圍第1、2或3項所述之積體電路結構，其中 該第二凹槽具有一V型(V-shaped)底部。     The integrated circuit structure as described in claim 1, 2, or 3, wherein the second groove has a V-shaped bottom.     如申請專利範圍第6項所述之積體電路結構，其中該些長條半導體之一及該第二凹槽大抵上具有相同之寬度。     According to the integrated circuit structure described in item 6 of the scope of the patent application, one of the long semiconductors and the second groove have substantially the same width.     一種積體電路結構，包括：一半導體基板；複數隔離區域，延伸至該半導體基板之中；以及一第一長條半導體，包括於該半導體基板之中且為一冠狀長條半導體，包括：一底座，位於該隔離區域；複數鰭式半導體，直接位於該底座之上；一第二長條半導體，包括於該半導體基板，且為一單鰭式長條半導體；一第一凹槽，位於兩相鄰第一長條半導體之間；一第二凹槽，形成於該第一凹槽之中，且延伸自兩相鄰之該第一長條半導體之一底部至該半導體基板之一較低部分，其中該些隔離區域包括一延伸進入該第二凹槽之第一部分，且該第二凹槽及該第一長條半導體之底座具有一大抵上相同之寬度；一第三凹槽，位於兩相鄰第二長條半導體之間；以及一第四凹槽，形成於該第三凹槽之中，且延伸自兩相鄰之該第二長條半導體之一底部至該半導體基板之該較低部分，其中該隔離區域包括一延伸進入該第四凹槽之第二部分，且該第四凹槽及該第二長條半導體具有一大抵上相同之寬度。     An integrated circuit structure includes: a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; and a first elongated semiconductor included in the semiconductor substrate and being a crown-shaped elongated semiconductor including: a A base is located in the isolation region; a plurality of fin-shaped semiconductors are directly above the base; a second long semiconductor is included in the semiconductor substrate and is a single-fin long semiconductor; a first groove is located at two Between adjacent first long semiconductors; a second groove formed in the first groove and extending from the bottom of one of the two adjacent first semiconductors to a lower one of the semiconductor substrates Part, wherein the isolation regions include a first part extending into the second groove, and the second groove and the base of the first elongated semiconductor have a large width that is equal to or greater than one; a third groove is located at Between two adjacent second elongated semiconductors; and a fourth groove formed in the third groove and extending from the bottom of one of the two adjacent second elongated semiconductors to the semiconductor substrate Compare Portion, wherein the isolation region comprises a second portion extending into the recess of the fourth, and the fourth recess and the second strip of the same semiconductor having a width probably.     如申請專利範圍第8項所述之積體電路結構，其中該第二長條半導體、該些鰭式半導體及該第四凹槽相互平行且大抵上具有一均勻節距。     According to the integrated circuit structure described in item 8 of the scope of the patent application, the second strip semiconductor, the fin semiconductors, and the fourth groove are parallel to each other and have a uniform pitch substantially.     如申請專利範圍第8項所述之積體電路結構，其中該第四凹槽具有一V型底部；或其中該第二凹槽具有一U型剖面，且該第二凹槽之一底部有複數凹陷。     The integrated circuit structure according to item 8 of the scope of the patent application, wherein the fourth groove has a V-shaped bottom; or wherein the second groove has a U-shaped cross section and one of the bottoms of the second groove has Plural depressions.     如申請專利範圍第8-10項中任一項所述之積體電路結構，該結構更包括：一磊晶半導體區域，位於一部分之該底座之上且包括面向上之晶面及面向下之晶面；以及一閘極堆疊，位於該些鰭式半導體之上。     According to the integrated circuit structure described in any one of claims 8-10, the structure further includes: an epitaxial semiconductor region, which is located on a part of the base and includes a crystal plane facing upward and a crystal plane facing downward. A crystal plane; and a gate stack located on the fin semiconductors.     一種積體電路結構的製造方法，包括：自一半導體基板形成一第一長條半導體及一第二長條半導體；蝕刻該第一長條半導體；以及蝕刻一部分之該半導體基板，該部分直接位於該蝕刻後之第一條狀半導體之下以形成一凹槽。     A manufacturing method of an integrated circuit structure includes: forming a first long semiconductor and a second long semiconductor from a semiconductor substrate; etching the first long semiconductor; and etching a part of the semiconductor substrate, the part is directly located at A groove is formed under the etched first strip-shaped semiconductor.     如申請專利範圍第12項所述之積體電路結構的製造方法，其中該第一長條半導體包括一底座，及複數直接位於該底座之上之鰭式半導體，且該底座於該第一長條半導體之蝕刻過程中完全被去除。     The manufacturing method of the integrated circuit structure according to item 12 of the scope of patent application, wherein the first long semiconductor includes a base, and a plurality of fin semiconductors directly above the base, and the base is on the first long The semiconductor is completely removed during the etching process.     如申請專利範圍第13項所述之積體電路結構的製造方法，其中該凹槽形成於該半導體基板且具有一U形剖面。     The manufacturing method of the integrated circuit structure according to item 13 of the patent application scope, wherein the groove is formed in the semiconductor substrate and has a U-shaped cross section.     如申請專利範圍第12-14任一項所述之積體電路結構的製 造方法，其中當該第一長條半導體被蝕刻時，該第二長條半導體也被蝕刻，且當該凹槽形成時，一直接位於該被蝕刻之第二長條半導體之下之該半導體基板之額外部分也被蝕刻以形成一額外凹槽，且該額外凹槽具有一V形底部。     The method for manufacturing an integrated circuit structure according to any one of claims 12-14, wherein when the first long semiconductor is etched, the second long semiconductor is also etched, and when the groove is formed At this time, an additional portion of the semiconductor substrate directly under the etched second long semiconductor is also etched to form an additional groove, and the additional groove has a V-shaped bottom.     如申請專利範圍第15項所述之積體電路結構的製造方法，該凹槽形成於該半導體基板且具有一U形剖面，且該V形較該U形淺。     According to the manufacturing method of the integrated circuit structure described in item 15 of the scope of patent application, the groove is formed on the semiconductor substrate and has a U-shaped cross section, and the V-shape is shallower than the U-shape.    
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