TW201814865A - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a flexible circuit substrate and a chip. The flexible circuit substrate includes a flexible base and a circuit structure disposed on the flexible base. The flexible base includes a chip bonding area. The circuit structure includes a plurality of leads and at least one dummy lead. Each lead includes an inner lead portion, and the at least one dummy lead includes an alignment pattern in the chip bonding area. The chip includes a plurality of bumps and at least one dummy bump. The chip is disposed in the chip bonding area, and the bumps are connected to the inner lead portions. The alignment pattern of the at least one dummy lead corresponds to the at least one dummy bump, and a projection image of the alignment pattern on the chip surrounds the at least one dummy bump, and a gap G exists between the projection image and a side of the at least one dummy bump.

Description

Film flip chip package structure

The present invention relates to a package structure, and more particularly to a film flip chip package structure.

With the improvement of semiconductor technology, liquid crystal displays have the advantages of low power consumption, light weight, high resolution, high color saturation, long life, etc., and thus are widely used in mobile phones, notebook computers or desktop computers. LCD screens and LCD TVs and other electronic products that are closely related to life. Among them, the driver IC of the display is an indispensable component of the liquid crystal display. In order to meet the needs of various applications of liquid crystal display device driving wafers, tape automatic bonding (TAB) packaging technology is generally used for chip packaging, and chip-on-film (COF) package structure is one of them. Widely used package structure for tape and tape automated bonding technology.

The thin film flip chip package structure bonds the wafer to the flexible circuit substrate by flip chip bonding, and the bumps on the wafer are bonded to the pins on the flexible circuit substrate. However, there is currently no significant pattern or image on the wafer and the flexible circuit substrate for the machine to calculate the joint angle and position between the wafer and the flexible circuit substrate, resulting in a relationship between the wafer and the flexible circuit substrate. The bonding accuracy is poor, and it is difficult to accurately arrange the pins of the flexible wiring carrier in the center of the corresponding bumps. Even, it is possible that the pin connection bumps are incomplete, not connected to the bumps, or connected to the wrong bumps due to wafer offset.

The present invention provides a thin film flip chip package structure that precisely bonds bumps of a wafer to pins of a flexible wiring carrier.

A thin film flip chip package structure of the present invention comprises a flexible circuit carrier and a wafer. The flexible circuit carrier includes a flexible substrate and a circuit structure disposed on the flexible substrate. The flexible substrate includes a die bond region, wherein the circuit structure includes a plurality of pins and at least one dummy pin. Wherein each of the pins has an inner lead portion located within the die bond region, and at least one dummy pin has a pair of bit patterns located within the die bond region. The wafer includes a plurality of bumps and at least one dummy bump, the wafers are disposed in the wafer bonding region, and the bumps are respectively connected to the inner lead portions, and the alignment pattern of the at least one dummy pin corresponds to the at least one dummy bump, and The orthographic projection of the alignment pattern on the wafer surrounds at least one dummy bump and there is a gap G with the edge of the at least one dummy bump.

Based on the above, the film flip-chip package structure of the present invention has a dummy bump disposed on the wafer, and a dummy pin is disposed on the flexible circuit carrier, and the dummy pin has a alignment pattern located in the wafer bonding region, so that The bit pattern corresponds to the dummy bump, and therefore, the thin film flip chip package structure of the present invention is provided with a dummy pin on the flexible line carrier when the inner pin bonding process is performed to bond the wafer to the flexible line carrier. The alignment pattern is aligned with the dummy bump of the wafer such that the orthographic projection of the alignment pattern on the wafer surrounds the dummy bump and there is a gap G with the edge of the dummy bump, using the spacing between the alignment pattern and the dummy bump The production equipment can effectively calculate the correctness of the joint angle and position to confirm that the wafer is bonded to the correct position on the flexible circuit carrier, so that the bumps of the wafer can be accurately connected to the flexible circuit carrier. Inner pin section. In addition, the field operator can easily judge the joint precision between the lead and the bump, and effectively improve the joint quality.

The above described features and advantages of the invention will be apparent from the following description.

1 is a partial top plan view of a thin film flip chip package structure in accordance with an embodiment of the invention. Referring to FIG. 1 , the thin film flip chip package structure 100 of the present embodiment includes a flexible circuit carrier 110 and a wafer 120 . The flexible circuit carrier 110 includes a flexible substrate 111 and a line structure 113 disposed on the flexible substrate 111. The flexible substrate 111 is, for example, a part of a film web. The flexible substrate 111 includes a wafer bonding region 112.

2 is a partial bottom view showing the flexible substrate of the thin film flip chip package structure of FIG. 1. Fig. 3 is a partially enlarged schematic view of Fig. 2; In order to clearly describe the connection relationship between the bumps of the wafer 120 and the leads on the flexible wiring carrier 110, FIG. 2 specifically depicts the bump configuration on the active surface of the wafer 120 and the flexible lines from another perspective. The relative position of the pins on the carrier 110.

As shown in FIG. 1, the line structure 113 includes a plurality of pins. In this embodiment, the flexible circuit carrier 110 has an input end located above the drawing surface and an output end located below the drawing surface, and the pins on the flexible circuit carrier 110 are divided to extend above the drawing surface. The input pin 114 is connected to the output pin 116 extending below the drawing. As shown in FIG. 2, each pin has an inner lead portion located within the wafer bond region 112. Thus, the input terminal pin 114 has an input internal pin portion 114a located within the wafer bond region 112, and the output terminal pin 116 has an output internal pin portion 116a located within the wafer bond region 112.

In addition, the line structure 113 also includes at least one dummy pin 118. In the present embodiment, the line structure 113 includes a plurality of dummy pins 118. Each dummy pin 118 has a pair of bit patterns 119 located within the wafer bond region 112. In this embodiment, each of the alignment patterns 119 is a non-closed pattern, such as a U-shaped pattern. The alignment patterns 119 of the dummy pins 118 are respectively located at the four corners C1, C2, C3, and C4 of the wafer bonding region 112. Of course, the shape of the alignment pattern 119 and the total number and arrangement positions of the dummy pins 118 are not This is a limitation.

The wafer 120 includes a plurality of bumps. The wafers 120 are disposed in the wafer bonding region 112. The bumps are respectively connected to the inner lead portions to electrically connect the wafer 120 to the flexible wiring carrier 110. More specifically, in the present embodiment, the wafer 120 includes a plurality of input bumps 122 and a plurality of output bumps 123. The input bumps 122 are respectively connected to the input inner lead portions 114a, and the outputs are respectively output. The end bumps 123 are respectively connected to the output terminal inner lead portions 116a.

In addition, the wafer 120 further includes at least one dummy bump 124. In the embodiment, the wafer 120 includes a plurality of dummy bumps 124 respectively located at four corners of the wafer 120, that is, dummy bumps. The configuration position of 124 corresponds to the configuration position of the alignment pattern 119 of the dummy pin 118. Of course, the number of the dummy bumps 124 is not limited thereto, and the configuration position is not limited by four corners.

As shown in FIG. 2, in the present embodiment, the alignment patterns 119 have the same shape, but the number or arrangement of the alignment patterns 119 at any two corners on the same side of the wafer bonding region 112 are not the same. For example, as seen in FIG. 2, the number of alignment patterns 119 of the two corners C1 and C2 on the long side LS1 of the wafer bonding region 112 is three and two, respectively, and the number of the two is different. In addition, the number of alignment patterns 119 of the two corners C2 and C3 located on the short side SS1 of the wafer bonding region 112 is two, but one of the alignment patterns 119 located at the corner C2 is correspondingly arranged along the long side LS1. The dummy bumps 124a, one is a dummy bump 124b corresponding to the short side SS1, and the alignment pattern 119 located at the corner C3 is a virtual bump 124a corresponding to the long side LS2, and the arrangement of the two The way is different. By analogy, the alignment patterns 119 of the two corners C3 and C4 on the long side LS2 of the wafer bonding region 112 are arranged differently, and the two corners C1 and C4 on the short side SS2 of the wafer bonding region 112 are located. The number of alignment patterns 119 is different.

Moreover, in other embodiments, the shape of the alignment patterns 119 at the two corners on the same side of the wafer bonding region 112 may also be different. By arranging the alignment patterns 119 of different shapes, numbers, and/or arrangements, it is possible to prevent the wafers 120 from being misaligned when disposed in the wafer bonding region 112. However, the present invention is not limited thereto. In other embodiments, when the wafer 120 and the flexible circuit carrier 110 are additionally provided with other foolproof mechanisms for preventing misalignment during wafer bonding, the wafer bonding region is located. The shape, number, and/or arrangement of the alignment patterns 119 at various corners of 112 may be the same. In other words, the number, shape, and/or arrangement of the alignment patterns 119 at the two corners on the same side of the wafer bonding region 112 are not limited to the above.

2 and FIG. 3, the alignment pattern 119 of each dummy pin 118 corresponds to its corresponding dummy bump 124, and the orthographic projection of each alignment pattern 119 on the wafer 120 at least partially surrounds its corresponding The dummy bump 124 has a gap G with the edge of the dummy bump 124. In this embodiment, the dummy bumps 124 are rectangular, and the alignment pattern 119 is U-shaped. Therefore, the orthographic projection of each alignment pattern 119 on the wafer 120 is around three sides of the corresponding dummy bumps 124 and There is a gap G with each of the three sides. However, the shape of the dummy bump 124 and the shape of the alignment pattern 119 are not limited to the above, and the shape of the alignment pattern 119 is designed to conform to the shape of the dummy bump 124 so that the alignment pattern 119 is on the wafer 120. A gap G is maintained between the orthographic projection and the edge of the imaginary bump 124 it surrounds. With such a configuration, when the inner pin bonding process is to be performed to place the wafer 120 in the wafer bonding region 112 of the flexible wiring carrier 110, the production device can confirm whether the alignment pattern 119 of the dummy pin 118 is correct. The dummy bumps 124 located on the wafer 120, and identifying and calculating whether the orthographic projection of the alignment pattern 119 on the wafer 120 surrounds the edge of the dummy bump 124 and having a gap G with the edge, can confirm whether the wafer 120 is bonded to the flexible portion. The correct position on the line carrier 110. As a result, the bumps (input bumps 122 and output bumps 123) of the wafer 120 are accurately connected to the inner lead portions of the flexible wiring carrier 110 (input terminal inner portion 114a and output) In-terminal lead portion 116a). Field workers can also more easily determine the joint accuracy between the inner leads and the bumps, effectively improving the joint quality.

In addition, the bumps on the wafer 120 have different widths according to different functional requirements. Accordingly, the pins on the flexible circuit carrier 110 are also designed to have different widths in accordance with the corresponding bumps. In general, as shown in FIGS. 2 and 3, the width of the output bump 123 may be smaller than the width of the input bump 122, and the width of the output pin 116 may be smaller than the width of the input pin 114. Thus, the distance between the edge of the output pin 116 and the edge of the output bump 123 will be different than the distance between the edge of the input pin 114 and the edge of the input bump 122.

As shown in FIG. 2, in the present embodiment, the edges of the inner lead portions (the input inner lead portion 114a or the output inner lead portion 116a) and the correspondingly connected bumps (input bumps 122 or There is a minimum distance D between the edges of the output bumps 123), and the minimum value _{Dmin of} these minimum distances D will typically be between the edge of the lead portion 116a and the edge of the output bump 123 in the output. In a preferred embodiment, the gap G between the orthographic projection of the alignment pattern 119 on the wafer 120 and the edge of the dummy bump 124 is between 1.6 and 2.4 times the minimum value _Dmin of the minimum distances D ( That is 1.6D _min ≦G≦2.4D _min ). The gap G is such that when the wafer 120 is bonded to the flexible wiring carrier 110, the inner lead portion (the input inner lead portion 114a and the output inner lead portion 116a) is correctly connected to the corresponding bump (input terminal) The bump 122 and the output bump 123) are not excessively offset from the joint position, even in the case of being unconnected or connected to the wrong pin.

Figure 4 is a partial cross-sectional view of Figure 1. Referring to FIG. 4, after the internal pin bonding process, the output bump 123 is in contact with the output inner pin portion 116a, and the orthographic projection of the alignment pattern 119 surrounds the edge of the dummy bump 124 and the edge. There is a gap G between them, that is, the dummy bump 124 is located in the space surrounded by the alignment pattern 119, and is not in contact with the alignment pattern 119, and the height of the dummy bump 124 is smaller than the output bump 123 and The total height of the lead portions 116a in the output end after bonding is such that the dummy bumps 124 do not contact the flexible substrate 111.

In addition, in the present embodiment, the thin film flip chip package structure 100 further includes an encapsulant 130 disposed between the flexible circuit carrier 110 and the wafer 120. The encapsulant 130 covers the inner leads of the pins. The alignment pattern 119 of the dummy pins 118, the bumps, and the dummy bumps 124 are such that the wafer 120 can be firmly connected to the flexible wiring carrier 110 and protect the wafer 120 from the flexible wiring carrier 110. Electrical contacts (these inner leads and bumps). More specifically, the encapsulant 130 also covers the periphery of the wafer 120 in order to effectively prevent the intrusion of moisture or foreign matter from causing electrical contact damage or electrical anomalies.

In the following embodiments, the same or similar elements as those of the foregoing embodiments are denoted by the same or similar symbols and will not be further described.

FIG. 5 is a bottom plan view of a thin film flip-chip package structure concealing a flexible substrate according to another embodiment of the invention. Referring to FIG. 5, the main difference between FIG. 5 and FIG. 2 is that, in FIG. 2, the dummy bumps 124 are respectively located at four corners of the wafer 120, and the alignment patterns 119 of the dummy pins 118 are respectively located at the wafer bonding region 112. Four corners. In the present embodiment, the dummy bumps 124 of the thin film flip chip package structure 100a are respectively located at two corners (upper right and lower left corners) on the diagonal of the wafer 120. Accordingly, these alignments of the dummy pins 118 are correspondingly The patterns 119 are respectively located at two corners (upper right and lower left corners) on the diagonal of the wafer bonding region 112. However, the number of corners in which the wafer 120 is provided with the dummy bumps 124 and the wafer bonding regions 112 are provided with the alignment patterns 119 can be set according to the requirements of the alignment identification mechanism of the production equipment, and is not limited to the above embodiments.

Further, the form of the alignment pattern 119 of the dummy pin 118 is not limited to the above. 6 to 8 are partial bottom views of a plurality of thin film flip-chip packages for hiding a flexible substrate according to other embodiments of the present invention.

Please refer to FIG. 6. In this embodiment, the alignment pattern 119b is a closed pattern, and the closed pattern is, for example, a one-letter pattern. Of course, the form of the alignment pattern 119b is not limited thereto. In other embodiments, the alignment pattern 119b may also be a closed ring pattern, or other closed shape, in combination with the shape of the dummy bump 124. The pattern is such that the gap G is maintained between the orthographic projection of the alignment pattern on the wafer 120 and the edge of the dummy bump surrounded by it.

Referring to FIG. 7, in the embodiment, the alignment pattern 119c is a non-closed pattern, and the alignment pattern 119c is, for example, a non-closed bifurcated pattern. In the present embodiment, the opening of the cross pattern of the alignment pattern 119c is toward the inside of the wafer 120. Referring to FIG. 8, in the embodiment, the alignment pattern 119d is a non-closed pattern in the shape of a inverted fork, that is, the opening of the inverted pattern of the alignment pattern 119d is toward the edge of the wafer 120. Of course, only the shapes of the plurality of alignment patterns 119, 119b, 119c, and 119d are mentioned above, and the shapes of the alignment patterns 119, 119b, 119c, and 119d are not limited to the above.

In summary, the thin film flip chip package structure of the present invention has a dummy bump disposed on the wafer, and a dummy pin is disposed on the flexible circuit carrier, and the dummy pin has a alignment pattern located in the wafer bonding region. The alignment pattern is made to correspond to the dummy bumps. Therefore, when the inner lead bonding process is performed to bond the wafer to the flexible wiring carrier, the thin film flip chip package structure of the present invention is virtualized by the flexible wiring carrier The alignment pattern of the pins is aligned with the dummy bumps of the wafer, so that the orthographic projection of the alignment pattern on the wafer surrounds the dummy bumps and there is a gap G with the edges of the dummy bumps, which exists between the alignment pattern and the dummy bumps. The spacing allows the production equipment to efficiently calculate the joint angle and position to ensure that the wafer is bonded to the correct position on the flexible circuit carrier, allowing the bumps on the wafer to be accurately connected to the flexible line. The inner lead portion of the board. In addition, field workers can more easily determine the joint accuracy between the pins and the bumps, effectively improving the joint quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a‧‧‧ film flip chip package structure
110‧‧‧Flexible line carrier
111‧‧‧Flexible substrate
112‧‧‧ wafer junction area
113‧‧‧Line structure
114‧‧‧Input pin
114a‧‧‧Input pin section
116‧‧‧Output pin
116a‧‧‧Output pin section
118‧‧‧virtual pins
119, 119b, 119c, 119d‧‧‧ alignment pattern
120‧‧‧ wafer
122‧‧‧Input bumps
123‧‧‧Output bumps
124, 124a, 124b‧‧‧ virtual bumps
130‧‧‧Package colloid
C1, C2, C3, C4‧‧‧ corner
D‧‧‧Minimum distance
D _min ‧‧‧minimum of minimum distance
G‧‧‧ gap
LS1, LS2‧‧‧ long side
SS1, SS2‧‧‧ short side

1 is a partial top plan view of a thin film flip chip package structure in accordance with an embodiment of the invention. 2 is a partial bottom view showing the flexible substrate of the thin film flip chip package structure of FIG. 1. Fig. 3 is a partially enlarged schematic view of Fig. 2; Figure 4 is a partial cross-sectional view of Figure 1. FIG. 5 is a bottom plan view of a thin film flip-chip package structure concealing a flexible substrate according to another embodiment of the invention. 6 to 8 are partial bottom views of a plurality of thin film flip-chip packages for hiding a flexible substrate according to other embodiments of the present invention.

Claims (11)

A film flip chip package structure comprising: a flexible circuit carrier, comprising a flexible substrate and a line structure disposed on the flexible substrate, the flexible substrate comprising a wafer bonding region, wherein the The wiring structure includes a plurality of pins and at least one dummy pin, wherein each of the pins has an inner lead portion located in the die bond region, and the at least one dummy pin has a pair of bits located in the die bond region And a wafer comprising a plurality of bumps and at least one dummy bump disposed in the wafer bonding region, wherein the bumps are respectively connected to the inner lead portions, the at least one dummy pin The alignment pattern corresponds to at least one dummy bump, and the orthographic projection of the alignment pattern on the wafer at least partially surrounds the at least one dummy bump and has a gap G with the edge of the at least one dummy bump. The film flip-chip package structure of claim 1, wherein the orthographic projection of the alignment pattern on the wafer surrounds at least three sides of the at least one dummy bump and the gap G exists respectively with the at least three sides . The thin film flip chip package structure of claim 1, wherein the at least one dummy bump is located at at least one corner of the wafer, and the alignment pattern of the at least one dummy pin is located in at least one of the wafer bonding regions. corner. The thin film flip chip package structure of claim 3, wherein the number of the at least one dummy bump is plural, and the dummy bumps are respectively located at four corners of the chip, the at least one dummy pin The number is a plurality of, and the alignment patterns of the dummy pins are respectively located at four corners of the wafer bonding area. The film flip-chip package structure according to claim 4, wherein the shape, the number, the arrangement, or any combination thereof of the alignment patterns at any two corners on the same side of the wafer bonding region are not the same. The thin film flip chip package structure of claim 3, wherein the number of the at least one dummy bump is plural, and the dummy bumps are respectively located at two corners on a diagonal of the wafer, the at least one The number of dummy pins is plural, and the alignment patterns of the dummy pins are respectively located at two corners on the diagonal of the wafer bonding region. The film flip-chip package structure according to claim 1, wherein an edge of each of the inner lead portions has a minimum distance D between the edges of the correspondingly connected bumps, and the gap G is between the gaps G The minimum distance D is between 1.6 and 2.4 times the minimum value D _min (1.6 D _min ≦ G ≦ 2.4 D _min ). The film flip chip package structure according to claim 1, wherein the alignment pattern is a non-closed pattern, and the non-closed pattern comprises a U-shaped pattern, a U-shaped pattern, a crossed pattern or a inverted fork. Shaped pattern. The film flip chip package structure according to claim 1, wherein the alignment pattern is a closed pattern, and the closed pattern comprises a dot pattern or a ring pattern. The thin film flip chip package structure of claim 1, wherein the at least one dummy bump does not contact the corresponding alignment pattern and the flexible substrate. The film flip chip package structure of claim 1, further comprising an encapsulant disposed between the flexible circuit carrier and the wafer, the encapsulant covering the leads of the pins a footprint, the alignment pattern of the at least one dummy pin, the bumps, and the at least one dummy bump.