TW201810571A - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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Publication number
TW201810571A
TW201810571A TW105142339A TW105142339A TW201810571A TW 201810571 A TW201810571 A TW 201810571A TW 105142339 A TW105142339 A TW 105142339A TW 105142339 A TW105142339 A TW 105142339A TW 201810571 A TW201810571 A TW 201810571A
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Taiwan
Prior art keywords
layer
fan
interconnecting member
semiconductor package
redistribution layer
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TW105142339A
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Chinese (zh)
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TWI737662B (en
Inventor
李斗煥
金宗立
金亨俊
金鎭栗
吳暻燮
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三星電機股份有限公司
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Publication of TWI737662B publication Critical patent/TWI737662B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.

Description

扇出型半導體封裝Fan-out type semiconductor package

本發明是有關於一種半導體封裝，且更具體而言，有關於一種連接端子可在安置有半導體晶片的區之外延伸的扇出型半導體封裝。The present invention relates to a semiconductor package, and more particularly to a fan-out type semiconductor package in which a connection terminal can extend beyond a region in which a semiconductor wafer is disposed.

近來，與半導體晶片相關的技術發展中的近期顯著趨勢是減小半導體晶片的尺寸。因此，在封裝技術領域中，隨著對小尺寸半導體晶片等的需求的快速增加，已經需要實作在包括多個引腳的同時具有緊湊的尺寸的半導體封裝。Recently, a recent significant trend in the development of technology related to semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers and the like, it has been required to implement a semiconductor package having a compact size while including a plurality of leads.

為滿足上述技術要求所建議的一種封裝技術是扇出型封裝。此種扇出型封裝藉由在安置有半導體晶片的區之外對連接端子進行重佈線而具有緊湊的尺寸且可達成對多個引腳的實作。One packaging technique suggested to meet the above technical requirements is a fan-out package. Such a fan-out type package has a compact size by rewiring a connection terminal outside a region in which a semiconductor wafer is placed, and an implementation of a plurality of pins can be achieved.

本發明的態樣可提供一種其板級可靠性（board level reliability）得以提高的扇出型半導體封裝。Aspects of the present invention can provide a fan-out type semiconductor package in which board level reliability is improved.

根據本發明的態樣，可提供一種扇出型半導體封裝，其中使用滿足某些條件的材料作為保護層的材料。According to an aspect of the present invention, a fan-out type semiconductor package in which a material satisfying certain conditions is used as a material of a protective layer can be provided.

根據本發明的態樣，一種扇出型半導體封裝可包括：第一互連構件，具有貫穿孔；半導體晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊；囊封體，囊封所述第一互連構件的至少某些部分及所述半導體晶片的所述被動表面的至少某些部分；第二互連構件，安置於所述第一互連構件上及所述半導體晶片的所述主動表面上；以及保護層，安置於所述第二互連構件上。所述第一互連構件及所述第二互連構件分別包括重佈線層，所述重佈線層電性連接至所述半導體晶片的所述連接墊，所述第二互連構件包括絕緣層，所述第二互連構件的所述重佈線層安置於所述絕緣層上，且所述保護層的彈性模數較所述第二互連構件的所述絕緣層的彈性模數大。According to an aspect of the present invention, a fan-out type semiconductor package may include: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface and a passive surface opposite the active surface, the active surface having a connection pad disposed thereon; an encapsulation encapsulating at least some portion of the first interconnect member and at least some of the passive surface of the semiconductor wafer And a second interconnecting member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; and a protective layer disposed on the second interconnecting member. The first interconnecting member and the second interconnecting member respectively comprise a redistribution layer electrically connected to the connection pad of the semiconductor wafer, the second interconnecting member comprising an insulating layer The redistribution layer of the second interconnecting member is disposed on the insulating layer, and a modulus of elasticity of the protective layer is greater than a modulus of elasticity of the insulating layer of the second interconnecting member.

根據本發明的另一態樣，一種扇出型半導體封裝可包括：第一互連構件，具有貫穿孔；半導體晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊；囊封體，囊封所述第一互連構件的至少某些部分及所述半導體晶片的所述被動表面的至少某些部分；第二互連構件，安置於所述第一互連構件上及所述半導體晶片的所述主動表面上；以及保護層，安置於所述第二互連構件上。所述第一互連構件及所述第二互連構件分別包括重佈線層，所述重佈線層電性連接至所述半導體晶片的所述連接墊，所述第二互連構件包括絕緣層，所述第二互連構件的所述重佈線層安置於所述絕緣層上，所述保護層及所述第二互連構件的所述絕緣層中的每一者包含無機填料及絕緣樹脂，且所述保護層中所包含的所述無機填料的重量百分比大於所述第二互連構件的所述絕緣層中所包含的所述無機填料的重量百分比。According to another aspect of the present invention, a fan-out type semiconductor package may include: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface And a passive surface opposite the active surface, the active surface having a connection pad disposed thereon; an encapsulation encapsulating at least some portions of the first interconnect member and the passive surface of the semiconductor wafer At least some portions; a second interconnecting member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; and a protective layer disposed on the second interconnecting member. The first interconnecting member and the second interconnecting member respectively comprise a redistribution layer electrically connected to the connection pad of the semiconductor wafer, the second interconnecting member comprising an insulating layer The redistribution layer of the second interconnecting member is disposed on the insulating layer, and each of the insulating layer and the insulating layer of the second interconnecting member comprises an inorganic filler and an insulating resin And the weight percentage of the inorganic filler contained in the protective layer is greater than the weight percentage of the inorganic filler contained in the insulating layer of the second interconnecting member.

在下文中，將參照附圖闡述本發明中的各示例性實施例。在所述附圖中，為清晰起見，可誇大或縮短各組件的形狀、尺寸等。Hereinafter, various exemplary embodiments of the present invention will be described with reference to the drawings. In the drawings, the shapes, dimensions, and the like of the various components may be exaggerated or shortened for clarity.

在說明中組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及兩個組件之間的直接連接。另外，「電性連接」意為包括實體連接及實體斷開的概念。應理解，當以「第一」及「第二」來指代元件時，所述元件並非由此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的，且可不限制所述元件的順序或重要性。在某些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。The meaning of "connected" to another component in the description includes an indirect connection via an adhesive layer and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It will be understood that when the elements are referred to as "first" and "second", the elements are not limited thereby. The use of "first" and "second" may be used only for the purpose of distinguishing the elements from the other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the scope of the invention as set forth herein. Similarly, the second element may also be referred to as a first element.

本文中所使用的用語「示例性實施例」並不指代同一示例性實施例，而是為強調與另一示例性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的示例性實施例被視為能夠藉由彼此整體地或部分地組合而實作。舉例而言，即使並未在另一示例性實施例中闡述在特定示例性實施例中闡述的一個元件，然而除非在本文中提供了相反或矛盾的說明，否則所述元件亦可被理解為與另一示例性實施例相關的說明。The term "exemplary embodiment" as used herein is not intended to refer to the same exemplary embodiment, but is provided to emphasize particular features or characteristics that are different from the specific features or characteristics of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be capable of being implemented in combination, in whole or in part, with each other. For example, even if an element set forth in a particular exemplary embodiment is not illustrated in another exemplary embodiment, the element may be understood as An explanation related to another exemplary embodiment.

使用本文中所使用的用語僅為了闡述示例性實施例而非限制本發明。在此種情形中，除非在上下文中另有解釋，否則單數形式包括複數形式。 電子裝置 The use of the terms used herein is merely illustrative of exemplary embodiments and not limiting of the invention. In this case, the singular forms include the plural unless the context dictates otherwise. Electronic device

圖1是說明電子裝置系統的實例的示意性方塊圖。FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

參照圖1，電子裝置1000中可容置有主板1010。主板1010可包括實體地連接至或電性地連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件，以形成各種訊號線1090。Referring to FIG. 1 , a motherboard 1010 can be housed in the electronic device 1000 . The motherboard 1010 can include a wafer related component 1020, a network related component 1030, other components 1040, etc. that are physically connected or electrically connected to the motherboard 1010. The components can be connected to other components as will be described below to form various signal lines 1090.

晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體（例如，動態隨機存取記憶體（dynamic random access memory，DRAM））、非揮發性記憶體（例如，唯讀記憶體（read only memory，ROM））、快閃記憶體等；應用處理器晶片，例如中央處理器（例如，中央處理單元（central processing unit，CPU））、圖形處理器（例如，圖形處理單元（graphic processing unit，GPU））、數位訊號處理器、密碼處理器（cryptographic processor）、微處理器、微控制器等；及邏輯晶片，例如類比至數位轉換器（analog-to-digital converter，ADC）、應用專用積體電路（application-specific integrated circuit，ASIC）等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。The wafer related component 1020 can include: a memory chip such as a volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (read only) Memory, ROM), flash memory, etc.; application processor chips, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (graphic processing unit) GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific products Application-specific integrated circuit (ASIC), etc. However, wafer related component 1020 is not limited thereto, but may include other types of wafer related components. Additionally, wafer related components 1020 can be combined with each other.

網路相關組件1030可包括例如以下協定：無線保真（wireless fidelity，Wi-Fi）（電氣及電子工程師學會（Institute of Electrical And Electronics Engineers，IEEE）802.11家族等）、全球互通微波存取（worldwide interoperability for microwave access，WiMAX）（IEEE 802.16家族等）、IEEE 802.20、長期演進（long term evolution，LTE）、僅支援資料的演進（evolution data only，Ev-DO）、高速封包存取+（high speed packet access +，HSPA+）、高速下行封包存取+（high speed downlink packet access +，HSDPA+）、高速上行封包存取+（high speed uplink packet access +，HSUPA+）、增強型資料GSM環境（enhanced data GSM environment，EDGE）、全球行動通訊系統（global system for mobile communications，GSM）、全球定位系統（global positioning system，GPS）、通用封包無線電服務（general packet radio service，GPRS）、分碼多重存取（code division multiple access，CDMA）、分時多重存取（time division multiple access，TDMA）、數位增強型無線電訊（digital enhanced cordless telecommunications，DECT）、藍芽、3G協定、4G協定、5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與上述晶片相關組件1020一起彼此組合。Network related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperability microwave access (worldwide) Interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access + (high speed Packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (enhanced data GSM) Environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code) Division multiple access, CDMA), Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G, and any other wireless agreement specified after the agreement And cable agreements. However, network related component 1030 is not limited thereto, but may also include a variety of other wireless standards or protocols or wired standards or protocols. Additionally, network related components 1030 can be combined with one another as described above with wafer related components 1020.

其他組件1040可包括高頻電感器、鐵氧體電感器（ferrite inductor）、功率電感器、鐵氧體珠粒、低溫共燒陶瓷（low temperature co-fired ceramic，LTCC）、電磁干擾（electromagnetic interference，EMI）濾波器、多層陶瓷電容器（multilayer ceramic capacitor，MLCC）等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。另外，其他組件1040可與上述晶片相關組件1020或網路相關組件1030一起彼此組合。Other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-fired ceramic (LTCC), and an electromagnetic interference. , EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components and the like for various other purposes. Additionally, other components 1040 can be combined with one another as described above with wafer related component 1020 or network related component 1030.

端視電子裝置1000的類型，電子裝置1000可包括可實體地連接至或電性地連接至主板1010或可不實體地連接至或不電性地連接至主板1010的其他組件。該些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器（圖中未示出）、視訊編解碼器（圖中未示出）、功率放大器（圖中未示出）、羅盤（圖中未示出）、加速度計（圖中未示出）、陀螺儀（圖中未示出）、揚聲器（圖中未示出）、大容量儲存單元（例如硬碟驅動機）（圖中未示出）、光碟（compact disk，CD）驅動機（圖中未示出）、數位多功能光碟（digital versatile disk，DVD）驅動機（圖中未示出）等。然而，該些其他組件並非僅限於此，而是端視電子裝置1000等的類型亦可包括用於各種目的的其他組件。Depending on the type of electronic device 1000, the electronic device 1000 can include other components that can be physically connected or electrically connected to the motherboard 1010 or that can be physically connected or not electrically connected to the motherboard 1010. The other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (figure Not shown), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (eg A hard disk drive (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown) Wait. However, the other components are not limited thereto, but the types of the end-view electronic device 1000 and the like may also include other components for various purposes.

電子裝置1000可為智慧型電話、個人數位助理（personal digital assistant，PDA）、數位攝影機、數位照相機（digital still camera）、網路系統、電腦、監視器、平板個人電腦（tablet PC）、膝上型個人電腦、隨身型易網機個人電腦（netbook PC）、電視、視訊遊戲機（video game machine）、智慧型手錶、汽車組件等。然而，電子裝置1000並非僅限於此，且可為處理資料的任何其他電子裝置。The electronic device 1000 can be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop. Personal computer, portable Internet computer (netbook PC), TV, video game machine, smart watch, car components, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

圖2是說明電子裝置的實例的示意性立體圖。FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

參照圖2，半導體封裝可出於各種目的而在如上所述的各種電子裝置1000中使用。舉例而言，主板1110可容置於智慧型電話1100的主體1101中，且各種電子組件1120可實體地連接至或電性地連接至主板1110。另外，可實體地連接至或電性地連接至主板1110或可不實體地連接至或不電性地連接至主板1110的其他組件（例如照相機模組1130）可容置於主體1101中。電子組件1120中的某些電子組件可為晶片相關組件，且半導體封裝100可例如為晶片相關組件中的應用處理器，但並非僅限於此。所述電子裝置不必僅限於智慧型電話1100，而是可為如上所述其他電子裝置。 半導體封裝 Referring to FIG. 2, a semiconductor package can be used in various electronic devices 1000 as described above for various purposes. For example, the main board 1110 can be housed in the main body 1101 of the smart phone 1100, and the various electronic components 1120 can be physically connected or electrically connected to the main board 1110. Additionally, other components (eg, camera module 1130) that may be physically connected or electrically connected to the main board 1110 or that may not be physically connected or electrically connected to the main board 1110 may be housed in the main body 1101. Some of the electronic components in the electronic component 1120 can be wafer related components, and the semiconductor package 100 can be, for example, an application processor in a wafer related component, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

一般而言，在半導體晶片中整合有諸多精細的電路。然而，半導體晶片本身無法用作完成的半導體產品，且可因外部物理衝擊或化學衝擊而被損壞。因此，半導體晶片無法單獨使用，而是可被封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。In general, many fine circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot be used as a completed semiconductor product and can be damaged by external physical impact or chemical shock. Therefore, the semiconductor wafer cannot be used alone, but can be packaged in an electronic device or the like and used in a package state in an electronic device or the like.

此處，由於在電性連接方面，半導體晶片與電子裝置的主板之間存在電路寬度差，因此需要進行半導體封裝。詳言之，半導體晶片的連接墊的尺寸及半導體晶片的各連接墊之間的間隔是非常精細的，但在電子裝置中使用的主板的組件安裝墊的尺寸及主板的各組件安裝墊之間的間隔顯著地大於半導體晶片的連接墊的尺寸及各連接墊之間的間隔。因此，可能難以將半導體晶片直接安裝於主板上，且需要用於緩衝半導體晶片與主板之間的電路寬度差的封裝技術。Here, since there is a circuit width difference between the semiconductor wafer and the main board of the electronic device in terms of electrical connection, it is necessary to perform semiconductor packaging. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are very fine, but the size of the component mounting pads of the motherboard used in the electronic device and the mounting pads of the components of the motherboard The spacing is significantly greater than the size of the connection pads of the semiconductor wafer and the spacing between the connection pads. Therefore, it may be difficult to mount the semiconductor wafer directly on the main board, and a packaging technique for buffering a circuit width difference between the semiconductor wafer and the main board is required.

端視半導體封裝的結構及目的，由封裝技術製造的半導體封裝可被分類成扇入型半導體封裝或扇出型半導體封裝。Depending on the structure and purpose of the semiconductor package, the semiconductor package fabricated by the package technology can be classified into a fan-in type semiconductor package or a fan-out type semiconductor package.

將在下文中參照圖式更詳細地闡述所述扇入型半導體封裝及所述扇出型半導體封裝。 扇入型 半導體封裝 The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings. Fan-in semiconductor package

圖3A及圖3B是說明扇入型半導體封裝在被封裝之前及被封裝之後的狀態的示意性剖視圖。3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before being packaged and after being packaged.

圖4是說明扇入型半導體封裝的封裝製程的示意性剖視圖。4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package.

參照所述圖式，半導體晶片2220可為例如處於裸露狀態下的積體電路（integrated circuit，IC），半導體晶片2220包括：主體2221，包含矽（Si）、鍺（Ge）、砷化鎵（GaAs）等；連接墊2222，形成於主體2221的一個表面上且包含例如鋁（Al）等導電材料；以及保護層2223，其例如是氧化物膜、氮化物膜等，且形成於主體2221的一個表面上且覆蓋連接墊2222的至少某些部分。在此種情形中，由於連接墊2222是顯著小的，因此難以將積體電路（IC）安裝於中級印刷電路板（printed circuit board，PCB）上以及電子裝置的主板上等。Referring to the drawing, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, and the semiconductor wafer 2220 includes a body 2221 including germanium (Si), germanium (Ge), gallium arsenide ( GaAs) or the like; a connection pad 2222 formed on one surface of the main body 2221 and containing a conductive material such as aluminum (Al); and a protective layer 2223 which is, for example, an oxide film, a nitride film, or the like, and formed on the main body 2221. At least some portions of the surface of the connection pad 2222 are covered on one surface. In this case, since the connection pad 2222 is remarkably small, it is difficult to mount an integrated circuit (IC) on a printed circuit board (PCB) and a main board of an electronic device or the like.

因此，可端視半導體晶片2220的尺寸而在半導體晶片2220上形成互連構件2240，以對連接墊2222進行重佈線。可藉由以下步驟來形成互連構件2240：利用例如感光成像介電（photoimagable dielectric，PID）樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241；形成敞開連接墊2222的介層窗孔2243h；且接著形成配線圖案2242及介層窗2243。接著，可形成保護互連構件2240的保護層2250、可形成開口2251及可形成凸塊下金屬層2260等。亦即，可藉由一系列製程來製造包括例如半導體晶片2220、互連構件2240、保護層2250、及凸塊下金屬層2260的扇入型半導體封裝2200。Accordingly, the interconnect member 2240 can be formed on the semiconductor wafer 2220 by looking at the size of the semiconductor wafer 2220 to rewire the connection pads 2222. The interconnection member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 by using an insulating material such as a photoimageable dielectric (PID) resin; forming a via hole 2243h of the open connection pad 2222; Then, the wiring pattern 2242 and the via 2243 are formed. Next, a protective layer 2250 that protects the interconnect member 2240, an opening 2251, a bump under metal layer 2260, and the like may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the interconnecting member 2240, the protective layer 2250, and the under bump metal layer 2260 can be fabricated by a series of processes.

如上所述，所述扇入型半導體封裝可具有所述半導體晶片的例如輸入/輸出（input/output，I/O）端子等所有的連接墊均安置於所述半導體晶片內的封裝形式，且可具有極佳的電性特性且以低成本進行生產。因此，已以扇入型半導體封裝形式製造出安裝於智慧型電話中的諸多元件。詳言之，已開發出安裝於智慧型電話中的諸多元件以在具有緊湊尺寸的同時實作快速訊號轉移。As described above, the fan-in type semiconductor package may have a package form in which all of the connection pads of the semiconductor wafer, such as input/output (I/O) terminals, are disposed in the semiconductor wafer, and It can have excellent electrical properties and can be produced at low cost. Therefore, many components mounted in a smart phone have been manufactured in a fan-in type semiconductor package. In particular, many components installed in smart phones have been developed to implement fast signal transfer while having a compact size.

然而，由於所有的輸入/輸出端子均需要安置於扇入型半導體封裝中的半導體晶片內，因此，扇入型半導體封裝具有大的空間限制。因此，難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有緊湊尺寸的半導體晶片。另外，由於上述缺點，扇入型半導體封裝無法在電子裝置的主板上直接安裝及使用。原因在於即使在藉由重佈線製程增大了半導體晶片的輸入/輸出端子的尺寸及半導體晶片的各輸入/輸出端子之間的間隔的情形中，半導體晶片的輸入/輸出端子的尺寸及半導體晶片的各輸入/輸出端子之間的間隔可能仍不足以將扇入型半導體封裝直接安裝於電子裝置的主板上。However, since all of the input/output terminals need to be disposed in a semiconductor wafer in a fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, the fan-in type semiconductor package cannot be directly mounted and used on the main board of the electronic device. The reason is that the size of the input/output terminal of the semiconductor wafer and the semiconductor wafer even in the case where the size of the input/output terminal of the semiconductor wafer and the interval between the respective input/output terminals of the semiconductor wafer are increased by the rewiring process The spacing between the various input/output terminals may still be insufficient to mount the fan-in type semiconductor package directly on the motherboard of the electronic device.

圖5是說明扇入型半導體封裝安裝於插入式基板上且最終安裝於電子裝置的主板上的情形的示意性剖視圖。5 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device.

圖6是說明扇入型半導體封裝嵌於插入式基板中且最終安裝於電子裝置的主板上的情形的示意性剖視圖。6 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device.

參照所述圖式，在扇入型半導體封裝2200中，半導體晶片2220的連接墊2222（即，輸入/輸出端子）可經由插入式基板2301進行重佈線，且扇入型半導體封裝2200可在扇入型半導體封裝2200安裝於插入式基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此種情形中，可藉由底部填充樹脂2280等來固定焊料球2270等，且半導體晶片2220的外側可被覆蓋以模製材料2290等。作為另外一種選擇，扇入型半導體封裝2200可嵌於單獨的插入式基板2302中，半導體晶片2220的連接墊2222（即，輸入/輸出端子）可在扇入型半導體封裝2200嵌於插入式基板2302中的狀態下藉由插入式基板2302進行重佈線，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。Referring to the drawings, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input/output terminals) of the semiconductor wafer 2220 can be re-routed via the interposer substrate 2301, and the fan-in type semiconductor package 2200 can be in the fan. The in-type semiconductor package 2200 is finally mounted on the main board 2500 of the electronic device in a state of being mounted on the interposer substrate 2301. In this case, the solder ball 2270 or the like may be fixed by the underfill resin 2280 or the like, and the outer side of the semiconductor wafer 2220 may be covered with the molding material 2290 or the like. Alternatively, the fan-in type semiconductor package 2200 can be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input/output terminals) of the semiconductor wafer 2220 can be embedded in the interposer substrate in the fan-in type semiconductor package 2200. In the state of 2302, rewiring is performed by the interposer substrate 2302, and the fan-in type semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

如上所述，可能難以在電子裝置的主板上直接安裝並使用扇入型半導體封裝。因此，扇入型半導體封裝可安裝於單獨的插入式基板上且接著藉由封裝製程安裝於電子裝置的主板上，或者可在其中扇入型半導體封裝嵌於插入式基板中的狀態下在電子裝置的主板上安裝及使用。 扇出型 半導體封裝 As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device by a packaging process, or in a state in which the fan-in type semiconductor package is embedded in the interposer substrate. Install and use on the motherboard of the device. Fan-out type semiconductor package

圖7是說明扇出型半導體封裝的示意性剖視圖。Fig. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

參照所述圖式，在扇出型半導體封裝2100中，舉例而言，半導體晶片2120的外側可被囊封體2130保護，且半導體晶片2120的連接墊2122可藉由互連構件2140而在半導體晶片2120之外進行重佈線。在此種情形中，在互連構件2140上可進一步形成保護層2150，且在保護層2150的開口中可進一步形成凸塊下金屬層2160。在凸塊下金屬層2160上可進一步形成焊料球2170。半導體晶片2120可為包括主體2121、連接墊2122、保護層（圖中未示出）等的積體電路（IC）。互連構件2140可包括絕緣層2141、形成於絕緣層2141上的重佈線層2142以及將連接墊2122與重佈線層2142電性連接至彼此的介層窗2143。Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outer side of the semiconductor wafer 2120 may be protected by the encapsulation 2130, and the connection pads 2122 of the semiconductor wafer 2120 may be in the semiconductor by the interconnecting member 2140. Rewiring is performed outside the wafer 2120. In this case, the protective layer 2150 may be further formed on the interconnect member 2140, and the under bump metal layer 2160 may be further formed in the opening of the protective layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a main body 2121, a connection pad 2122, a protective layer (not shown), and the like. The interconnecting member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

如上所述，所述扇出型半導體封裝可具有半導體晶片的輸入/輸出端子藉由形成於所述半導體晶片上的互連構件而在所述半導體晶片之外進行重佈線並安置於所述半導體晶片之外的形式。如上所述，在扇入型半導體封裝中，半導體晶片的所有輸入/輸出端子均需要安置於半導體晶片內。因此，當半導體晶片的尺寸減小時，需要減小球的尺寸及節距，進而使得可能無法在扇入型半導體封裝中使用標準化球佈局。另一方面，所述扇出型半導體封裝具有半導體晶片的輸入/輸出端子如上所述藉由形成於半導體晶片上的互連構件而在半導體晶片之外進行重佈線並安置於半導體晶片之外的形式。因此，即使在半導體晶片的尺寸減小的情形中，實際上仍可在扇出型半導體封裝中使用標準化球佈局，進而使得所述扇出型半導體封裝可在不使用單獨的插入式基板的條件下安裝於電子裝置的主板上，如以下所闡述。As described above, the fan-out type semiconductor package may have an input/output terminal of a semiconductor wafer re-wiring outside the semiconductor wafer and disposed on the semiconductor by an interconnection member formed on the semiconductor wafer A form other than a wafer. As described above, in the fan-in type semiconductor package, all of the input/output terminals of the semiconductor wafer need to be disposed in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, thereby making it impossible to use a standardized ball layout in the fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has an input/output terminal of a semiconductor wafer which is rewired outside the semiconductor wafer and disposed outside the semiconductor wafer by an interconnection member formed on the semiconductor wafer as described above. form. Therefore, even in the case where the size of the semiconductor wafer is reduced, a standardized ball layout can be actually used in the fan-out type semiconductor package, thereby making the fan-out type semiconductor package available without using a separate interposer substrate. It is mounted on the main board of the electronic device as explained below.

圖8是說明扇出型半導體封裝安裝於電子裝置的主板上的情形的示意性剖視圖。8 is a schematic cross-sectional view illustrating a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

參照所述圖式，扇出型半導體封裝2100可藉由焊料球2170等安裝於電子裝置的主板2500上。亦即，如上所述，扇出型半導體封裝2100包括互連構件2140，互連構件2140形成於半導體晶片2120上且能夠將連接墊2122重佈線至半導體晶片2120的尺寸外的扇出區，進而使得實際上可在扇出型半導體封裝2100中使用標準化球佈局。因此，扇出型半導體封裝2100可在不使用單獨的插入式基板等的條件下安裝於電子裝置的主板2500上。Referring to the drawing, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device by solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the interconnecting member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to the fan-out area outside the size of the semiconductor wafer 2120, thereby This makes it possible to actually use a standardized ball layout in the fan-out type semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate or the like.

如上所述，由於所述扇出型半導體封裝可在不使用單獨的插入式基板的條件下安裝於電子裝置的主板上，因此所述扇出型半導體封裝可以較使用插入式基板的扇入型半導體封裝的厚度小的厚度來實作。因此，所述扇出型半導體封裝可被微型化及薄化。另外，所述扇出型半導體封裝具有極佳的熱特性及電性特性，進而使得所述扇出型半導體封裝尤其適合用於行動產品。因此，比起使用印刷電路板（PCB）的通用堆疊封裝（package-on-package，POP）型的形式，所述扇出型半導體封裝可被實作成更為緊密的形式，且可解決因出現翹曲（warpage）現象而產生的問題。As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the fan-out type semiconductor package can be more fan-in type than the interposer type substrate. The thickness of the semiconductor package is small and the thickness is implemented. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal characteristics and electrical characteristics, which in turn makes the fan-out type semiconductor package particularly suitable for use in mobile products. Therefore, the fan-out type semiconductor package can be implemented in a more compact form than in the form of a package-on-package (POP) type using a printed circuit board (PCB), and can be solved due to appearance. The problem caused by the warpage phenomenon.

同時，所述扇出型半導體封裝指代用於上述將半導體晶片安裝於電子裝置等的主板上且保護所述半導體晶片不受外部衝擊的封裝技術，且所述扇出型半導體封裝是與具有與扇出型半導體封裝的規模、目的等不同的規模、目的等的印刷電路板（PCB）（例如插入式基板等）的概念不同的概念，且所述印刷電路板中嵌置有扇入型半導體封裝。Meanwhile, the fan-out type semiconductor package refers to a packaging technology for mounting the semiconductor wafer on a main board of an electronic device or the like and protecting the semiconductor wafer from external impact, and the fan-out type semiconductor package has and A concept of a printed circuit board (PCB) (for example, a plug-in substrate) having different scales and purposes such as the size and purpose of the fan-out type semiconductor package, and a fan-in type semiconductor is embedded in the printed circuit board Package.

在下文中將參照圖式闡述可靠性得以提高的扇出型半導體封裝。A fan-out type semiconductor package in which reliability is improved will be described hereinafter with reference to the drawings.

圖9是說明扇出型半導體封裝的實例的示意性剖視圖。9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

圖10是沿圖9所示的扇出型半導體封裝的線I-I’截取的示意性平面圖。Figure 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package shown in Figure 9.

參照所述圖式，根據本發明中的示例性實施例的扇出型半導體封裝100A可包括：第一互連構件110，具有貫穿孔110H；半導體晶片120，安置於第一互連構件110的貫穿孔110H中且具有主動表面及與所述主動表面相對的被動表面，在所述主動表面上安置有連接墊122；囊封體130，囊封第一互連構件110的至少某些部分及半導體晶片120的被動表面的至少某些部分；第二互連構件140，安置於第一互連構件110上及半導體晶片120的主動表面上；保護層150，安置於第二互連構件140上；凸塊下金屬層160，形成於保護層150的開口151中；以及連接端子170，形成於凸塊下金屬層160上。在此種情形中，保護層150的彈性模數可較第二互連構件140的絕緣層141的彈性模數大。在保護層150及第二互連構件140的絕緣層141中的每一者包含無機填料及絕緣樹脂的情形中，保護層150中所包含的無機填料的重量百分比可大於第二互連構件140的絕緣層141中所包含的無機填料的重量百分比。Referring to the drawings, the fan-out type semiconductor package 100A according to an exemplary embodiment of the present invention may include: a first interconnecting member 110 having a through hole 110H; and a semiconductor wafer 120 disposed at the first interconnecting member 110 In the through hole 110H and having an active surface and a passive surface opposite to the active surface, a connection pad 122 is disposed on the active surface; an encapsulation body 130 encapsulating at least some portions of the first interconnection member 110 and At least some portions of the passive surface of the semiconductor wafer 120; a second interconnecting member 140 disposed on the first interconnecting member 110 and on the active surface of the semiconductor wafer 120; and a protective layer 150 disposed on the second interconnecting member 140 The under bump metal layer 160 is formed in the opening 151 of the protective layer 150; and the connection terminal 170 is formed on the under bump metal layer 160. In this case, the elastic modulus of the protective layer 150 may be larger than the elastic modulus of the insulating layer 141 of the second interconnecting member 140. In the case where each of the insulating layer 141 of the protective layer 150 and the second interconnecting member 140 includes an inorganic filler and an insulating resin, the weight percentage of the inorganic filler contained in the protective layer 150 may be greater than that of the second interconnecting member 140 The weight percentage of the inorganic filler contained in the insulating layer 141.

近來與半導體封裝相關的主要問題是當上述半導體封裝安裝於電子裝置的主板上時，半導體封裝是否具有足夠的可靠性。亦即，已進行了諸多努力來確保介層窗與半導體晶片的連接墊的匹配可靠性及連接至連接墊的重佈線層的連接可靠性。一般而言，所述半導體封裝更包括形成於重佈線層的外表面上的保護層。在此種情形中，使用物理性質與重佈線層的絕緣層的材料（即，感光性樹脂）的物理性質相似的阻焊劑作為保護層的材料。然而，在此種情形中，當半導體封裝安裝於電子裝置的主板上時，應力自主板原樣地轉移至半導體封裝，且因此難以確保上述可靠性。A major problem recently associated with semiconductor packaging is whether the semiconductor package has sufficient reliability when the above semiconductor package is mounted on a main board of an electronic device. That is, many efforts have been made to ensure the matching reliability of the connection pads of the via and the semiconductor wafer and the connection reliability of the redistribution layer connected to the connection pads. In general, the semiconductor package further includes a protective layer formed on an outer surface of the redistribution layer. In this case, a solder resist having physical properties similar to those of the material of the insulating layer of the redistribution layer (i.e., photosensitive resin) is used as the material of the protective layer. However, in this case, when the semiconductor package is mounted on the main board of the electronic device, the stress independent board is transferred as it is to the semiconductor package, and thus it is difficult to ensure the above reliability.

另一方面，在根據示例性實施例的扇出型半導體封裝100A中，可使用滿足某些條件的材料作為保護層150的材料，且因此可容易地確保上述可靠性。詳言之，保護層150的彈性模數可較第二互連構件140的絕緣層141的彈性模數大，且因此施加至保護層150的應力可增大。在應力集中於保護層150上而非絕緣層141上的情形中，可容易地確保在絕緣層141的可靠性可能成問題的區C中的可靠性，區域C例如為以下部分：介層窗143結合至半導體晶片的連接墊的部分、重佈線層142結合至絕緣層141的部分等。彈性模數被定義為應力與變形之間的比率，且可藉由在例如JIS C-6481、KS M 3001、KS M 527-3、ASTM D882等中所規定的標準拉伸試驗（standard tension test）而量測。在保護層150及第二互連構件140的絕緣層141中的每一者均包含無機填料及絕緣樹脂的情形中，保護層150中所包含的無機填料的重量百分比可大於第二互連構件140的絕緣層141中所包含的無機填料的重量百分比。在此種情形中，施加至保護層150的應力亦可增大，且可容易地確保可靠性。On the other hand, in the fan-out type semiconductor package 100A according to the exemplary embodiment, a material satisfying certain conditions can be used as the material of the protective layer 150, and thus the above reliability can be easily ensured. In detail, the elastic modulus of the protective layer 150 may be larger than the elastic modulus of the insulating layer 141 of the second interconnecting member 140, and thus the stress applied to the protective layer 150 may increase. In the case where stress is concentrated on the protective layer 150 instead of the insulating layer 141, reliability in the region C where the reliability of the insulating layer 141 may be problematic can be easily ensured, and the region C is, for example, the following portion: via window 143 is bonded to a portion of the connection pad of the semiconductor wafer, a portion where the redistribution layer 142 is bonded to the insulating layer 141, and the like. The elastic modulus is defined as the ratio between stress and deformation, and can be determined by a standard tensile test as specified in, for example, JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, and the like. ) and measure. In the case where each of the insulating layer 150 of the protective layer 150 and the second interconnecting member 140 contains an inorganic filler and an insulating resin, the weight percentage of the inorganic filler contained in the protective layer 150 may be greater than that of the second interconnecting member The weight percentage of the inorganic filler contained in the insulating layer 141 of 140. In this case, the stress applied to the protective layer 150 can also be increased, and reliability can be easily ensured.

同時，保護層150的厚度t2可為10微米或大於10微米，例如約10微米至30微米。在保護層150的厚度t2增大時，施加至保護層150的應力可減小，其中由主板產生的應力主要經由連接端子170而轉移至保護層150。另外，抗裂性（crack resistance）可提高。亦即，在保護層150的厚度t2為10微米或大於10微米的情形中，可確保具有提高的可靠性。為了集中應力，保護層150的厚度t2可大於第二互連構件140的絕緣層141的厚度t1。厚度t2指代保護層150在硬化之後的厚度，且可利用通用厚度量測設備而量測。Meanwhile, the thickness t2 of the protective layer 150 may be 10 micrometers or more, such as about 10 micrometers to 30 micrometers. When the thickness t2 of the protective layer 150 is increased, the stress applied to the protective layer 150 may be reduced, wherein stress generated by the main board is mainly transferred to the protective layer 150 via the connection terminal 170. In addition, the crack resistance can be improved. That is, in the case where the thickness t2 of the protective layer 150 is 10 μm or more, it is ensured that the reliability is improved. In order to concentrate the stress, the thickness t2 of the protective layer 150 may be greater than the thickness t1 of the insulating layer 141 of the second interconnecting member 140. The thickness t2 refers to the thickness of the protective layer 150 after hardening, and can be measured using a general thickness measuring device.

另外，保護層150的表面粗糙度Ra可為1奈米或大於1奈米，例如約1奈米至1000奈米。在最外層處形成的第二互連構件140的重佈線層142可接觸保護層150。在此種情形中，當保護層150的表面粗糙度Ra為至少1奈米或大於1奈米時，保護層150與重佈線層142之間的緊密黏合可足以減小施加至保護層150的應力。另外，可防止初始破裂的產生。亦即，在保護層150的表面粗糙度Ra為1奈米或大於1奈米的情形中，同樣可確保具有提高的可靠性。在保護層150的厚度t2為10微米或大於10微米的情形中，可確保具有提高的可靠性。所述表面粗糙度可藉由例如使用立方氧化鋯（cubic zirconia，CZ）進行的表面處理等習知方法而形成。然而，保護層150的所有表面未必均需要具有此表面粗糙度，且保護層150的與第二互連構件140的重佈線層142接觸的表面具有此表面粗糙度便可足夠。所述表面粗糙度亦可利用通用粗糙度量測設備而量測。In addition, the surface roughness Ra of the protective layer 150 may be 1 nm or more, such as about 1 nm to 1000 nm. The redistribution layer 142 of the second interconnecting member 140 formed at the outermost layer may contact the protective layer 150. In this case, when the surface roughness Ra of the protective layer 150 is at least 1 nm or more than 1 nm, the close adhesion between the protective layer 150 and the redistribution layer 142 may be sufficient to reduce the application to the protective layer 150. stress. In addition, the occurrence of initial cracking can be prevented. That is, in the case where the surface roughness Ra of the protective layer 150 is 1 nm or more, it is also ensured that the reliability is improved. In the case where the thickness t2 of the protective layer 150 is 10 μm or more, it is ensured that the reliability is improved. The surface roughness can be formed by a conventional method such as surface treatment using cubic zirconia (CZ). However, it is not necessary for all surfaces of the protective layer 150 to have such surface roughness, and it may be sufficient that the surface of the protective layer 150 that is in contact with the redistribution layer 142 of the second interconnecting member 140 has this surface roughness. The surface roughness can also be measured using a universal roughness measuring device.

另外，保護層150的吸水率可為1.5%或小於1.5%，例如約0.5%至1.5%。當在扇出型半導體封裝100A的最外部分處形成的保護層150的吸水率變得更低時，可有效地防止水等滲透至扇出型半導體封裝100A中，從而防止扇出型半導體封裝100A中的組件之間的緊密黏合的降低。另外，亦可防止絕緣層141、保護層150等的物理性質的降低。此外，亦可有效地防止在扇出型半導體封裝100A中的組件中產生介面蒸汽壓力（interface vapor pressure）。亦即，在保護層150的吸水率為1.5%或小於1.5%的情形中，同樣可確保具有提高的可靠性。在保護層150的厚度為10微米或大於10微米且保護層150的表面粗糙度為1奈米或大於1奈米的情形中以及在保護層150的吸水率為1.5%或小於1.5%的情形中，可確保具有提高的可靠性。所述吸水率可藉由習知方法而量測。In addition, the water absorption of the protective layer 150 may be 1.5% or less, for example, about 0.5% to 1.5%. When the water absorption rate of the protective layer 150 formed at the outermost portion of the fan-out type semiconductor package 100A becomes lower, water or the like can be effectively prevented from penetrating into the fan-out type semiconductor package 100A, thereby preventing the fan-out type semiconductor package A reduction in the tight bond between the components in 100A. In addition, it is also possible to prevent a decrease in physical properties of the insulating layer 141, the protective layer 150, and the like. Further, it is also possible to effectively prevent the interface vapor pressure from being generated in the components in the fan-out type semiconductor package 100A. That is, in the case where the water absorption rate of the protective layer 150 is 1.5% or less, it is also ensured that the reliability is improved. In the case where the thickness of the protective layer 150 is 10 μm or more and the surface roughness of the protective layer 150 is 1 nm or more, and the water absorption rate of the protective layer 150 is 1.5% or less. In order to ensure improved reliability. The water absorption can be measured by a conventional method.

另外，藉由將保護層150的彈性模數乘以熱膨脹係數（coefficient of thermal expansion，CTE）而獲得的值可為230 GPa·ppm/°C或小於230 GPa·ppm/°C，例如約130 GPa·ppm/°C至230 GPa·ppm/°C。當藉由將保護層150的彈性模數乘以熱膨脹係數而獲得的值變得更大時，施加至保護層150的應力可增大。所述熱膨脹係數可使用熱機械分析儀（thermo-mechanical analyzer，TMA）、動態機械分析儀（dynamic mechanical analyzer，DMA）等而量測。In addition, the value obtained by multiplying the elastic modulus of the protective layer 150 by the coefficient of thermal expansion (CTE) may be 230 GPa·ppm/° C. or less than 230 GPa·ppm/° C., for example, about 130. GPa·ppm/°C to 230 GPa·ppm/°C. When the value obtained by multiplying the elastic modulus of the protective layer 150 by the thermal expansion coefficient becomes larger, the stress applied to the protective layer 150 can be increased. The coefficient of thermal expansion can be measured using a thermo-mechanical analyzer (TMA), a dynamic mechanical analyzer (DMA), or the like.

以下將在下文中更詳細地闡述根據示例性實施例的包含於扇出型半導體封裝100A中的相應組件。The respective components included in the fan-out type semiconductor package 100A according to an exemplary embodiment will be explained in more detail below.

第一互連構件110可包括對半導體晶片120的連接墊122進行重佈線以因此減少第二互連構件140的層的數目的重佈線層112a及重佈線層112b。視需要，第一互連構件110可端視某些材料而維持扇出型半導體封裝100A的剛性，並用於確保囊封體130的厚度的均勻度。在某些情形中，根據示例性實施例的扇出型半導體封裝100A歸因於第一互連構件110可用作堆疊封裝的一部分。第一互連構件110可具有貫穿孔110H。貫穿孔110H中可安置有半導體晶片120，以與第一互連構件110間隔開預定距離。半導體晶片120的側表面可被第一互連構件110環繞。然而，該種形式僅為實例且可進行各種修改以具有其他形式，且扇出型半導體封裝100A可端視該種形式而執行另一功能。The first interconnecting member 110 may include a redistribution layer 112a and a redistribution layer 112b that rewire the connection pads 122 of the semiconductor wafer 120 to thereby reduce the number of layers of the second interconnecting member 140. The first interconnecting member 110 may maintain the rigidity of the fan-out type semiconductor package 100A depending on certain materials, as needed, and serve to ensure uniformity of the thickness of the encapsulant 130. In some cases, the fan-out type semiconductor package 100A according to an exemplary embodiment may be used as part of a stacked package due to the first interconnect member 110. The first interconnecting member 110 may have a through hole 110H. A semiconductor wafer 120 may be disposed in the through hole 110H to be spaced apart from the first interconnecting member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 may be surrounded by the first interconnecting member 110. However, this form is merely an example and various modifications can be made to have other forms, and the fan-out type semiconductor package 100A can perform another function by looking at this form.

第一互連構件110可包括：絕緣層111，接觸第二互連構件140；第一重佈線層112a，接觸第二互連構件140且嵌於絕緣層111中；以及第二重佈線層112b，安置於絕緣層111的與嵌有第一重佈線層112a的絕緣層111的一個表面相對的另一表面上。第一互連構件110可包括穿透過絕緣層111並將第一重佈線層112a與第二重佈線層112b電性連接至彼此的介層窗113。第一重佈線層112a及第二重佈線層112b可電性連接至連接墊122。當第一重佈線層112a嵌於絕緣層111中時，可顯著地減少因第一重佈線層112a的厚度而產生的台階部分，且第二互連構件140的絕緣距離可因此變為恆定的。亦即，自第二互連構件140的重佈線層142至絕緣層111的下表面的距離與自第二互連構件140的重佈線層142至連接墊122的距離之差可小於第一重佈線層112a的厚度。因此，第二互連構件140的高密度配線設計可為容易的。The first interconnecting member 110 may include: an insulating layer 111 contacting the second interconnecting member 140; a first redistribution layer 112a contacting the second interconnecting member 140 and embedded in the insulating layer 111; and a second redistribution layer 112b It is disposed on the other surface of the insulating layer 111 opposite to one surface of the insulating layer 111 in which the first redistribution layer 112a is embedded. The first interconnecting member 110 may include a via 113 that penetrates through the insulating layer 111 and electrically connects the first redistribution layer 112a and the second redistribution layer 112b to each other. The first redistribution layer 112a and the second redistribution layer 112b may be electrically connected to the connection pads 122. When the first redistribution layer 112a is embedded in the insulating layer 111, the step portion due to the thickness of the first redistribution layer 112a can be remarkably reduced, and the insulation distance of the second interconnection member 140 can thus become constant . That is, the difference between the distance from the redistribution layer 142 of the second interconnecting member 140 to the lower surface of the insulating layer 111 and the distance from the redistribution layer 142 of the second interconnecting member 140 to the connection pad 122 may be less than the first weight. The thickness of the wiring layer 112a. Therefore, the high density wiring design of the second interconnecting member 140 can be easy.

絕緣層111的材料不受特別限制。舉例而言，可使用絕緣材料作為絕緣層111的材料。在此種情形中，所述絕緣材料可為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；將熱固性樹脂或熱塑性樹脂與無機填料一起浸入於例如玻璃布（或玻璃纖維）等核心材料中的樹脂，例如預浸體（prepreg）、味之素構成膜（Ajinomoto Build up Film，ABF）、FR-4、雙馬來醯亞胺三嗪（Bismaleimide Triazine，BT）等。作為另外一種選擇，亦可使用感光成像介電（PID）樹脂作為所述絕緣材料。The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer 111. In this case, the insulating material may be: a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; and a thermosetting resin or a thermoplastic resin together with an inorganic filler such as glass cloth (or glass fiber) The resin in the core material, for example, a prepreg, an Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a photosensitive dielectric (PID) resin may be used as the insulating material.

重佈線層112a及重佈線層112b可用於對半導體晶片120的連接墊122進行重佈線。重佈線層112a及重佈線層112b中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。重佈線層112a及重佈線層112b可端視其對應層的設計而執行各種功能。舉例而言，重佈線層112a及重佈線層112b可包括接地（ground，GND）圖案、功率（power，PWR）圖案、訊號（signal，S）圖案等。此處，訊號（S）圖案可包括除接地（GND）圖案、功率（PWR）圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層112a及重佈線層112b可包括介層窗墊、連接端子墊等。作為非限制性實例，重佈線層112a及重佈線層112b二者均可包括接地圖案。在此種情形中，可顯著地減少在第二互連構件140的重佈線層142上形成的接地圖案的數目，進而使得配線設計自由度可得以提高。The redistribution layer 112a and the redistribution layer 112b can be used to rewire the connection pads 122 of the semiconductor wafer 120. The material of each of the redistribution layer 112a and the redistribution layer 112b may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead. A conductive material such as (Pb), titanium (Ti) or an alloy thereof. The redistribution layer 112a and the redistribution layer 112b can perform various functions depending on the design of their corresponding layers. For example, the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the redistribution layer 112a and the redistribution layer 112b may include a via window pad, a connection terminal pad, and the like. As a non-limiting example, both the redistribution layer 112a and the redistribution layer 112b may include a ground pattern. In this case, the number of ground patterns formed on the redistribution layer 142 of the second interconnecting member 140 can be remarkably reduced, so that the degree of freedom in wiring design can be improved.

視需要，在經由在囊封體130中形成的開口131而暴露出的重佈線層112b的某些部分上可進一步形成表面處理層（圖中未示出）。所述表面處理層（圖中未示出）並不受特別限制，只要所述表面處理層（圖中未示出）在相關技術中是習知的即可，且所述表面處理層（圖中未示出）可藉由例如電解鍍金、無電鍍金、有機可焊性保護（organic solderability preservative，OSP）或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金（direct immersion gold，DIG）鍍覆、熱空氣焊料均塗（hot air solder leveling，HASL）等形成。A surface treatment layer (not shown) may be further formed on some portions of the redistribution layer 112b exposed through the opening 131 formed in the encapsulant 130, as needed. The surface treatment layer (not shown in the drawings) is not particularly limited as long as the surface treatment layer (not shown) is conventionally known in the related art, and the surface treatment layer (Fig. Not shown) by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/displacement gold plating, direct immersion gold (direct immersion) Gold, DIG) plating, hot air solder leveling (HASL) and the like.

介層窗113可將形成於不同層上的重佈線層112a及重佈線層112b電性連接至彼此，從而在第一互連構件110中形成電性路徑。介層窗113中的每一者亦可由導電材料形成。介層窗113中的每一者可如圖10中所示被完全地填充以導電材料；或者所述導電材料亦可沿介層窗113中的每一者的壁而形成。另外，介層窗113中的每一者可具有在相關技術中習知的所有形狀，例如錐形形狀、柱形形狀等。同時，如自以下將闡述的製程所見，當形成介層窗113的孔時，第一重佈線層112a的墊中的某些墊可充當塞子（stopper），且因此在介層窗113中的每一者的具有上表面的寬度較下表面的寬度大的錐形形狀的製程中可為有利的。在此種情形中，介層窗113可與第二重佈線層112b的某些部分整合。The vias 113 may electrically connect the redistribution layer 112a and the redistribution layer 112b formed on the different layers to each other, thereby forming an electrical path in the first interconnecting member 110. Each of the vias 113 may also be formed of a conductive material. Each of the vias 113 may be completely filled with a conductive material as shown in FIG. 10; or the conductive material may also be formed along the walls of each of the vias 113. In addition, each of the vias 113 may have all of the shapes well known in the related art, such as a tapered shape, a cylindrical shape, and the like. Meanwhile, as seen from the process to be explained below, when forming the vias of the vias 113, some of the pads of the first redistribution layer 112a may serve as a stopper, and thus in the via 113. It may be advantageous in each of the processes having a tapered shape having a width of the upper surface that is greater than the width of the lower surface. In this case, the vias 113 may be integrated with portions of the second redistribution layer 112b.

半導體晶片120可為被設置成將數量為數百個至數百萬個的元件或更多元件整合於單個晶片中的積體電路（IC）。舉例而言，所述積體電路可為應用處理器晶片，例如，中央處理器（例如中央處理單元）、圖形處理器（例如圖形處理單元）、數位訊號處理器、密碼處理器、微處理器、微控制器等，但並非僅限於此。半導體晶片120可基於主動晶圓而形成。在此種情形中，主體121的基材（base material）可為矽（Si）、鍺（Ge）、砷化鎵（GaAs）等。在主體121上可形成各種電路。連接墊122可將半導體晶片120電性連接至其他組件。連接墊122的材料可為例如鋁（Al）等導電材料。在主體121上可形成暴露出連接墊122的保護層123，且保護層123可為氧化物膜、氮化物膜等或氧化物層與氮化物層構成的雙層。連接墊122的下表面透過保護層123可具有相對於囊封體130的下表面的台階部分。作為結果，在某些程度上可防止囊封體130滲透入連接墊122的下表面中的現象。亦可在其他需要的位置中進一步安置絕緣層（圖中未示出）等。The semiconductor wafer 120 may be an integrated circuit (IC) that is configured to integrate a number of hundreds or millions of elements or more into a single wafer. For example, the integrated circuit can be an application processor chip, for example, a central processing unit (such as a central processing unit), a graphics processor (such as a graphics processing unit), a digital signal processor, a cryptographic processor, a microprocessor. , microcontrollers, etc., but not limited to this. The semiconductor wafer 120 can be formed based on an active wafer. In this case, the base material of the body 121 may be bismuth (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the main body 121. The connection pads 122 can electrically connect the semiconductor wafer 120 to other components. The material of the connection pad 122 may be a conductive material such as aluminum (Al). A protective layer 123 exposing the connection pads 122 may be formed on the main body 121, and the protective layer 123 may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer. The lower surface of the connection pad 122 may have a stepped portion with respect to the lower surface of the encapsulant 130 through the protective layer 123. As a result, the phenomenon that the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. An insulating layer (not shown) or the like may be further disposed in other required positions.

半導體晶片120的被動表面可安置於低於第一互連構件110的第二重佈線層112b的上表面的水平高度上。舉例而言，半導體晶片120的被動表面可安置於低於第一互連構件110的絕緣層111的上表面的水平高度上。半導體晶片120的被動表面與第一互連構件110的第二重佈線層112b的上表面之間的高度差可為2微米（μm）或大於2微米，例如5微米或大於5微米。在此種情形中，可有效地防止在半導體晶片120的被動表面的隅角中產生破裂。另外，在使用囊封體130的情形中在半導體晶片120的被動表面上的絕緣距離的偏差可顯著減小。The passive surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the second redistribution layer 112b of the first interconnecting member 110. For example, the passive surface of the semiconductor wafer 120 can be disposed at a level lower than the upper surface of the insulating layer 111 of the first interconnecting member 110. The height difference between the passive surface of the semiconductor wafer 120 and the upper surface of the second redistribution layer 112b of the first interconnecting member 110 may be 2 micrometers (μm) or greater than 2 micrometers, such as 5 micrometers or greater than 5 micrometers. In this case, cracking in the corner of the passive surface of the semiconductor wafer 120 can be effectively prevented. In addition, the deviation of the insulation distance on the passive surface of the semiconductor wafer 120 in the case of using the encapsulation 130 can be significantly reduced.

囊封體130可保護第一互連構件110及/或半導體晶片120。囊封體130的囊封形式不受特別限制，但可為囊封體130環繞第一互連構件110的至少某些部分及/或半導體晶片120的至少某些部分的形式。舉例而言，囊封體130可覆蓋第一互連構件110及半導體晶片120的被動表面，且填充貫穿孔110H的壁與半導體晶片120的側表面之間的空間。另外，囊封體130亦可填充半導體晶片120的保護層123與第二互連構件140之間的空間的至少一部分。同時，囊封體130可填充貫穿孔110H，以因此充當黏合劑並端視某些材料而減少半導體晶片120的彎曲（buckling）。The encapsulant 130 can protect the first interconnect member 110 and/or the semiconductor wafer 120. The encapsulated form of the encapsulant 130 is not particularly limited, but may be in the form of an encapsulation 130 surrounding at least some portions of the first interconnecting member 110 and/or at least portions of the semiconductor wafer 120. For example, the encapsulant 130 may cover the first interconnecting member 110 and the passive surface of the semiconductor wafer 120 and fill the space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulant 130 may also fill at least a portion of the space between the protective layer 123 of the semiconductor wafer 120 and the second interconnecting member 140. At the same time, the encapsulant 130 can fill the through-hole 110H to thereby act as a binder and look at certain materials to reduce the buckling of the semiconductor wafer 120.

囊封體130的某些材料不受特別限制。舉例而言，絕緣材料可用作囊封體130的材料。在此種情形中，所述絕緣材料可為包括無機填料及絕緣樹脂的材料，所述絕緣樹脂例如為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有例如浸入於熱固性樹脂及熱塑性樹脂中的無機填料等加強材料的樹脂，例如味之素構成膜、FR-4、雙馬來醯亞胺三嗪、感光成像介電樹脂等。另外，亦可使用例如環氧樹脂模製化合物（epoxy molding compound，EMC）等習知模製材料。作為另外一種選擇，亦可使用將熱固性樹脂或熱塑性樹脂與無機填料一起浸入於例如玻璃布（或玻璃纖維）等核心材料中的材料作為所述絕緣材料。Certain materials of the envelope 130 are not particularly limited. For example, an insulating material can be used as the material of the encapsulant 130. In this case, the insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; having, for example, immersed in A resin of a reinforcing material such as an inorganic filler in a thermosetting resin or a thermoplastic resin, for example, a peptide comprising aj, a FR-4, a bismaleimide triazine, a photosensitive imaging dielectric resin, or the like. Further, a conventional molding material such as an epoxy molding compound (EMC) can also be used. Alternatively, a material in which a thermosetting resin or a thermoplastic resin is immersed together with an inorganic filler in a core material such as glass cloth (or glass fiber) may be used as the insulating material.

囊封體130可包括由多個材料形成的多個層。舉例而言，位於貫穿孔110H內的空間可被填充以第一囊封體，且第一互連構件110及半導體晶片120可被覆蓋以第二囊封體。作為另外一種選擇，第一囊封體在填充貫穿孔110H內的空間的同時可以預定厚度覆蓋第一互連構件110及半導體晶片120，且第二囊封體可以預定厚度再次覆蓋第一囊封體。除上述的形式之外，亦可使用各種形式。The encapsulant 130 can include multiple layers formed from a plurality of materials. For example, a space located within the through hole 110H may be filled with the first encapsulant, and the first interconnecting member 110 and the semiconductor wafer 120 may be covered with the second encapsulant. Alternatively, the first encapsulant may cover the first interconnecting member 110 and the semiconductor wafer 120 with a predetermined thickness while filling the space in the through hole 110H, and the second encapsulant may cover the first encapsulation again with a predetermined thickness body. In addition to the above forms, various forms can also be used.

視需要，囊封體130可包含導電顆粒以阻擋電磁波。舉例而言，所述導電顆粒可為可阻擋電磁波的任何材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）、焊料等。然而，此僅為實例，且所述導電顆粒並不受特別限制。The encapsulant 130 may contain conductive particles to block electromagnetic waves, as needed. For example, the conductive particles may be any material that can block electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti), solder, and the like. However, this is merely an example, and the conductive particles are not particularly limited.

第二互連構件140可被配置成對半導體晶片120的連接墊122進行重佈線。具有各種功能的數十至數百個連接墊122可藉由第二互連構件140而進行重佈線，且可經由以下將端視所述功能所闡述的連接端子170而實體地連接至或電性地連接至外源。第二互連構件140可包括：絕緣層141；重佈線層142，安置於絕緣層141上；以及介層窗143，穿透過絕緣層141並將各重佈線層142連接至彼此。在根據示例性實施例的扇出型半導體封裝100A中，第二互連構件140可包括單層，但亦可包括多個層。The second interconnecting member 140 can be configured to rewire the connection pads 122 of the semiconductor wafer 120. The tens to hundreds of connection pads 122 having various functions may be re-wired by the second interconnecting member 140, and may be physically connected to or electrically via the connection terminal 170 as exemplified by the function described below. Sexually connected to an external source. The second interconnecting member 140 may include: an insulating layer 141; a redistribution layer 142 disposed on the insulating layer 141; and a via 143 penetrating through the insulating layer 141 and connecting the respective rewiring layers 142 to each other. In the fan-out type semiconductor package 100A according to an exemplary embodiment, the second interconnecting member 140 may include a single layer, but may also include a plurality of layers.

可使用絕緣材料作為絕緣層141的材料。在此種情形中，亦可使用例如感光成像介電（PID）樹脂等感光性絕緣材料作為所述絕緣材料。亦即，絕緣層141可為感光性絕緣材料層。在絕緣層141具有感光性質的情形中，絕緣層141可被形成為具有較小的厚度，且可更容易地達成介層窗143的精細節距。絕緣層141可為包含絕緣樹脂及無機填料的感光性絕緣層。視需要，當絕緣層141為多個層時，絕緣層141的材料可彼此相同，且亦可彼此不同。當絕緣層141為多個層時，絕緣層141可端視製程而彼此整合，進而使得各絕緣層141之間的邊界亦可不明顯。An insulating material can be used as the material of the insulating layer 141. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may also be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating material layer. In the case where the insulating layer 141 has a photosensitive property, the insulating layer 141 can be formed to have a small thickness, and the fine pitch of the via 143 can be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 is a plurality of layers, the materials of the insulating layer 141 may be identical to each other, and may be different from each other, as needed. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other in a process depending on the process, so that the boundary between the insulating layers 141 may also be inconspicuous.

重佈線層142可實質上用於對連接墊122進行重佈線。重佈線層142中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。重佈線層142可端視其對應層的設計而執行各種功能。舉例而言，重佈線層142可包括接地（GND）圖案、功率（PWR）圖案、訊號（S）圖案等。此處，訊號（S）圖案可包括除接地（GND）圖案、功率（PWR）圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層142可包括介層窗墊、連接端子墊等。The redistribution layer 142 can be used substantially to rewire the connection pads 122. The material of each of the redistribution layers 142 may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium. A conductive material such as (Ti) or an alloy thereof. The redistribution layer 142 can perform various functions depending on the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the redistribution layer 142 may include a via window pad, a connection terminal pad, or the like.

視需要，在暴露出的重佈線層142上可形成表面處理層（圖中未示出）。所述表面處理層（圖中未示出）並不受特別限制，只要所述表面處理層在相關技術中是所習知的即可，且所述表面處理層可藉由例如電解鍍金、無電鍍金、有機可焊性保護（OSP）、或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金（DIG）鍍覆、熱空氣焊料均塗（HASL）等來形成。A surface treatment layer (not shown) may be formed on the exposed redistribution layer 142 as needed. The surface treatment layer (not shown) is not particularly limited as long as the surface treatment layer is known in the related art, and the surface treatment layer can be, for example, electrolytically plated with gold, Electroplated gold, organic solderability protection (OSP), or electroless tin plating, electroless silver plating, electroless nickel plating/displacement gold plating, direct immersion gold (DIG) plating, hot air solder coating (HASL), and the like.

介層窗143可將在不同的層上形成的重佈線層142、連接墊122等電性連接至彼此，從而在扇出型半導體封裝100A中產生電性路徑。介層窗143中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。介層窗143可被完全地填充以所述導電材料；或所述導電材料亦可沿所述介層窗的壁形成。另外，介層窗143可具有在相關技術中的習知所有形狀，例如錐形形狀、柱形形狀等。The via 143 can electrically connect the redistribution layer 142, the connection pads 122, and the like formed on the different layers to each other, thereby generating an electrical path in the fan-out type semiconductor package 100A. The material of each of the vias 143 may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium. A conductive material such as (Ti) or an alloy thereof. The via 143 may be completely filled with the conductive material; or the conductive material may also be formed along the walls of the via. In addition, the via 143 may have all of the conventional shapes in the related art, such as a tapered shape, a cylindrical shape, and the like.

第一互連構件110的重佈線層112a及重佈線層112b的厚度可較第二互連構件140的重佈線層142的厚度大。由於第一互連構件110的厚度可與半導體晶片120的厚度相等或較半導體晶片120的厚度大，因此端視第一互連構件110的規模，在第一互連構件110中形成的重佈線層112a及重佈線層112b可被形成為具有大的尺寸。另一方面，可以較第一互連構件110的重佈線層112a及重佈線層112b的尺寸相對小的尺寸來形成第二互連構件140的重佈線層142，以達成第二互連構件140的薄度。The thickness of the redistribution layer 112a and the redistribution layer 112b of the first interconnecting member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnecting member 140. Since the thickness of the first interconnecting member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution formed in the first interconnecting member 110 is viewed in a manner depending on the scale of the first interconnecting member 110. The layer 112a and the redistribution layer 112b may be formed to have a large size. On the other hand, the redistribution layer 142 of the second interconnect member 140 may be formed in a relatively smaller size than the size of the redistribution layer 112a and the redistribution layer 112b of the first interconnecting member 110 to achieve the second interconnect member 140. Thinness.

保護層150可被配置成保護第二互連構件140不受外部物理損壞或化學損壞。保護層150可具有由多個孔形成的開口151，所述開口暴露出第二互連構件140的重佈線層142的至少某些部分。在保護層150中形成的開口151的數目可為數十至數千。The protective layer 150 may be configured to protect the second interconnecting member 140 from external physical or chemical damage. The protective layer 150 may have an opening 151 formed of a plurality of holes that expose at least some portions of the redistribution layer 142 of the second interconnecting member 140. The number of the openings 151 formed in the protective layer 150 may be several tens to several thousands.

可使用彈性模數較第二互連構件140的絕緣層141的彈性模數大的材料作為保護層150的材料。舉例而言，可使用不包含玻璃布（或玻璃纖維）而是包含無機填料及絕緣樹脂的味之素構成膜等作為保護層150的材料。當使用味之素構成膜等作為保護層150的材料時，保護層150中所包含的無機填料的重量百分比可大於第二互連構件140的絕緣層141中所包含的無機填料的重量百分比。在此種條件下，可靠性可得以提高。當使用味之素構成膜等作為保護層150的材料時，保護層150可為包含無機填料的非感光性絕緣層，且可靠性可得以有效地提高，但並非僅限於此。As the material of the protective layer 150, a material having a larger elastic modulus than the insulating layer 141 of the second interconnecting member 140 may be used. For example, a film or the like which comprises a glass cloth (or glass fiber) and an inorganic filler and an insulating resin may be used as the material of the protective layer 150. When a film or the like is used as the material of the protective layer 150, the weight percentage of the inorganic filler contained in the protective layer 150 may be greater than the weight percentage of the inorganic filler contained in the insulating layer 141 of the second interconnecting member 140. Under such conditions, reliability can be improved. When a film such as Ajinomoto is used as the material of the protective layer 150, the protective layer 150 may be a non-photosensitive insulating layer containing an inorganic filler, and reliability can be effectively improved, but is not limited thereto.

凸塊下金屬層160可另外地被配置成提高連接端子170的連接可靠性及提高扇出型半導體封裝100A的板級可靠性。凸塊下金屬層160可連接至經由保護層150的開口151而暴露出的第二互連構件140的重佈線層142。凸塊下金屬層160可藉由使用習知導電金屬材料（例如金屬）的習知金屬化方法而形成於保護層150的開口151中，但並非僅限於此。The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 and to improve the board level reliability of the fan-out type semiconductor package 100A. The under bump metal layer 160 may be connected to the redistribution layer 142 of the second interconnect member 140 exposed through the opening 151 of the protective layer 150. The under bump metal layer 160 may be formed in the opening 151 of the protective layer 150 by a conventional metallization method using a conventional conductive metal material such as a metal, but is not limited thereto.

連接端子170可另外地被配置成在外部實體地或電性地對扇出型半導體封裝100A進行連接。舉例而言，扇出型半導體封裝100A可經由連接端子170而安裝於電子裝置的主板上。連接端子170中的每一者可由例如焊料等導電材料形成。然而，此僅為實例，且連接端子170中的每一者的材料不受特別限制。連接端子170中的每一者可為焊盤（land）、球、引腳等。連接端子170可被形成為多層式結構或單層式結構。當連接端子170被形成為多層式結構時，連接端子170可包含銅（Cu）柱及焊料。當連接端子17由單個層形成時，連接端子170可包含錫-銀焊料或銅（Cu）。然而，此僅為實例，且連接端子170並非僅限於此。The connection terminal 170 may be additionally configured to physically or electrically connect the fan-out type semiconductor package 100A externally. For example, the fan-out type semiconductor package 100A can be mounted on the main board of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder. However, this is merely an example, and the material of each of the connection terminals 170 is not particularly limited. Each of the connection terminals 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed in a multilayer structure or a single layer structure. When the connection terminal 170 is formed in a multi-layered structure, the connection terminal 170 may include a copper (Cu) pillar and solder. When the connection terminal 17 is formed of a single layer, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is merely an example, and the connection terminal 170 is not limited thereto.

連接端子170的數目、間隔、佈置等不受特別限制，而是可由熟習此項技術者端視設計詳情而進行充分地修改。舉例而言，根據半導體晶片120的連接墊122的數目，連接端子170可被設置成數十至數千的數量，但並非僅限於此，且亦可被設置成數十至數千或更多的數量或者數十至數千或更少的數量。當連接端子170是焊料球時，連接端子170可覆蓋凸塊下金屬層160的延伸至保護層150的一個表面上的側表面，且連接可靠性可得到提高。The number, spacing, arrangement, and the like of the connection terminals 170 are not particularly limited, but can be sufficiently modified by those skilled in the art to look at the design details. For example, according to the number of the connection pads 122 of the semiconductor wafer 120, the connection terminals 170 may be set in the number of tens to thousands, but are not limited thereto, and may be set to tens to thousands or more. The number or the number of tens to thousands or less. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover a side surface of the under bump metal layer 160 that extends to one surface of the protective layer 150, and connection reliability may be improved.

連接端子170中的至少一者可安置於扇出區中。所述扇出區為除安置有半導體晶片120的區之外的區。亦即，根據示例性實施例的扇出型半導體封裝100A可為扇出型封裝。相較於扇入型封裝而言，所述扇出型封裝可具有極佳的可靠性，所述扇出型封裝可實作多個輸入/輸出（I/O）端子，且可有利於3D互連。另外，相較於球柵陣列（ball grid array，BGA）封裝、焊盤柵陣列（land grid array，LGA）封裝等而言，所述扇出型封裝可在無需單獨的板的條件下安裝於電子裝置上。因此，所述扇出型封裝可被製造成具有小的厚度，且可具有價格競爭力。At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is a region other than the area in which the semiconductor wafer 120 is placed. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. The fan-out package can have excellent reliability compared to a fan-in type package, which can implement multiple input/output (I/O) terminals and can facilitate 3D interconnection. In addition, the fan-out package can be mounted without a separate board as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like. On the electronic device. Therefore, the fan-out type package can be manufactured to have a small thickness and can be price competitive.

儘管圖式中未示出，然而視需要，可在第一互連構件110的貫穿孔110H的內側壁上進一步安置金屬層。亦即，半導體晶片120的側表面亦可被所述金屬層環繞。透過所述金屬層，由半導體晶片120產生的熱可在扇出型半導體封裝100A的向上方向或向下方向上被有效地擴散，且透過所述金屬層，電磁波可被有效地阻擋。另外，視需要，在第一互連構件110的貫穿孔110H中可安置多個半導體晶片，且第一互連構件110的貫穿孔110H的數目可為多個且半導體晶片可分別安置於所述貫穿孔中。另外，例如電容器（condenser）、感應器等單獨的被動組件可與半導體晶片一起安置於貫穿孔110H中。另外，表面安裝組件亦可安裝於保護層150上，以定位於與連接端子170的水平高度實質上相同的水平高度上。Although not shown in the drawings, a metal layer may be further disposed on the inner side wall of the through hole 110H of the first interconnecting member 110 as needed. That is, the side surface of the semiconductor wafer 120 may also be surrounded by the metal layer. Through the metal layer, heat generated by the semiconductor wafer 120 can be effectively diffused in the upward or downward direction of the fan-out type semiconductor package 100A, and electromagnetic waves can be effectively blocked by the metal layer. In addition, a plurality of semiconductor wafers may be disposed in the through holes 110H of the first interconnecting member 110, and the number of the through holes 110H of the first interconnecting member 110 may be plural and the semiconductor wafers may be respectively disposed in the Through the hole. In addition, a separate passive component such as a condenser, an inductor, or the like may be disposed in the through hole 110H together with the semiconductor wafer. In addition, the surface mount component can also be mounted on the protective layer 150 to be positioned at substantially the same level as the level of the connection terminal 170.

圖11A及圖11B分別是說明圖9所示的扇出型半導體封裝的保護層的開口及凸塊下金屬層的經修改實例的示意性剖視圖及示意性平面圖。11A and 11B are respectively a schematic cross-sectional view and a schematic plan view illustrating a modified example of the opening of the protective layer and the under-bump metal layer of the fan-out type semiconductor package shown in Fig. 9.

參照所述圖式，保護層150的開口151可由多個孔形成，且凸塊下金屬層160可包括形成於保護層150上的外部連接墊162及多個介層窗161a、161b、161c、161d，所述多個介層窗161a、161b、161c、161d形成於保護層150的由所述多個孔形成的開口151中且將外部連接墊162與第二互連構件140的重佈線層142連接至彼此。在此種情形中，應力可藉由所述多個介層窗161a、161b、161c、161d而得以分散，且金屬部分可藉由所述多個介層窗161a、161b、161c、161d而得以增大以確保充分的抗應力性。結果，上述板級可靠性的問題可得以防止。所述多個介層窗161a、161b、161c、161d可完全地填充構成保護層150的開口的所述多個孔；或者在某些情形中，僅沿相應孔的壁填充所述孔中的某些部分。外部連接墊162可形成於所述多個介層窗161a、161b、161c、161d上，且可延伸至保護層150的表面。Referring to the drawing, the opening 151 of the protective layer 150 may be formed by a plurality of holes, and the under bump metal layer 160 may include an external connection pad 162 formed on the protective layer 150 and a plurality of vias 161a, 161b, 161c, 161d, the plurality of vias 161a, 161b, 161c, 161d are formed in the opening 151 of the protective layer 150 formed by the plurality of holes and the redistribution layer of the external connection pad 162 and the second interconnecting member 140 142 are connected to each other. In this case, the stress can be dispersed by the plurality of vias 161a, 161b, 161c, 161d, and the metal portion can be obtained by the plurality of vias 161a, 161b, 161c, 161d Increase to ensure adequate stress resistance. As a result, the above-described problem of board level reliability can be prevented. The plurality of vias 161a, 161b, 161c, 161d may completely fill the plurality of holes constituting the opening of the protective layer 150; or in some cases, only fill the holes in the holes along the walls of the corresponding holes Some parts. An external connection pad 162 may be formed on the plurality of vias 161a, 161b, 161c, 161d and may extend to a surface of the protective layer 150.

在材料方面，凸塊下金屬層160可包括：第一導體層160a，形成於構成暴露出重佈線層142的開口的所述多個孔的壁上及保護層150的表面上；以及第二導體層160b，形成於第一導體層160a上。第一導體層160a可充當晶種層，且第二導體層160b可實質上充當凸塊下金屬層160。第一導體層160a及第二導體層160b可分別包含習知導電材料，較佳為無電鍍銅（Cu）及電解銅（Cu）。第一導體層160a可充當晶種層以因此具有非常薄的厚度。因此，第一導體層160a的厚度可較第二導體層160b的厚度小。In terms of materials, the under bump metal layer 160 may include: a first conductor layer 160a formed on a wall of the plurality of holes constituting an opening exposing the redistribution layer 142 and a surface of the protective layer 150; and a second The conductor layer 160b is formed on the first conductor layer 160a. The first conductor layer 160a may serve as a seed layer, and the second conductor layer 160b may substantially function as the under bump metal layer 160. The first conductor layer 160a and the second conductor layer 160b may each comprise a conventional conductive material, preferably electroless copper (Cu) and electrolytic copper (Cu). The first conductor layer 160a can serve as a seed layer to thus have a very thin thickness. Therefore, the thickness of the first conductor layer 160a may be smaller than the thickness of the second conductor layer 160b.

在外部連接墊162的表面上可形成分別與所述多個介層窗161a、161b、161c、161d對應的多個凹坑，以到達所述多個介層窗161a、161b、161c、161d的內側部分。結果，可靠性可進一步得以提高。A plurality of pits respectively corresponding to the plurality of vias 161a, 161b, 161c, 161d may be formed on a surface of the external connection pad 162 to reach the plurality of vias 161a, 161b, 161c, 161d Inner part. As a result, the reliability can be further improved.

圖12A及圖12B分別是說明圖9所示的扇出型半導體封裝的保護層的開口及凸塊下金屬層的另一經修改實例的示意性剖視圖及示意性平面圖。12A and 12B are respectively a schematic cross-sectional view and a schematic plan view illustrating another modified example of the opening of the protective layer and the under-bump metal layer of the fan-out type semiconductor package shown in Fig. 9.

參照所述圖式，保護層150的開口151可由更多數目的孔形成，且凸塊下金屬層160可包括形成於保護層150上的外部連接墊162及更多數目的介層窗161a至161i，所述更多數目的介層窗161a至161i形成於保護層150的由更多數目的孔形成的開口151中且將外部連接墊162與第二互連構件140的重佈線層142連接至彼此。亦即，介層窗的數目不受特別限制。除上述配置之外的其他配置的說明與上述說明重疊。Referring to the drawing, the opening 151 of the protective layer 150 may be formed by a greater number of holes, and the under bump metal layer 160 may include an external connection pad 162 formed on the protective layer 150 and a greater number of vias 161a to 161i, the greater number of vias 161a through 161i are formed in the opening 151 of the protective layer 150 formed by a greater number of holes and connect the external connection pads 162 to the redistribution layer 142 of the second interconnecting member 140 To each other. That is, the number of vias is not particularly limited. The description of the configuration other than the above configuration overlaps with the above description.

圖13是說明扇出型半導體封裝的另一實例的示意性剖視圖。Figure 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參照所述圖式，根據本發明中另一示例性實施例的扇出型半導體封裝100B可更包括安置於囊封體130上的加強層181。加強層181可為例如包含無機填料及絕緣樹脂的味之素構成膜，但並非僅限於此。在某些情形中，加強層181的組成可與保護層150的組成相同。此種情形可更加有益於藉由對稱效果來控制翹曲。加強層181的彈性模數可較囊封體130的彈性模數大。加強層181中所包含的無機填料的重量百分比可大於囊封體130中所包含的無機填料的重量百分比。在此種情形中，加強層181的熱膨脹係數可較囊封體130的熱膨脹係數低。另外，加強層181相對於半導體晶片120的被動表面的厚度可大於囊封體130相對於半導體晶片120的被動表面的厚度。藉由引入上述加強層181，扇出型半導體封裝100B的翹曲可得以抑制。加強層181可在硬化的狀態下貼合至囊封體130，且加強層181的接觸囊封體130的表面可因此為平的。暴露出第一互連構件110的第二重佈線層112b的至少某些部分的開口182可形成於加強層181及囊封體130中，且其可用作記號等。除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。Referring to the drawings, the fan-out type semiconductor package 100B according to another exemplary embodiment of the present invention may further include a reinforcement layer 181 disposed on the encapsulation body 130. The reinforcing layer 181 may be, for example, a film composed of astringent containing an inorganic filler and an insulating resin, but is not limited thereto. In some cases, the composition of the reinforcement layer 181 may be the same as the composition of the protective layer 150. This situation can be more beneficial for controlling warpage by symmetrical effects. The elastic modulus of the reinforcing layer 181 may be larger than the elastic modulus of the encapsulant 130. The weight percentage of the inorganic filler contained in the reinforcing layer 181 may be greater than the weight percentage of the inorganic filler contained in the encapsulant 130. In this case, the coefficient of thermal expansion of the reinforcing layer 181 may be lower than the coefficient of thermal expansion of the encapsulant 130. Additionally, the thickness of the reinforcing layer 181 relative to the passive surface of the semiconductor wafer 120 can be greater than the thickness of the encapsulant 130 relative to the passive surface of the semiconductor wafer 120. By introducing the above-described reinforcing layer 181, the warpage of the fan-out type semiconductor package 100B can be suppressed. The reinforcing layer 181 may be attached to the encapsulant 130 in a hardened state, and the surface of the reinforcing layer 181 contacting the encapsulant 130 may thus be flat. An opening 182 exposing at least some portions of the second redistribution layer 112b of the first interconnecting member 110 may be formed in the reinforcing layer 181 and the encapsulant 130, and it may be used as a mark or the like. Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again.

圖14是說明扇出型半導體封裝的另一實例的示意性剖視圖。Fig. 14 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

參照所述圖式，根據本發明中另一示例性實施例的扇出型半導體封裝100C可更包括安置於囊封體130上的加強層183。在此種情形中，加強層183可包含核心材料、無機填料及絕緣樹脂。加強層183可為例如未被覆蓋的覆銅疊層板（copper clad laminate，CCL）。未被硬化-收縮的未被覆蓋的覆銅疊層板可在對囊封體130硬化-收縮時保持扇出型半導體封裝100C。在此種情形中，加強層183可包含所述核心材料以因此具有相對大的彈性模數。亦即，加強層183的彈性模數可較囊封體130的彈性模數大。亦即，在硬化-收縮時出現的扇出型半導體封裝100C的翹曲可得以抑制。加強層183可在硬化的狀態下貼合至囊封體130，且加強層183的接觸囊封體130的表面可因此為平的。Referring to the drawings, a fan-out type semiconductor package 100C according to another exemplary embodiment of the present invention may further include a reinforcement layer 183 disposed on the encapsulation body 130. In this case, the reinforcing layer 183 may include a core material, an inorganic filler, and an insulating resin. The reinforcing layer 183 can be, for example, an uncovered copper clad laminate (CCL). The uncovered, shrink-covered, uncovered copper clad laminate can maintain the fan-out type semiconductor package 100C while hardening-shrinking the encapsulant 130. In this case, the reinforcing layer 183 may comprise the core material to thus have a relatively large modulus of elasticity. That is, the elastic modulus of the reinforcing layer 183 may be larger than the elastic modulus of the encapsulant 130. That is, the warpage of the fan-out type semiconductor package 100C which occurs at the time of hardening-shrinking can be suppressed. The reinforcing layer 183 may be attached to the encapsulant 130 in a hardened state, and the surface of the reinforcing layer 183 contacting the encapsulant 130 may thus be flat.

在加強層183上可進一步安置有樹脂層184。樹脂層184可由與囊封體130的組分相同或相似的組分形成。舉例而言，樹脂層184可包含無機填料及絕緣樹脂，但亦可包含核心材料。亦即，樹脂層184可為性質與囊封體130的性質相同或相似的味之素構成膜，但並非僅限於此。可安置樹脂層184以有助於形成開口185。當在最外部分處形成加強層183時，可能難以形成開口185。然而，當樹脂層184安置於加強層183上時，可易於形成開口185。開口185可被用作記號等。另外，當進一步安置樹脂層184時，可更有效地抑制翹曲。樹脂層184可在硬化狀態下貼合至加強層183，且樹脂層184的接觸加強層183的表面可因此為平的。除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。A resin layer 184 may be further disposed on the reinforcing layer 183. The resin layer 184 may be formed of the same or similar components as the components of the encapsulant 130. For example, the resin layer 184 may include an inorganic filler and an insulating resin, but may also include a core material. That is, the resin layer 184 may be a sinusoidal film having the same or similar properties as those of the encapsulated body 130, but is not limited thereto. The resin layer 184 may be disposed to help form the opening 185. When the reinforcing layer 183 is formed at the outermost portion, it may be difficult to form the opening 185. However, when the resin layer 184 is disposed on the reinforcing layer 183, the opening 185 can be easily formed. The opening 185 can be used as a mark or the like. In addition, when the resin layer 184 is further disposed, warpage can be more effectively suppressed. The resin layer 184 may be attached to the reinforcing layer 183 in a hardened state, and the surface of the contact reinforcing layer 183 of the resin layer 184 may thus be flat. Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again.

圖15是說明扇出型半導體封裝的另一實例的示意性剖視圖。Fig. 15 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

參照所述圖式，根據本發明中另一示例性實施例的扇出型半導體封裝100D可更包括安置於囊封體130上的加強層191。在此種情形中，加強層191可包含無機填料及絕緣樹脂。然而，加強層191可在非硬化狀態下貼合至囊封體130且接著被硬化。亦即，可使用非硬化狀態下的味之素構成膜等作為加強層191的材料。在此種情形中，具有小的熱膨脹係數的加強層191的材料可因彼此接觸的異質材料之間的混合或邊界表面的移動而滲透至貫穿孔110H中。因此，囊封體130的填充第一互連構件110與半導體晶片120之間的空間的區可具有填充有加強層191的凹坑191P。在此種情形中，加強層191與囊封體130之間的緊密黏合可進一步得以增強。亦即，加強層191的接觸囊封體130的表面可不為平的。加強層191中所包含的無機填料的重量百分比可大於囊封體130中所包含的無機填料的重量百分比。因此，加強層191的熱膨脹係數可較囊封體130的熱膨脹係數低。此外，加強層191相對於半導體晶片120的被動表面的厚度可大於囊封體130相對於半導體晶片120的被動表面的厚度。藉由引入上述加強層191，扇出型半導體封裝100D的翹曲可得以抑制。除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。Referring to the drawings, the fan-out type semiconductor package 100D according to another exemplary embodiment of the present invention may further include a reinforcement layer 191 disposed on the encapsulation body 130. In this case, the reinforcing layer 191 may contain an inorganic filler and an insulating resin. However, the reinforcing layer 191 can be attached to the encapsulant 130 in a non-hardened state and then hardened. That is, a film or the like can be used as the material of the reinforcing layer 191 using Ajinomoto in a non-hardened state. In this case, the material of the reinforcing layer 191 having a small coefficient of thermal expansion may penetrate into the through hole 110H due to mixing between the foreign materials in contact with each other or movement of the boundary surface. Therefore, a region of the encapsulation 130 filling the space between the first interconnecting member 110 and the semiconductor wafer 120 may have a pit 191P filled with the reinforcing layer 191. In this case, the tight adhesion between the reinforcing layer 191 and the encapsulant 130 can be further enhanced. That is, the surface of the reinforcing layer 191 contacting the encapsulant 130 may not be flat. The weight percentage of the inorganic filler contained in the reinforcing layer 191 may be greater than the weight percentage of the inorganic filler contained in the encapsulant 130. Therefore, the coefficient of thermal expansion of the reinforcing layer 191 can be lower than the coefficient of thermal expansion of the encapsulant 130. Moreover, the thickness of the reinforcing layer 191 relative to the passive surface of the semiconductor wafer 120 can be greater than the thickness of the encapsulant 130 relative to the passive surface of the semiconductor wafer 120. By introducing the above-described reinforcing layer 191, the warpage of the fan-out type semiconductor package 100D can be suppressed. Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again.

圖16是說明扇出型半導體封裝的另一實例的示意性剖視圖。Fig. 16 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

參照所述圖式，根據本發明中另一示例性實施例的扇出型半導體封裝100E可更包括安置於囊封體130上的加強層192。在此種情形中，加強層192可包含核心材料、無機填料及絕緣樹脂。然而，加強層192可在非硬化狀態下貼合至囊封體130且接著被硬化。亦即，可使用非硬化狀態下的預浸體等作為加強層192的材料。在此種情形中，具有小的熱膨脹係數的加強層192的材料可因彼此接觸的異質材料之間的混合或邊界表面的移動而滲透至貫穿孔110H中。亦即，囊封體130的填充第一互連構件110與半導體晶片120之間的空間的區可具有填充有加強層192的凹坑192P。在此種情形中，加強層192與囊封體130之間的緊密黏合可進一步得以提高。亦即，加強層192的接觸囊封體130的表面可不為平的。在某些情形中，亦可使用相對於核心材料而言無機填料的量彼此不同的非對稱材料作為加強層192的材料。亦即，亦可使用非硬化狀態下的非對稱預浸體作為加強層192的材料。在此種情形中，無機填料的重量百分比可以以下順序遞增：囊封體130、加強層192的相鄰於囊封體130的一部分以及加強層192的與加強層192的相鄰於囊封體130的所述一部分相對的部分。除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。Referring to the drawings, the fan-out type semiconductor package 100E according to another exemplary embodiment of the present invention may further include a reinforcement layer 192 disposed on the encapsulation body 130. In this case, the reinforcing layer 192 may include a core material, an inorganic filler, and an insulating resin. However, the reinforcing layer 192 can be attached to the encapsulant 130 in a non-hardened state and then hardened. That is, a prepreg or the like in a non-hardened state can be used as the material of the reinforcing layer 192. In this case, the material of the reinforcing layer 192 having a small coefficient of thermal expansion may penetrate into the through hole 110H due to the mixing between the foreign materials contacting each other or the movement of the boundary surface. That is, the region of the encapsulant 130 that fills the space between the first interconnecting member 110 and the semiconductor wafer 120 may have pits 192P filled with the reinforcing layer 192. In this case, the tight adhesion between the reinforcing layer 192 and the encapsulant 130 can be further improved. That is, the surface of the reinforcing layer 192 contacting the encapsulant 130 may not be flat. In some cases, an asymmetrical material in which the amounts of the inorganic fillers are different from each other with respect to the core material may be used as the material of the reinforcing layer 192. That is, an asymmetric prepreg in a non-hardened state can also be used as the material of the reinforcing layer 192. In this case, the weight percentage of the inorganic filler may be increased in the following order: the encapsulant 130, a portion of the reinforcing layer 192 adjacent to the encapsulant 130, and the reinforcing layer 192 adjacent to the encapsulating layer 192. The opposite portion of the portion of 130. Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again.

圖17是說明扇出型半導體封裝的另一實例的示意性剖視圖。Figure 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參照所述圖式，根據本發明中的另一示例性實施例的扇出型半導體封裝100F可更包括安置於囊封體130上的背面重佈線層132及穿透過囊封體130並將背面重佈線層132連接至第一互連構件110的第二重佈線層112b的背面介層窗133。另外，扇出型半導體封裝100F可更包括安置於囊封體130上並覆蓋背面重佈線層132的加強層181。加強層181可具有暴露出背面重佈線層132的至少某些部分的開口182。背面重佈線層132可用作各種重佈線圖案，且可用作連接端子墊等。在某種情形中，可利用背面重佈線層132作為熱輻射圖案及電磁干擾（electromagnetic interference，EMI）阻擋圖案。背面重佈線層132及背面介層窗133可包含習知導電材料。加強層181可為例如包含無機填料及絕緣樹脂的味之素構成膜，但並非僅限於此。亦可安置由與加強層181的材料不同的材料形成的加強層183、加強層191及加強層192來替代加強層181。除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。Referring to the drawings, the fan-out type semiconductor package 100F according to another exemplary embodiment of the present invention may further include a back surface redistribution layer 132 disposed on the encapsulation body 130 and penetrating through the encapsulation body 130 and having the back surface The redistribution layer 132 is connected to the back via 133 of the second redistribution layer 112b of the first interconnecting member 110. In addition, the fan-out type semiconductor package 100F may further include a reinforcement layer 181 disposed on the encapsulant 130 and covering the back surface rewiring layer 132. The reinforcement layer 181 can have an opening 182 that exposes at least some portions of the back surface redistribution layer 132. The back redistribution layer 132 can be used as various rewiring patterns, and can be used as a connection terminal pad or the like. In some cases, the back surface redistribution layer 132 can be utilized as a heat radiation pattern and an electromagnetic interference (EMI) blocking pattern. The back redistribution layer 132 and the back via 133 may comprise conventional conductive materials. The reinforcing layer 181 may be, for example, a film composed of astringent containing an inorganic filler and an insulating resin, but is not limited thereto. Instead of the reinforcing layer 181, a reinforcing layer 183, a reinforcing layer 191, and a reinforcing layer 192 which are formed of a material different from that of the reinforcing layer 181 may be disposed. Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again.

圖18是說明扇出型半導體封裝的另一實例的示意性剖視圖。Figure 18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參照所述圖式，在根據本發明中的另一示例性實施例的扇出型半導體封裝100G中，第一互連構件110可包括：第一絕緣層111a，接觸第二互連構件140；第一重佈線層112a，接觸第二互連構件140且嵌於第一絕緣層111a中；第二重佈線層112b，安置於第一絕緣層111a的與第一絕緣層111a的嵌有第一重佈線層112a的一個表面相對的另一表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第三重佈線層112c，安置於第二絕緣層111b上。第一重佈線層112a、第二重佈線層112b及第三重佈線層112c可電性連接至連接墊122。同時，儘管未在圖式中示出，但第一重佈線層112a與第二重佈線層112b以及第二重佈線層112b與第三重佈線層112c可經由分別穿透過第一絕緣層111a及第二絕緣層111b的第一介層窗及第二介層窗而電性連接至彼此。Referring to the drawings, in the fan-out type semiconductor package 100G according to another exemplary embodiment of the present invention, the first interconnecting member 110 may include: a first insulating layer 111a contacting the second interconnecting member 140; The first redistribution layer 112a contacts the second interconnecting member 140 and is embedded in the first insulating layer 111a. The second redistribution layer 112b is disposed on the first insulating layer 111a and the first insulating layer 111a. On the other surface opposite to one surface of the redistribution layer 112a; a second insulating layer 111b disposed on the first insulating layer 111a and covering the second redistribution layer 112b; and a third redistribution layer 112c disposed on the second insulation On layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pads 122. Meanwhile, although not shown in the drawings, the first redistribution layer 112a and the second redistribution layer 112b and the second redistribution layer 112b and the third redistribution layer 112c may penetrate through the first insulating layer 111a and The first via and the second via of the second insulating layer 111b are electrically connected to each other.

由於嵌置了第一重佈線層112a，因此上述第二互連構件140的絕緣層141的絕緣距離可為實質上恆定的。由於第一互連構件110可包括大數目的重佈線層112a、重佈線層112b及重佈線層112c，因此可進一步簡化第二互連構件140。因此，可抑制因在形成第二互連構件140的製程中出現的缺陷而導致的良率的下降。第一重佈線層112a可凹陷至第一絕緣層111a中，進而使得在第一絕緣層111a的下表面與第一重佈線層112a的下表面之間具有台階。因此，當形成囊封體130時，可防止囊封體130的材料滲透污染第一重佈線層112a的現象。Since the first redistribution layer 112a is embedded, the insulation distance of the insulating layer 141 of the second interconnection member 140 described above may be substantially constant. Since the first interconnecting member 110 may include a large number of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c, the second interconnecting member 140 may be further simplified. Therefore, a decrease in yield due to a defect occurring in the process of forming the second interconnecting member 140 can be suppressed. The first redistribution layer 112a may be recessed into the first insulating layer 111a such that there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulant 130 is formed, the phenomenon that the material of the encapsulant 130 penetrates the first rewiring layer 112a can be prevented from penetrating.

可在高於半導體晶片120的連接墊122的下表面的水平高度上安置第一互連構件110的第一重佈線層112a的下表面。另外，第二互連構件140的重佈線層142與第一互連構件110的第一重佈線層112a之間的距離可大於第二互連構件140的重佈線層142與半導體晶片120的連接墊122之間的距離。原因在於第一重佈線層112a可凹陷至絕緣層111中。可在半導體晶片120的主動表面與被動表面之間的水平高度上安置第一互連構件110的第二重佈線層112b。可以與半導體晶片120的厚度對應的厚度形成第一互連構件110。因此，可在半導體晶片120的主動表面與被動表面之間的水平高度上安置形成於第一互連構件110中的第二重佈線層112b。The lower surface of the first redistribution layer 112a of the first interconnecting member 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second interconnecting member 140 and the first redistribution layer 112a of the first interconnecting member 110 may be greater than the connection of the redistribution layer 142 of the second interconnecting member 140 to the semiconductor wafer 120. The distance between the pads 122. The reason is that the first redistribution layer 112a can be recessed into the insulating layer 111. The second redistribution layer 112b of the first interconnect member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnecting member 110 may be formed in a thickness corresponding to the thickness of the semiconductor wafer 120. Accordingly, the second redistribution layer 112b formed in the first interconnecting member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

第一互連構件110的重佈線層112a、重佈線層112b及重佈線層112c的厚度可較第二互連構件140的重佈線層142的厚度大。由於第一互連構件110的厚度可與半導體晶片120的厚度相等或較半導體晶片120的厚度大，因此端視第一互連構件110的規模，重佈線層112a、重佈線層112b及重佈線層112c可被形成為具有大的尺寸。另一方面，可以相對小的尺寸來形成第二互連構件140的重佈線層142以達成薄度。The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnecting member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnecting member 140. Since the thickness of the first interconnecting member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the scale of the first interconnecting member 110, the redistribution layer 112a, the redistribution layer 112b, and the redistribution are viewed. The layer 112c can be formed to have a large size. On the other hand, the redistribution layer 142 of the second interconnecting member 140 may be formed in a relatively small size to achieve thinness.

除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。同時，上述扇出型半導體封裝100B至扇出型半導體封裝100F的說明亦可被應用於扇出型半導體封裝100G。Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again. Meanwhile, the description of the fan-out type semiconductor package 100B to the fan-out type semiconductor package 100F can also be applied to the fan-out type semiconductor package 100G.

圖19是說明扇出型半導體封裝的另一實例的示意性剖視圖。19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參照所述圖式，在根據本發明中的另一示例性實施例的扇出型半導體封裝100H中，第一互連構件110可包括：第一絕緣層111a；第一重佈線層112a及第二重佈線層112b，分別安置於第一絕緣層111a的相對的兩個表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第一重佈線層112a；第三重佈線層112c，安置於第二絕緣層111b上；第三絕緣層111c，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第四重佈線層112d，安置於第三絕緣層111c上。第一重佈線層112a、第二重佈線層112b、第三重佈線層112c及第四重佈線層112d可電性連接至連接墊122。由於第一互連構件110可包括較大數目的重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d，因此可進一步簡化第二互連構件140。因此，可抑制因在形成第二互連構件140的製程中出現的缺陷而導致的良率的下降。同時，儘管未在圖式中示出，但第一重佈線層112a、第二重佈線層112b、第三重佈線層112c及第四重佈線層112d可經由分別穿透過第一絕緣層111a、第二絕緣層111b及第三絕緣層111c的第一介層窗至第三介層窗而電性連接至彼此。Referring to the drawings, in the fan-out type semiconductor package 100H according to another exemplary embodiment of the present invention, the first interconnecting member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and a The second wiring layer 112b is disposed on the opposite surfaces of the first insulating layer 111a, and the second insulating layer 111b is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; the third redistribution layer 112c, disposed on the second insulating layer 111b; a third insulating layer 111c disposed on the first insulating layer 111a and covering the second redistribution layer 112b; and a fourth redistribution layer 112d disposed on the third insulating layer 111c . The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pads 122. Since the first interconnecting member 110 may include a larger number of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d, the second interconnection member 140 may be further simplified. Therefore, a decrease in yield due to a defect occurring in the process of forming the second interconnecting member 140 can be suppressed. Meanwhile, although not shown in the drawings, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may penetrate through the first insulating layer 111a, respectively. The first via to the third via of the second insulating layer 111b and the third insulating layer 111c are electrically connected to each other.

第一絕緣層111a的厚度可較第二絕緣層111b及第三絕緣層111c的厚度大。第一絕緣層111a可為相對厚的以維持剛性，且第二絕緣層111b及第三絕緣層111c可被引入以形成較大數目的重佈線層112c及重佈線層112d。第一絕緣層111a包括的絕緣材料可與第二絕緣層111b及第三絕緣層111c包括的絕緣材料不同。舉例而言，第一絕緣層111a可為例如包含核心材料、無機填料及絕緣樹脂的預浸體，且第二絕緣層111b及第三絕緣層111c可為包含無機填料及絕緣樹脂的味之素構成膜或感光性絕緣膜。然而，第一絕緣層111a的材料以及第二絕緣層111b及第三絕緣層111c的材料並非僅限於此。The thickness of the first insulating layer 111a may be larger than the thickness of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of the redistribution layer 112c and the redistribution layer 112d. The first insulating layer 111a may include an insulating material different from the insulating material included in the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be a flavor containing an inorganic filler and an insulating resin. A film or a photosensitive insulating film is formed. However, the material of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

可在低於半導體晶片120的連接墊122的下表面的水平高度上安置第一互連構件110的第三重佈線層112c的下表面。另外，第二互連構件140的重佈線層142與第一互連構件110的第三重佈線層112c之間的距離可小於第二互連構件140的重佈線層142與半導體晶片120的連接墊122之間的距離。原因在於第三重佈線層112c可以突出的形式安置於第二絕緣層111b上，從而接觸第二互連構件140。可在半導體晶片120的主動表面與被動表面之間的水平高度上安置第一互連構件110的第一重佈線層112a及第二重佈線層112b。可以與半導體晶片120的厚度對應的厚度形成第一互連構件110。因此，可在半導體晶片120的主動表面與被動表面之間的水平高度上安置形成於第一互連構件110中的第一重佈線層112a及第二重佈線層112b。The lower surface of the third redistribution layer 112c of the first interconnecting member 110 may be disposed at a level lower than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second interconnecting member 140 and the third redistribution layer 112c of the first interconnecting member 110 may be smaller than the connection of the redistribution layer 142 of the second interconnecting member 140 to the semiconductor wafer 120. The distance between the pads 122. The reason is that the third redistribution layer 112c can be disposed on the second insulating layer 111b in a protruding form to contact the second interconnecting member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first interconnecting member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnecting member 110 may be formed in a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112a and the second redistribution layer 112b formed in the first interconnecting member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

第一互連構件110的重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d的厚度可大於第二互連構件140的重佈線層142的厚度。由於第一互連構件110的厚度可與半導體晶片120的厚度相等或較半導體晶片120的厚度大，因此重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d亦可被形成為具有大的尺寸。另一方面，可以相對小的尺寸來形成第二互連構件140的重佈線層142以達成薄度。The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first interconnecting member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnecting member 140. Since the thickness of the first interconnecting member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed. To have a large size. On the other hand, the redistribution layer 142 of the second interconnecting member 140 may be formed in a relatively small size to achieve thinness.

除上述配置之外的其他配置的說明等與上述說明重疊，且因此不再對其予以贅述。同時，上述扇出型半導體封裝100B至扇出型半導體封裝100F的說明亦可被應用於扇出型半導體封裝100H。Descriptions of other configurations than the above configurations overlap with the above description, and thus will not be described again. Meanwhile, the description of the fan-out type semiconductor package 100B to the fan-out type semiconductor package 100F can also be applied to the fan-out type semiconductor package 100H.

如以上所提出，根據本發明中的示例性實施例，可提供一種其板級可靠性得以提高的扇出型半導體封裝。As proposed above, according to an exemplary embodiment of the present invention, a fan-out type semiconductor package whose board level reliability can be improved can be provided.

儘管以上已示出並闡述了各示例性實施例，然而對於熟習此項技術者而言將顯而易見，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出修改及變型。While the various exemplary embodiments have been shown and described, it will be understood by those skilled in the art that modifications and modifications may be made without departing from the scope of the invention as defined by the scope of the appended claims. transform.

100‧‧‧半導體封裝100‧‧‧Semiconductor package

100A、100B、100C、100D、100E、100F、100G、100H、2100‧‧‧扇出型半導體封裝100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 2100‧‧‧ Fan-out semiconductor packages

110‧‧‧第一互連構件110‧‧‧First interconnected component

110H‧‧‧貫穿孔110H‧‧‧through hole

111、111a、111b、111c、141、2141、2241‧‧‧絕緣層111, 111a, 111b, 111c, 141, 2141, 2241‧ ‧ insulation

112a、112b、112c、112d‧‧‧重佈線層112a, 112b, 112c, 112d‧‧‧ rewiring layer

113、143、161a、161b、161c、161d、161e、161f、161g、161h、161i、2143、2243‧‧‧介層窗113, 143, 161a, 161b, 161c, 161d, 161e, 161f, 161g, 161h, 161i, 2143, 2243‧‧

120、2120、2220‧‧‧半導體晶片120, 2120, 2220‧‧‧ semiconductor wafer

121、1101、2121、2221‧‧‧主體121, 1101, 2121, 2221‧‧‧ subjects

122、2122、2222‧‧‧連接墊122, 2122, 2222‧‧‧ connection pads

123、150、2150、2223、2250‧‧‧保護層123, 150, 2150, 2223, 2250‧‧ ‧ protective layer

130、2130‧‧‧囊封體130, 2130‧‧‧ Encapsulation

131、151、182、185、2251‧‧‧開口131, 151, 182, 185, 2251‧‧

140‧‧‧第二互連構件140‧‧‧Second interconnecting member

142、2142‧‧‧重佈線層142, 2142‧‧‧Rewiring layer

160、2160、2260‧‧‧凸塊下金屬層160, 2160, 2260‧‧‧ under bump metal layer

160a‧‧‧第一導體層160a‧‧‧First conductor layer

160b‧‧‧第二導體層160b‧‧‧Second conductor layer

162‧‧‧外部連接墊162‧‧‧External connection pads

170‧‧‧連接端子170‧‧‧Connecting terminal

181、183、191、192‧‧‧加強層181, 183, 191, 192‧‧ ‧ reinforcement layer

184‧‧‧樹脂層184‧‧‧ resin layer

191P、192P‧‧‧凹坑191P, 192P‧‧‧ pit

1000‧‧‧電子裝置1000‧‧‧Electronic devices

1010、1110、2500‧‧‧主板1010, 1110, 2500‧‧‧ motherboard

1020‧‧‧晶片相關組件1020‧‧‧ wafer related components

1030‧‧‧網路相關組件1030‧‧‧Network related components

1040‧‧‧其他組件1040‧‧‧Other components

1050、1130‧‧‧照相機模組1050, 1130‧‧‧ camera module

1060‧‧‧天線1060‧‧‧Antenna

1070‧‧‧顯示器裝置1070‧‧‧Display device

1080‧‧‧電池1080‧‧‧Battery

1090‧‧‧訊號線1090‧‧‧Signal line

1100‧‧‧智慧型電話1100‧‧‧Smart Phone

1120‧‧‧電子組件1120‧‧‧Electronic components

2140、2240‧‧‧互連構件2140, 2240‧‧‧ interconnected components

2170、2270‧‧‧焊料球2170, 2270‧‧‧ solder balls

2200‧‧‧扇入型半導體封裝2200‧‧‧Fan-in semiconductor package

2242‧‧‧配線圖案2242‧‧‧Wiring pattern

2243h‧‧‧介層窗孔2243h‧‧・Intermediate window hole

2280‧‧‧底部填充樹脂2280‧‧‧ underfill resin

2290‧‧‧模製材料2290‧‧‧Molded materials

2301、2302‧‧‧插入式基板2301, 2302‧‧‧ insert substrate

C‧‧‧區C‧‧‧ District

I-I’、II-II’、III-III’‧‧‧線I-I’, II-II’, III-III’‧‧‧ lines

t1、t2‧‧‧厚度T1, t2‧‧‧ thickness

藉由結合附圖閱讀以下詳細說明，將更清晰地理解本發明的以上及其他態樣、特徵、及優點，在附圖中： 圖1是說明電子裝置系統的實例的示意性方塊圖。 圖2是說明電子裝置的實例的示意性立體圖。 圖3A及圖3B是說明扇入型半導體封裝在被封裝之前及被封裝之後的狀態的示意性剖視圖。 圖4是說明扇入型半導體封裝的封裝製程的示意性剖視圖。 圖5是說明扇入型半導體封裝安裝於插入式基板上且最終安裝於電子裝置的主板上的情形的示意性剖視圖。 圖6是說明扇入型半導體封裝嵌於插入式基板中且最終安裝於電子裝置的主板上的情形的示意性剖視圖。 圖7是說明扇出型半導體封裝的示意性剖視圖。 圖8是說明扇出型半導體封裝安裝於電子裝置的主板上的情形的示意性剖視圖。 圖9是說明扇出型半導體封裝的實例的示意性剖視圖。 圖10是沿圖9所示的扇出型半導體封裝的線I-I’截取的示意性平面圖。 圖11A及圖11B分別是說明圖9所示的扇出型半導體封裝的保護層的開口及凸塊下金屬層的經修改實例的示意性剖視圖及示意性平面圖。 圖12A及圖12B分別是說明圖9所示的扇出型半導體封裝的保護層的開口及凸塊下金屬層的另一經修改實例的示意性剖視圖及示意性平面圖。 圖13是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖14是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖15是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖16是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖17是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖18是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖19是說明扇出型半導體封裝的另一實例的示意性剖視圖。The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following description of the appended claims. FIG. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before being packaged and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package. 5 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device. Fig. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. 8 is a schematic cross-sectional view illustrating a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. Figure 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package shown in Figure 9. 11A and 11B are respectively a schematic cross-sectional view and a schematic plan view illustrating a modified example of the opening of the protective layer and the under-bump metal layer of the fan-out type semiconductor package shown in Fig. 9. 12A and 12B are respectively a schematic cross-sectional view and a schematic plan view illustrating another modified example of the opening of the protective layer and the under-bump metal layer of the fan-out type semiconductor package shown in Fig. 9. Figure 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. Fig. 14 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. Fig. 15 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. Fig. 16 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. Figure 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. Figure 18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Claims (24)

一種扇出型半導體封裝，包括： 第一互連構件，具有貫穿孔； 半導體晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊； 囊封體，囊封所述第一互連構件的至少某些部分及所述半導體晶片的所述被動表面的至少某些部分； 第二互連構件，安置於所述第一互連構件上及所述半導體晶片的所述主動表面上；以及 保護層，安置於所述第二互連構件上， 其中所述第一互連構件及所述第二互連構件各自包括電性連接至所述半導體晶片的所述連接墊的重佈線層； 所述第二互連構件包括絕緣層，所述第二互連構件的所述重佈線層安置於所述絕緣層上，且 所述保護層的彈性模數較所述第二互連構件的所述絕緣層的彈性模數大。A fan-out type semiconductor package comprising: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface and a passive opposite to the active surface a surface on which the connection pad is disposed; an encapsulation encapsulating at least some portions of the first interconnect member and at least portions of the passive surface of the semiconductor wafer; a member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; and a protective layer disposed on the second interconnecting member, wherein the first interconnecting member and the The second interconnecting members each include a redistribution layer electrically connected to the connection pads of the semiconductor wafer; the second interconnecting member includes an insulating layer, the redistribution layer of the second interconnecting member is disposed And on the insulating layer, and the elastic modulus of the protective layer is larger than the elastic modulus of the insulating layer of the second interconnecting member. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述保護層的厚度為10微米或大於10微米。The fan-out type semiconductor package of claim 1, wherein the protective layer has a thickness of 10 μm or more. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述保護層的表面粗糙度為1奈米或大於1奈米。The fan-out type semiconductor package according to claim 1, wherein the protective layer has a surface roughness of 1 nm or more. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述保護層的吸水率為1.5%或小於1.5%。The fan-out type semiconductor package according to claim 1, wherein the protective layer has a water absorption ratio of 1.5% or less. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第二互連構件的所述絕緣層是感光性絕緣層，且 所述保護層是包含無機填料的非感光性絕緣層。The fan-out type semiconductor package according to claim 1, wherein the insulating layer of the second interconnecting member is a photosensitive insulating layer, and the protective layer is a non-photosensitive insulating layer containing an inorganic filler. . 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一互連構件包括第一絕緣層、第一重佈線層以及第二重佈線層，所述第一重佈線層與所述第二互連構件接觸並嵌於所述第一絕緣層中，所述第二重佈線層安置於所述第一絕緣層的與所述第一絕緣層的嵌有所述第一重佈線層的一個表面相對的另一表面上，且 所述第一重佈線層及所述第二重佈線層電性連接至所述連接墊。The fan-out type semiconductor package of claim 1, wherein the first interconnecting member comprises a first insulating layer, a first redistribution layer, and a second redistribution layer, the first redistribution layer and The second interconnecting member is in contact with and embedded in the first insulating layer, and the second redistribution layer is disposed on the first insulating layer and the first insulating layer is embedded with the first weight The other surface of the wiring layer is opposite to the other surface, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pad. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第一互連構件更包括第二絕緣層及第三重佈線層，所述第二絕緣層安置於所述第一絕緣層上且覆蓋所述第二重佈線層，所述第三重佈線層安置於所述第二絕緣層上，且 所述第三重佈線層電性連接至所述連接墊。The fan-out type semiconductor package of claim 6, wherein the first interconnecting member further comprises a second insulating layer and a third redistribution layer, wherein the second insulating layer is disposed on the first insulating layer And covering the second redistribution layer, the third redistribution layer is disposed on the second insulation layer, and the third redistribution layer is electrically connected to the connection pad. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第二互連構件的所述重佈線層與所述第一重佈線層之間的距離大於所述第二互連構件的所述重佈線層與所述連接墊之間的距離。The fan-out type semiconductor package of claim 6, wherein a distance between the redistribution layer of the second interconnecting member and the first redistribution layer is greater than the second interconnecting member The distance between the redistribution layer and the connection pad. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第一重佈線層的厚度較所述第二互連構件的所述重佈線層的厚度大。The fan-out type semiconductor package of claim 6, wherein the first redistribution layer has a thickness greater than a thickness of the redistribution layer of the second interconnect member. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第一重佈線層的下表面安置於高於所述連接墊的下表面的水平高度上。The fan-out type semiconductor package according to claim 6, wherein a lower surface of the first redistribution layer is disposed at a level higher than a lower surface of the connection pad. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第二重佈線層安置於所述半導體晶片的所述主動表面與所述被動表面之間的水平高度上。The fan-out type semiconductor package of claim 6, wherein the second redistribution layer is disposed at a level between the active surface of the semiconductor wafer and the passive surface. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一互連構件包括第一絕緣層、分別安置於所述第一絕緣層的相對的表面上的第一重佈線層及第二重佈線層、安置於所述第一絕緣層上並覆蓋所述第一重佈線層的第二絕緣層以及安置於所述第二絕緣層上的第三重佈線層，且 所述第一重佈線層至所述第三重佈線層電性連接至所述連接墊。The fan-out type semiconductor package of claim 1, wherein the first interconnecting member comprises a first insulating layer, and a first redistribution layer respectively disposed on opposite surfaces of the first insulating layer And a second redistribution layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and The first redistribution layer to the third redistribution layer are electrically connected to the connection pad. 如申請專利範圍第12項所述的扇出型半導體封裝，其中所述第一互連構件更包括安置於所述第一絕緣層上並覆蓋所述第二重佈線層的第三絕緣層以及安置於所述第三絕緣層上的第四重佈線層，且 所述第四重佈線層電性連接至所述連接墊。The fan-out type semiconductor package of claim 12, wherein the first interconnecting member further comprises a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and And a fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. 如申請專利範圍第12項所述的扇出型半導體封裝，其中所述第一絕緣層的厚度較所述第二絕緣層的厚度大。The fan-out type semiconductor package of claim 12, wherein the first insulating layer has a thickness greater than a thickness of the second insulating layer. 如申請專利範圍第12項所述的扇出型半導體封裝，其中所述第三重佈線層的厚度較所述第二互連構件的所述重佈線層的厚度大。The fan-out type semiconductor package according to claim 12, wherein the thickness of the third redistribution layer is larger than the thickness of the redistribution layer of the second interconnect member. 如申請專利範圍第12項所述的扇出型半導體封裝，其中所述第一重佈線層安置於所述半導體晶片的所述主動表面與所述被動表面之間的水平高度上。The fan-out type semiconductor package of claim 12, wherein the first redistribution layer is disposed at a level between the active surface of the semiconductor wafer and the passive surface. 如申請專利範圍第12項所述的扇出型半導體封裝，其中所述第三重佈線層的下表面安置於低於所述連接墊的下表面的水平高度上。The fan-out type semiconductor package of claim 12, wherein a lower surface of the third redistribution layer is disposed at a level lower than a lower surface of the connection pad. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述囊封體包含無機填料及絕緣樹脂。The fan-out type semiconductor package according to claim 1, wherein the encapsulant comprises an inorganic filler and an insulating resin. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括安置於所述囊封體上的加強層， 其中所述加強層的彈性模數較所述囊封體的彈性模數大。The fan-out type semiconductor package of claim 1, further comprising a reinforcing layer disposed on the encapsulant, wherein a modulus of elasticity of the reinforcing layer is larger than a modulus of elasticity of the encapsulant . 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 開口，穿透過所述保護層並暴露出所述第二互連構件的所述重佈線層的至少某些部分； 凸塊下金屬層，形成於所述開口上，且所述凸塊下金屬層連接至所述第二互連構件的經暴露的所述重佈線層；以及 連接端子，形成於所述凸塊下金屬層上，所述連接端子中的至少一者安置於扇出區中。The fan-out type semiconductor package of claim 1, further comprising: an opening penetrating through the protective layer and exposing at least some portions of the redistribution layer of the second interconnecting member; a lower underlying metal layer formed on the opening, and the under bump metal layer is connected to the exposed redistribution layer of the second interconnecting member; and a connection terminal formed under the bump On the metal layer, at least one of the connection terminals is disposed in the fan-out area. 如申請專利範圍第20項所述的扇出型半導體封裝，其中所述凸塊下金屬層包括外部連接墊及多個介層窗，所述外部連接墊形成於所述保護層上，所述多個介層窗形成於所述開口中且將所述外部連接墊與所述第二互連構件的所述重佈線層連接至彼此。The fan-out type semiconductor package of claim 20, wherein the under bump metal layer comprises an external connection pad and a plurality of vias, the external connection pads being formed on the protective layer, A plurality of vias are formed in the opening and connect the external connection pads and the redistribution layer of the second interconnect member to each other. 如申請專利範圍第21項所述的扇出型半導體封裝，其中在所述外部連接墊的表面上形成有各自對應於所述多個介層窗的多個凹坑。The fan-out type semiconductor package according to claim 21, wherein a plurality of pits respectively corresponding to the plurality of vias are formed on a surface of the external connection pad. 一種扇出型半導體封裝，包括： 第一互連構件，具有貫穿孔； 半導體晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊； 囊封體，囊封所述第一互連構件的至少某些部分及所述半導體晶片的所述被動表面的至少某些部分； 第二互連構件，安置於所述第一互連構件上及所述半導體晶片的所述主動表面上；以及 保護層，安置於所述第二互連構件上， 其中所述第一互連構件及所述第二互連構件各自包括電性連接至所述半導體晶片的所述連接墊的重佈線層， 所述第二互連構件包括絕緣層，所述第二互連構件的所述重佈線層安置於所述絕緣層上， 所述保護層及所述第二互連構件的所述絕緣層中的每一者包含無機填料及絕緣樹脂，且 所述保護層中所包含的所述無機填料的重量百分比大於所述第二互連構件的所述絕緣層中所包含的所述無機填料的重量百分比。A fan-out type semiconductor package comprising: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface and a passive opposite to the active surface a surface on which the connection pad is disposed; an encapsulation encapsulating at least some portions of the first interconnect member and at least portions of the passive surface of the semiconductor wafer; a member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; and a protective layer disposed on the second interconnecting member, wherein the first interconnecting member and the The second interconnecting members each include a redistribution layer electrically connected to the connection pads of the semiconductor wafer, the second interconnecting member including an insulating layer, the redistribution layer of the second interconnecting member disposed On the insulating layer, each of the protective layer and the insulating layer of the second interconnecting member comprises an inorganic filler and an insulating resin, and the inorganic filler contained in the protective layer weight Percentage points greater than said second inorganic insulating layer of the interconnecting member included in the weight of the filler. 一種扇出型半導體封裝，包括： 第一互連構件，具有貫穿孔； 半導體晶片，安置於所述第一互連構件的所述貫穿孔中並具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊； 囊封體，囊封所述第一互連構件的至少某些部分及所述半導體晶片的所述被動表面的至少某些部分； 第二互連構件，安置於所述第一互連構件上及所述半導體晶片的所述主動表面上； 保護層，安置於所述第二互連構件上且包括多個開口，所述多個開口暴露出所述第二互連構件的重佈線層的至少某些部分； 凸塊下金屬層，形成於所述多個開口上且連接至所述第二互連構件的經暴露的所述重佈線層；以及 連接端子，形成於所述凸塊下金屬層上並經由所述凸塊下金屬層電性連接至所述第二互連構件的所述重佈線層， 其中所述第一互連構件的重佈線層經由所述第二互連構件的所述重佈線層電性連接至所述半導體晶片的所述連接墊。A fan-out type semiconductor package comprising: a first interconnecting member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface and a passive opposite to the active surface a surface on which the connection pad is disposed; an encapsulation encapsulating at least some portions of the first interconnect member and at least portions of the passive surface of the semiconductor wafer; a member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; a protective layer disposed on the second interconnecting member and including a plurality of openings, the plurality of openings being exposed At least some portions of the redistribution layer of the second interconnect member; an under bump metal layer formed on the plurality of openings and connected to the exposed redistribution layer of the second interconnect member And a connection terminal formed on the under bump metal layer and electrically connected to the redistribution layer of the second interconnect member via the under bump metal layer, wherein the first interconnect member Heavy wiring layer Said second interconnecting member, said re-wiring layer is electrically connected to connection pads of the semiconductor wafer.
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