TW201810271A - Five-transistor static random access memory for effectively preventing the difficulty of writing logic 1 in the write mode and improving the read speed in the read mode while avoiding unnecessary power consumption - Google Patents

Abstract

The present invention provides a 5T (five-transistor) static random access memory (SRAM), which comprises a memory array, a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby startup circuit (4), and a plurality of word line voltage level conversion circuits (5). The memory array is composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each row of memory cells is provided with a control circuit, and each memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12) and an access transistor (composed of a third NMOS transistor M13). Each control unit (2) is connected to the source of the first NMOS transistor (M11) and the source of the second NMOS transistor (M12) of each memory cell in the corresponding row of memory cells, so as to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes. As such, in the write mode, the difficulty of writing logic 1 can be effectively prevented and, in the read mode, the read speed can be improved while avoiding unnecessary power consumption. In the standby mode, leakage current can be effectively reduced. In the data-retaining mode, the original electrical characteristics can be retained. Furthermore, the standby startup circuit (4) is designed to effectively cause a single-port SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the 5T SRAM. In addition, through the design of the plurality of word line voltage level conversion circuits (5), the on-resistance of the third NMOS transistor (M13) in the read mode can be increased, thereby effectively reducing the half-selected cell disturbance in the reading process.

Description

5T static random access memory

The invention relates to a 5T port static random access memory (SRAM), in particular to a method that effectively improves the standby performance of the port SRAM, and can effectively improve the reading speed and reduce the leakage current ( Leakage current) and can effectively avoid unnecessary power loss in the port SRAM.

As shown in Figure 1a, the conventional 5T static random access memory (SRAM) mainly includes a memory array. The memory array is composed of a plurality of memory blocks (MB ₁ , MB ₂ and so on), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL ₂ etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to one in the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows a schematic circuit diagram of a 6T5T static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors, and the NMOS transistor (M1) ) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB It is a bit line and a complementary bit line, respectively. Since this SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) The other driving transistor is turned on, and the initial instantaneous voltage (V _AR ) read by node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 ( 1)

In order to effectively prevent half-selected cell disturbance during reading, V _AR represents the initial instantaneous voltage of node A, and R _M1 and R _M3 represent the NMOS transistor (M1) and The on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which results in the current driving capability between the driving transistor and the access transistor The ratio (that is, the cell ratio) is usually set between 2.2 and 3.5 (please refer to column 8-10 of column 2 of patent specification US76060B2 of October 20, 1998).

Figure 1b shows the simulation results of HSPICE transient analysis of the 6T5T static random access memory cell during a write operation. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T5T SRAM cell with a single bit line. Compared with the 6T5T SRAM cell in Figure 1b, this 5T SRAM cell The body cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width-to-length ratio of M2 and M3 (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell), there is a problem that it is quite difficult to write logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transmitted from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 And R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) and Equation (2), it can be seen that the initial instantaneous voltage (V _AW ) written is smaller than the NMOS transistor (M2) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

So far, many 5T static random access memory cell technologies with a single bit line have been proposed, such as the "Memory System" and patent documents proposed in Patent Document 1 (April 27, 1999, US7706203 B2). 2 (TWI426514 B of February 11, 103) "5T Static Random Access Memory Reducing Power Supply Voltage during Write Operation", Patent Document 3 (US2014 / 0029333 A1, January 30, 103 ), "Five Transistor SRAM Cell", Non-Patent Document 4 (Satyanand Nalam et al., "5T SRAM with asymmetric sizing for improved read stability", IEEE Journal of Solid-State Circuits. , Vol . 46.No. 10 , pp 2431-2442, Oct. 2011.), "High-performance 5T Static Random Access Memory" proposed by Patent Document 5 (TWI478165 of March 21, 104), Non-Patent Document 6 (Chua- Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and non-patent literature 7 (Shyam Akashe et al., "High density an d low leakage current based 5T SRAM cell using 45nm technology ", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.) and so on. Although these technologies can effectively solve writing Difficulties in entering logic 1, but none of these technologies take into account the word line voltage level conversion circuit to pull down the word line voltage applied to the access transistor of the selected cell to the selected cell during a read operation It is lower than the power supply voltage and cooperates with the first stage of the reading operation. The source voltage of the NMOS transistor (M11) is pulled down from the original ground voltage to lower than the ground voltage to effectively reduce the half selection during reading. While the cell interference can also effectively improve the reading speed, there is still room for improvement.

In view of this, a main object of the present invention is to propose a 5T static random access memory, which can use a word line voltage level conversion circuit to apply an access transistor to a selected cell during a read operation. The voltage of the word line is pulled down below the power supply voltage to effectively reduce half-selected cell interference during reading.

The secondary object of the present invention is to propose a 5T static random access memory, which can effectively improve the reading speed by the control circuit, and can improve the reading speed by the two-stage read control. Avoid unnecessary power loss.

Another object of the present invention is to provide a 5T static random access memory, which can effectively avoid the problem of writing logic 1 to a conventional port SRAM with a single bit line through a control circuit.

The invention provides a 5T static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of word lines. A voltage level conversion circuit (5). The memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells. Each column of memory cells is provided with a control circuit, and each memory cell ( 1) It consists of a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12) and an access transistor (composed of a third NMOS transistor M13). Each control unit (2) is connected to the source of the first NMOS transistor (M11) and the source of the second NMOS transistor (M12) connected to each memory cell in a corresponding row of memory cells. In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) according to different operation modes, thereby effectively preventing the write logic in the write mode 1 Difficult problem, in the reading mode, it can improve the reading speed while avoiding unnecessary power consumption. In the standby mode, it can effectively reduce the leakage current, and in the hold mode, it can maintain the original electrical characteristic. In addition, the design of the standby start circuit (4) can effectively promote the SRAM with a port to enter the standby mode quickly, and thus effectively improve the standby performance of the 5T static random access memory; in addition, by the plurality of words The element line voltage level conversion circuit (5) is designed to increase the on-resistance of the third NMOS transistor (M13) in the reading mode, and thus effectively reduce half-selected cell interference during reading.

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

BLB‧‧‧ Complementary Bit Line

MB ₁ ^… MB _k ‧‧‧Memory block

WL ₁ ^… WL _n ‧‧‧Character line

BL ₁ ^… BL _m ‧‧‧bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧Word line voltage level conversion Electric circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

BL‧‧‧bit line

WLC‧‧‧Word line control signal

S‧‧‧Standby mode control signal

/ S ‧‧‧ Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

WC‧‧‧Write control signal

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/ RC‧‧‧ Inverted read control signal

/ WC‧‧‧ Inverted write control signal

INV‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Third PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧Twelfth NMOS transistor

P41‧‧‧Fourth PMOS transistor

D2‧‧‧Second Delay Circuit

V _DD ‧‧‧ Power supply voltage

WL‧‧‧Character Line

C‧‧‧node

P51‧‧‧Fifth PMOS transistor

M51‧thirteenth NMOS transistor

M52‧‧‧14th NMOS Transistor

M28‧‧‧11th NMOS transistor

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a schematic circuit diagram of the preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention during writing in FIG. 5; and FIG. 7 is a diagram of the fifth embodiment. The timing diagram of the write operation of the preferred embodiment of the invention; Figure 8 is a simplified circuit diagram showing the preferred embodiment of the invention during reading in Figure 5; Figure 9 is the preferred embodiment of the invention shown in Figure 5 Simplified circuit diagram during standby.

According to the above main object, the present invention proposes a 5T static random access memory, which mainly includes a memory array. The memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells. The memory cell and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) promotes the SRAM to enter the standby mode quickly to effectively improve the standby performance of the SRAM; and A plurality of word line voltage level conversion circuits (5), and each column of the memory cell is provided with a word line voltage level conversion circuit (5).

For the convenience of explanation, the static random access memory shown in Figure 5 consists of only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit. The circuit (2), a precharge circuit (3), a standby start circuit (4), and a word line voltage level conversion circuit (5) are described as examples. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) The crystal P12 is composed of a second NMOS transistor M12) and a third NMOS transistor (M13), wherein the first inverter and the second inverter are mutually coupled and connected, that is, the first inverter The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first inverter, and the first inverter The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel aspect ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also has the same channel width-to-length ratio

Please refer to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal ( / WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the inverted standby mode control signal (/ S) and a second low voltage node (VL2); the fifth NMOS transistor (M22) source, gate and drain are connected separately To the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate And the drain are connected to the first low voltage node (VL1); the source, gate, and drain of the seventh NMOS transistor (M24) are connected to the eighth NMOS transistor (M25) ) 'S drain, the read control signal (RC) and the first low voltage node (VL1); the source, gate and drain of the eighth NMOS transistor (M25) are connected to the accelerated read respectively The voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the third inverter (INV) Between the output and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the first delay circuit (D1) input; the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27), and the first low-voltage node (VL1); the first The source, gate and drain of the ten NMOS transistor (M27) are connected to the gate of the standby mode control signal (S), the write control signal (WC) and the ninth NMOS transistor (M26), respectively. ; And the source, gate, and drain of the eleventh NMOS transistor (M28) are connected to the inverted standby mode control signal (/ S), the inverted write control signal (/ WC), and the Gate of the ninth NMOS transistor (M26). It is worth noting here that the inverted standby mode control signal (/ S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/ WC) is obtained by The write control signal (WC) is obtained via another inverter.

It is worth noting here that the drain of the tenth NMOS transistor (M27), the drain of the eleventh NMOS transistor (M28) and the gate of the ninth NMOS transistor (M26) are connected together. A node (C) is formed. The logic high level of the node (C) is a voltage level at which a power supply voltage (V _DD ) is deducted from a threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28). Therefore, when the 5T static random access memory is in a non-write mode (the corresponding inverted write control signal (/ WC) is a logic high level at this time), the node (C) is the power supply voltage (V _DD ) _deducts the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), instead of the voltage level of the power supply voltage (V _DD ), so it can have a lower Power consumption; and when the write mode is subsequently entered (when the corresponding write control signal (WC) is at a logic high level), the charge stored in the node (C) can be quickly passed through the tenth NMOS power The crystal (M27) is discharged enough to turn off the ninth NMOS transistor (M26) with the node (C) as a gate, so it can enter the write mode relatively quickly.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (i.e., the first low voltage node VL1) of the driving transistor (i.e., the first NMOS transistor M11) that is closer to the bit line (BL) is set to a predetermined voltage (i.e. The gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (i.e., the second NMOS transistor M12) in the selected unit cell (i.e., the second NMOS transistor M12) The low-voltage node VL2) is set to a ground voltage to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (BL) in the selected cell is selected. ) Is set to the accelerated reading voltage (RGND) which is lower than the ground voltage, and the accelerated reading voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed, and in the second stage of the reading mode The source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the selected unit cell is set back to the ground voltage, so as to reduce unnecessary power consumption. Power consumption, wherein the time interval between the second stage and the first stage of the read mode is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the eighth NMOS transistor. The gate voltage of (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit (D1). Provide the delay time to adjust.

In the standby mode, the source voltages of the driving transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current. In the hold mode, the driving voltages in the memory cells are set. The source voltage of the crystal is set to ground voltage in order to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W ) Signal and the word line (WL) signal are at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal (R) and the word The result of the AND operation of the element line (WL) signal. It is worth noting here that for this read during non-read mode The control signal (RC) is set to the level of the accelerated read voltage (RGND) to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to Fig. 5. The precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that during the precharge period, the precharge signal (P ) To pre-charge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 5 again, the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fourth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S), and the twelfth NMOS transistor. The drain of (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

Please refer to FIG. 5 again, the word line voltage level conversion circuit (5) is composed of a fifth PMOS transistor (P51), a thirteenth NMOS transistor (M51), and a fourteenth NMOS transistor ( M52), the read control signal (RC), the inverted write control signal (/ WC), an inverted read control signal (/ RC), and a word line control signal (WLC). The source, gate, and drain of the fifth PMOS transistor (P51) are connected to the word line (WL), the inverted write control signal (/ WC), and the word line control signal (WLC), respectively. ); The thirteenth NMOS The source, gate, and drain of the transistor (M51) are connected to the word line control signal (WLC), the read control signal (RC), and the word line (WL) respectively; and the fourteenth The source, gate and drain of the NMOS transistor (M52) are connected to the word line control signal (WLC), the inverted read control signal (/ RC) and the word line (WL), respectively.

The detailed working voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

V _TM51 represents the threshold voltage of the thirteenth NMOS transistor (M51). It is worth noting here that on the one hand, the present invention uses a two-stage read control to improve the reading speed while avoiding unnecessary power loss, and on the other hand, the word line voltage level conversion circuit ( 5) During the reading operation, the word line voltage applied to the access transistor of the selected cell is _pulled down to a voltage lower than the power supply voltage (that is, V _DD -V _TM51 ) to effectively reduce the half of the reading time. Selected cell interference.

The working mode of the Ziyibu SRAM is described in Figure 5. The working principle of the preferred embodiment of the present invention is as follows:

(I) write mode

Before the write operation starts, the inverted write control signal (/ WC) is at a logic high level, so that the The eleventh NMOS transistor (M28) is turned on and the tenth NMOS transistor (M27) is turned off (OFF). At this time, the inverting standby mode control signal (/ S) is at a logic high level, so The drain of the eleventh NMOS transistor (M28) is at a logic high level, and the drain of the eleventh NMOS transistor (M28) at the logic high level will turn on the ninth NMOS transistor (M26), and The low-voltage node (VL1) is brought to a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, but at this time, the standby mode control signal (S) is at a logic low level, which makes the drain of the tenth NMOS transistor (M27) At a logic low level, the drain of the tenth NMOS transistor (M27) at the logic low level will cause the ninth NMOS transistor (M26) to turn off and make the low voltage node (VL1) equal to the sixth NMOS transistor The gate-source voltage V _{GS (M26) of the} crystal (M23) can effectively prevent the problem of writing logic 1 effectively. FIG. 6 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during a writing period.

The following describes how the write operation of the preferred embodiment of the present invention shown in FIG. 6 is completed according to the four write states of the port SRAM.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) changes from OFF to OFF Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first NMOS transistor (M11) is turned on. Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the node A The voltage of R is increased following the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, Because the bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the power supply voltage ( V _DD ) is the initial state of the voltage level, so the first PMOS transistor (P11) is still OFF, and the initial initial write voltage (V _AW ) of the node A satisfies equation (3): V _AW = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3)

Among them, V _AW represents the initial instantaneous voltage of node A, and R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor, respectively. (M23), and V _DD and V _TM12 respectively represent the power supply voltage and the threshold voltage of the second NMOS transistor (M12), so it can effectively avoid the problem of writing logic 1 because the third The NMOS transistor (M13) still works in the saturation region and the first NMOS transistor (M11) still works in the triode region, although the on-resistance (R) of the third NMOS transistor (M13) _M13 ) will be greater than the on-resistance (R _M11 ) of the first NMOS transistor (M11), but since the sixth NMOS transistor (M23) is diode-connected, it can be connected to the first low-voltage node (VL1 ) Provides a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23). As a result, the voltage value of the divided voltage level presented by node A will be higher than that of the fourth voltage level. The voltage level of the node A of the conventional 5T SRAM cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B will make the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value. The higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A. The The higher voltage level of node A passes through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of B will pass through the first inverter (consisting of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A will obtain a higher voltage level, and so on. Then, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

It is worth noting here that the first low-voltage node (VL1) originally stores logic 0 in node A, and while it is being written to logic 1, it has a gate-source voltage equal to that of the sixth NMOS transistor (M23). The voltage level of V _{GS (M23)} , and after the logic 1 is written, it will have a ground voltage level due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) changes from OFF to ON; at this time, because the bit line (BL) is High (the power supply voltage V _DD ), and because the first A PMOS transistor (P11) is still ON, so the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) changes from OFF to ON. At this time, because the bit line (BL) is Low (ground voltage), the node A and the The first low voltage node (VL1) is discharged to complete the logic 0 writing operation until the writing cycle ends.

The preferred embodiment of the present invention shown in FIG. 6 is the simulation result of HSPICE transient analysis during a write operation. As shown in FIG. 7, it is simulated using TSMC 90 nm CMOS process parameters. From the simulation result, It can be confirmed that the 5T static random access memory proposed by the present invention can effectively increase the voltage level of the first low voltage node (VL1) during writing to effectively avoid the 5T static with a single bit line. The random access memory cell suffers from the difficulty of writing logic 1.

(II) read mode

Before the read operation starts, the write control signal (WC) and the standby mode control signal (S) are logic low levels, and the inverted write control signal (/ WC) and the inverted standby mode control signal (/ S) are logic low levels, making the eleventh NMOS transistor (M28) on and turning the tenth NMOS transistor (M27) off, so the node C is at a logic high level, The node C will turn on the ninth NMOS transistor (M26), and make the first low voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.

The preferred embodiment of the present invention shown in FIG. 6 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of a reading operation, the reading The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is approximately The accelerated reading voltage (RGND) whose ground voltage is low, and the accelerated reading voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of one of the read operations, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor (M25) is turned off, so the first low voltage node (VL1) will be at a ground voltage through the ninth NMOS transistor (M26) that is turned on, thereby effectively reducing unnecessary power consumption. It is worth noting here that the time interval between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level. The gate voltage of the eight NMOS transistor (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit. (D1) Adjust the delay time provided. Moreover, the ninth NMOS transistor (M26) is in a conducting state regardless of whether the first stage or the second stage of the read operation (because the gate of the ninth NMOS transistor (M26) is at the power supply voltage). V _DD level). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during reading.

Next, the two read states of the port SRAM are used to explain how to set the accelerated read voltage (RGND) of the preferred embodiment of the present invention in FIG. 8 and how to reduce the half-selected cell interference during read.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON. The node (A) and the node (B) are respectively The power supply voltage (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the word line control signal (WLC) _deducts the threshold voltage (ie, V _DD -V _TM51 ) of the thirteenth NMOS transistor (M51) for the power supply voltage, the third NMOS voltage The crystal (M13) is turned on, thereby effectively maintaining the bit line (BL) to supply the power supply voltage until the end of the read cycle to successfully complete the read logic 1 operation. It is worth noting that, since the first low voltage node (VL1) is approximately the accelerated read voltage (RGND) at this time, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the The absolute value of the accelerated read voltage (RGND) is set to make the voltage level of the first low voltage node (VL1) smaller than the threshold voltage (V _TM11 ) of the first NMOS transistor (M11) when reading, of course, also The absolute value of the accelerated read voltage (RGND) can be set more conservatively than the threshold voltage (V _TM11 ) of the first NMOS transistor (M11), that is, | RGND | <V _TM11 (4) where, | RGND | and V _TM11 respectively represent the absolute value of the accelerated read voltage and the threshold voltage of the first NMOS transistor (M11).

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is ON and the second NMOS transistor (M12) is OFF. The node (A) and the node (B) are respectively The ground voltage and the power supply voltage (V _DD ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). Because the first NMOS transistor (M11) is ON, when the read operation starts, the word line control signal (WLC) changes from Low (ground voltage) to High (the power supply voltage deducts the thirteenth NMOS Threshold voltage V _DD -V _{TM51 of} transistor M51). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, The initial instantaneous voltage (V _AR ) of this node A must satisfy equation (5): V _AR = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥R _M26 ) / (R _M13 + R _M11 + ( R _M24 + R _M25 ) ∥R _M26 ) + RGND × (R _M11 + R _M13 ) ∥R _M26 / (R _M24 + R _M25 + (R _M11 + R _M13 ) ∥R _M26 ) × R _M13 / (R _M11 + R _M13 ) <V _TM12 (5), where V _AR represents the initial instantaneous voltage when node A reads logic 0, and R _M11 , R _M13, R _M24, R _M25 and R _M26 respectively represent the first NMOS transistor (M11 ), The on resistance of the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the ninth NMOS transistor (M26), and V _DD , RGND And V _TM12 represent the _threshold voltages of the power supply voltage (V _DD ), the accelerated read voltage (RGND), and the second NMOS transistor (M12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) of the present invention during reading is set to the power supply voltage to _deduct the threshold voltage (V _DD -V _TM51 ) of the thirteenth NMOS transistor (M51), which On the one hand, the half-selected cell interference during reading can be effectively reduced; on the other hand, the on-resistance (R _M13 ) of the third NMOS transistor (M13) can be increased to easily satisfy Equation (5).

(III) Standby mode

First, explain how the standby start circuit (4) in Fig. 5 prompts the port SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: (1) before entering the standby mode, the inverted standby mode control signal (/ S ) Is logic High. The inverted standby mode control signal (/ S) of the logic High turns off the fourth PMOS transistor (P41) and turns on the twelfth NMOS transistor (M41). (2) After entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of the logic Low makes the fourth PMOS transistor (P41) ON, but within the initial period of the standby mode (the initial period is equal to the inversion standby mode control signal (/ S) transition from logic High to logic Low, to the twelfth NMOS transistor (M41) The gate voltage is enough time to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor ( M41) is still on, so the first low voltage node (VL1) can be quickly charged to the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V _TM23 ), that is, the port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 5. In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/ S) is a logic low level, and the logic low level is the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are all equal to the voltage levels of the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 9. FIG. 9 describes the respective leakage currents I ₁ generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that because the second low voltage node (VL2 The voltage level of) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of node A being logic Low is also maintained at the voltage level of V _TM23 ) , And the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9 to explain the comparison of the static random access memory proposed by the present invention with the 6T SRAM of FIG. 1b in terms of leakage current. The leakage current I _{1 of the} third NMOS transistor (M13), because the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that the word line (WL) is in the standby mode Is set to ground voltage, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention It is a negative value. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the prior art in FIG. 1b is equal to 0. According to the gate-induced drain leakage (GIDL) effect Or according to the results of Figures 3 (A) and 3 (B) of Patent No. US6865119 on March 8, 2005, it can be known that for NMOS transistors, the sub-critical current when the gate-source voltage is -0.1 volt is about the gate The source voltage is 1% of the subcritical current at 0 volts, so the current flowing through the invention caused by the GIDL effect is caused by The leakage current I _{1 of} the third NMOS transistor (M13) is much smaller than that of the NMOS transistor (M3) of the prior art in FIG. 1b; further, the drain-source voltage of the third NMOS transistor (M13) of the present invention ( V _DS ) _deducts the voltage level of V _TM23 for the power supply voltage (V _DD ). In contrast, in the standby mode, the drain source voltage of the NMOS transistor (M3) of the traditional random access memory of FIG. (V _DS ) is equal to the power supply voltage (V _DD ). According to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor caused by the DIBL effect flows through the present invention. The leakage current I _{1 of} (M13) is also smaller than the NMOS transistor (M3) of the prior art in FIG. 1b; as a result, the leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention is much smaller than that of FIG. 1b. Those who are skilled in NMOS transistor (M3).

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 . Therefore, the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) _deducts the voltage level of the V _TM23 . In contrast, in the standby mode, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the prior art in FIG. 1b is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, in the standby mode, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the prior art in FIG. 1b is equal to 0, and the drain of the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first Figure 1b shows the NMOS transistor (M2) of the prior art. It can be known from the above analysis that the 5T static random access memory proposed by the present invention has a lower leakage current than the prior art of FIG. 1b.

(IV) Hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of the traditional 5T SRAM cell with a single bit line in Figure 3. I won't go into details here.

[Effect of Invention]

The 5T static random access memory proposed by the present invention has the following effects:

(1) High design freedom: Since the present invention reads logic 0, the storage node (A) is _pulled down to a threshold voltage (V _TM12 ) below the second NMOS transistor (M12). There are two mechanisms, one is The word line voltage level conversion circuit (5) is used to pull down the word line voltage applied to the selected transistor (ie, the third NMOS transistor M13) to a voltage lower than the power supply voltage (ie, V _DD -V _TM51 ), the other is to pull down the storage node (A) by the accelerated read voltage (RGND) lower than the ground voltage, so it has the effect of high design freedom;

(2) Effectively reduce half-selected cell interference during reading: The present invention can use a word line voltage level conversion circuit (5) to apply an access transistor (5) to a selected cell during a read operation ( That is, the word line voltage of the third NMOS transistor N13) is _pulled down to be lower than the power supply voltage (ie, V _DD -V _TM51 ). On the one hand, it can reduce the voltage of the third NMOS transistor (M13) in the half-selected cell. Read interference, on the other hand, can reduce the read interference of the first NMOS transistor (N11) in the semi-selected cell by reducing the accelerated read voltage (RGND) required to satisfy equation (5). Effectively reduce the effect of half-selected cell interference during reading;

(3) High read speed and avoid unnecessary power consumption: The present invention adopts a two-stage read operation. In the first stage of the read operation, the first low voltage node (VL1) is set to be lower than the ground voltage. Accelerate the read voltage (RGND) to effectively improve the read speed, and in the second stage of the read operation, set the first low voltage node (VL1) back to the ground voltage in order to reduce unnecessary power consumption;

(4) Quickly enter standby mode: Because the present invention is provided with a standby startup circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek to improve the standby efficiency of the port SRAM;

(5) Avoiding the difficulty of writing logic 1: In the writing operation of the present invention, the voltage level of the first low-voltage node (VL1) can be increased to effectively avoid the familiar port with a single bit line. SRAM has the problem of writing logic 1;

(6) Low standby current: Since the present invention is in the standby mode, the fifth NMOS transistor (M22) can be turned on to make the voltage level of the first low voltage node (VL1) equal to the first low voltage node (VL1). The voltage level of the second low voltage node (VL2) and the voltage levels are equal to the threshold voltage level of the sixth NMOS transistor (M23), so the invention also has the effect of low standby current;

(7) Low number of transistors: For a SRAM array with 1024 columns and 1024 rows, the conventional static random access memory array of Figure 1b, Figure 6T requires a total of 1024 × 1024 × 6 = 6,291,456 transistors. The static random access memory only needs at least 1024 × 1024 × 5 + 1024 × 24 + 6 = 5,267,462 transistors, which reduces the number of transistors by 16.3%.

(8) Effectively prevent the problem that the standby mode control signal (S) cannot be written to a logic high level due to unexpected factors when writing to logic 1: because the standby mode control signal (S) is a logic high On time, the voltage level of the node (C) is the ground voltage, so it can effectively prevent the standby mode control signal (S) from temporarily becoming a logic high level due to unexpected factors when writing to logic 1 and cannot be written Into the problem.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧Word line voltage level conversion circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

BL‧‧‧bit line

WLC‧‧‧Word line control signal

S‧‧‧Standby mode control signal

/ S ‧‧‧ Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

/ RC‧‧‧ Inverted read control signal

/ WC‧‧‧ Inverted write control signal

INV‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Third PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧Twelfth NMOS transistor

P41‧‧‧Fourth PMOS transistor

D2‧‧‧Second Delay Circuit

V _DD ‧‧‧ Power supply voltage

WL‧‧‧Character Line

R‧‧‧ Read signal

P51‧‧‧Fifth PMOS transistor

M51‧thirteenth NMOS transistor

M52‧‧‧14th NMOS Transistor

C‧‧‧node

WC‧‧‧ write control signal

Claims (10)

A 5T static random access memory includes: a memory array, the memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each row of memory cells and each row of memory cells Each cell contains a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells Set a pre-charge circuit (3); a standby start circuit (4), the standby start circuit (4) promotes the 5T static random access memory to quickly enter the standby mode to effectively improve the 5T static random access memory Standby performance; and a plurality of word line voltage level conversion circuits (5), each row of memory cell is provided with a word line voltage level conversion circuit (5); wherein each memory cell (1) It also includes a first inverter composed of a first PMOS transistor (P11) and a first NMOS transistor (M11). The first inverter is connected to a power supply voltage (V _DD ) And a first low voltage node (VL1); a second inverter is connected by a first PMOS transistor (P12) and a second NMOS transistor (M12) is composed of lines of the second inverter is connected between the power supply voltage (V _DD) and a second low voltage node (VL2); a The storage node (A) is formed by the output terminal of the first inverter; an inverting storage node (B) is formed by the output terminal of the second inverter; a third NMOS transistor ( M13) is connected between the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); wherein the first inverter and the second inverter The inverters are connected in an interactive coupling, that is, the output terminal of the first inverter (that is, the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (Ie, the inverting storage node B) is connected to the input terminal of the first inverter; and each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor ( M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor ( M27), an eleventh NMOS transistor (M2 8), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a Inverted write control signal (/ WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S); wherein the source, gate, and the fourth NMOS transistor (M21) are The drain is connected to the ground voltage, the inverting standby mode control signal (/ S), and the second low voltage node (VL2); the source, gate, and drain of the fifth NMOS transistor (M22) Respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage And the gate and the drain are connected together and connected to the first low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the eighth NMOS transistor The drain of the crystal (M25), the read control signal (RC) and the first low voltage node (VL1); the source, gate and drain of the eighth NMOS transistor (M25) are connected to the Speed up reading voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the output of the third inverter (INV) And the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the first delay circuit ( D1) input; the source, gate and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate, and drain of the tenth NMOS transistor (M27) are connected to the standby mode control signal (S), the write control signal (WC), and the ninth NMOS transistor, respectively The gate of (M26); the source, gate, and drain of the eleventh NMOS transistor (M28) are connected to the inverted standby mode control signal (/ S) and the inverted write control signal ( / WC) and the drain of the tenth NMOS transistor (M27); it is worth noting here that the drain of the tenth NMOS transistor (M27) and the drain of the eleventh NMOS transistor (M28) And the gate of the ninth NMOS transistor (M26) Connected together and form a node (C), the node (C) of the logic high level based deduct the eleventh NMOS transistor (M28) for the power supply voltage (V _DD) of the threshold voltage (V _TM28) of Voltage level, so when the 5T SRAM is in a non-write mode (at this time, the corresponding inverted write control signal (/ WC) is a logic high level), the node (C) is the The power supply voltage (V _DD ) is deducted from the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), rather than the voltage level of the power supply voltage (V _DD ). Lower power consumption; and when the write mode is subsequently entered (the corresponding write control signal (WC) is at a logic high level), the charge stored in the node (C) can be quickly passed through the first The ten NMOS transistors (M27) are discharged enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, so it can enter the write mode faster; among the non-read mode periods, The read control signal (RC) is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) from being in a non-read mode. Leakage current during the period; further, the standby start circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the sixth NMOS voltage during an initial period of entering the standby mode. The voltage level of the threshold voltage (V _TM23 ) of the crystal (M23); in addition, each word line voltage level conversion circuit (5) further includes: a fifth PMOS transistor (P51), a thirteenth NMOS transistor Crystal (M51), a fourteenth NMOS transistor (M52), the read control signal (RC), the inverted write control signal (/ WC), an inverted read control signal (/ RC), and the Word line control signal (WLC); wherein the source, gate, and drain of the fifth PMOS transistor (P51) are connected to a word line (WL), and the inverted write control signal (/ WC) and the word line control signal (WLC); the source, gate and drain of the thirteenth NMOS transistor (M51) are connected to the word line control signal (WLC) and the read control respectively The signal (RC) and the word line (WL); and the source, gate and drain of the fourteenth NMOS transistor (M52) are connected to the word line control signal (WLC) and the inversion Read control signal (/ R C) and the word line (WL); it is worth noting here that, during a read operation, the voltage level conversion circuit (5) of each word line selects the word line (WL) of the selected cell from The power supply voltage (V _DD ) is converted to the power supply voltage (V _DD ) and deducted from the threshold voltage (V _TM51 ) of the thirteenth NMOS transistor (M51) (that is, V _DD -V _TM51 ) and is provided to the Word line control signal (WLC); and during the write operation, the power supply voltage (V _DD ) of the word line (WL) of the selected cell is provided to the word line control signal (WLC) . The 5T static random access memory according to item 1 of the scope of patent application, wherein the first NMOS transistor (M11) and the second NMOS transistor (M12) in each memory cell (1) ) Have the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width-to-length ratio. The 5T static random access memory according to item 2 of the scope of patent application, wherein the accelerated read voltage (RGND) in each control circuit (2) is set to be lower than the ground voltage, and the acceleration The absolute value of the read voltage (RGND) is set to make the voltage level of the first low voltage node (VL1) smaller than the threshold voltage (V _TM11 ) of the first NMOS transistor (M11) during reading. The 5T static random access memory according to item 3 of the scope of patent application, wherein the absolute value of the accelerated read voltage (RGND) is set to be smaller than the threshold voltage (V of the first NMOS transistor (M11)). _TM11 ). The 5T static random access memory according to item 4 of the scope of patent application, wherein the write control signal (WC) in each control circuit (2) is a write signal (W) and the character The result of the AND gate operation of the line (WL) signal, that is, only when the write signal (W) and the word line (WL) signal are at a logic high level, the write control signal (WC) Is a logic high level, where the inverted write signal (/ W) is an inverted signal of the write signal (W). The 5T static random access memory described in item 5 of the scope of patent application, wherein the read control signal (RC) in each control circuit (2) is a read signal (R) and the character AND gate result of the line (WL) signal, that is, only when the read signal (R) and the word line (WL) signal are at a logic high level, the read control signal (RC) Is a logic high level. The 5T static random access memory according to item 6 of the scope of patent application, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P); The source, gate, and drain of the third PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P), and the bit line (BL), so that During a precharge period, the bit line (BL) is precharged to the level of the power supply voltage (V _DD ) by the precharge signal (P) at a logic low level. The 5T static random access memory described in item 7 of the scope of patent application, wherein the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), A second delay circuit (D2) and the inverting standby mode control signal (/ S); wherein a source, a gate and a drain of the fourth PMOS transistor (P41) are respectively connected to the power supply Voltage (V _DD ), the inverted standby mode control signal (/ S) and the drain of the twelfth NMOS transistor (M41); the source, gate and drain of the twelfth NMOS transistor (M41) The poles are respectively connected to the output of the first low voltage node (VL1), the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input connection of the second delay circuit (D2) To the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is connected to the gate of the twelfth NMOS transistor (M41). The 5T static random access memory according to item 8 of the scope of the patent application, wherein the initial period during which the standby start circuit (4) enters the standby mode is equal to the inverted standby mode control signal (/ S) by a logic high The time until the gate voltage of the twelfth NMOS transistor (M41) is enough to turn off the twelfth NMOS transistor (M41) is calculated from the quasi-transition to a logic low level, which can be achieved by the second delay circuit (D2 ) To adjust one of the delay times provided. The 5T static random access memory according to item 9 of the scope of the patent application, wherein the read operation of each memory cell (1) can be further subdivided into two phases, and one of the read operations The first stage is to set the first low voltage node (VL1) to the accelerated read voltage (RGND) which is lower than the ground voltage to effectively improve the read speed, and one of the read operations is second In this stage, the first low voltage node (VL1) is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second stage and the first stage of the read operation is equal to the read The control signal (RC) changes from a logic low level to a logic high level. The time until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by using the The falling delay time of the third inverter (INV) is adjusted with another delay time provided by the first delay circuit (D1).