TW201807801A - ESD metal-oxide-semiconductor field-effect transistor with substrate external resistance and manufacturing method thereof - Google Patents

Abstract

Disclosed is an electrostatic discharge protection (ESD) metal- oxide -semiconductor field-effect transistor with substrate external resistance and manufacturing method thereof. The resistors are utilized to connect the substrate pickups of the N-type metal oxide semiconductor field-effect transistor (NMOS) to improve the ESD protection of the butting and the inserted substrate pickup arrangements. By utilizing the characteristic that the single resistor or variable resistors are capable of cooperating with the butting or inserted substrate pickup arrangement, the ESD protection ability of the present application are better than that of the conventional arrangements.

Description

Electrostatic protection gold-oxygen half field effect transistor with external resistor of base and manufacturing method thereof

The invention relates to a gold oxide half field effect transistor with electrostatic protection and a manufacturing method thereof, in particular to an electrostatic protection effect which can effectively improve a gold oxide half field effect transistor through an external resistance method.

Electrostatic discharge (ESD) will cause serious reliability problems in semiconductor components and electronic systems, and the multi-finger layout type gate-grounded N-type MOS field-effect transistor (Grounded-gate n) -type MOSFET, GGNMOSFET) Due to the development of semiconductor technology with shrinking component sizes, the problem of uneven current distribution is generated, and the task of static protection can no longer be easily achieved.

Then, in order to improve the problem, the short-circuit type pedestal contact terminal pickups and the embedded substrate pickups are developed in the layout form by P-type base. The contact diffusion region is short-circuited or placed in the source region of the transistor, and the N-type MOSFET of the contact region of the contact terminal of the short-circuit or the implanted pedestal forms an N-type-P-N-type connection. A bipolar junction transistor (BJT) structure, thus creating a parasitic BJT, which initiates an electrostatic current to prevent electrostatic damage to the internal component circuitry. However, in advanced process technology, such as 0.18 micron process, the susceptor resistance (Rsub) of the parasitic bipolar transistor is too small due to short circuit or placement type layout, and the parasitic BJT is difficult to start, which still causes severe deterioration of electrostatic strength, resulting in N The MOSFET is damaged in advance.

In view of the above problems, an object of the present invention is to provide a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a pedestal external resistor for solving a conventional MOSFET. The shortcomings.

According to an object of the present invention, an electrostatic protection MOSFET having a pedestal external resistor is provided, comprising a plurality of N-type MOSFETs arranged in parallel, a plurality of first P-type contact diffusion regions, and a second P-type contact diffusion region, at least An N-type external resistor. The plurality of N-type MOSFETs each have a source region, a gate region, a drain region, and a P-type well region, the source region is at one end of the N-type MOSFET, the drain region is at the other end of the N-type MOSFET, and the gate region is at the source. Between the polar region and the bungee region, the P-type well region is located below the source region, the gate region, and the bungee region. A plurality of first P-type contact diffusion regions are distributed in a plurality of N-type MOSFET source regions. The second P-type contact diffusion region is surrounded by a plurality of N-type MOSFETs. One end of the N-type resistor is connected to the diffusion region of the first P-type contact terminal, and the other end is connected to a plurality of diffusion regions of the second P-type contact terminal and ground.

Preferably, the plurality of N-type MOSFETs are divided into a central region and a peripheral region, and the resistance value of the N-type resistor corresponding to the central region is small, and the resistance value of the N-type resistor corresponding to the peripheral region is large.

Preferably, the N-type external resistor may comprise an N-type well or an N-type diffusion region.

Preferably, the drain region has a metal halide isolation region configuration.

Preferably, the first P-type contact end diffusion region is adjacent to or spaced apart from the source region.

According to an object of the present invention, a method for fabricating a MOSFET with electrostatic protection includes the following method: configuring a plurality of N-type MOSFETs each having a source region, a gate region, a drain region, and a P-well region, Wherein, the source region is at one end of the N-type MOSFET, the drain region is at the other end of the N-type MOSFET, and the gate region is located between the source region and the drain region, and the P-type well region is located in the source region and the gate region. And under the bungee area. A plurality of first P-type contact diffusion regions are disposed in a plurality of N-type MOSFET source regions. A second P-type contact diffusion region is disposed to surround the periphery of the plurality of N-type MOSFETs. And configuring at least one N-type external resistor, wherein one end of the N-type resistor is connected to the first P-type contact end diffusion region, and the other end is connected to the plurality of second P-type contact end diffusion regions and ground.

Preferably, the plurality of N-type MOSFETs are divided into a central region and a peripheral region, and the resistance value of the N-type resistor corresponding to the central region is small, and the resistance value of the N-type resistor corresponding to the peripheral region is large.

Preferably, the N-type resistor may comprise an N-type well or an N-type diffusion region.

Preferably, the drain region has a metal halide isolation region configuration.

Preferably, the first P-type contact end diffusion region is adjacent to or spaced apart from the source region.

According to the above invention, the electrostatically protective gold-oxygen half field effect transistor and the method of manufacturing the same according to the present invention may have one or more of the following advantages:

(1) The gold-oxygen half-field effect transistor with electrostatic protection of the present invention can have a good electrostatic protection effect without excessively increasing the area.

(2) The electrostatically-protected gold-oxygen half-field effect transistor of the present invention can effectively improve the electrostatic protection effect in a simple manner through an external resistor.

The technical features, contents, and advantages of the present invention, as well as the advantages thereof, can be understood by the present inventors, and the present invention will be described in detail with reference to the accompanying drawings. The subject matter is only for the purpose of illustration and description, and is not necessarily the true proportion and precise configuration after the implementation of the present invention. Therefore, the scope and configuration relationship of the attached drawings should not be interpreted or limited. First described.

The embodiments of the smart effect device according to the present invention will be described below with reference to the related drawings. For the sake of understanding, the same components in the following embodiments are denoted by the same reference numerals.

Please refer to FIG. 1 to FIG. 2b respectively, which are respectively a cross-sectional view of the MOSFET of the present invention, a layout diagram of the short-circuit type pedestal contact terminal MOSFET of the present invention, and a layout diagram of the MOSFET contact terminal MOSFET of the present invention. As shown in the figure, the electrostatic protection metal oxide semiconductor field effect transistor of the present invention has a plurality of N-type MOSFETs 10, a second P-type contact diffusion region 20, and a plurality of first P-type contact diffusions. Zone 30 and pedestal 105.

Each of the N-type MOSFETs 10 has a source region 101, a gate region 102, a drain region 103, and a P-type well region 104. The source region 101 is located at one end of the N-type MOSFET 10, and the drain region 103 is located at the other end of the N-type MOSFET 10, and the gate region 102 is located between the source region 101 and the drain region 103, and has a metal on the drain region 103. The telluride isolation region configuration 1031. On the other hand, the P-type well region 104 is located below the source region 101, the gate region 102, and the drain region 103. The present invention is to adjust the susceptor resistance (Rsub) by the contact end of the external resistor connection base 105, and the present invention will be further disclosed below.

As shown in FIGS. 2a and 2b, the first P-type contact diffusion region 30 is placed in the N-type MOSFET 10 in addition to the second P-type contact diffusion region 20 surrounding the periphery of the plurality of N-type MOSFETs 10. Within the source region 101, thereby forming short-circuited pedestal contact tails and embedded substrate pickups, wherein the short-circuited pedestal contact diffusion region is The first P-type contact diffusion region 30 is disposed in the N-type source region 101 such that the first P-type contact diffusion region 30 is adjacent to the source region 101. Therefore, as shown in Fig. 2a, the short-circuit type pedestal contact terminal pickups in which the source region 101 and the first P-type contact-end diffusion region 30 are in contact are formed. The first pedestal diffusion diffusion region 30 is placed in the source region 101, but the first P-type contact diffusion region 30 is spaced apart from the source region 101. A well region or a substrate or the like is interposed therebetween to form an implanted substrate pickups, so that the equivalent susceptor resistance is larger than that of the short-circuit pedestal contact end.

Referring now to FIG. 3, which is a schematic diagram of the layout of an external variable resistance resistor transistor according to an embodiment of the present invention, as shown in FIG. 2a and FIG. 2b, in FIG. The N-type MOSFET 10 is short-circuited with an external resistor or placed at the contact end of the pedestal to improve the loss of the pedestal resistance in FIGS. 2b and 3, thereby changing the disadvantage of degradation of the electrostatic protection capability, so that the parasitic bipolar The transistor starts normally.

More specifically, the N-type MOSFET in FIG. 3 can be implemented in a 0.18 micron semiconductor process, and the external resistor is a plurality of N-type diffusion resistors 401, 402, and 403, and a plurality of N-type diffusion resistors 401 are connected in series with each other. , 402, 403, so that the N-type MOSFETs located at different positions may have different resistance values. For example, the N-type MOSFET 43 close to the N-type MOSFET 43 is a central region, so that only a section of the N-type diffusion resistor 403 is connected, and the resistance is small, and N The N-type MOSFET 41 on the right side of the MOSFET 42 is a peripheral region, so the length of the external N-type diffusion resistor is long and the resistance value is large. By this method, the current conduction is evenly distributed as much as possible. The length of the N-type diffusion resistor 401 can be 2.2 micrometers, the length of the N-type diffusion resistor 402 can be 2.6 micrometers, the length of the N-type diffusion resistor 403 can be 2.2 micrometers, and the N-type diffusion resistor 401 and the N-type diffusion resistor 402 And the width of the N-type diffusion resistor 403 can be 2.1 microns. Further, the N-type diffusion resistor 401, the N-type diffusion resistor 402, and the N-type diffusion resistor 403 may be replaced by an N-type well resistance.

Referring now to Figure 4, Figure 4 is a schematic illustration of the layout of a single resistive transistor in accordance with an embodiment of the present invention. In addition to being configured in the manner of FIG. 3, the present invention can also be connected to a short circuit or a contact end of a pedestal using a single N-type well resistor 501 as shown in FIG. 4, wherein the resistance value of the N-type well resistance 501 is approximately It is 1000 ohms, which can also effectively increase the electrostatic protection capability.

Referring now to FIGS. 3 and 4, the N-type diffusion resistor 401, the N-type diffusion resistor 402, the N-type diffusion resistor 403, and the N-type well resistor 501 are all connected to a short circuit inside the source or placed in the pedestal. The diffusion region 30 is contacted, and the other end is connected to the second P-type contact diffusion region 20 and grounded.

Please refer to FIG. 5a and FIG. 5b, which are respectively a graph of a variable resistance resistor transistor current and voltage measurement according to an embodiment of the present invention, and a single resistor transistor current and voltage measurement graph according to an embodiment of the present invention.

It can be seen from Fig. 5a that the resistance variable resistors are connected to the same resistance line resistance voltage under the same transmission line pulse voltage (TLP Voltage). The secondary breakdown current It2 in the measurement curve is significantly higher than that of the conventional external resistor transistor, and therefore has a better electrostatic protection effect.

Table 1 below shows the improved It2 current data of the external resistor of the short-circuit type pedestal contact end of the present invention and the conventional unconnected N-type resistor. The comparison in Table 1 represents the traditional condition, normal represents the 4 μm condition of the surrounding P-type diffusion region from the transistor, no-ring represents no peripheral surrounding P-type diffusion region, and ring 40 μm represents the peripheral surrounding P-type diffusion region from the transistor 40 μm. condition.

For example, in Table 1, it can be seen that the external resistance of the short-circuit type pedestal contact end diffusion region is 1.8V and 3.3V, whether it is an external 1000 ohm resistor (1K-NWR) or an external varistor resistance (var-NWR). Compared with the traditional conditions, it can effectively improve the It2 current data.

Table 1

It can be seen from Fig. 5b that the secondary breakdown current It2 in the current-voltage measurement curve of the single-resistance transistor is significantly higher than that of the single-resistance in the inserted substrate pickups. Conventional transistors that do not have an external resistor have a better electrostatic protection effect.

Table 2 below shows the improved It2 current data of the external N-type resistor and the non-external N-type resistor in the diffusion region of the contact-type contact end of the present invention. Similarly, Table 2 represents the traditional condition, normal represents the 4 μm condition of the surrounding P-type diffusion region from the transistor, no-ring represents no peripheral surrounding P-type diffusion region, and ring 40 μm represents the peripheral surrounding P-type diffusion region. Crystal 40 micron conditions.

As shown in Table 2, the short-circuit type pedestal contact end diffusion area external resistance is 1.8V and 3.3V, whether it is an external 1000 ohm resistor (1K-NWR) or an external varistor resistance (var-NWR) Compared with the traditional conditions, the It2 current data can be effectively improved.

Table 2

In summary, the present invention has an electrostatic protection MOSFET with a pedestal external resistor and a manufacturing method thereof, and the external varistor resistance or a single resistor can effectively improve the electrostatic protection of the MOSFET without excessively increasing the area. effect.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

10, 41, 42, 43‧‧‧N type MOSFET

30‧‧‧First P-type contact diffusion region

20‧‧‧Second P-type contact diffusion region

101‧‧‧ source area

102‧‧‧The gate area

103‧‧‧Bungee Area

1031‧‧‧Metal Telluride Isolation Zone Structure

104‧‧‧P type well area

105‧‧‧Base

401, 402, 403‧‧‧N type diffusion resistor

501‧‧‧N type well resistance

It2‧‧‧Second Crash Current

Figure 1 is a cross-sectional view of a MOSFET in accordance with an embodiment of the present invention.

Figure 2a is a schematic diagram of a short circuit type pedestal contact MOSFET layout in accordance with an embodiment of the present invention.

Figure 2b is a schematic diagram of the placement of a MOSFET contact terminal MOSFET in accordance with an embodiment of the present invention.

Fig. 3 is a schematic view showing the layout of a variable resistance resistor transistor according to an embodiment of the present invention.

Figure 4 is a schematic illustration of the layout of a single resistive transistor in accordance with an embodiment of the present invention.

Fig. 5a is a graph showing a current-voltage measurement curve of a variable resistance resistor transistor layout according to an embodiment of the present invention.

Figure 5b is a graph of a single resistor transistor layout current and voltage measurement in accordance with an embodiment of the present invention.

Claims (10)

A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) having a pedestal external resistor includes: a plurality of N-type MOSFETs juxtaposed, each of the plurality of N-type MOSFETs having a source a polar region, a gate region, a drain region, and a P-type well region, the source region being at one end of the N-type MOSFET, the drain region being at the other end of the N-type MOSFET, the gate region being located Between the source region and the drain region, the P-type well region is located under the source region, the gate region and the drain region; and the plurality of first P-type contact-end diffusion regions are distributed The plurality of N-type MOSFET source regions are connected to the P-type well region; a second P-type contact terminal diffusion region surrounds the plurality of N-type MOSFET peripherals; and at least one N-type resistor, wherein the N One end of the resistor is connected to the diffusion region of the first P-type contact terminal, and the other end is connected to the plurality of second P-type contact diffusion regions and ground. The electrostatic protection MOSFET with a pedestal external resistor according to claim 1, wherein the plurality of N-type MOSFETs are divided into a central region and a peripheral region, corresponding to the resistance value of the N-type resistor in the central region. It is small, and the resistance value of the N-type resistor corresponding to the peripheral region is large. The electrostatic protection MOSFET with a pedestal external resistor according to claim 1, wherein the N-type resistor comprises an N-type well or an N-type diffusion region. The electrostatic protection MOSFET with a pedestal external resistor as described in claim 1, wherein the drain region has a metal halide isolation region structure. The electrostatic protection MOSFET with a pedestal external resistor according to claim 1, wherein the first P-type contact diffusion region is adjacent to the source region or has a spacing from the source region. A method for manufacturing an electrostatic protection MOSFET with a pedestal external resistor includes the following methods: arranging a plurality of N-type MOSFETs each having a source region, a gate region, a drain region, and a P-well region, wherein The source region is at one end of the N-type MOSFET, and the drain region is at the other end of the N-type MOSFET. The gate region is located between the source region and the drain region, and the P-type well region is Located in the source region, the gate region and the drain region; and configuring a plurality of first P-type contact diffusion regions distributed in the source regions of the plurality of N-type MOSFETs, and the P-well region Connecting a second P-type contact diffusion region surrounding the periphery of the plurality of N-type MOSFETs; and configuring at least one N-type resistor, wherein the N-type resistor is connected to the first P-type contact diffusion region at one end, and One end is connected to the plurality of second P-type contact end diffusion regions and grounded. The method for manufacturing an electrostatic protection MOSFET with a pedestal external resistor according to claim 6, wherein the plurality of N-type MOSFETs are divided into a central region and a peripheral region, corresponding to the N-type resistor of the central region. The resistance value is small, and the resistance value of the N-type resistor corresponding to the peripheral region is large. The method for manufacturing an electrostatic protection MOSFET having a pedestal external resistor according to claim 6, wherein the N-type resistor comprises an N-type well or an N-type diffusion region. The method for manufacturing an electrostatic protection MOSFET with a pedestal external resistor according to claim 6, wherein the drain region has a metal telluride isolation region structure. The method for manufacturing an electrostatic protection MOSFET with a pedestal external resistor according to claim 6, wherein the first P-type contact end diffusion region is adjacent to the source region or has a spacing from the source region. .