TW201804580A - Substrate for package and manufacturing method thereof and package - Google Patents
Substrate for package and manufacturing method thereof and package Download PDFInfo
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- TW201804580A TW201804580A TW105123657A TW105123657A TW201804580A TW 201804580 A TW201804580 A TW 201804580A TW 105123657 A TW105123657 A TW 105123657A TW 105123657 A TW105123657 A TW 105123657A TW 201804580 A TW201804580 A TW 201804580A
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- conductor layer
- patterned conductor
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- substrate
- carrier
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- 239000000758 substrate Substances 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 238000010146 3D printing Methods 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims description 131
- 238000000034 method Methods 0.000 claims description 72
- 229910000679 solder Inorganic materials 0.000 claims description 38
- 238000007646 gravure printing Methods 0.000 claims description 6
- 238000007641 inkjet printing Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 104
- 239000000463 material Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229920001940 conductive polymer Polymers 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000005553 drilling Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
本發明是有關於一種封裝體用基板、其製造方法以及封裝體，且特別是有關於一種利用三維列印技術所製作的封裝體用基板、其製造方法以及封裝體。The present invention relates to a substrate for a package, a method for manufacturing the same, and a package, and more particularly to a substrate for a package produced by a three-dimensional printing technique, a method for manufacturing the same, and a package.
在半導體元件的封裝製程中，習知技術的導線架形式封裝往往受限於導線架單層結構與製造要求，無法自由進行導線架的線路設計。In the packaging process of a semiconductor component, the lead frame package of the prior art is often limited by the single-layer structure and manufacturing requirements of the lead frame, and the circuit design of the lead frame cannot be freely performed.
此外，採用可繞線設計的基板進行半導體封裝，就必須在基板上設計導通孔(via)以連接不同層間的線路。導通孔一般使用CNC機械或是雷射在基材上進行加工，其需要經由減薄、鑽孔、刷磨、沉積、電鍍與塞孔等多道製程才可實現導線互連。上述製造方法除了製造方法過於繁複外，更會造成對於材料使用的消耗和對環境產生的影響等缺點。In addition, for semiconductor packaging using a wire-wrapable substrate, vias must be designed on the substrate to connect the wires between the different layers. The vias are typically processed on a substrate using CNC machinery or lasers, which require wire bonding through multiple processes such as thinning, drilling, brushing, depositing, plating, and plugging. In addition to the cumbersome manufacturing method, the above manufacturing method has disadvantages such as consumption of materials and environmental impact.
本發明提出一種封裝體用基板，包括載板、第一圖案化導體層、第二圖案化導體層與三維列印導線。載板具有第一表面、第二表面與第三表面。第一表面相對於第二表面，且第三表面連接於第一表面與第二表面之間。第一圖案化導體層設置於第一表面上。第二圖案化導體層設置於第二表面上。三維列印導線設置於第三表面上，且連接於第一圖案化導體層與第二圖案化導體層之間。The invention provides a substrate for a package, comprising a carrier, a first patterned conductor layer, a second patterned conductor layer and a three-dimensional printed conductor. The carrier has a first surface, a second surface, and a third surface. The first surface is opposite the second surface, and the third surface is coupled between the first surface and the second surface. The first patterned conductor layer is disposed on the first surface. The second patterned conductor layer is disposed on the second surface. The three-dimensional printed wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer.
本發明提出一種封裝體用基板的製造方法，包括下列步驟。提供載板。載板具有第一表面、第二表面與第三表面。第一表面相對於第二表面，且第三表面連接於第一表面與第二表面之間。於第一表面上形成第一圖案化導體層。於第二表面上形成第二圖案化導體層。使用三維列印法於第三表面上形成三維列印導線。三維列印導線連接於第一圖案化導體層與第二圖案化導體層之間。The present invention provides a method of manufacturing a substrate for a package, comprising the following steps. A carrier board is provided. The carrier has a first surface, a second surface, and a third surface. The first surface is opposite the second surface, and the third surface is coupled between the first surface and the second surface. A first patterned conductor layer is formed on the first surface. A second patterned conductor layer is formed on the second surface. A three-dimensional printing line is formed on the third surface using three-dimensional printing. The three-dimensional printed conductor is connected between the first patterned conductor layer and the second patterned conductor layer.
本發明提出一種封裝體，包括封裝體用基板與第一電子元件。封裝體用基板包括載板、第一圖案化導體層、第二圖案化導體層與三維列印導線。載板具有第一表面、第二表面與第三表面。第一表面相對於第二表面，且第三表面連接於第一表面與第二表面之間。第一圖案化導體層設置於第一表面上。第二圖案化導體層設置於第二表面上。三維列印導線設置於第三表面上，且連接於第一圖案化導體層與第二圖案化導體層之間。第一電子元件設置於第一表面上，且電性連接於第一圖案化導體層。The invention provides a package comprising a substrate for a package and a first electronic component. The package substrate includes a carrier, a first patterned conductor layer, a second patterned conductor layer, and a three-dimensional printed conductor. The carrier has a first surface, a second surface, and a third surface. The first surface is opposite the second surface, and the third surface is coupled between the first surface and the second surface. The first patterned conductor layer is disposed on the first surface. The second patterned conductor layer is disposed on the second surface. The three-dimensional printed wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer. The first electronic component is disposed on the first surface and electrically connected to the first patterned conductor layer.
基於上述，在本發明所提出的封裝體用基板及其製造方法中，由於三維列印技術具有可於立體表面進行列印的特性，所以能夠利用三維列印法在載板的第三表面列印出三維列印導線，因此無須採用導通孔製程，即可藉由簡易的方式來完成第一圖案化導體層與第二圖案化導體層線路之間的互連，且更可依據封裝產品特性要求，設計基板外型以進行封裝。此外，上述封裝體用基板的製造方法可有效地降低生產複雜度與所需耗材，因此可有效地降低封裝體用基板的製造時程與成本。另外，在本發明所提出的封裝體中，由於使用了上述封裝體用基板，因此可具有較佳的設計彈性。Based on the above, in the substrate for a package and the method of manufacturing the same according to the present invention, since the three-dimensional printing technique has the characteristics of being printable on a three-dimensional surface, it is possible to use the three-dimensional printing method on the third surface of the carrier. The three-dimensional printed wiring is printed, so that the interconnection between the first patterned conductor layer and the second patterned conductor layer line can be completed in a simple manner without using a via process, and the package product characteristics can be further determined. It is required to design the substrate shape for packaging. Further, the method for manufacturing a substrate for a package described above can effectively reduce production complexity and required consumables, and thus can effectively reduce the manufacturing time and cost of the substrate for a package. Further, in the package proposed by the present invention, since the substrate for a package described above is used, it is possible to have a preferable design flexibility.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A、圖2A與圖3A為本發明一實施例的封裝體用基板的製造流程上視圖。圖1B、圖2B與圖3B分別為圖1A、圖2A與圖3A的右側視圖。圖1C、圖2C與圖3C分別為圖1A、圖2B與圖3A的下視圖。圖2D為沿圖2A中的I-I’剖面線的三維列印導線與載板交界處的剖面圖。圖3D為沿圖3A中的II-II’剖面線的三維列印導線與載板交界處的剖面圖。為了清楚地進行說明，在圖1B、圖2B與圖3B中省略繪示位於載板的第一表面與第二表面上的構件，在圖2D與圖3D中僅繪示出三維列印導線與載板。1A, 2A, and 3A are top views of a manufacturing process of a substrate for a package according to an embodiment of the present invention. 1B, 2B, and 3B are right side views of Figs. 1A, 2A, and 3A, respectively. 1C, 2C, and 3C are lower views of Figs. 1A, 2B, and 3A, respectively. Figure 2D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line I-I' in Figure 2A. Figure 3D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line II-II' in Figure 3A. For the sake of clarity, the members on the first surface and the second surface of the carrier are omitted in FIGS. 1B, 2B and 3B, and only the three-dimensional printed wires are illustrated in FIGS. 2D and 3D. Carrier board.
請參照圖1A至圖1C，提供載板100。載板100的材料可視封裝體的封裝要求而定。舉例來說，載板100的材料可為塑膠、陶瓷或玻璃等材料，以提供多樣化的封裝外型，且可用於各種半導體元件封裝。載板100具有第一表面102a、第二表面102b與第三表面102c。第一表面102a相對於第二表面102b，且第三表面102c連接於第一表面102a與第二表面102b之間。Referring to FIGS. 1A through 1C, a carrier 100 is provided. The material of the carrier 100 can depend on the packaging requirements of the package. For example, the material of the carrier 100 may be a material such as plastic, ceramic or glass to provide a variety of package shapes and can be used for various semiconductor component packages. The carrier 100 has a first surface 102a, a second surface 102b, and a third surface 102c. The first surface 102a is opposite the second surface 102b, and the third surface 102c is coupled between the first surface 102a and the second surface 102b.
此外，載板100可選擇性地具有位於載板100中的開口104或位於載板100的邊緣的至少一個缺口106。開口104與缺口106的形成方法例如是機械鑽孔、雷射鑽孔或藉由射出成型直接形成。在圖1A與圖1C中的缺口106的數量僅為舉例說明，本發明並不以此為限。Additionally, the carrier 100 can optionally have an opening 104 in the carrier 100 or at least one notch 106 at the edge of the carrier 100. The method of forming the opening 104 and the notch 106 is, for example, mechanical drilling, laser drilling or directly formed by injection molding. The number of notches 106 in FIGS. 1A and 1C is merely illustrative, and the invention is not limited thereto.
第三表面102c可為載板100中的開口104的表面、載板100邊緣的側面或載板100邊緣的缺口106的表面，但本發明並不以此為限。只要第三表面102c為連接於第一表面102a與第二表面102b之間的表面即屬於本發明所保護的範圍。在此實施例中，第三表面102c是以載板100中的開口104的表面與載板100的邊緣的缺口106的表面為例來進行說明。The third surface 102c may be the surface of the opening 104 in the carrier 100, the side of the edge of the carrier 100, or the surface of the notch 106 at the edge of the carrier 100, but the invention is not limited thereto. As long as the third surface 102c is a surface that is connected between the first surface 102a and the second surface 102b, it is within the scope of the present invention. In this embodiment, the third surface 102c is exemplified by the surface of the opening 104 in the carrier 100 and the surface of the notch 106 at the edge of the carrier 100.
請參照圖2A至圖2D，於第一表面102a上形成圖案化導體層108。圖案化導體層108可包括接點108a與導線108b，其中接點108a連接於導線108b。圖案化導體層108的材料可為銅、銀、金或導電高分子等導電材料，且其形成方法例如是藉由三維列印法、網版印刷法、噴墨印刷法、凹版印刷法、彈性印刷法或平版印刷法將銅膏、銀膏、金膏或導電高分子等導電材料列印在第一表面102a上。圖案化導體層108的形成方法更包括對列印在第一表面102a上的導電材料進行烘烤製程，其中烘烤製程的溫度例如是80℃至260℃。Referring to FIGS. 2A through 2D, a patterned conductor layer 108 is formed on the first surface 102a. The patterned conductor layer 108 can include contacts 108a and wires 108b with contacts 108a coupled to wires 108b. The material of the patterned conductor layer 108 may be a conductive material such as copper, silver, gold or a conductive polymer, and is formed by, for example, three-dimensional printing, screen printing, inkjet printing, gravure printing, and elasticity. A printing method or a lithography method prints a conductive material such as a copper paste, a silver paste, a gold paste or a conductive polymer on the first surface 102a. The method of forming the patterned conductor layer 108 further includes performing a baking process on the conductive material printed on the first surface 102a, wherein the temperature of the baking process is, for example, 80 ° C to 260 ° C.
於第二表面102b上形成圖案化導體層110。圖案化導體層110可包括接點110a與導線110b，其中接點110a連接於導線110b。圖案化導體層110的材料可為銅、銀、金或導電高分子等導電材料，且其形成方法例如是藉由三維列印法、網版印刷法、噴墨印刷法、凹版印刷法、彈性印刷法或平版印刷法將銅膏、銀膏、金膏或導電高分子等導電材料列印在第二表面102b上。圖案化導體層110的形成方法更包括對列印在第二表面102b上的導電材料進行烘烤製程，其中烘烤製程的溫度例如是80℃至260℃。A patterned conductor layer 110 is formed on the second surface 102b. The patterned conductor layer 110 can include a contact 110a and a wire 110b, wherein the contact 110a is connected to the wire 110b. The material of the patterned conductor layer 110 may be a conductive material such as copper, silver, gold or a conductive polymer, and is formed by, for example, three-dimensional printing, screen printing, inkjet printing, gravure printing, and elasticity. A printing method or a lithography method prints a conductive material such as a copper paste, a silver paste, a gold paste or a conductive polymer on the second surface 102b. The method of forming the patterned conductor layer 110 further includes performing a baking process on the conductive material printed on the second surface 102b, wherein the temperature of the baking process is, for example, 80 ° C to 260 ° C.
使用三維列印法於第三表面102c上形成三維列印導線112。在此實施例中，三維列印導線112可形成於開口104的表面上與缺口106的表面上。三維列印導線三維列印導線112連接於圖案化導體層108與圖案化導體層110之間。詳細來說，圖案化導體層108可經由導線108b、三維列印導線112與導線110b而電性連接至圖案化導體層110。三維列印導線112的材料可為銅、銀、金或導電高分子等導電材料，且其形成方法例如是藉由三維列印法將銅膏、銀膏、金膏或導電高分子等導電材料列印在第三表面102c上。三維列印導線112的形成方法更包括對列印在第三表面102c上的導電材料進行烘烤製程，其中烘烤製程的溫度例如是80℃至260℃。A three-dimensional printed conductor 112 is formed on the third surface 102c using three-dimensional printing. In this embodiment, a three-dimensional printed conductor 112 can be formed on the surface of the opening 104 and on the surface of the indentation 106. The three-dimensional printed conductor three-dimensional printed conductor 112 is connected between the patterned conductor layer 108 and the patterned conductor layer 110. In detail, the patterned conductor layer 108 can be electrically connected to the patterned conductor layer 110 via the wires 108b, the three-dimensionally printed wires 112 and the wires 110b. The material of the three-dimensional printing wire 112 may be a conductive material such as copper, silver, gold or a conductive polymer, and the forming method thereof is, for example, a conductive material such as a copper paste, a silver paste, a gold paste or a conductive polymer by a three-dimensional printing method. The print is on the third surface 102c. The method of forming the three-dimensional printed wiring 112 further includes performing a baking process on the conductive material printed on the third surface 102c, wherein the temperature of the baking process is, for example, 80 ° C to 260 ° C.
在此實施例中，藉由三維列印導線112突出於第一表面102a與第二表面102b，而使得三維列印導線112連接於圖案化導體層108與圖案化導體層110之間，但本發明並不以此為限。在另一實施例中，亦可藉由圖案化導體層108的導線108b突出於第一表面102a與圖案化導體層110的導線110b突出於第二表面102b，而使得三維列印導線112連接於圖案化導體層108與圖案化導體層110之間。於此技術領域具有通常知識者可依照製程需求來調整三維列印導線112連接於圖案化導體層108與圖案化導體層110之間的方式。In this embodiment, the three-dimensional printed conductor 112 is connected between the patterned conductor layer 108 and the patterned conductor layer 110 by the three-dimensional printed conductor 112 protruding from the first surface 102a and the second surface 102b. The invention is not limited to this. In another embodiment, the wire 110b protruding from the first surface 102a and the patterned conductor layer 110 protrudes from the second surface 102b by the wire 108b of the patterned conductor layer 108, so that the three-dimensional printed wire 112 is connected to Between the patterned conductor layer 108 and the patterned conductor layer 110. Those skilled in the art can adjust the manner in which the three-dimensional printed conductor 112 is connected between the patterned conductor layer 108 and the patterned conductor layer 110 in accordance with process requirements.
此外，圖案化導體層108、圖案化導體層110與三維列印導線112可分別形成或同時形成。亦即，圖案化導體層108、圖案化導體層110與三維列印導線112的形成順序可根據製程需求而定。In addition, the patterned conductor layer 108, the patterned conductor layer 110, and the three-dimensional printed wiring 112 may be formed separately or simultaneously. That is, the order in which the patterned conductor layer 108, the patterned conductor layer 110, and the three-dimensional printed wiring 112 are formed may be determined according to process requirements.
請參照圖3A至圖3D，可選擇性地於第一表面102a上形成防焊層114，可用以保護第一表面102a上的圖案化導體層108。防焊層114覆蓋圖案化導體層108且暴露出部分圖案化導體層108。舉例來說，防焊層114可暴露出圖案化導體層108的接點108a。此外，防焊層114更可覆蓋三維列印導線112的上表面。防焊層114的材料例如是絕緣材料，且其形成方法例如是三維列印法、網版印刷法、噴墨印刷法、凹版印刷法、彈性印刷法、平版印刷法或對感光性絕緣材料照射UV光而進行圖案化。Referring to FIGS. 3A-3D, a solder mask layer 114 may be selectively formed on the first surface 102a to protect the patterned conductor layer 108 on the first surface 102a. The solder resist layer 114 covers the patterned conductor layer 108 and exposes a portion of the patterned conductor layer 108. For example, the solder mask 114 may expose the contacts 108a of the patterned conductor layer 108. In addition, the solder resist layer 114 can cover the upper surface of the three-dimensional printed wiring 112. The material of the solder resist layer 114 is, for example, an insulating material, and the forming method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, an elastic printing method, a lithography method, or irradiation of a photosensitive insulating material. Patterning by UV light.
另外，可選擇性地於第二表面102b上形成防焊層116，可用以保護第二表面102b上的圖案化導體層110。防焊層116覆蓋圖案化導體層110且暴露出部分圖案化導體層110。舉例來說，防焊層116可暴露出圖案化導體層110的接點110a。此外，防焊層116更可覆蓋三維列印導線112的下表面。防焊層116的材料例如是絕緣材料，且其形成方法例如是三維列印法、網版印刷法、噴墨印刷法、凹版印刷法、彈性印刷法、平版印刷法或對感光性絕緣材料照射UV光而進行圖案化。此外，防焊層114與防焊層116可分別形成或同時形成。亦即，防焊層114與防焊層116的形成順序可根據製程需求而定。Additionally, a solder mask layer 116 may be selectively formed on the second surface 102b to protect the patterned conductor layer 110 on the second surface 102b. The solder resist layer 116 covers the patterned conductor layer 110 and exposes a portion of the patterned conductor layer 110. For example, the solder mask 116 may expose the contacts 110a of the patterned conductor layer 110. In addition, the solder resist layer 116 can cover the lower surface of the three-dimensional printed wiring 112. The material of the solder resist layer 116 is, for example, an insulating material, and the forming method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, an elastic printing method, a lithography method, or a photosensitive insulating material. Patterning by UV light. Further, the solder resist layer 114 and the solder resist layer 116 may be formed separately or simultaneously. That is, the order in which the solder resist layer 114 and the solder resist layer 116 are formed may be determined according to the process requirements.
在此實施例中，由於三維列印導線112是形成在開口104與缺口106中，因此即使不在第三表面102c上形成覆蓋三維列印導線112的防焊層，三維列印導線112也不容易因受到外力而造成損壞。此外，不在缺口106的表面上形成覆蓋三維列印導線112的防焊層，可有利於在後續製程中進行電性測試。在另一實施例中，亦可於第三表面102c上形成覆蓋三維列印導線112的防焊層。In this embodiment, since the three-dimensional printed wiring 112 is formed in the opening 104 and the notch 106, even if the solder resist layer covering the three-dimensional printed wiring 112 is not formed on the third surface 102c, the three-dimensional printed wiring 112 is not easy. Damage caused by external force. In addition, the formation of a solder mask covering the three-dimensional printed conductor 112 on the surface of the notch 106 can facilitate electrical testing in subsequent processes. In another embodiment, a solder resist layer covering the three-dimensional printed wiring 112 may also be formed on the third surface 102c.
以下，藉由圖3A至圖3D來說明本實施例的封裝體用基板。此外，本實施例的封裝體用基板的製造方法雖然是以上述製造方法為例進行說明，但本發明的封裝體用基板的製造方法並不以此為限。請參照圖3A至圖3D，封裝體用基板10包括載板100、圖案化導體層108、圖案化導體層110與三維列印導線112。載板100具有第一表面102a、第二表面102b與第三表面102c。第一表面102a相對於第二表面102b，且第三表面102c連接於第一表面102a與第二表面102b之間。圖案化導體層108設置於第一表面102a上。圖案化導體層110設置於第二表面102b上。三維列印導線112設置於第三表面102c上，且連接於圖案化導體層108與圖案化導體層110之間。此外，封裝體用基板10更可包括防焊層114與防焊層116。防焊層114覆蓋圖案化導體層108且暴露出部分圖案化導體層108。防焊層116覆蓋圖案化導體層110且暴露出部分圖案化導體層110。此外，封裝體用基板10的各構件的材料、設置方式、形成方法與功效已於上述圖1A至圖3D的製造方法中進行詳盡地說明，故於此不再贅述。Hereinafter, the substrate for a package of the present embodiment will be described with reference to FIGS. 3A to 3D. In the method for manufacturing a package substrate of the present embodiment, the above-described manufacturing method will be described as an example. However, the method for manufacturing the package substrate of the present invention is not limited thereto. Referring to FIGS. 3A to 3D , the package substrate 10 includes a carrier 100 , a patterned conductor layer 108 , a patterned conductor layer 110 , and a three-dimensional printed wiring 112 . The carrier 100 has a first surface 102a, a second surface 102b, and a third surface 102c. The first surface 102a is opposite the second surface 102b, and the third surface 102c is coupled between the first surface 102a and the second surface 102b. The patterned conductor layer 108 is disposed on the first surface 102a. The patterned conductor layer 110 is disposed on the second surface 102b. The three-dimensional printed wire 112 is disposed on the third surface 102c and is connected between the patterned conductive layer 108 and the patterned conductive layer 110. In addition, the package substrate 10 may further include a solder resist layer 114 and a solder resist layer 116. The solder resist layer 114 covers the patterned conductor layer 108 and exposes a portion of the patterned conductor layer 108. The solder resist layer 116 covers the patterned conductor layer 110 and exposes a portion of the patterned conductor layer 110. In addition, the materials, installation methods, forming methods, and effects of the respective members of the package substrate 10 have been described in detail in the above-described manufacturing methods of FIGS. 1A to 3D, and thus will not be described herein.
基於上述實施例可知，在上述封裝體用基板10及其製造方法中，由於三維列印技術具有可於立體表面進行列印的特性，所以能夠利用三維列印法在載板100的第三表面102c列印出三維列印導線112，因此無須採用導通孔製程，即可藉由簡易的方式來完成圖案化導體層108與圖案化導體層110線路之間的互連，且更可依據封裝產品特性要求，設計基板外型以進行封裝。此外，上述封裝體用基板10的製造方法可有效地降低生產複雜度與所需耗材，因此可有效地降低封裝體用基板10的製造時程與成本。According to the above embodiment, in the above-described package substrate 10 and the method of manufacturing the same, since the three-dimensional printing technique has the characteristics of being printable on a three-dimensional surface, it is possible to use the three-dimensional printing method on the third surface of the carrier 100. 102c prints the three-dimensional printed conductor 112, so that the interconnection between the patterned conductor layer 108 and the patterned conductor layer 110 can be completed in a simple manner without using a via process, and can be based on the package product. Characteristic requirements, design the substrate shape for packaging. Further, the method for manufacturing the package substrate 10 described above can effectively reduce the production complexity and the required consumables, so that the manufacturing time and cost of the package substrate 10 can be effectively reduced.
圖4A為本發明另一實施例的封裝體用基板的上視圖。圖4B為圖4A的右側視圖。為了清楚地進行說明，在圖4B中省略繪示位於載板的第一表面與第二表面上的構件。圖4C為圖4A的下視圖。請同時參照圖3A至圖3D與圖4A至圖4C，封裝體用基板20與封裝體用基板10的差異如下。封裝體用基板20僅以缺口106的表面作為第三表面102c。亦即，封裝體用基板20的載板100不具有開口104，因此也不具有位於開口104的表面上的三維列印導線112。在封裝體用基板20中，圖案化導體層108與圖案化導體層110藉由位於缺口106的表面上的三維列印導線112進行連接。此外，封裝體用基板20與封裝體用基板10相同的構件以相同的符號表示，且於此不再重複說明。4A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 4B is a right side view of Figure 4A. For clarity of illustration, the members on the first and second surfaces of the carrier are omitted in FIG. 4B. Figure 4C is a bottom view of Figure 4A. 3A to 3D and FIGS. 4A to 4C, the difference between the package substrate 20 and the package substrate 10 is as follows. The package substrate 20 has only the surface of the notch 106 as the third surface 102c. That is, the carrier 100 of the package substrate 20 does not have the opening 104, and therefore does not have the three-dimensional printed wiring 112 on the surface of the opening 104. In the package substrate 20, the patterned conductor layer 108 and the patterned conductor layer 110 are connected by a three-dimensional printed wiring line 112 on the surface of the notch 106. In addition, the same members of the package substrate 20 and the package substrate 10 are denoted by the same reference numerals, and the description thereof will not be repeated.
圖5A為本發明另一實施例的封裝體用基板的上視圖。圖5B為圖5A的右側視圖。為了清楚地進行說明，在圖5B中省略繪示位於載板的第一表面與第二表面上的構件。圖5C為圖5A的下視圖。請同時參照圖4A至圖5C，封裝體用基板30與封裝體用基板20的差異如下。封裝體用基板30的載板100不具有缺口106。封裝體用基板30是以載板100的邊緣的側面作為第三表面102c。亦即，三維列印導線112是位於載板100的邊緣的側面上。在封裝體用基板30中，圖案化導體層108與圖案化導體層110藉由位於載板100的邊緣的側面上的三維列印導線112進行連接。此外，更可選擇性地在第三表面102c上形成覆蓋三維列印導線112的防焊層118，可用以保護第三表面102c上的三維列印導線112。此外，封裝體用基板30與封裝體用基板20相同的構件以相同的符號表示，且於此不再重複說明。Fig. 5A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 5B is a right side view of Figure 5A. For clarity of illustration, the members on the first and second surfaces of the carrier are omitted in FIG. 5B. Figure 5C is a bottom view of Figure 5A. 4A to 5C, the difference between the package substrate 30 and the package substrate 20 is as follows. The carrier 100 of the package substrate 30 does not have the notch 106. The package substrate 30 is a third surface 102c which is a side surface of the edge of the carrier 100. That is, the three-dimensional printed wiring 112 is on the side of the edge of the carrier 100. In the package substrate 30, the patterned conductor layer 108 and the patterned conductor layer 110 are connected by a three-dimensional printed wiring line 112 on the side of the edge of the carrier 100. In addition, a solder resist layer 118 covering the three-dimensional print conductor 112 may be selectively formed on the third surface 102c to protect the three-dimensional print conductor 112 on the third surface 102c. In addition, the same members of the package substrate 30 and the package substrate 20 are denoted by the same reference numerals, and the description thereof will not be repeated.
圖6A為本發明另一實施例的封裝體用基板的上視圖。圖6B為圖6A的右側視圖。圖6C為圖6A的下視圖。圖6D為沿圖6A中的III-III’剖面線的三維列印導線與載板交界處的剖面圖。為了清楚地進行說明，在圖6B中省略繪示位於載板的第一表面與第二表面上的構件，且在圖6D中僅繪示出三維列印導線與載板。Fig. 6A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 6B is a right side view of Figure 6A. Figure 6C is a bottom view of Figure 6A. Figure 6D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line III-III' in Figure 6A. For clarity of explanation, the members on the first and second surfaces of the carrier are omitted in FIG. 6B, and only the three-dimensional printed wiring and the carrier are illustrated in FIG. 6D.
請同時參照圖3A至圖3D與圖6A至圖6D，封裝體用基板40與封裝體用基板10的差異如下。封裝體用基板40僅以開口104的表面作為第三表面102c。亦即，封裝體用基板40的載板100不具有缺口106，因此也不具有位於缺口106的表面上的三維列印導線112。在封裝體用基板40中，圖案化導體層108與圖案化導體層110藉由位於開口104的表面上的三維列印導線112進行連接。此外，封裝體用基板40與封裝體用基板10相同的構件以相同的符號表示，且於此不再重複說明。3A to 3D and FIGS. 6A to 6D, the difference between the package substrate 40 and the package substrate 10 is as follows. The package substrate 40 has only the surface of the opening 104 as the third surface 102c. That is, the carrier 100 of the package substrate 40 does not have the notch 106, and therefore does not have the three-dimensional printed wiring 112 on the surface of the notch 106. In the package substrate 40, the patterned conductor layer 108 and the patterned conductor layer 110 are connected by a three-dimensional printed wiring 112 on the surface of the opening 104. In addition, the same members of the package substrate 40 and the package substrate 10 are denoted by the same reference numerals, and the description thereof will not be repeated.
上述實施例的封裝體用基板10、20、30、40可應用於藉由黏晶或覆晶方式所進行的封裝製程。此外，上述實施例的封裝體用基板10、20、30、40亦可應用於單晶片封裝、雙晶片封裝或封裝堆疊封裝(Package on package；PoP)。The package substrates 10, 20, 30, and 40 of the above embodiments can be applied to a packaging process by die bonding or flip chip. In addition, the package substrates 10, 20, 30, 40 of the above embodiments may also be applied to a single chip package, a two-chip package, or a package on package (PoP).
接著，藉由下列實施例來舉例說明本發明的封裝體。Next, the package of the present invention will be exemplified by the following examples.
圖7為本發明一實施例的封裝體的剖面圖。請參照圖4A至圖4C與圖7，封裝體50包括封裝體用基板20與第一電子元件200。封裝體用基板20的結構已於上述實施例進行詳盡地說明，故於此不再重複說明。在本實施例中，是以使用圖4A至圖4C的封裝體用基板20製作封裝體50為例來進行說明，但本發明並不以此為限。在另一實施例中，亦可使用圖5A至圖5C的封裝體用基板30製作進行封裝體50。Figure 7 is a cross-sectional view showing a package in accordance with an embodiment of the present invention. Referring to FIGS. 4A-4C and 7 , the package 50 includes a package substrate 20 and a first electronic component 200 . The structure of the package substrate 20 has been described in detail in the above embodiments, and thus the description thereof will not be repeated. In the present embodiment, the package 50 is formed by using the package substrate 20 of FIGS. 4A to 4C as an example, but the present invention is not limited thereto. In another embodiment, the package 50 may be fabricated using the package substrate 30 of FIGS. 5A to 5C.
第一電子元件200設置於封裝體用基板20的第一表面102a上，且電性連接於封裝體用基板20的圖案化導體層108(圖4A)。第一電子元件200例如是晶片，但本發明並不以此為限。第一電子元件200可藉由黏著劑202貼附到封裝體用基板20的第一表面102a上。第一電子元件200可藉由銲線(bonding wire)204電性連接至封裝體用基板20的圖案化導體層108。The first electronic component 200 is disposed on the first surface 102a of the package substrate 20 and electrically connected to the patterned conductor layer 108 of the package substrate 20 (FIG. 4A). The first electronic component 200 is, for example, a wafer, but the invention is not limited thereto. The first electronic component 200 can be attached to the first surface 102a of the package substrate 20 by the adhesive 202. The first electronic component 200 can be electrically connected to the patterned conductor layer 108 of the package substrate 20 by a bonding wire 204.
此外，封裝體50更可包括銲球(solder ball)206。銲球206設置於封裝體用基板20的第二表面102b上，且電性連接於封裝體用基板20的圖案化導體層110(圖4C)。第一電子元件200可經由封裝體用基板20的圖案化導體層108、三維列印導線112與圖案畫導體層100(圖4A至圖4C)電性連接至銲球206。In addition, the package 50 may further include a solder ball 206. The solder ball 206 is provided on the second surface 102b of the package substrate 20, and is electrically connected to the patterned conductor layer 110 of the package substrate 20 (FIG. 4C). The first electronic component 200 can be electrically connected to the solder ball 206 via the patterned conductor layer 108 of the package substrate 20, the three-dimensional printed wiring 112, and the patterned conductive layer 100 (FIGS. 4A-4C).
另外，封裝體50更可包括封膠(encapsulation) 208。封膠208包覆第一電子元件200，可用以保護第一電子元件200。封膠208的材料例如是介電高分子材料。Additionally, the package 50 may further include an encapsulation 208. The encapsulant 208 encases the first electronic component 200 and can be used to protect the first electronic component 200. The material of the sealant 208 is, for example, a dielectric polymer material.
圖8為本發明另一實施例的封裝體的剖面圖。請參照圖3A至圖3D與圖8，封裝體60包括封裝體用基板10與第一電子元件300a、300b。封裝體用基板10的結構已於上述實施例進行詳盡地說明，故於此不再重複說明。在本實施例中，是以使用圖3A至圖4D的封裝體用基板10製作封裝體60為例來進行說明，但本發明並不以此為限。在另一實施例中，亦可使用圖6A至圖6D的封裝體用基板40製作進行封裝體60。Figure 8 is a cross-sectional view showing a package according to another embodiment of the present invention. Referring to FIGS. 3A to 3D and FIG. 8, the package 60 includes a package substrate 10 and first electronic components 300a and 300b. The structure of the package substrate 10 has been described in detail in the above embodiments, and thus the description thereof will not be repeated. In the present embodiment, the package 60 is formed by using the package substrate 10 of FIGS. 3A to 4D as an example, but the present invention is not limited thereto. In another embodiment, the package 60 may be fabricated using the package substrate 40 of FIGS. 6A to 6D.
第一電子元件300a、300b設置於封裝體用基板10的第一表面102a上，且分別電性連接於封裝體用基板10的圖案化導體層108(圖3A)。第一電子元件300a例如是驅動晶片(driver IC)，且第一電子元件300b例如是被動元件，但本發明並不以此為限。第一電子元件300a可藉由凸塊(bump)302電性連接至封裝體用基板10的圖案化導體層108。第一電子元件300b可藉由表面黏著技術（surface mount technology，SMT)裝配到封裝體用基板10的第一表面102a上。第一電子元件300b可藉由導電膠304電性連接至封裝體用基板10的圖案化導體層108。The first electronic components 300a and 300b are provided on the first surface 102a of the package substrate 10, and are electrically connected to the patterned conductor layer 108 of the package substrate 10 (FIG. 3A). The first electronic component 300a is, for example, a driver IC, and the first electronic component 300b is, for example, a passive component, but the invention is not limited thereto. The first electronic component 300a can be electrically connected to the patterned conductor layer 108 of the package substrate 10 by a bump 302. The first electronic component 300b can be mounted on the first surface 102a of the package substrate 10 by surface mount technology (SMT). The first electronic component 300b can be electrically connected to the patterned conductor layer 108 of the package substrate 10 by the conductive paste 304.
此外，封裝體60更可包括第二電子元件306與銲球308中的至少一者。第二電子元件306與銲球308設置於封裝體用基板10的第二表面102b上，且分別電性連接於封裝體用基板10的圖案化導體層110(圖3C)。封裝體用基板10的開口104暴露出設置於第二表面102b上的第二電子元件306。第二電子元件306例如是影像感測器，但本發明並不以此為限。第二電子元件306可藉由凸塊310電性連接至封裝體用基板10的圖案化導體層110，且可藉由底膠312來保護凸塊310。第一電子元件300a、300b分別可經由封裝體用基板10的圖案化導體層108、三維列印導線112與圖案化導體層100(圖3A至圖3D)電性連接至第二電子元件306及/或銲球308。In addition, the package 60 may further include at least one of the second electronic component 306 and the solder ball 308. The second electronic component 306 and the solder ball 308 are disposed on the second surface 102b of the package substrate 10, and are electrically connected to the patterned conductive layer 110 of the package substrate 10 (FIG. 3C). The opening 104 of the package substrate 10 exposes the second electronic component 306 disposed on the second surface 102b. The second electronic component 306 is, for example, an image sensor, but the invention is not limited thereto. The second electronic component 306 can be electrically connected to the patterned conductor layer 110 of the package substrate 10 by the bumps 310, and the bumps 310 can be protected by the primer 312. The first electronic components 300a, 300b can be electrically connected to the second electronic component 306 via the patterned conductive layer 108 of the package substrate 10, the three-dimensional printed wiring 112 and the patterned conductive layer 100 (FIGS. 3A to 3D), respectively. / or solder balls 308.
另外，封裝體60更可包括透光板314，且光線可穿過透光板314而到達第二電子元件306。透光板314設置於封裝體用基板10的第一表面102a上且覆蓋開口104。透光板314的材料例如是玻璃。透光板314可藉由黏著劑316貼附於封裝體用基板10的第一表面102a上。In addition, the package body 60 may further include a light-transmitting plate 314, and the light may pass through the light-transmitting plate 314 to reach the second electronic component 306. The light-transmitting plate 314 is disposed on the first surface 102a of the package substrate 10 and covers the opening 104. The material of the light-transmitting plate 314 is, for example, glass. The light-transmitting plate 314 can be attached to the first surface 102a of the package substrate 10 by an adhesive 316.
基於上述實施例可知，藉由使用封裝體用基板10、20、30、40來製作封裝體50、60，可使得封裝體50、60具有較佳的設計彈性。Based on the above embodiments, it is understood that the packages 50 and 60 can be formed by using the package substrates 10, 20, 30, and 40, so that the packages 50 and 60 have better design flexibility.
綜上所述，上述實施例的封裝體用基板及其製造方法無須採用導通孔製程，即可藉由簡易的方式來完成圖案化導體層與圖案化導體層線路之間的互連，且更可依據封裝產品特性要求，設計基板外型以進行封裝。此外，上述封裝體用基板的製造方法可有效地降低封裝體用基板的製造時程與成本。另外，在上述實施例的封裝體中，由於使用了上述封裝體用基板，因此可具有較佳的設計彈性。In summary, the substrate for a package of the above embodiment and the method of manufacturing the same do not require a via process, and the interconnection between the patterned conductor layer and the patterned conductor layer can be completed in a simple manner, and The substrate can be designed for packaging according to the characteristics of the packaged product. Further, the method for manufacturing a substrate for a package described above can effectively reduce the manufacturing time and cost of the substrate for a package. Further, in the package of the above-described embodiment, since the above-described substrate for a package is used, it is possible to have a preferable design flexibility.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、20、30、40‧‧‧封裝體用基板
50、60‧‧‧封裝體
100‧‧‧載板
102a‧‧‧第一表面
102b‧‧‧第二表面
102c‧‧‧第三表面
104‧‧‧開口
106‧‧‧缺口
108、110‧‧‧圖案化導體層
108a、110a‧‧‧接點
108b、110b‧‧‧導線
112‧‧‧三維列印導線
114、116、118‧‧‧防焊層
200、300a、300b‧‧‧第一電子元件
202、316‧‧‧黏著劑
204‧‧‧銲線
206、308‧‧‧銲球
208‧‧‧封膠
302、310‧‧‧凸塊
304‧‧‧導電膠
306‧‧‧第二電子元件
312‧‧‧底膠
314‧‧‧透光板10, 20, 30, 40‧‧‧Package substrate
50, 60‧‧‧ package
100‧‧‧ Carrier Board
102a‧‧‧ first surface
102b‧‧‧second surface
102c‧‧‧ third surface
104‧‧‧ openings
106‧‧‧ gap
108, 110‧‧‧ patterned conductor layer
108a, 110a‧‧‧Contacts
108b, 110b‧‧‧ wire
112‧‧‧Three-dimensional printed conductor
114, 116, 118‧‧‧ solder mask
200, 300a, 300b‧‧‧ first electronic components
202, 316‧‧‧Adhesive
204‧‧‧welding line
206, 308‧‧‧ solder balls
208‧‧‧Packing
302, 310‧‧‧Bumps
304‧‧‧ conductive adhesive
306‧‧‧Second electronic components
312‧‧‧Bottom glue
314‧‧‧Translucent plate
圖1A、圖2A與圖3A為本發明一實施例的封裝體用基板的製造流程上視圖。 圖1B、圖2B與圖3B分別為圖1A、圖2A與圖3A的右側視圖。 圖1C、圖2C與圖3C分別為圖1A、圖2B與圖3A的下視圖。 圖2D為沿圖2A中的I-I’剖面線的三維列印導線與載板交界處的剖面圖。 圖3D為沿圖3A中的II-II’剖面線的三維列印導線與載板交界處的剖面圖。 圖4A為本發明另一實施例的封裝體用基板的上視圖。 圖4B為圖4A的右側視圖。 圖4C為圖4A的下視圖。 圖5A為本發明另一實施例的封裝體用基板的上視圖。 圖5B為圖5A的右側視圖。 圖5C為圖5A的下視圖。 圖6A為本發明另一實施例的封裝體用基板的上視圖。 圖6B為圖6A的右側視圖。 圖6C為圖6A的下視圖。 圖6D為沿圖6A中的III-III’剖面線的三維列印導線與載板交界處的剖面圖。 圖7為本發明一實施例的封裝體的剖面圖。 圖8為本發明另一實施例的封裝體的剖面圖。1A, 2A, and 3A are top views of a manufacturing process of a substrate for a package according to an embodiment of the present invention. 1B, 2B, and 3B are right side views of Figs. 1A, 2A, and 3A, respectively. 1C, 2C, and 3C are lower views of Figs. 1A, 2B, and 3A, respectively. Figure 2D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line I-I' in Figure 2A. Figure 3D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line II-II' in Figure 3A. 4A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 4B is a right side view of Figure 4A. Figure 4C is a bottom view of Figure 4A. Fig. 5A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 5B is a right side view of Figure 5A. Figure 5C is a bottom view of Figure 5A. Fig. 6A is a top view of a substrate for a package according to another embodiment of the present invention. Figure 6B is a right side view of Figure 6A. Figure 6C is a bottom view of Figure 6A. Figure 6D is a cross-sectional view of the intersection of the three-dimensional printed conductor and the carrier along the line III-III' in Figure 6A. Figure 7 is a cross-sectional view showing a package in accordance with an embodiment of the present invention. Figure 8 is a cross-sectional view showing a package according to another embodiment of the present invention.
10‧‧‧封裝體用基板 10‧‧‧Package substrate
100‧‧‧載板 100‧‧‧ Carrier Board
102a‧‧‧第一表面 102a‧‧‧ first surface
102b‧‧‧第二表面 102b‧‧‧second surface
102c‧‧‧第三表面 102c‧‧‧ third surface
106‧‧‧缺口 106‧‧‧ gap
112‧‧‧三維列印導線 112‧‧‧Three-dimensional printed conductor
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105123657A TWI659511B (en) | 2016-07-27 | 2016-07-27 | Substrate for package and manufacturing method thereof and package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105123657A TWI659511B (en) | 2016-07-27 | 2016-07-27 | Substrate for package and manufacturing method thereof and package |
Publications (2)
| Publication Number | Publication Date |
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| TW201804580A true TW201804580A (en) | 2018-02-01 |
| TWI659511B TWI659511B (en) | 2019-05-11 |
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| JP2006186297A (en) * | 2004-12-03 | 2006-07-13 | Toshiba Corp | Semiconductor light emitting device and manufacturing method thereof |
| US8963135B2 (en) * | 2012-11-30 | 2015-02-24 | Intel Corporation | Integrated circuits and systems and methods for producing the same |
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