TW201801345A - Nitride semiconductor template, method for manufacturing same, and ultraviolet led - Google Patents
Nitride semiconductor template, method for manufacturing same, and ultraviolet led Download PDFInfo
- Publication number
- TW201801345A TW201801345A TW106104838A TW106104838A TW201801345A TW 201801345 A TW201801345 A TW 201801345A TW 106104838 A TW106104838 A TW 106104838A TW 106104838 A TW106104838 A TW 106104838A TW 201801345 A TW201801345 A TW 201801345A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- nitride semiconductor
- dimensional growth
- stress relaxation
- main component
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02414—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
Description
本發明是關於氮化物半導體模板及其製造方法、以及紫外線發光二極體。The present invention relates to a nitride semiconductor template, a method for manufacturing the same, and an ultraviolet light emitting diode.
先前，已知有一種氮化物半導體模板，其在Ga2 O3 (氧化鎵)基板上隔著AlN(氮化鋁)緩衝層形成有氮化物半導體層(例如，參照專利文獻1)。Conventionally, a nitride semiconductor template is known in which a nitride semiconductor layer is formed on a Ga 2 O 3 (gallium oxide) substrate via an AlN (aluminum nitride) buffer layer (for example, refer to Patent Document 1).
根據專利文獻1，藉由選擇Ga2 O3 基板的主面的面方位，能夠將氮化物半導體層的表面作成鏡面。According to Patent Document 1, the surface of the nitride semiconductor layer can be made a mirror surface by selecting the surface orientation of the main surface of the Ga 2 O 3 substrate.
(先前技術文獻) [專利文獻] 專利文獻1：日本特開2014－199935號公報。(Prior Art Document) [Patent Document] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-199935.
(發明所欲解決的問題) 本發明的目的是要提供一種氮化物半導體模板及其製造方法，並提供一種包含該氮化物半導體模板之紫外線發光二極體，該氮化物半導體具有優異的結晶品質，且能夠有效地抑制表面發生破裂。(Problems to be Solved by the Invention) An object of the present invention is to provide a nitride semiconductor template and a method for manufacturing the same, and provide an ultraviolet light emitting diode including the nitride semiconductor template. The nitride semiconductor has excellent crystal quality. , And can effectively prevent the surface from cracking.
(用來解決問題的手段) 本發明的一態樣，為了達成上述目的而提供以下[1]～[6]之氮化物半導體模板、[7]之紫外線發光二極體、[8]～[10]之半導體模板的製造方法。(Means for Solving the Problems) In one aspect of the present invention, in order to achieve the above object, the following nitride semiconductor templates of [1] to [6], ultraviolet light emitting diodes of [7], [8] to [ 10] A method for manufacturing a semiconductor template.
[1] 一種氮化物半導體模板，其具有：基板，其以Ga2 O3 作為主成分；緩衝層，其被形成於前述基板上，且以AlN作為主成分；界面電阻降低層，其被形成於前述緩衝層上，且以Alx Ga1 － x N作為主成分，其中，0.1≦x≦0.4；應力緩和層，其被形成於前述界面電阻降低層上，且以Aly Ga1 － y N作為主成分，其中，0.5＜y≦0.6；以及，n型氮化物半導體層，其被形成於前述應力緩和層上，且以Alz Ga1 － z N作為主成分，其中，0.2≦z≦0.5。[1] A nitride semiconductor template comprising: a substrate having Ga 2 O 3 as a main component; a buffer layer formed on the aforementioned substrate and having AlN as a main component; and an interface resistance reducing layer which is formed on the buffer layer, and with Al x Ga 1 - x N as a main component, wherein, 0.1 ≦ x ≦ 0.4; stress relief layer which is formed at the interface resistance reducing layer, and with Al y Ga 1 - y N as a main component, wherein, 0.5 <y ≦ 0.6; and, n-type nitride semiconductor layer which is formed on the stress relieving layer, and with Al z Ga 1 - z N as a main component, wherein, 0.2 ≦ z ≦ 0.5.
[2] 如上述[1]所述之氮化物半導體模板，其中，前述應力緩和層是由前述y值不同的複數個層所構成，且前述複數個層中的最上層的前述y值最低，最下層的前述y值最高。[2] The nitride semiconductor template according to the above [1], wherein the stress relaxation layer is composed of a plurality of layers with different y values, and the uppermost layer of the plurality of layers has the lowest y value, The lowest y value is the highest.
[3] 如上述[1]或[2]所述之氮化物半導體模板，其中，前述應力緩和層的厚度為150nm以上且300nm以下。[3] The nitride semiconductor template according to the above [1] or [2], wherein a thickness of the stress relaxation layer is 150 nm or more and 300 nm or less.
[4] 如上述[1]或[2]所述之氮化物半導體模板，其中，前述n型氮化物半導體層包含三維成長層與二維成長層，該三維成長層是藉由結晶的三維成長而形成，該二維成長層是藉由結晶的二維成長而形成，且位於前述三維成長層上。[4] The nitride semiconductor template according to the above [1] or [2], wherein the n-type nitride semiconductor layer includes a three-dimensional growth layer and a two-dimensional growth layer, and the three-dimensional growth layer is three-dimensionally grown by crystallization. The two-dimensional growth layer is formed by two-dimensional growth of crystals, and is located on the three-dimensional growth layer.
[5] 如上述[1]或[2]所述之氮化物半導體模板，其中，前述應力緩和層的表面沒有破裂的情形。[5] The nitride semiconductor template according to [1] or [2] above, wherein the surface of the stress relaxation layer is not cracked.
[6] 如上述[1]或[2]所述之氮化物半導體模板，其中，前述n型氮化物半導體層的表面沒有破裂的情形，或者在與前述破裂正交的方向的每1cm長度中的破裂的平均條數未滿2條。[6] The nitride semiconductor template according to the above [1] or [2], wherein the surface of the n-type nitride semiconductor layer is not cracked, or in each 1 cm length in a direction orthogonal to the crack The average number of cracks was less than 2.
[7] 一種紫外線發光二極體，其包含上述[1]～[6]中任一項所述的氮化物半導體模板。[7] An ultraviolet light emitting diode comprising the nitride semiconductor template according to any one of the above [1] to [6].
[8] 一種氮化物半導體模板的製造方法，其具有以下步驟：在以Ga2 O3 作為主成分的基板上，形成以AlN作為主成分的緩衝層；在前述緩衝層上成長出以Alx Ga1 － x N作為主成分之結晶，而形成界面電阻降低層其中，0.1≦x≦0.4；在前述界面電阻降低層上二維成長出以Aly Ga1 － y N作為主成分之結晶，而形成應力緩和層，其中，0.5＜y≦0.6；以及，在前述應力緩和層上成長出以Alz Ga1 － z N作為主成分之結晶，而形成n型氮化物半導體層，其中，0.2≦z≦0.5。[8] A method for manufacturing a nitride semiconductor template, comprising the steps of: forming a buffer layer containing AlN as a main component on a substrate containing Ga 2 O 3 as a main component; and growing Al x Ga 1 - x N is used as the main component crystal to form an interface resistance reduction layer, where 0.1 ≦ x ≦ 0.4; a crystal with Al y Ga 1 - y N as the main component is two-dimensionally grown on the interface resistance reduction layer, to form a stress relaxation layer, wherein, 0.5 <y ≦ 0.6; and grow out to Al z Ga 1 on the stress relieving layer - z N crystalline main component of, and an n-type nitride semiconductor layer, wherein 0.2 ≦ z ≦ 0.5.
[9] 如上述[8]所述之氮化物半導體模板的製造方法，其中，前述應力緩和層是由前述y值不同的複數個層所構成，且前述複數個層中的最上層的前述y值最低，最下層的前述y值最高。[9] The method for manufacturing a nitride semiconductor template according to the above [8], wherein the stress relaxation layer is composed of a plurality of layers having different y values, and the y of an uppermost layer of the plurality of layers is the y The lowest value, the lowest y value is the highest.
[10] 如上述[9]所述之氮化物半導體模板的製造方法，其中，前述n型氮化物半導體層包含三維成長層與二維成長層，該三維成長層是藉由結晶的三維成長而形成，該二維成長層是藉由結晶的二維成長而形成於前述三維成長層上。[10] The method for manufacturing a nitride semiconductor template according to the above [9], wherein the n-type nitride semiconductor layer includes a three-dimensional growth layer and a two-dimensional growth layer, and the three-dimensional growth layer is formed by three-dimensional growth of a crystal. The two-dimensional growth layer is formed on the three-dimensional growth layer by two-dimensional growth of crystals.
(發明的功效) 根據本發明，能夠提供一種氮化物半導體模板及其製造方法，並提供一種包含該氮化物半導體模板之紫外線發光二極體，該氮化物半導體具有優異的結晶品質，且能夠有效地抑制表面發生破裂的情形。(Effect of the Invention) According to the present invention, it is possible to provide a nitride semiconductor template and a method for manufacturing the same, and to provide an ultraviolet light emitting diode including the nitride semiconductor template. The nitride semiconductor has excellent crystal quality and is effective. In order to prevent the surface from cracking.
(第1實施型態) [氮化物半導體模板的結構] 第1圖是第1實施型態之氮化物半導體模板1的垂直剖面圖。氮化物半導體模板1，包含：基板10、基板10上的緩衝層11、緩衝層11上的界面電阻降低層12、界面電阻降低層12上的應力緩和層13、以及應力緩和層13上的n型氮化物半導體層14。(First Embodiment) [Structure of Nitride Semiconductor Template] FIG. 1 is a vertical sectional view of a nitride semiconductor template 1 according to a first embodiment. The nitride semiconductor template 1 includes a substrate 10, a buffer layer 11 on the substrate 10, an interface resistance reduction layer 12 on the buffer layer 11, a stress relaxation layer 13 on the interface resistance reduction layer 12, and n on the stress relaxation layer 13. Type nitride semiconductor layer 14.
基板10，是以Ga2 O3 作為主成分之基板，例如是由β－Ga2 O3 結晶所構成的Ga2 O3 基板。基板10的主面的面方位，例如為(－201)、(101)、(310)或是(3－10)。在基板10的主面具有這些面方位的情況下，界面電阻降低層12、應力緩和層13以及n型氮化物半導體層14的主面的面方位會成為(0001)。基板10，例如包含濃度3×1018 ／cm3 的Sn(錫)等之n型雜質。Substrate 10, the substrate is Ga 2 O 3 Ga 2 O 3 as the main component of the substrate, for example a β-Ga 2 O 3 crystals thereof. The plane orientation of the main surface of the substrate 10 is, for example, (−201), (101), (310), or (3-10). When the principal faces of the substrate 10 have these plane orientations, the plane orientations of the principal faces of the interface resistance reduction layer 12, the stress relaxation layer 13, and the n-type nitride semiconductor layer 14 are (0001). The substrate 10 contains, for example, n-type impurities such as Sn (tin) at a concentration of 3 × 10 18 / cm 3 .
緩衝層11，以AlN作為主成分。緩衝層11，可覆蓋基板10的上表面的整個區域，亦可只覆蓋一部分。為了要有效地作為基板10與界面電阻降低層12間的緩衝層來發揮作用，緩衝層11的厚度較佳為10nm以下。另一方面，若是太薄，形成於緩衝層11上的層的表面容易發生表面不良(氮氣的面成長、凹洞等)的情形，因此緩衝層的厚度較佳為1nm以上。The buffer layer 11 contains AlN as a main component. The buffer layer 11 may cover the entire area of the upper surface of the substrate 10 or may cover only a part thereof. In order to effectively function as a buffer layer between the substrate 10 and the interface resistance reducing layer 12, the thickness of the buffer layer 11 is preferably 10 nm or less. On the other hand, if it is too thin, the surface of the layer formed on the buffer layer 11 is liable to cause surface defects (surface growth of nitrogen, pits, etc.). Therefore, the thickness of the buffer layer is preferably 1 nm or more.
界面電阻降低層12，是為了降低基板10與應力緩和層13之界面的電阻而形成的層，並且是由以包含Si(矽)等n型雜質之Alx Ga1 － x N(0.1≦x≦0.4)作為主成分之結晶所構成。在使用氮化物半導體模板來製造發光二極體的情況下，由光吸收的觀點來看，界面電阻降低層12的Al組成必須要比發光層的井層的Al組成更高約0.1以上。在製造發光波長300～360nm之發光二極體的情況下，由於發光層的井層的Al組成大約是在0以上且0.3以下，因此界面電阻降低層12的Al組成只要在0.1以上且0.4以下，亦即0.1≦x≦0.4即可。此外，x即使超過0.4，從光吸收的觀點來看也沒有問題，但x若超過0.4便會無法有效地降低界面電阻。此外，為了降低界面電阻，界面電阻降低層12的Al組成x較佳為盡可能的小，不僅當然要比後述之應力緩和層13的Al組成y更小，並且較佳為還要比n型氮化物半導體層14的Al組成z更小。界面電阻降低層12的n型雜質的濃度，例如為4×1018 ／cm3 。The interface resistance reducing layer 12 is a layer formed to reduce the resistance at the interface between the substrate 10 and the stress relaxation layer 13. The interface resistance reducing layer 12 is made of Al x Ga 1 - x N (0.1 ≦ x) containing n-type impurities such as Si (silicon). ≦ 0.4) is composed of crystals as a main component. When a nitride semiconductor template is used to manufacture a light emitting diode, from the viewpoint of light absorption, the Al composition of the interface resistance reduction layer 12 must be higher than the Al composition of the well layer of the light emitting layer by about 0.1 or more. In the case of manufacturing a light-emitting diode having an emission wavelength of 300 to 360 nm, since the Al composition of the well layer of the light-emitting layer is approximately 0 to 0.3, the Al composition of the interface resistance reduction layer 12 needs to be 0.1 to 0.4. , That is, 0.1 ≦ x ≦ 0.4. In addition, even if x exceeds 0.4, there is no problem from the viewpoint of light absorption, but if x exceeds 0.4, the interface resistance cannot be effectively reduced. In addition, in order to reduce the interfacial resistance, the Al composition x of the interfacial resistance reduction layer 12 is preferably as small as possible, and of course not only smaller than the Al composition y of the stress relaxation layer 13 to be described later, but also preferably more than n-type The Al composition z of the nitride semiconductor layer 14 is smaller. The concentration of the n-type impurity in the interface resistance reduction layer 12 is, for example, 4 × 10 18 / cm 3 .
應力緩和層13，是為了緩和對n型氮化物半導體層14發生之應力而形成的層，並且是由以包含Si等n型雜質之Aly Ga1 － y N(0.5＜y≦0.6)作為主成分之結晶所構成，其中，前述應力是因為基板10與n型氮化物半導體層14間的晶格常數差異而發生。在組成式中的y為0.5以下的情況下，會無法有效地緩和對n型氮化物半導體層14發生之應力。又，在y超過0.6的情況下，應力緩和層13會高電阻化，因此變得難以將氮化物半導體模板1用於紫外線發光二極體等之元件的製造中。應力緩和層13的n型雜質的濃度，例如為4×1018 ／cm3 。The stress relaxation layer 13 is a layer formed to relax the stress generated on the n-type nitride semiconductor layer 14 and is made of Al y Ga 1 - y N (0.5 <y ≦ 0.6) containing n-type impurities such as Si. The main component is composed of crystals, and the aforementioned stress occurs due to a difference in lattice constant between the substrate 10 and the n-type nitride semiconductor layer 14. When y in the composition formula is 0.5 or less, the stress generated in the n-type nitride semiconductor layer 14 cannot be effectively alleviated. When y exceeds 0.6, the stress relaxation layer 13 has high resistance, and it becomes difficult to use the nitride semiconductor template 1 for the production of an element such as an ultraviolet light emitting diode. The concentration of the n-type impurity in the stress relaxation layer 13 is, for example, 4 × 10 18 / cm 3 .
若應力緩和層13的厚度未滿150nm，則應力緩和功能無法有效地運作，而容易在n型氮化物半導體層14中發生破裂的情形。為了抑制在n型氮化物半導體層14中發生破裂的情形，應力緩和層13的厚度較佳為150nm以上，且更佳為200nm以上。又，應力緩和層13的厚度若超過300nm，則容易在應力緩和層13中發生破裂的情形，因此較佳為300nm以下。If the thickness of the stress relaxation layer 13 is less than 150 nm, the stress relaxation function cannot be effectively operated, and cracks may easily occur in the n-type nitride semiconductor layer 14. In order to suppress the occurrence of cracks in the n-type nitride semiconductor layer 14, the thickness of the stress relaxation layer 13 is preferably 150 nm or more, and more preferably 200 nm or more. When the thickness of the stress relaxation layer 13 exceeds 300 nm, cracks are likely to occur in the stress relaxation layer 13. Therefore, the thickness is preferably 300 nm or less.
n型氮化物半導體層14，是由以包含Si等n型雜質之Alz Ga1 － z N(0.2≦z≦0.5)作為主成分之結晶所構成。在使用氮化物半導體模板1來製造發光二極體，且將n型氮化物半導體層14作為包覆層的情況下，由封住載子與光吸收的觀點來看，n型氮化物半導體層14的Al組成必須要比發光層的井層的Al組成更高約0.2以上。在製造發光波長300～360nm之發光二極體的情況下，由於發光層的井層的Al組成大約是在0以上且0.3以下，因此n型氮化物半導體層14的Al組成只要在0.2以上且0.5以下，亦即0.2≦z≦0.5即可。此外，z即使超過0.5，從封住載子與光吸收的觀點來看也沒有問題，但z若超過0.5，便會在n型氮化物半導體層14的表面上發生許多凹洞，而使表面狀態惡化。n型氮化物半導體層14的n型雜質的濃度，例如為4×1018 ／cm3 。n-type nitride semiconductor layer 14, it is made to include the Al n-type impurity such as Si z Ga 1 - constituted crystallized z N (0.2 ≦ z ≦ 0.5 ) as the main component. When the nitride semiconductor template 1 is used to manufacture a light-emitting diode, and the n-type nitride semiconductor layer 14 is used as a cladding layer, the n-type nitride semiconductor layer is considered from the viewpoint of sealing carriers and light absorption. The Al composition of 14 must be higher than the Al composition of the well layer of the light emitting layer by about 0.2 or more. In the case of manufacturing a light-emitting diode having an emission wavelength of 300 to 360 nm, since the Al composition of the well layer of the light-emitting layer is approximately 0 to 0.3, the Al composition of the n-type nitride semiconductor layer 14 needs to be 0.2 or more and 0.5 or less, that is, 0.2 ≦ z ≦ 0.5 is sufficient. In addition, even if z exceeds 0.5, there is no problem from the viewpoint of sealing the carrier and light absorption, but if z exceeds 0.5, many pits will occur on the surface of the n-type nitride semiconductor layer 14 and the surface will be Deterioration. The n-type impurity concentration of the n-type nitride semiconductor layer 14 is, for example, 4 × 10 18 / cm 3 .
n型氮化物半導體層14的較佳厚度，會根據組成式z的數值而變動。例如當z為約0.3～0.4時，只要厚度在2μm以下便不容易發生破裂的情形。The preferred thickness of the n-type nitride semiconductor layer 14 varies depending on the value of the composition formula z. For example, when z is about 0.3 to 0.4, as long as the thickness is 2 μm or less, cracking is unlikely to occur.
n型氮化物半導體層14，如第1圖所示，較佳為包含三維成長層14a與二維成長層14b，其中三維成長層14a是藉由結晶的三維成長而形成，二維成長層14b是藉由結晶的二維成長而形成，且位於三維成長層14a上。藉由形成這樣的結構，便能夠提高n型氮化物半導體層14的結晶品質。三維成長層14a與二維成長層14b，能夠藉由改變結晶的成長溫度來分別製作。例如利用950～1030℃的成長溫度來形成三維成長層14a，並利用1100～1150℃的成長溫度來形成二維成長層14b。此處，所謂三維成長，是指以三維的方式使結晶自島狀的結晶核針對所希望的結晶主面來進行成長，而所謂二維成長，是指以二維的方式使結晶針對所希望的結晶主面來進行成長。As shown in FIG. 1, the n-type nitride semiconductor layer 14 preferably includes a three-dimensional growth layer 14 a and a two-dimensional growth layer 14 b. The three-dimensional growth layer 14 a is formed by three-dimensional growth of a crystal and the two-dimensional growth layer 14 b. It is formed by two-dimensional growth of crystals and is located on the three-dimensional growth layer 14a. By forming such a structure, the crystal quality of the n-type nitride semiconductor layer 14 can be improved. The three-dimensional growth layer 14a and the two-dimensional growth layer 14b can be separately produced by changing the crystal growth temperature. For example, the three-dimensional growth layer 14a is formed using a growth temperature of 950 to 1030 ° C, and the two-dimensional growth layer 14b is formed using a growth temperature of 1100 to 1150 ° C. Here, the so-called three-dimensional growth refers to the three-dimensional growth of crystals from island-shaped crystal nuclei to the main surface of the desired crystal, and the two-dimensional growth refers to the two-dimensional growth of the crystals to the desired The main surface of the crystal to grow.
在基板10、界面電阻降低層12以及應力緩和層13具有導電性的情況下，能夠將氮化物半導體模板1用來作為縱型發光元件的構成構件。When the substrate 10, the interface resistance reduction layer 12, and the stress relaxation layer 13 have conductivity, the nitride semiconductor template 1 can be used as a constituent member of a vertical light-emitting element.
(氮化物半導體模板的製造方法) 以下，對於氮化物半導體模板1的製造步驟的一例進行說明。(Manufacturing method of nitride semiconductor template) An example of the manufacturing process of the nitride semiconductor template 1 is demonstrated below.
第2圖的上側是表示在第1實施型態之氮化物半導體模板1的製造步驟中，供給氣體的供給時序的圖表。第2圖的下側是表示伴隨時間經過的溫度條件的變化的圖表。The upper side of FIG. 2 is a graph showing the supply timing of the supply gas in the manufacturing steps of the nitride semiconductor template 1 according to the first embodiment. The lower side of FIG. 2 is a graph showing changes in temperature conditions over time.
首先，針對經過CMP(Chemical Mechanical Polishing，化學機械研磨)處理後的基板10施加有機清洗和SPM(Sulfuric acid/ hydrogen Peroxide Mixture，硫酸／過氧化氫混合液)清洗。First, organic cleaning and SPM (Sulfuric acid / hydrogen Peroxide Mixture) cleaning are applied to the substrate 10 after CMP (Chemical Mechanical Polishing) treatment.
接著，將基板10搬送至MOCVD(Metal Organic Chemical Vapor Deposition，有機金屬化學氣相沈積)裝置的腔室內後，開始供給作為環境氣體之N2 (氮氣)氣體，並將腔室內的溫度提高至T1(步驟S1)。此處，T1為500～550℃，例如為550℃。Next, the substrate 10 is transferred into a chamber of a MOCVD (Metal Organic Chemical Vapor Deposition) device, and then N 2 (nitrogen) gas as an ambient gas is supplied, and the temperature in the chamber is increased to T1. (Step S1). Here, T1 is 500 to 550 ° C, for example, 550 ° C.
又，在腔室內的溫度完全上升至T1之前，開始供給作為氮(N)之原料之NH3 (氨氣)氣體。Before the temperature in the chamber completely rises to T1, supply of NH 3 (ammonia) gas as a raw material of nitrogen (N) is started.
接著，將腔室內的溫度保持在T1，開始供給作為鋁(Al)的原料之三甲基鋁(TMA)，而在基板10上形成由AlN所構成的緩衝層11(步驟S2)。Next, the temperature in the chamber is maintained at T1, and trimethylaluminum (TMA), which is a raw material of aluminum (Al), is started to form a buffer layer 11 made of AlN on the substrate 10 (step S2).
此外，在緩衝層11的組成中包含鎵(Ga)的情況下，便在與TMA氣體相同的時序中供給作為Ga的原料之三甲基鎵(TMG)。When gallium (Ga) is included in the composition of the buffer layer 11, trimethylgallium (TMG), which is a raw material of Ga, is supplied at the same timing as the TMA gas.
接著，停止供給TMA氣體，將環境氣體切換成H2 (氫氣)氣體，並將腔室內的溫度提高至T2(步驟S3)。此處，T2為950～1030℃，例如為1020℃。Next, the supply of TMA gas is stopped, the ambient gas is switched to H 2 (hydrogen) gas, and the temperature in the chamber is increased to T 2 (step S3). Here, T2 is 950 to 1030 ° C, for example, 1020 ° C.
接著，將腔室內的溫度保持在T2，供給作為Ga的原料之TMG氣體、作為Al的原料之TMA氣體以及作為Si(矽)雜質的原料之SiH4 氣體，在緩衝層11上三維成長出以Alx Ga1 － x N(0.1≦x≦0.4)作為主成分之結晶，而形成界面電阻降低層12(步驟S4)。Next, the temperature in the chamber is maintained at T2, and TMG gas as a raw material for Ga, TMA gas as a raw material for Al, and SiH 4 gas as a raw material for Si (silicon) impurities are three-dimensionally grown on the buffer layer 11 to Al x Ga 1 - x N (0.1 ≦ x ≦ 0.4) is used as a crystal of the main component to form the interface resistance reduction layer 12 (step S4).
接著，一邊持續供給各原料氣體，一邊將腔室內的溫度提高至T3(步驟S5)。此處，T3為1100～1150℃，例如為1120℃。Next, while continuously supplying each raw material gas, the temperature in the chamber is increased to T3 (step S5). Here, T3 is 1100 to 1150 ° C, for example, 1120 ° C.
接著，在將腔室內的溫度保持在T3的狀態下，改變TMG氣體與TMA氣體的流量比，在界面電阻降低層12上二維成長出以Aly Ga1 － y N(x＜y，0.5＜y≦0.6)作為主成分之結晶，而形成應力緩和層13(步驟S6)。Next, while maintaining the temperature in the chamber at T3, changing the flow rate ratio of TMG gas to TMA gas, two-dimensional growth of Al y Ga 1 - y N (x <y, 0.5 <Y ≦ 0.6) as a main component crystal to form a stress relaxation layer 13 (step S6).
接著，一邊持續供給各原料氣體，一邊將腔室內的溫度降低至T2(步驟S7)。Next, while continuously supplying each raw material gas, the temperature in the chamber is lowered to T2 (step S7).
接著，在將腔室內的溫度保持在T2的狀態下，改變TMG氣體與TMA氣體的流量比，在應力緩和層13上三維成長出以Alz Ga1 － z N(0.2≦z≦0.5)作為主成分之結晶，而形成n型氮化物半導體層14的三維成長層14a(步驟S8)。Subsequently, in a state where the temperature of the chamber is maintained at T2, changing the flow rate ratio of TMG gas and TMA gas in the stress relaxing layer 13 is a three-dimensional growth of the to Al z Ga 1 - z N ( 0.2 ≦ z ≦ 0.5) as The main component is crystallized to form a three-dimensional growth layer 14a of the n-type nitride semiconductor layer 14 (step S8).
此外，三維成長層14a的成長溫度，只要是結晶可進行三維成長的溫度，則亦可與界面電阻降低層12的成長溫度不同。The growth temperature of the three-dimensional growth layer 14 a may be different from the growth temperature of the interface resistance-reducing layer 12 as long as the crystal can be three-dimensionally grown.
接著，一邊持續供給各原料氣體，一邊將腔室內的溫度提高至T3(步驟S9)。Next, the temperature in the chamber is raised to T3 while continuously supplying each source gas (step S9).
接著，在將腔室內的溫度保持在T3的狀態下，在應力緩和層13上二維成長出以Alz Ga1 － z N(0.2≦z≦0.5)作為主成分之結晶，而形成n型氮化物半導體層14的二維成長層14b(步驟S10)。藉此，便可得到結晶積層結構體1。Subsequently, in a state where the temperature of the chamber is maintained at T3, the stress relaxation layer 13 on a two-dimensional growth to an Al z Ga 1 - z N ( 0.2 ≦ z ≦ 0.5) as the main component of the crystal, and an n-type The two-dimensional growth layer 14b of the nitride semiconductor layer 14 (step S10). Thereby, the crystal laminated structure 1 can be obtained.
之後，停止III族原料氣體和SiH4 氣體的供給，並降低腔室內的溫度(步驟S11)。NH3 氣體在降溫途中停止供給。環境氣體，在降溫開始時自H2 氣體切換成N2氣體。降溫後，自腔室內取出結晶積層結構體1。After that, the supply of the group III source gas and the SiH 4 gas is stopped, and the temperature in the chamber is lowered (step S11). The supply of NH 3 gas was stopped while cooling down. The ambient gas is switched from H 2 gas to N 2 gas at the beginning of the temperature decrease. After cooling down, the crystalline laminated structure 1 was taken out of the chamber.
(第2實施型態) 第2實施型態在應力緩和層的結構中與第1實施型態不同。此外，關於與第1實施型態相同之處，會省略或簡化其說明。(Second Embodiment Mode) The second embodiment mode differs from the first embodiment mode in the structure of the stress relaxation layer. In addition, the same points as the first embodiment will be omitted or simplified.
[氮化物半導體模板的結構] 第3圖表示第2實施型態之氮化物半導體模板2的垂直剖面圖。氮化物半導體模板2，與第1實施型態之氮化物半導體模板1不同之處在於，應力緩和層13是由組成式中的y值不同的複數個層所構成。關於應力緩和層13以外的結構，與氮化物半導體模板1的結構相同。[Structure of Nitride Semiconductor Template] FIG. 3 is a vertical sectional view of a nitride semiconductor template 2 according to a second embodiment. The nitride semiconductor template 2 is different from the nitride semiconductor template 1 of the first embodiment in that the stress relaxation layer 13 is composed of a plurality of layers having different y values in the composition formula. The structure other than the stress relaxation layer 13 is the same as the structure of the nitride semiconductor template 1.
在應力緩和層13是由組成式中的y值不同的複數個層所構成的情況下，該等複數個層之中，最上層的y值最低，而最下層的y值最高。在應力緩和層13具有這樣的結構的情況下，相較於由單一層所構成的情況，會更不容易在n型氮化物半導體層14發生破裂的情形，因此能夠增加n型氮化物半導體層14的膜厚，並提高結晶品質。When the stress relaxation layer 13 is composed of a plurality of layers having different y values in the composition formula, among the plurality of layers, the y value of the uppermost layer is the lowest, and the y value of the lowermost layer is the highest. In the case where the stress relaxation layer 13 has such a structure, it is less likely that cracks will occur in the n-type nitride semiconductor layer 14 than in the case where the stress relaxation layer 13 is composed of a single layer. Therefore, the n-type nitride semiconductor layer can be increased. 14 film thickness and improve crystal quality.
在第3圖所示的例子中，應力緩和層13，是由第1層13a與第1層13a上的第2層13b所構成。第1層13a與第2層13b均是以Aly Ga1 － y N(x＜y，0.5＜y≦0.6)作為主成分，且第1層13a的y值比第2層13b的y值更大。In the example shown in FIG. 3, the stress relaxation layer 13 is composed of the first layer 13a and the second layer 13b on the first layer 13a. The first layer 13a and the second layer 13b both have Al y Ga 1 - y N (x <y, 0.5 <y ≦ 0.6) as the main component, and the y value of the first layer 13a is greater than the y value of the second layer 13b Bigger.
例如，當第1層13a的組成式中的y為大約0.6時，若厚度在200nm以下便不容易在第1層13a中發生破裂的情形，且當第2層13b的組成式中的y為大約0.5～0.55時，若厚度在100nm以下便不容易在第2層13b中發生破裂的情形。又，在應力緩和層13是由3個以上的層所構成，且在第2層13b上進一步形成以Aly Ga1 － y N(x＜y，0.5＜y≦0.6)作為主成分之其他層的情況下，當該層的y為大約0.5～0.55時，若厚度在100nm以下便不容易發生破裂的情形。For example, when y in the composition formula of the first layer 13a is approximately 0.6, if the thickness is 200 nm or less, it is not easy to crack in the first layer 13a, and when y in the composition formula of the second layer 13b is When the thickness is about 0.5 to 0.55, if the thickness is 100 nm or less, the second layer 13b is unlikely to be cracked. In addition, the stress relaxation layer 13 is composed of three or more layers, and the second layer 13b is further formed with other components containing Al y Ga 1 - y N (x <y, 0.5 <y ≦ 0.6) as a main component. In the case of a layer, when the y of the layer is about 0.5 to 0.55, if the thickness is 100 nm or less, cracking is unlikely to occur.
又，與應力緩和層13為單層的情況相同的，為了抑制在n型氮化物半導體層14中發生破裂的情形，應力緩和層13的厚度(複數個層的厚度合計)較佳為150nm以上，而更佳為200nm以上。又，若超過300nm則容易在應力緩和層13中發生破裂的情形，因此應力緩和層13的厚度較佳為300nm以下。In addition, as in the case where the stress relaxation layer 13 is a single layer, in order to prevent cracks from occurring in the n-type nitride semiconductor layer 14, the thickness of the stress relaxation layer 13 (total thickness of the plurality of layers) is preferably 150 nm or more. And more preferably 200 nm or more. When the thickness exceeds 300 nm, cracks are likely to occur in the stress relaxation layer 13. Therefore, the thickness of the stress relaxation layer 13 is preferably 300 nm or less.
關於製造步驟，在上述的步驟S6中，藉由在途中改變TMG氣體與TMA氣體的流量比，便能夠形成由y值不同的複數個層所構成的應力緩和層13。Regarding the manufacturing steps, in step S6 described above, by changing the flow rate ratio of the TMG gas to the TMA gas on the way, the stress relaxation layer 13 composed of a plurality of layers having different y values can be formed.
(第3實施型態) [紫外線發光二極體的結構] 第3實施型態是關於紫外線發光二極體的型態，且該紫外線發光二極體包含第1實施型態之氮化物半導體模板1或是第2實施型態之氮化物半導體模板2。(Third Embodiment) [Structure of Ultraviolet Light Emitting Diode] The third embodiment is a type of an ultraviolet light emitting diode, and the ultraviolet light emitting diode includes a nitride semiconductor template of the first embodiment. 1 or the nitride semiconductor template 2 of the second embodiment.
第4圖是第3實施型態之紫外線發光二極體3的垂直剖面圖。紫外線發光二極體3具有：基板10、基板10上的緩衝層11、緩衝層11上的界面電阻降低層12、界面電阻降低層12上的應力緩和層13、應力緩和層13上的n型氮化物半導體層14、n型氮化物半導體層14上的發光層、發光層30上的p型電子阻隔層31、p型電子阻隔層31上的p型包覆層32、p型包覆層32上的接觸層33、接觸層33上的p側電極34、以及在基板10的與緩衝層11相反之一側的表面上的n側電極35。FIG. 4 is a vertical sectional view of the ultraviolet light emitting diode 3 according to the third embodiment. The ultraviolet light emitting diode 3 includes a substrate 10, a buffer layer 11 on the substrate 10, an interface resistance reduction layer 12 on the buffer layer 11, a stress relaxation layer 13 on the interface resistance reduction layer 12, and an n-type on the stress relaxation layer 13. Nitride semiconductor layer 14, light-emitting layer on n-type nitride semiconductor layer 14, p-type electron blocking layer 31 on light-emitting layer 30, p-type cladding layer 32, p-type cladding layer on p-type electron blocking layer 31 The contact layer 33 on 32, the p-side electrode 34 on the contact layer 33, and the n-side electrode 35 on the surface of the substrate 10 on the side opposite to the buffer layer 11.
此處，基板10、緩衝層11、界面電阻降低層12、應力緩和層13以及n型氮化物半導體層14，與第1實施型態之氮化物半導體模板1或是第2實施型態之氮化物半導體模板2中的該等構件相同。Here, the substrate 10, the buffer layer 11, the interface resistance reduction layer 12, the stress relaxation layer 13, and the n-type nitride semiconductor layer 14 are the same as the nitride semiconductor template 1 of the first embodiment or the nitrogen of the second embodiment. These components in the compound semiconductor template 2 are the same.
又，n型氮化物半導體層14，在紫外線發光二極體3中作為n型包覆層來發揮功能。The n-type nitride semiconductor layer 14 functions as an n-type cladding layer in the ultraviolet light emitting diode 3.
發光層30，例如具有多層構造，該多層構造包含將Inu1 Alv1 Gaw1 N層(0.02≦u1≦0.03，u1+v1+w1=1)的兩面以Inu2 Alv2 Gaw2 N層(0.02≦u2≦0.03，u2+v2+w2=1，v1+0.05≦v2≦v1+0.2)來加以夾持的結構。發光層30的代表性結構，是由3層的In0.02 Al0.19 Ga0.79 N層與合計4層的In0.02 Al0.29 Ga0.69 N層所構成的結構，其中該等4層In0.02 Al0.29 Ga0.69 N層的其中2層被形成在3層的In0.02 Al0.19 Ga0.79 N層的各層之間，其餘2層則是在最上層和最下層各形成1層。Light emitting layer 30, for example, a multilayer structure, the multilayer structure comprises In u1 Al v1 Ga w1 N layer (0.02 ≦ u1 ≦ 0.03, u1 + v1 + w1 = 1) on both sides to In u2 Al v2 Ga w2 N layer (0.02 ≦ u2 ≦ 0.03, u2 + v2 + w2 = 1, v1 + 0.05 ≦ v2 ≦ v1 + 0.2). The typical structure of the light-emitting layer 30 is a structure composed of three layers of In 0.02 Al 0.19 Ga 0.79 N layers and a total of four layers of In 0.02 Al 0.29 Ga 0.69 N layers, in which the four layers of In 0.02 Al 0.29 Ga 0.69 Two layers of the N layer are formed between the three layers of the In 0.02 Al 0.19 Ga 0.79 N layer, and the remaining two layers are each formed at the uppermost layer and the lowermost layer.
發光層30的Inu1 Alv1 Gaw1 N層的厚度，例如為2nm。又，Inu2 Alv2 Gaw2 N層的厚度，例如為5nm。在發光層30中，Inu1 Alv1 Gaw1 N層作為井層來發揮功能，而Inu2 Alv2 Gaw2 N層作為障壁層來發揮功能。例如，藉由將Inu1 Alv1 Gaw1 N層的Al組成v1作成0以上且0.3以下，能夠得到發光波長約300～360nm的發光二極體。The thickness of the In u1 Al v1 Ga w1 N layer of the light emitting layer 30 is, for example, 2 nm. The thickness of the In u2 Al v2 Ga w2 N layer is, for example, 5 nm. In the light emitting layer 30, the In u1 Al v1 Ga w1 N layer functions as a well layer, and the In u2 Al v2 Ga w2 N layer functions as a barrier layer. For example, by setting the Al composition v1 of the In u1 Al v1 Ga w1 N layer to 0 or more and 0.3 or less, a light emitting diode having an emission wavelength of about 300 to 360 nm can be obtained.
p型電子阻隔層31，例如為厚度30nm的In0.02 Al0.39 Ga0.59 N層。The p-type electron blocking layer 31 is, for example, an In 0.02 Al 0.39 Ga 0.59 N layer having a thickness of 30 nm.
p型包覆層32，例如為厚度30nm的In0.02 Al0.39 Ga0.59 N層。The p-type cladding layer 32 is, for example, an In 0.02 Al 0.39 Ga 0.59 N layer having a thickness of 30 nm.
接觸層33，例如為厚度20nm的In0.02 Al0.29 Ga0.69 N層。The contact layer 33 is, for example, an In 0.02 Al 0.29 Ga 0.69 N layer having a thickness of 20 nm.
p側電極34，是與接觸層33進行歐姆接合的電極，例如由Al所構成。N側電極35，是與基板10進行歐姆接合的電極，例如具有Ti／Au積層構造。The p-side electrode 34 is an electrode that is ohmically bonded to the contact layer 33 and is made of, for example, Al. The N-side electrode 35 is an electrode that is ohmically bonded to the substrate 10 and has, for example, a Ti / Au multilayer structure.
紫外線發光二極體3，例如是自基板10側取出光的發光二極體晶片，並藉由蒸鍍Al而被構裝於筒式(can type)封裝的底座上。The ultraviolet light emitting diode 3 is, for example, a light emitting diode wafer from which light is taken out from the substrate 10 side, and is mounted on a base of a can type package by vapor-depositing Al.
(實施型態的功效) 根據上述第1、2實施型態，能夠提供一種高品質的氮化物半導體模板，其抑制在n型氮化物半導體層中發生應力生，使得破裂的情形較少。(Effect of Implementation Mode) According to the above-mentioned first and second implementation modes, it is possible to provide a high-quality nitride semiconductor template which suppresses stress generation in the n-type nitride semiconductor layer and makes it less likely to crack.
並且，根據上述第3實施型態，藉由使用這樣的高品質的氮化物半導體模板，能夠以高良率來製造高品質的發光二極體元件等之紫外線發光二極體。In addition, according to the third embodiment, by using such a high-quality nitride semiconductor template, a high-quality ultraviolet light-emitting diode such as a light-emitting diode element can be manufactured with a high yield.
(實施例1) 以下，針對下述各者的關係進行評價：上述實施型態之界面電阻降低層12、應力緩和層13以及n型氮化物半導體層14的結構和形成條件、應力緩和層13和n型氮化物半導體層14發生破裂的情形的容易程度和n型氮化物半導體層14的結晶品質。在以下之表1中，表示該評價結果。(Example 1) Hereinafter, the relationship between the structure and formation conditions of the interface resistance reduction layer 12, the stress relaxation layer 13, and the n-type nitride semiconductor layer 14 and the stress relaxation layer 13 of the above-described embodiment is evaluated. The ease with which the n-type nitride semiconductor layer 14 is cracked and the crystal quality of the n-type nitride semiconductor layer 14. The evaluation results are shown in Table 1 below.
此評價中所使用的13種氮化物半導體模板(試樣1～13)的基板，均為以(－201)面作為主面之直徑2吋的圓形Ga2 O3 基板，且緩衝層均為厚度2nm的AlN層。又，試樣1～13的界面電阻降低層、應力緩和層以及n型氮化物半導體層的n型雜質的濃度，均為4×1018 ／cm3 。The substrates of the 13 kinds of nitride semiconductor templates (samples 1 to 13) used in this evaluation were all circular Ga 2 O 3 substrates having a diameter of 2 inches with the (-201) plane as the main surface, and the buffer layers were all It is an AlN layer with a thickness of 2 nm. The concentrations of the n-type impurities in the interface resistance reducing layer, the stress relaxation layer, and the n-type nitride semiconductor layer of the samples 1 to 13 were all 4 × 10 18 / cm 3 .
又，試樣1～13的界面電阻降低層、應力緩和層以及n型氮化物半導體層的成長壓力為76Torr(100hpa)。又，試樣1～12的n型氮化物半導體層的成長速率為2.5μm／h，試樣13的n型氮化物半導體層的成長速率為1.25μm／h。In addition, the growth pressure of the interface resistance reducing layer, the stress relaxation layer, and the n-type nitride semiconductor layer of the samples 1 to 13 was 76 Torr (100 hpa). The growth rate of the n-type nitride semiconductor layers of samples 1 to 12 was 2.5 μm / h, and the growth rate of the n-type nitride semiconductor layer of samples 13 was 1.25 μm / h.
[表1]
表1中表示出試樣1～13的以下資料：界面電阻降低層、應力緩和層以及n型氮化物半導體層的化學組成式和厚度、應力緩和層以及n型氮化物半導體層的表面的破裂數、以及n型氮化物半導體層的(002)面和(102)面的X射線搖擺曲線(X-ray rocking curve，XRC)的半值寬度。Table 1 shows the following data of samples 1 to 13: the chemical composition formula and thickness of the interface resistance reduction layer, the stress relaxation layer, and the n-type nitride semiconductor layer, and the surface cracks of the stress relaxation layer and the n-type nitride semiconductor layer. And the half-value width of the X-ray rocking curve (XRC) of the (002) plane and the (102) plane of the n-type nitride semiconductor layer.
此處，所謂破裂數，是指與破裂正交之方向的每1cm長度中的平均條數。在n型氮化物半導體層的表面所發生的破裂情形，會沿著面內的特定一方向出現。因此，能夠沿著與破裂正交之方向對破裂的條數進行計數。此外，在應力緩和層中發生的破裂，是以100條以上／cm的密度分別發生於自Ga2 O3 結晶的[010]方向偏離60°後之三次對稱(three-fold symmetry)之方向上。但是，在應力緩和層中發生破裂的情形，能夠藉由適當設定應力緩和層的厚度而幾乎完全防止住，因此以破裂情形的「有、無」來加以判定。Here, the number of ruptures means an average number per 1 cm of length in a direction orthogonal to the ruptures. A crack that occurs on the surface of the n-type nitride semiconductor layer may occur along a specific direction within the plane. Therefore, the number of cracks can be counted in a direction orthogonal to the cracks. In addition, the cracks occurring in the stress relaxation layer occurred at a density of 100 lines / cm or more in three-fold symmetry directions after the [010] direction of the Ga 2 O 3 crystal deviated from 60 °. . However, the occurrence of cracking in the stress relaxation layer can be almost completely prevented by appropriately setting the thickness of the stress relaxation layer. Therefore, the presence or absence of the cracking condition is used to determine.
試樣1～7，即使在基板與n型氮化物半導體層之間施加電壓也沒有足夠的電流流過，不適合用來製造紫外線發光二極體等之元件。這被認為是因為試樣1～7中的自上方緊鄰緩衝層之層也就是Al0.75 Ga0.25 N層的Al組成太大，使得與基板之間的界面電阻變大的緣故。亦即，雖然在表1中Al0.75 Ga0.25 N層被記載為界面電阻降低層，但實際上並沒有作為界面電阻降低層來發揮功能。Samples 1 to 7 did not have sufficient current flowing even when a voltage was applied between the substrate and the n-type nitride semiconductor layer, and were not suitable for use in the production of devices such as ultraviolet light emitting diodes. This is considered to be because the Al composition of the layer immediately above the buffer layer, that is, the Al 0.75 Ga 0.25 N layer in samples 1 to 7, is too large, which causes the interface resistance with the substrate to increase. That is, although the Al 0.75 Ga 0.25 N layer is described as the interface resistance reduction layer in Table 1, it does not actually function as the interface resistance reduction layer.
又，試樣3、4，在n型氮化物半導體層中發生破裂的條數比其他試樣更多。這被認為是因為應力緩和層太薄的緣故。In the samples 3 and 4, the number of cracks in the n-type nitride semiconductor layer was larger than in other samples. This is considered to be because the stress relaxation layer is too thin.
又，試樣5、6，在應力緩和層中有破裂情形發生。這被認為是因為應力緩和層太厚的緣故。In addition, in the samples 5 and 6, cracks occurred in the stress relaxation layer. This is considered to be because the stress relaxation layer is too thick.
試樣8，即使在基板與n型氮化物半導體層之間施加電壓也沒有足夠的電流流過，不適合用來製造紫外線發光二極體等之元件。這被認為是因為試樣8所具有用來作為應力緩和層之Al0.75 Ga0.25 N層的Al組成較大，使得應力緩和層被高電阻化的緣故。Sample 8 did not have sufficient current flowing even when a voltage was applied between the substrate and the n-type nitride semiconductor layer, and was not suitable for use in the production of an element such as an ultraviolet light emitting diode. This is considered to be because the Al composition of the Al 0.75 Ga 0.25 N layer used as the stress relaxation layer in the sample 8 is large, so that the stress relaxation layer is highly resistive.
試樣9～13，其界面電阻降低層、應力緩和層以及n型氮化物半導體層的化學組成式和厚度滿足第1實施型態所記載之條件，在電流－電壓特性以及應力緩和層與n型氮化物半導體層的表面的破裂數上都沒有問題。In samples 9 to 13, the chemical composition formula and thickness of the interface resistance reduction layer, the stress relaxation layer, and the n-type nitride semiconductor layer satisfy the conditions described in the first embodiment. The current-voltage characteristics, the stress relaxation layer, and n There is no problem in the number of cracks on the surface of the type nitride semiconductor layer.
第5A圖、第5B圖表示試樣1的n型氮化物半導體層的(002)面和(102)面的X射線搖擺曲線。第6A圖、第6B圖表示試樣11的n型氮化物半導體層的(002)面和(102)面的X射線搖擺曲線。第7A圖、第7B圖表示試樣13的n型氮化物半導體層的(002)面和(102)面的X射線搖擺曲線。5A and 5B show X-ray rocking curves of the (002) plane and the (102) plane of the n-type nitride semiconductor layer of the sample 1. FIG. 6A and 6B show X-ray rocking curves of the (002) plane and the (102) plane of the n-type nitride semiconductor layer of the sample 11. 7A and 7B show X-ray rocking curves of the (002) plane and the (102) plane of the n-type nitride semiconductor layer of the sample 13.
若比較第5A圖、第5B圖與第6A圖、第6B圖，可觀察到試樣11的n型氮化物半導體層的X射線搖擺曲線的半峰全寬比試樣1的半峰全寬更小。這被認為是因為藉由以三維成長層與二維成長層來構成n型氮化物半導體層，而提高了結晶品質的緣故。Comparing FIGS. 5A and 5B with FIGS. 6A and 6B, it can be observed that the full width at half maximum of the X-ray rocking curve of the n-type nitride semiconductor layer of sample 11 is greater than the full width at half maximum of sample 1 smaller. This is considered to be because the n-type nitride semiconductor layer is composed of a three-dimensional growth layer and a two-dimensional growth layer, thereby improving the crystal quality.
又，若比較第6A圖、第6B圖與第7A圖、第7B圖，可觀察到試樣13的n型氮化物半導體層的X射線搖擺曲線的半峰全寬比試樣11的半峰全寬更小。這被認為是因為藉由將n型氮化物半導體層的成長速率設為一半，而提高了結晶品質的緣故。In addition, when comparing FIGS. 6A and 6B with FIGS. 7A and 7B, the full width at half maximum of the X-ray rocking curve of the n-type nitride semiconductor layer of sample 13 can be observed. Full width is smaller. This is considered to be because the growth rate of the n-type nitride semiconductor layer was set to half, thereby improving the crystal quality.
(實施例2) 針對上述實施型態之氮化物半導體層的Al組成與位能障壁間之關係進行評價。(Example 2) The relationship between the Al composition of the nitride semiconductor layer and the potential barrier in the above-described embodiment was evaluated.
在此評價中，製作出2種試樣來進行檢定，上述2種試樣，分別是在緩衝層與應力緩和層之間使用了摻雜有濃度4×1018 ／cm3 的Si之厚度50nm的Al0.3 Ga0.7 N界面電阻降低層的試樣、以及未使用該界面電阻降低層的試樣。又，在此評價中，使用以下各層：摻雜有濃度3×1018 ／cm3 的Sn且將(－201)面作為主面之Ga2 O3 基板、作為緩衝層的厚度2nm的AlN層、作為應力緩和層的摻雜有濃度4×1018 ／cm3 的Si之厚度150nm的Al0.6 Ga0.4 N層、摻雜有濃度4×1018 ／cm3 的Si之厚度1μm的Al0.4 Ga0.6 N層。針對這2個試樣，在Al0.4 Ga0.6 N層上形成直徑300μm的圓形TiAl電極，並在Ga2 O3 基板上形成直徑300μm的圓形TiAu電極，將電極合金化後，施加電壓並測量電壓－電流特性。In this evaluation, two types of samples were prepared and tested. The two types of samples were 50 nm thick with Si doped at a concentration of 4 × 10 18 / cm 3 between the buffer layer and the stress relaxation layer. A sample of Al 0.3 Ga 0.7 N interfacial resistance reducing layer and a sample not using the interfacial resistance reducing layer. In this evaluation, the following layers were used: a Ga 2 O 3 substrate doped with Sn at a concentration of 3 × 10 18 / cm 3 and having a (−201) plane as a main surface; and a 2 nm-thick AlN layer as a buffer layer. Al 0.6 Ga 0.4 N layer doped with Si at a concentration of 4 × 10 18 / cm 3 as a stress relaxation layer and having a thickness of 150 nm at a thickness of 4 × 10 18 / cm 3 , and Al 0.4 Ga doped with Si having a concentration of 4 × 10 18 / cm 3 at a thickness of 1 μm. 0.6 N layers. For these two samples, a circular TiAl electrode with a diameter of 300 μm was formed on the Al 0.4 Ga 0.6 N layer, and a circular TiAu electrode with a diameter of 300 μm was formed on a Ga 2 O 3 substrate. After the electrodes were alloyed, a voltage was applied and Measure voltage-current characteristics.
第8A圖表示未使用Al0.3 Ga0.7 N界面電阻降低層的情況下的電流密度－電壓特性。第8B圖表示有使用Al0.3 Ga0.7 N界面電阻降低層的情況下的電流密度－電壓特性。FIG. 8A shows the current density-voltage characteristics when the Al 0.3 Ga 0.7 N interface resistance reduction layer is not used. FIG. 8B shows a current density-voltage characteristic when an Al 0.3 Ga 0.7 N interface resistance reducing layer is used.
若比較第8A圖與第8B圖，未使用Al0.3 Ga0.7 N界面電阻降低層的情況下，電流開始流動之正側電壓與負側電壓的差(稱作偏移量)較大。這被認為是因為自上方緊鄰緩衝層之層也就是Al0.6 Ga0.4 N層的Al組成太大，使得與基板之間的界面電阻變大的緣故。由此結果可知，不適合使用Al0.6 Ga0.4 N層來作為上述實施型態之的界面電阻降低層。另一方面，在使用Al0.3 Ga0.7 N界面電阻降低層的情況下，能夠充分降低與基板之間的界面電阻。Comparing FIG. 8A and FIG. 8B, when the Al 0.3 Ga 0.7 N interface resistance reduction layer is not used, the difference between the positive-side voltage and the negative-side voltage (referred to as an offset) at which the current starts to flow is large. This is considered to be because the Al composition of the layer immediately above the buffer layer, that is, the Al 0.6 Ga 0.4 N layer, is too large, so that the interface resistance with the substrate becomes large. From this result, it can be seen that it is not suitable to use an Al 0.6 Ga 0.4 N layer as the interface resistance reduction layer in the above embodiment. On the other hand, when an Al 0.3 Ga 0.7 N interface resistance reducing layer is used, the interface resistance with the substrate can be sufficiently reduced.
以上，說明過了本發明的實施型態和實施例，但本發明並不限定於上述實施型態和實施例，在不逸脫發明主旨的範圍內可作各種變化之實施。The embodiments and examples of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments and examples, and various changes can be made without departing from the scope of the invention.
又，上述所記載的實施型態和實施例並非用來限定申請專利範圍之發明。又，應注意的是，在用來解決發明的問題的手段中，並不一定需要實施型態和實施例中所說明過的特徵的所有組合。In addition, the implementation modes and examples described above are not intended to limit the scope of the invention for which a patent is applied. In addition, it should be noted that, in the means for solving the problems of the invention, not all combinations of the features described in the embodiment and the embodiments are necessarily required.
1‧‧‧氮化物半導體模板
2‧‧‧氮化物半導體模板
3‧‧‧紫外線發光二極體
10‧‧‧基板
11‧‧‧緩衝層
12‧‧‧界面電阻降低層
13‧‧‧應力緩和層
14‧‧‧n型氮化物半導體層
14a‧‧‧三維成長層
14b‧‧‧二維成長層
30‧‧‧發光層
31‧‧‧電子阻隔層
32‧‧‧p型包覆層
33‧‧‧接觸層
34‧‧‧p側電極
35‧‧‧n側電極
S1～S12‧‧‧步驟
T1～T3‧‧‧溫度1‧‧‧Nitride semiconductor template
2‧‧‧Nitride Semiconductor Template
3‧‧‧ ultraviolet light emitting diode
10‧‧‧ substrate
11‧‧‧ buffer layer
12‧‧‧Interfacial resistance reduction layer
13‧‧‧ Stress Relief Layer
14‧‧‧n-type nitride semiconductor layer
14a‧‧‧Three-dimensional growth layer
14b‧‧‧Two-dimensional growth layer
30‧‧‧Light-emitting layer
31‧‧‧Electronic Barrier Layer
32‧‧‧p-type coating
33‧‧‧contact layer
34‧‧‧p side electrode
35‧‧‧n side electrode
Steps S1 ～ S12‧‧‧‧
T1 ～ T3‧‧‧‧Temperature
第1圖是第1實施型態之氮化物半導體模板的垂直剖面圖。 第2圖是表示在第1實施型態之氮化物半導體模板1的製造步驟中，供給氣體的供給時序的圖表、以及表示伴隨時間經過的溫度條件的變化的圖表。 第3圖是第2實施型態之氮化物半導體模板的垂直剖面圖。 第4圖是第3實施型態之紫外線發光二極體的垂直剖面圖。 第5A圖表示實施例1之試樣1的n型氮化物半導體層的(002)面的X射線搖擺曲線。 第5B圖表示實施例1之試樣1的n型氮化物半導體層的(102)面的X射線搖擺曲線。 第6A圖表示實施例1之試樣11的n型氮化物半導體層的(002)面的X射線搖擺曲線。 第6B圖表示實施例1之試樣11的n型氮化物半導體層的(102)面的X射線搖擺曲線。 第7A圖表示實施例1之試樣12的n型氮化物半導體層的(002)面的X射線搖擺曲線。 第7B圖表示實施例1之試樣12的n型氮化物半導體層的(102)面的X射線搖擺曲線。 第8A圖表示未使用第1圖中的界面電阻層，而在緩衝層上形成應力緩和層，然後在其上形成n型氮化物半導體層，並在上下製作電極來加以評價時的電流密度－電壓特性。 第8B圖表示根據與第1圖相同的結構來使用界面電阻降低層時的電流密度－電壓特性。FIG. 1 is a vertical sectional view of a nitride semiconductor template according to a first embodiment. FIG. 2 is a graph showing the supply timing of the supply gas in the manufacturing steps of the nitride semiconductor template 1 according to the first embodiment, and a graph showing changes in temperature conditions with the passage of time. FIG. 3 is a vertical sectional view of a nitride semiconductor template according to a second embodiment. Fig. 4 is a vertical sectional view of an ultraviolet light emitting diode according to a third embodiment. FIG. 5A shows an X-ray rocking curve of the (002) plane of the n-type nitride semiconductor layer of Sample 1 of Example 1. FIG. FIG. 5B shows an X-ray rocking curve of the (102) plane of the n-type nitride semiconductor layer of Sample 1 of Example 1. FIG. FIG. 6A shows an X-ray rocking curve of the (002) plane of the n-type nitride semiconductor layer of the sample 11 of Example 1. FIG. FIG. 6B shows an X-ray rocking curve of the (102) plane of the n-type nitride semiconductor layer of the sample 11 of Example 1. FIG. FIG. 7A shows an X-ray rocking curve of the (002) plane of the n-type nitride semiconductor layer of the sample 12 of Example 1. FIG. FIG. 7B shows an X-ray rocking curve of the (102) plane of the n-type nitride semiconductor layer of the sample 12 of Example 1. FIG. Fig. 8A shows the current density when the stress relief layer is formed on the buffer layer without using the interface resistance layer in Fig. 1, and then an n-type nitride semiconductor layer is formed thereon. Voltage characteristics. FIG. 8B shows a current density-voltage characteristic when an interface resistance reducing layer is used with the same structure as in FIG. 1.
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic hosting information (please note in order of hosting institution, date, and number) None
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Information on foreign deposits (please note in order of deposit country, institution, date, and number) None
(請換頁單獨記載) 無(Please page separately)
1‧‧‧氮化物半導體模板 1‧‧‧Nitride semiconductor template
10‧‧‧基板 10‧‧‧ substrate
11‧‧‧緩衝層 11‧‧‧ buffer layer
12‧‧‧界面電阻降低層 12‧‧‧Interfacial resistance reduction layer
13‧‧‧應力緩和層 13‧‧‧ Stress Relief Layer
14‧‧‧n型氮化物半導體層 14‧‧‧n-type nitride semiconductor layer
14a‧‧‧三維成長層 14a‧‧‧Three-dimensional growth layer
14b‧‧‧二維成長層 14b‧‧‧Two-dimensional growth layer
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016040531A JP2017157725A (en) | 2016-03-02 | 2016-03-02 | Nitride semiconductor template and manufacturing method thereof, and ultraviolet led |
| JP2016-040531 | 2016-03-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201801345A true TW201801345A (en) | 2018-01-01 |
Family
ID=59743833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106104838A TW201801345A (en) | 2016-03-02 | 2017-02-15 | Nitride semiconductor template, method for manufacturing same, and ultraviolet led |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2017157725A (en) |
| TW (1) | TW201801345A (en) |
| WO (1) | WO2017150161A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6934473B2 (en) * | 2016-06-24 | 2021-09-15 | スタンレー電気株式会社 | Group III nitride semiconductor light emitting device |
| CN110808320B (en) * | 2019-11-12 | 2020-11-20 | 清华大学 | Deep ultraviolet LED structure and manufacturing method thereof |
| CN111369759A (en) * | 2019-12-31 | 2020-07-03 | 浙江万芯集成科技有限公司 | Electrical fire monitoring system based on photoelectric type thin film chip |
| JP2022147881A (en) | 2021-03-24 | 2022-10-06 | アダマンド並木精密宝石株式会社 | Ga2O3-BASED SINGLE CRYSTAL SUBSTRATE AND MANUFACTURING METHOD OF Ga2O3-BASED SINGLE CRYSTAL SUBSTRATE |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234902A (en) * | 2006-03-01 | 2007-09-13 | Toyoda Gosei Co Ltd | Light-emitting element, and manufacturing method thereof |
| JP5596222B2 (en) * | 2011-04-08 | 2014-09-24 | 株式会社タムラ製作所 | Semiconductor laminate, method for manufacturing the same, and semiconductor element |
| US9165766B2 (en) * | 2012-02-03 | 2015-10-20 | Transphorm Inc. | Buffer layer structures suited for III-nitride devices with foreign substrates |
-
2016
- 2016-03-02 JP JP2016040531A patent/JP2017157725A/en active Pending
-
2017
- 2017-02-13 WO PCT/JP2017/005162 patent/WO2017150161A1/en active Application Filing
- 2017-02-15 TW TW106104838A patent/TW201801345A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017157725A (en) | 2017-09-07 |
| WO2017150161A1 (en) | 2017-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5853921B2 (en) | Group III nitride semiconductor light emitting device and method of manufacturing the same | |
| US7183578B2 (en) | Semiconductor apparatus, method for growing nitride semiconductor and method for producing semiconductor apparatus | |
| JP5596222B2 (en) | Semiconductor laminate, method for manufacturing the same, and semiconductor element | |
| TWI497766B (en) | Method for producing semiconductor device | |
| WO2010095550A1 (en) | Method for forming epitaxial wafer and method for manufacturing semiconductor element | |
| JP4891462B2 (en) | Gallium nitride compound semiconductor light emitting device | |
| TW201801345A (en) | Nitride semiconductor template, method for manufacturing same, and ultraviolet led | |
| KR101799330B1 (en) | Film formation method, method for manufacturing semiconductor light-emitting element, semiconductor light-emitting element, and lighting apparatus | |
| JPWO2008136504A1 (en) | Group III nitride semiconductor light emitting device manufacturing method | |
| JP5559814B2 (en) | Nitride-based semiconductor light-emitting diode and manufacturing method thereof | |
| JP2006332258A (en) | Nitride semiconductor device and its manufacturing method | |
| WO2006112167A1 (en) | METHOD FOR MANUFACTURING p TYPE NITRIDE SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURED BY SUCH METHOD | |
| JP2013207257A (en) | MANUFACTURING METHOD OF Ga-CONTAINING GROUP III NITRIDE SEMICONDUCTOR | |
| JP4770580B2 (en) | Method of manufacturing nitride semiconductor device | |
| JP4647723B2 (en) | Nitride semiconductor crystal growth method and semiconductor device manufacturing method | |
| JP2009238772A (en) | Epitaxial substrate, and manufacturing method of epitaxial substrate | |
| US9520527B1 (en) | Nitride semiconductor template and ultraviolet LED | |
| TW201543548A (en) | Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor device | |
| JP3064891B2 (en) | Group 3-5 compound semiconductor, method of manufacturing the same, and light emitting device | |
| JP4282976B2 (en) | BORON PHOSPHIDE COMPOUND SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND LIGHT EMITTING DIODE | |
| JP2004119423A (en) | Gallium nitride crystal substrate, its producing process, gallium nitride based semiconductor device, and light emitting diode | |
| JP4720519B2 (en) | Method for manufacturing p-type nitride semiconductor | |
| JP2015160752A (en) | Manufacturing method of multielemental mixed crystal of nitride semiconductor | |
| JP2016082200A (en) | Crystal laminate structure and manufacturing method thereof, and semiconductor device | |
| JP3752739B2 (en) | Light emitting element |