TW201742243A - Pixel structure and display device - Google Patents

Abstract

A pixel structure includes a first transistor and a first capacitor. The first transistor and a capacitor are disposed on a flexible substrate. The first transistor includes a gate electrode, and the capacitor includes a capacitor electrode. A first conductive electrode is formed correspondingly below the capacitor electrode, and the capacitor electrode overlaps at least one part of the first conductive electrode in a vertical projection on the flexible substrate.

Description

Pixel structure and its display panel

The present invention relates to a pixel structure and a display panel therefor.

Among various flat panel displays, Organic Light Emitting Display (OLED) is expected to become the mainstream of the next generation of flat panel display due to its wide viewing angle, good color contrast effect, fast response speed and low cost.

In order to maintain the required storage capacitance, an organic light-emitting display often needs to retain a sufficient area, and the setting of the storage capacitor causes the effective light-emitting area (effective light-emitting area) to become small, resulting in a problem of a small aperture ratio. Moreover, as the resolution of OLED products increases and the picture quality requirements increase, the pixel size becomes smaller and smaller, and the pixel circuits become more and more complicated. How to maintain the capacitance capacity without increasing the plane area of the storage capacitor and improve the stability of the pixel circuit drive is the goal of continuous efforts in this field.

The present invention provides a pixel structure including a flexible substrate, a buffer layer, a first conductive electrode, a first protective layer, a semiconductor layer, a gate insulating layer, an electrode layer, a gate, a capacitor electrode layer, and a second protective layer. , source and bungee, and pixel electrodes. The buffer layer is provided on the flexible substrate. The first conductive electrode is disposed on the buffer layer. The first protective layer is disposed on the first conductive electrode. A semiconductor layer is disposed on the first protective layer. The gate insulating layer is disposed on the semiconductor layer, and the gate insulating layer has a first through hole and a second through hole. The gate is disposed on the gate insulating layer. The electrode layer is disposed on the gate insulating layer, and the electrode layer has at least one gate and at least one capacitor electrode. The gate and the semiconductor layer partially overlap the vertical projection on the flexible substrate, and the capacitor electrode and the first conductive electrode are vertically projected on the flexible substrate to at least partially overlap. Wherein at least two of the capacitor electrode, the semiconductor layer and the first conductive electrode are coupled to form a storage capacitor. The second protective layer is disposed on the gate, the capacitor electrode and the gate insulating layer, and the second protective layer and the gate insulating layer have a first through hole and a second through hole. The source and the drain are respectively disposed on the second protective layer and are separated from each other, and the source and the drain are in contact with the semiconductor layer through the first through hole and the second through hole. The pixel electrode is disposed on the second protective layer and is connected to the source or the drain.

In one embodiment of the invention, the material of the semiconductor layer comprises polysilicon.

In an embodiment of the invention, the second conductive electrode is further disposed on the buffer layer, and the second conductive electrode and the vertical projection of the gate overlap at least a portion of the flexible substrate.

In one embodiment of the invention, the semiconductor layer does not extend below the capacitor electrode.

In an embodiment of the invention, at least a portion of the semiconductor layer extends below the capacitor electrode,

The capacitor electrode and the semiconductor layer under the capacitor electrode overlap at least partially on the flexible substrate, wherein the semiconductor layer under the capacitor electrode is a doped semiconductor layer.

In an embodiment of the invention, the first protective layer and the gate insulating layer have at least one connection hole, and the capacitor electrode is connected to the first conductive electrode through the connection hole.

In some embodiments of the present invention, a third protective layer is further disposed on the source, the drain and the second protective layer. The third protective layer has a third through hole. Wherein, the pixel electrode is in contact with the source or the drain by the third through hole.

In an embodiment of the invention, the pixel defining layer is further disposed on the third protective layer, and the pixel defining layer has an opening such that the pixel electrode is located in the opening.

In an embodiment of the invention, the organic flat layer is further disposed on a portion of the third protective layer.

In one embodiment of the invention, the first conductive electrode is a floating electrode.

In one embodiment of the invention, the projected shape or pattern of the first conductive electrode and the capacitor electrode perpendicularly projected onto the flexible substrate is substantially the same.

In an embodiment of the invention, the capacitor electrode is coupled to the first conductive electrode as a storage capacitor.

In one embodiment of the invention, the storage capacitor includes a first storage capacitor and a second storage capacitor, wherein the capacitor electrode layer is coupled to the semiconductor layer as a first storage capacitor, and the semiconductor layer is coupled to the first conductive electrode as a second storage capacitor.

The display panel of the present invention comprises a plurality of pixel structures, another substrate and a display medium layer. At least a portion of the pixel structures comprise a pixel structure as described in one of the embodiments of the present invention. The other substrate is disposed opposite to the flexible substrate. The display medium layer is disposed between the other substrate and the flexible substrate.

The present invention will be further understood by those skilled in the art to which the present invention pertains. . The layers of the elements drawn in the drawings are only for reference and do not represent the relative thickness of each component layer.

1 is a schematic diagram showing an equivalent circuit of a pixel structure of an organic light emitting diode display panel according to an embodiment of the invention. Referring to FIG. 1 , the pixel structure of the organic light emitting diode display panel includes an organic light emitting diode OLED, a data line Yn, a scan line Xn, a switching thin film transistor Ta, a driving thin film transistor Tb, and a storage capacitor Cst. The gate G1 of the switching thin film transistor Ta is coupled to the scan line Xn, the first electrode S1 is coupled to the data line Yn, and the second electrode D1 is coupled to the gate G2 of the driving thin film transistor Tb. The second electrode D2 of the driving film transistor Tb is coupled to the organic light emitting diode OLED, and the first electrode S2 is coupled to the power line Vdd. One end electrode of the storage capacitor Cst is electrically connected to the second electrode D2 of the driving film transistor Tb, and the other end electrode of the storage capacitor Cst is electrically connected to the second electrode D1 of the switching film transistor Ta. In this embodiment, the pixel structure is applied to an electroluminescent display panel, for example, a pixel structure of an organic electroluminescence display panel, and has a structure of two thin film transistors and one capacitor (2T1C). For example, the invention is not limited thereto. In other embodiments, the pixel structure may also be a combination of three thin film transistors (eg, 6T1C, 5T1C, 3T1C structure), 1T1C structure, or other combination of thin film transistors and capacitors. The structure can also be applied to other display panels, such as a liquid crystal display panel, an electrophoretic display panel, an electrowetting display panel, or other display panels. In addition, for the sake of brevity of the following embodiments, the cross-sectional views of FIGS. 2, 3, 4, and 5 are for the cross section of the driving thin film transistor Tb and the storage capacitor Cst in the pixel structure of 2T1C, but are not limited thereto. this.

2 illustrates a pixel structure 10 of a first embodiment of the present invention. The pixel structure 10 of the first embodiment. The pixel structure 10 includes a flexible substrate 100, a buffer layer B, a first conductive electrode 106, a first protective layer 108, a semiconductor layer SE, a gate insulating layer GI, a gate GE, an electrode layer 201, and a second protective layer 110. , source S and drain D and pixel electrode PE. The flexible substrate 100 may be made of, for example, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Organic materials such as polyamide (PA), but not limited to this. In order to make the display panel stiff, other types of support substrates such as glass, quartz, ceramics, metals, alloys or other suitable materials may be attached to the outer surface of the flexible substrate 100 through static electricity or adhesive. The buffer stack B, optionally including the first buffer layer 102 and the second buffer layer 104, is disposed on the inner surface of the substrate 100. The material of the buffer layer B includes an inorganic material (for example: cerium oxide, cerium nitride, cerium oxynitride or other suitable materials), an organic material (for example, polyimide (PI), poly(ethylene terephthalate). Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or other suitable materials, or other suitable materials, or combinations thereof. The number of buffer layers B can be adjusted according to actual needs. The first buffer layer 102 and the second buffer layer 104 of the buffer layer B of this embodiment are only for example, the number of buffer layers B is greater than 1, and should be within the scope of the present embodiment. Preferably, the buffer layer B includes the first buffer layer 102 and the second buffer layer 104, and the foregoing materials are respectively an example of tantalum nitride and hafnium oxide, which can prevent impurities of the flexible substrate 100 from entering the subsequent film layer. The adhesion of the subsequent film layer to the flexible substrate 100 can also be increased.

The first conductive electrode 106 is disposed on the buffer layer B. The first conductive electrode 106 is preferably a folating or floating electrode, that is, the first conductive electrode 106 is not connected to other potentials. In other embodiments, the first conductive electrode 106 can be selectively connected to a fixed potential, such as ground or a common potential. The first conductive electrode 106 may be a single layer or a plurality of layers, and the material thereof may be selected from a non-transmissive conductive material (for example, aluminum, copper, silver, chromium, titanium, molybdenum, or other suitable materials, or alloys of the above materials). ), a transparent conductive material, but not limited thereto, other materials having conductive properties may be used. The first protective layer 108 is disposed on the first conductive layer 106. The first protective layer 108 may be a single layer or a plurality of layers, and the material thereof comprises an inorganic material (for example: yttria, tantalum nitride, ytterbium oxynitride, other suitable materials, or a combination thereof), an organic material (for example: photoresist) , polyimide (PI), benzocyclobutene (BCB), epoxy (Epoxy), perfluorocyclobutane (PFCB), other suitable materials, or combinations thereof, or other suitable Material, or a combination of the above. The semiconductor layer SE is disposed on the first protective layer 108. It should be noted that, in this embodiment, the semiconductor layer SE extends from the predetermined thin film transistor, for example, the thin film transistor T in FIG. 2, to above the first conductive electrode 106. The semiconductor layer SE at which the thin film transistor is to be formed has a channel region CH and two doped regions (or ohmic contact regions) SE1 and SE2 respectively located on two sides of the channel region CH, and the channel region CH is an intrinsic region. The undoped region or a small amount of doping concentration for certain regulatory thin film transistors is less than or substantially equal to the lightly doped region (LDD). Preferably, the semiconductor layer SE extending over the first conductive electrode 106 is a doped region SE2 or a doped semiconductor, which can be used similarly to a conductive electrode. The semiconductor layer SE material is preferably composed of polycrystalline germanium, but in other applications, the semiconductor layer SE may also include amorphous germanium, microcrystalline germanium, single crystal germanium, organic semiconductor materials, and oxide semiconductor materials (eg, indium zinc oxide). , indium antimony zinc oxide, or other suitable materials, or combinations thereof, or other suitable materials, or containing dopants in the above materials, or a combination thereof.

Next, the gate insulating layer GI is provided on the semiconductor layer SE. The gate insulating layer GI may be a single layer or a multilayer structure, and the material thereof may be selected from the material of the first protective layer 108, and the materials of the two may be substantially the same or different. The electrode layer 201 is provided on the gate insulating layer GI. The semiconductor layer SE has doped regions SE1, SE2 and a channel region CH. The electrode layer 201 includes at least one gate GE and at least one capacitor electrode 201a respectively disposed on the gate insulating layer GI, and the gate GE and the capacitor electrode 201a are preferably separated. The material of the electrode layer 201 may be a single layer or a plurality of layers, and the material thereof may be selected from the materials described in the first conductive electrode 106, and the materials of the two may be substantially the same or different. The gate GE and the capacitor electrode 201a are preferably formed in the same process or film layer, but are not limited thereto. The gate electrode GE and the semiconductor layer SE are partially overlapped on the flexible substrate 100, that is, the gate electrode GE corresponds to and overlaps the channel region CH of the semiconductor layer SE, and the capacitor electrode 201a and the first conductive electrode 106 At least a portion of the vertical projection on the flexible substrate 100 overlaps. Preferably, the projection shape or pattern of the first conductive electrode 106 and the capacitor electrode 201a perpendicularly projected onto the flexible substrate 100 are substantially the same, and the aperture ratio is reduced to a small extent, but is not limited thereto. different. It should be noted that the semiconductor layer SE (for example, the doped region SE2 or the doped semiconductor) extends above the first conductive electrode 106, and the first conductive electrode 106 located under the semiconductor layer SE can be used to prevent the flexible The substrate 100 escapes the impurities contained in the semiconductor layer SE during the subsequent high-temperature process, and prevents the stress of the semiconductor layer SE from being affected by the buffer layer B, thereby improving the yield of the conductor layer SE. Further, at least two of the capacitor electrode 201a, the semiconductor layer SE and the first conductive electrode 106 are coupled into a storage capacitor C. In this embodiment, the storage capacitor C includes a first storage capacitor C1 and a second storage capacitor C2. That is, the capacitor electrode 201a is coupled to the semiconductor layer SE (eg, the doped region SE2 or the doped semiconductor) to form the storage capacitor C1 and the semiconductor layer SE (eg, the doped region SE2 or the doped semiconductor) and the first conductive electrode. The coupling 106 is coupled to the storage capacitor C2, and the semiconductor layer SE yield is improved, thereby increasing the capacitance of the pixel structure 10.

The second protective layer 110 is disposed on the gate GE, the capacitor electrode 201a, and the gate insulating layer GI. The gate insulating layer GI and the second protective layer have corresponding first through holes P1 and second through holes P2. In detail, the first through hole T1 and the second through hole T2 corresponding to the second insulating layer 110 may be formed in the same step, but are not limited thereto. The second protective layer 110 may be a single layer or a plurality of layers, and the material thereof may be selected from the material of the gate insulating layer GI, and the two are substantially the same or different, and the second protective layer 110 material may be substantially opposite to the first protective layer 108. Same or different.

The source S and the drain D are respectively disposed on the second protective layer 201, and the source S and the drain D are in contact with the semiconductor layer SE through the first through hole P1 and the second through hole P2, respectively. Therefore, the gate GE, the source S, the drain D, and the semiconductor layer SE interposed between the gate GE, the source S and the drain D constitute a thin film transistor T (for example, a switching thin film transistor Ta or a driving Thin film transistor Tb). The pixel electrode PE is disposed on the third protective layer 112, and the pixel electrode PE is connected to the source S or the drain D. In this embodiment, the third protective layer 112 is selectively disposed on the source S, the drain D and the second protective layer 110, and the third protective layer 112 has at least one third through hole P3, and then the pixel The electrode PE is connected to the source S or the drain D through the third through hole P3. The third protective layer 112 may be a single layer or a plurality of layers, and the material thereof may be selected from the materials described in the second protective layer 110, and the two are substantially the same or different. In this embodiment, the organic flat layer 114 is selectively included and disposed on the third protective layer 112. In this embodiment, the third protective layer 112 and the organic flat layer 114 are disposed on the second protective layer 112, the pixel electrode PE is disposed on the organic flat layer 114, and the third protective layer 112 is organically flat. The layer 114 has a third through hole P3, and the pixel electrode PE is connected to the source S or the drain D via the third through hole P3. Therefore, whether or not the organic flat layer 114 is disposed may be selected according to actual needs. The organic flat layer 114 may be a single layer or a plurality of layers, and the materials thereof include polyesters (PET), polyolefins, polypropylenes, polycarbonates, polyalkylene oxides, polyphenylenes, polyethers. , polyketones, polyalcohols, polyaldehydes, or other suitable materials. In this embodiment, a pixel defining layer (or dam bank) 116 may be selectively disposed, disposed on the organic flat layer 114, directly disposed on the third protective layer 112, or directly disposed on the second protective layer 110. And the pixel defining layer 116 has an opening 130, and the pixel electrode PE is located in the opening 130, that is, according to the presence or absence of the organic flat layer 114 and the third protective layer at the opening, the opening 130 exposes a part of the surface of the organic flat layer 114. (eg, the presence of the organic planarization layer 114 under the opening), the partial surface of the third protective layer 112 (eg, the absence of the organic planarization layer 114 under the opening), or the surface of the second protective layer 110 (eg, under the opening) There is no organic flat layer 114 and a third protective layer 112).

Referring to FIG. 3, a pixel structure 11 of a variation of the first embodiment of the present invention is illustrated. The pixel structure of the present embodiment is similar to the pixel structure of FIG. 2, and like components are denoted by the same reference numerals and have similar functions, and thus the description will not be repeated. The main difference between the two is that the pixel structure 11 of the modified embodiment further includes a second conductive electrode 206 disposed on the buffer layer B, and the second conductive electrode 206 and the gate GE are vertically projected on the flexible substrate. At least a portion of the 100 overlaps, and the pixel structure 10 of the embodiment shown in FIG. 2 does not include the second conductive electrode 206. The second conductive electrode 206 and the first conductive electrode 106 are preferably formed in the same process or film layer, but are not limited thereto. The second conductive electrode 206 may be a single layer or a plurality of layers, and the material thereof may be selected from the material of the first conductive electrode 106, and the two may be substantially the same or different. It should be noted that the second conductive electrode 206 is located under the gate GE to prevent the substrate 100 from escaping impurities contained in the semiconductor layer SE, thereby ensuring electrical stability of the thin film transistor T. In addition, the second conductive electrode 206 can be selectively used as another gate, that is, the thin film transistor T is an upper and lower double gate type, which can improve the transistor crystal properties, and if the second conductive electrode 206 is non-transparent. The material can further block a part of the light source (such as a backlight) from entering the semiconductor layer SE (for example, the channel region CH) at the thin film transistor T to improve the light leakage effect of the thin film transistor T. Moreover, the first conductive electrode 106 and the second conductive electrode 206 may be separated or connected according to the design requirements.

Referring to FIG. 4, a pixel structure 12 of a second embodiment of the present invention is illustrated. The pixel structure of the present embodiment is similar to the pixel structure of FIG. 2, and like components are denoted by the same reference numerals and have similar functions, and thus the description will not be repeated. The difference between the second embodiment and the first embodiment is that the first protective layer 108 and the gate insulating layer GI have a connection hole O, and the capacitor electrode 201a is connected to the first conductive electrode 106 through the connection hole O, that is, the capacitor electrode 201a and the first A storage electrode C is a storage capacitor C, and the storage capacitor C includes a first storage capacitor and a second storage capacitor. The first storage capacitor C1 and the second storage capacitor C2 are two capacitors connected in series. Therefore, the capacitance value of the storage capacitor C is substantially equal to the capacitance value of the first storage capacitor C1 plus the capacitance value of the second storage capacitor C2. Therefore, without increasing the plane area of the storage capacitor, the capacitance value of the storage capacitor C is effectively increased, and the stability of the pixel circuit driving is also improved. In this embodiment, the projection shape or pattern of the first conductive electrode 106 and the capacitor electrode 201a perpendicularly projected onto the flexible substrate 100 may be different according to the design requirements, but is not limited thereto. In another variation, the pixel structure 12 may optionally include a vertical projection of the second conductive electrode 206 and the gate GE of the variation of the first embodiment at least partially overlapping the flexible substrate 100.

Referring to FIG. 5, a pixel structure 13 of a third embodiment of the present invention is illustrated. The pixel structure of the present embodiment is similar to the pixel structure of FIG. 2, and like components are denoted by the same reference numerals and have similar functions, and thus the description will not be repeated. The difference between the third embodiment and the first embodiment is that the semiconductor layer SE (for example, the doped region SE2 or the doped semiconductor layer) does not extend below the capacitor electrode 201a, that is, the vertical projection of the semiconductor layer SE and the capacitor electrode 201a is The flexible substrate 100 does not overlap as shown in FIG. Compared with the storage capacitor C of the first embodiment, the semiconductor layer SE (for example, the doped region SE2 or the doped semiconductor layer) is used, and the capacitor lower electrode of the third embodiment is configured to store the first conductive electrode 106 and the capacitor electrode 201a. Capacitor C, since the surface flatness of the first conductive electrode 106 is superior to that of the semiconductor layer SE (for example, the doped region SE2 or the doped semiconductor layer), the leakage phenomenon of the storage capacitor C can be improved. In another variant embodiment, the pixel structure 13 may optionally include a vertical projection of the second conductive electrode 206 and the gate GE of the variation of the first embodiment at least partially overlapping the flexible substrate 100.

Referring to FIG. 6 , the flexible display panel 160 includes a plurality of pixel structures, wherein at least a portion of the pixel structures include the pixel structures 10 , 11 , 12 or 13 of the foregoing embodiment and are configured in the foregoing embodiments. The display medium layer 122 between the substrate 100 of the pixel structure 10, 11, 12 or 13 and the other substrate 120. In this embodiment, a pair of electrodes (not labeled) may be selectively disposed on the display medium layer 122. For example, the display dielectric layer 122 is an organic electroluminescent layer, and FIG. 2 is an example. The organic electroluminescent layer 122 is disposed on the pixel electrode PE, and the opposite electrode (not labeled) is disposed on the organic battery. The light layer 122 is excited. If the embodiment of FIG. 2 is provided with a pixel definition layer (or dam bank) 116, the organic electroluminescent layer 122 will be located in the opening 130. In other embodiments, the display dielectric layer 122 can be other materials, such as liquid crystal, then a pixel definition layer (or dam bank) 116, a counter electrode (not labeled), or other similar film layer (eg, organic At least one of the planar layers 114) is selectively not provided.

In the above embodiment, the storage capacitor C can provide a higher storage capacitance value before the same required area of the capacitor of the conventional pixel structure, thereby reducing the area required for the overall pixel structure. purpose. For example, applying the second embodiment to the driving circuit of the 6T1C can effectively increase the capacitance value by 40% compared to the pixel structure without the first conductive electrode 106. In addition, the first conductive electrode 106 or the second conductive electrode 206 of the present invention can be used to prevent the flexible substrate 100 from escaping impurities contained therein to enter the semiconductor layer SE during a subsequent high-temperature process, while avoiding the semiconductor layer SE. The stress is affected by the buffer layer B, thereby increasing the yield of the conductor layer SE. The rest of the description can be referred to the aforementioned embodiment.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 11, 12, 13‧‧‧ pixel structure
102‧‧‧First buffer layer
100‧‧‧Flexible substrate
104‧‧‧Second buffer layer
B‧‧‧buffer layer
106‧‧‧First conductive electrode
108‧‧‧First protective layer
P1‧‧‧ first through hole
SE‧‧‧Semiconductor layer
GI‧‧‧ gate insulation
G1, G2, GE‧‧‧ gate
201‧‧‧electrode layer
110‧‧‧Second protective layer
112‧‧‧ third protective layer
114‧‧‧Organic flat layer
116‧‧‧ pixel definition layer
S1, S2, S‧‧‧ source
D1, D2, D‧‧‧ bungee
P1‧‧‧ first through hole
PE‧‧‧ pixel electrode
P2‧‧‧ second through hole
O‧‧‧Contact hole
P3‧‧‧Through hole
130‧‧‧Opening
C, Cst‧‧‧ storage capacitor
C1‧‧‧First storage capacitor
C2‧‧‧Second storage capacitor
T‧‧‧film transistor
Ta‧‧‧Switch Film Transistor
Tb‧‧‧Drive film transistor
206‧‧‧Second conductive electrode
Vdd‧‧‧Power cord
Xn‧‧‧ scan line
Yn‧‧‧ data line
CH‧‧‧ passage area
SE1, SE2‧‧‧ doped area
120‧‧‧Other substrate
122‧‧‧Display media layer
201a‧‧‧Capacitor electrode

1 is a schematic diagram showing an equivalent circuit of a pixel structure of an organic light emitting diode display panel according to an embodiment of the invention. 2 is a cross-sectional view showing the pixel structure of the first embodiment of the present invention. 3 is a cross-sectional view showing a pixel structure of a variation of the first embodiment of the present invention. 4 is a cross-sectional view showing a pixel structure of a second embodiment of the present invention. FIG. 5 is a cross-sectional view showing a pixel structure of a third embodiment of the present invention. 6 is a cross-sectional view showing a display panel according to a fourth embodiment of the present invention.

10‧‧‧ pixel structure

100‧‧‧Flexible substrate

B‧‧‧buffer layer

102‧‧‧First buffer layer

104‧‧‧Second buffer layer

106‧‧‧First conductive electrode

108‧‧‧First protective layer

SE‧‧‧Semiconductor layer

GE‧‧‧ gate

110‧‧‧Second protective layer

114‧‧‧Organic flat layer

S‧‧‧ source

P1‧‧‧ first through hole

P2‧‧‧ second through hole

P3‧‧‧Through hole

C1‧‧‧First storage capacitor

C2‧‧‧Second storage capacitor

GI‧‧‧ gate insulation

201a‧‧‧Capacitor electrode layer

112‧‧‧ third protective layer

116‧‧‧ pixel definition layer

D‧‧‧汲

PE‧‧‧ pixel electrode

T‧‧‧film transistor

130‧‧‧Opening

CH‧‧‧ passage area

SE1, SE2‧‧‧ doped area

Claims (14)

A pixel structure includes: a flexible substrate; a buffer layer disposed on the flexible substrate; a first conductive electrode disposed on the buffer layer; a first protective layer disposed on the first conductive layer a semiconductor layer disposed on the first protective layer; a gate insulating layer disposed on the semiconductor layer; an electrode layer disposed on the gate insulating layer, and the electrode layer having at least one gate a pole and at least one capacitor electrode, wherein the gate partially overlaps the semiconductor layer on the flexible substrate, and the capacitor electrode and the first conductive electrode are vertically projected on the flexible substrate a portion of the capacitor electrode, the semiconductor layer and the first conductive electrode are coupled to form a storage capacitor; a second protective layer disposed on the gate, the electrode layer and the gate insulating layer The gate insulating layer and the second protective layer have a first through hole and a second through hole; a source and a drain are respectively disposed on the second protective layer and are separated from each other, the source and the The first pole and the first The through hole is in contact with the semiconductor layer, wherein the gate, the source, the drain, and the semiconductor layer interposed between the gate, the source and the drain form a thin film transistor; A pixel electrode is disposed on the second protective layer and connected to the source or the drain. The pixel structure of claim 1, wherein the material of the semiconductor layer comprises polysilicon. The pixel structure of claim 1, further comprising a second conductive electrode disposed on the buffer layer and overlapping at least a portion of the vertical projection of the gate on the substrate. The pixel structure of claim 1, wherein the semiconductor layer does not extend below the capacitor electrode. The pixel structure of claim 1, wherein the semiconductor layer extends under the capacitor electrode, and the capacitor electrode and the underlying semiconductor layer overlap at least partially on the flexible substrate, wherein The semiconductor layer under the capacitor electrode is a doped semiconductor layer. The pixel structure of claim 5, wherein the storage capacitor comprises a first storage capacitor and a second storage capacitor, wherein the capacitor electrode layer is coupled to the semiconductor layer as the first storage capacitor, and the semiconductor The first conductive electrode is coupled to the second storage capacitor. The pixel structure of claim 6, wherein the first protective layer and the gate insulating layer have at least one connection hole, and the capacitor electrode is connected to the first conductive electrode through the connection hole. The pixel structure of claim 4, wherein the capacitor electrode is coupled to the first conductive electrode to form the storage capacitor. The pixel structure of claim 2, further comprising: a third protective layer disposed on the source, the drain and the second protective layer, the third protective layer having at least a third pass a hole, wherein the pixel electrode is connected to the source or the drain by the third through hole. The pixel structure of claim 9, further comprising: a pixel defining layer disposed on the third protective layer and having an opening such that the pixel electrode is located in the opening. The pixel structure as claimed in claim 10, further comprising an organic flat layer disposed on a portion of the third protective layer. The pixel structure of claim 1, wherein the first conductive electrode is a floating electrode. The pixel structure of claim 1, wherein the projection shape or pattern of the first conductive electrode and the capacitor electrode perpendicularly projected onto the flexible substrate is substantially the same. A display panel comprising: a plurality of pixel structures, wherein at least a portion of the pixel structures comprise a pixel structure as claimed in claim 1; and another substrate disposed opposite the flexible substrate; A display medium layer is disposed between the other substrate and the flexible substrate.