JP2013238718A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor device including an MIS capacitor.SOLUTION: A semiconductor device has a plurality of capacitive elements arranged on a substrate 10. Each of the capacitive elements has a structure in which a lower electrode 11, a first insulating layer 12, a first upper electrode 13 composed of a semiconductor material, and a second upper electrode 15 are laminated in this order on the substrate. An end part of the first upper electrode 13 is covered with a second insulating layer 14. An end part of the second upper electrode 15 is arranged on the second insulating layer 14.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a technique for providing a highly reliable semiconductor device.

  2. Description of the Related Art Conventionally, semiconductor devices in which a plurality of capacitive elements are arranged on a substrate have been widely used for various display panel substrates and the like. In general, a semiconductor device as a display panel substrate includes a storage capacitor, a TFT (Thin Film Transistor), and an electro-optical element such as a liquid crystal element, an electro-powder fluid element, an electrophoretic element, or an organic EL (ElectroLuminescence) element for each pixel. An element is provided.

  Patent Document 1 discloses a semiconductor device as a substrate for a liquid crystal display panel.

  FIG. 9 is a cross-sectional view illustrating an example of a main part of the semiconductor device 9 disclosed in Patent Document 1. The main part of the semiconductor device 9 is a part that functions as a capacitor and a contact. On the substrate 90, a lower electrode 91, a dielectric layer 92, a semiconductor layer 93, a wiring layer 94, a protective layer 96, and a planarizing layer 97. And the pixel electrode 98 are stacked in this order.

  Here, a MIS (Metal Insulator Semiconductor) capacitor is formed by a laminated structure composed of the lower electrode 91, the dielectric layer 92, and the semiconductor layer 93. A liquid crystal (not shown) is formed above the pixel electrode 98. The lower electrode 91, the dielectric layer 92, the semiconductor layer 93, and the wiring layer 94 are respectively formed in extending portions of gate lines, gate insulating layers, semiconductor layers, and drain electrodes that constitute TFTs (not shown). .

  The semiconductor layer of the TFT and the semiconductor layer 93 of the capacitor are formed of an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide) having high mobility, for example. The pixel electrode 98 is made of a metal oxide such as ITO (Indium Tin Oxide).

  According to the semiconductor device of Patent Document 1, since the interface of the pixel electrode 98 made of ITO or the like and the interface of the semiconductor layer 93 made of IGZO or the like are in direct contact over a wide area, low contact resistance is obtained. Can be expected.

JP 2011-29304 A

  However, in the semiconductor device having the conventional structure, at least two factors that cause the semiconductor layer 93 to deteriorate can be considered. As shown in FIG. 9, these factors include light incident on the semiconductor layer 93 through the opening of the wiring layer 94 and the protective layer 96 to the semiconductor layer 93 that is one of the layers in direct contact with the semiconductor layer 93. It is a hydrogen radical that enters.

  Since the semiconductor layer 93 is composed of an oxide semiconductor, it is vulnerable to light and hydrogen radicals, and the characteristics of the MIS element fluctuate due to, for example, fluctuations in flat band voltage due to the influence of light and hydrogen radicals. Let That is, the deterioration of the semiconductor layer 93 changes the characteristics of the MIS capacitance and impairs the reliability of the semiconductor device.

  The present invention has been made in view of the above-described circumstances, and provides a highly reliable semiconductor device in which a change in capacitance characteristics hardly occurs and a method for manufacturing such a semiconductor device.

  In order to solve the above problems, one aspect of a semiconductor device according to the present invention is a semiconductor device in which a plurality of capacitive elements are arranged on a substrate, and each of the capacitive elements is formed on a lower portion of the substrate. An electrode, a first insulating layer, a first upper electrode made of a semiconductor material, and a second upper electrode are stacked in this order, and an end of the first upper electrode is covered with a second insulating layer. The end of the second upper electrode is disposed on the second insulating layer.

  According to the semiconductor device, the MIS capacitor is formed by a laminated structure including the lower electrode, the first insulating layer, the first upper electrode, and the second upper electrode. The end of the first upper electrode is covered with the second insulating layer, and the end of the second upper electrode is formed on the second insulating layer. It is in contact with at least one of the first insulating layer, the second insulating layer, and the second upper electrode.

  Therefore, according to the semiconductor device, unlike the conventional semiconductor device, for example, hydrogen radicals generated in the passivation layer or the like are blocked by at least one of the first insulating layer, the second insulating layer, and the second upper electrode, It does not enter the first upper electrode. As a result, deterioration due to hydrogen radicals in the first upper electrode and fluctuations in capacitance characteristics are suppressed, so that higher reliability can be obtained compared to conventional semiconductor devices.

FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device according to a comparative example. FIG. 2 is a diagram illustrating an example of a configuration of a semiconductor device according to a comparative example. FIG. 3 is a diagram illustrating an example of a configuration of a semiconductor device according to a comparative example. FIG. 4 is a diagram illustrating an example of a configuration of the semiconductor device according to the embodiment. FIG. 5 is a diagram for explaining the effect of the semiconductor device according to the embodiment. FIG. 6 is a functional block diagram illustrating an example of a configuration of the display device according to the embodiment. FIG. 7A is a circuit diagram illustrating an example of a configuration of a pixel portion according to the embodiment. FIG. 7B is a waveform diagram illustrating an example of a signal for driving the pixel portion according to the embodiment. FIG. 8 is a diagram illustrating an example of an appearance of the display device according to the embodiment. FIG. 9 is a diagram illustrating an example of a configuration of a semiconductor device according to a conventional example.

(Knowledge that became the basis of the present invention)
The present inventor has come up with a plurality of new semiconductor device structures while studying a technique for suppressing a variation in capacitance characteristics that may occur in a conventional semiconductor device. However, it has been found that there are other problems to be solved in the semiconductor devices having these new structures.

  In the following, first, the structure and problems of these semiconductor devices will be described as comparative examples of the present invention, and then aspects of the present invention will be described in detail by comparison with those semiconductor devices.

(Comparative Example 1)
FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device 6 as Comparative Example 1.

  The semiconductor device 6 is, for example, a semiconductor device that can be used as a display panel substrate on which a plurality of pixel portions are arranged. FIG. 1 shows an example of a cross-sectional structure of a pixel capacitor portion, a wiring intersection portion, and a TFT portion included in each of a plurality of pixel portions of the semiconductor device 6. In the following description, the wiring intersecting at the wiring intersection is referred to as a scanning line and a data line for convenience. However, in the following description, when the scanning line and the data line are interchanged, wirings with other names are also used. The same holds true when intersecting.

  In the semiconductor device 6, the pixel capacitor portion has a structure in which the lower electrode 11, the first insulating layer 12, the second insulating layer 14, and the second upper electrode 15 are stacked on the substrate 10 in this order. . The wiring intersection has a structure in which a scanning line 21, a first inter-wiring insulating layer 22, a second inter-wiring insulating layer 24, and a data line 25 are stacked on the substrate 10 in this order. The TFT portion has a structure in which a gate electrode 31, a gate insulating layer 32, a channel 33, a channel etching stopper 34, and a source / drain electrode 35 are laminated on the substrate 10 in this order.

  Here, the lower electrode 11, the scanning line 21, and the gate electrode 31 are made of, for example, a conductive material such as metal, and are formed in the same layer by patterning a film body of the conductive material. .

  Each of the first insulating layer 12, the first inter-wiring insulating layer 22, and the gate insulating layer 32 is, for example, a metal oxide, silicon oxide, silicon nitride, acrylic resin, polyimide resin, or a laminate thereof. The first insulating material is formed of the first insulating material such as a mixture thereof, and is formed in the same layer by patterning the film body of the first insulating material or using the film body of the first insulating material that is not patterned.

  The channel 33 is formed, for example, by patterning a film body of a semiconductor material.

  Each of the second insulating layer 14, the second inter-wiring insulating layer 24, and the channel etching stopper 34 is, for example, a metal oxide, silicon oxide, silicon nitride, acrylic resin, polyimide resin, a laminate thereof, or the like. They are made of a second insulating material such as a mixture thereof, and are formed in the same layer by patterning a film body of the second insulating material.

  The first insulating layer 12, the first inter-wiring insulating layer 22, the gate insulating layer 32, the second insulating layer 14, the second inter-wiring insulating layer 24, and the channel etching stopper 34 are in direct contact with the channel 33. It is desirable to select a material that does not generate hydrogen radicals or to perform a process that does not generate hydrogen radicals so that the channel 33 is not altered.

  The second upper electrode 15, the data line 25, and the source / drain electrode 35 are all made of a conductive material such as metal, and are formed in the same layer by patterning a film body of the conductive material. .

  Unlike the conventional semiconductor device 9, the pixel capacitor portion of the semiconductor device 6 does not have an electrode made of a semiconductor material, so that the capacitance characteristic variation due to electrode deterioration does not occur. Therefore, according to the semiconductor device 6, higher reliability than the conventional one can be obtained.

  In the semiconductor device 6, the first insulating layer 12 made of the first insulating material and the second insulating layer 14 made of the second insulating material are provided in the same pattern in the pixel capacitor portion. In addition, at the wiring intersection, the first inter-wiring insulating layer 22 made of the first insulating material and the second inter-wiring insulating layer 24 made of the second insulating material are provided in the same pattern. Yes. Such a structure does not require etching selectivity for the first insulating material and the second insulating material, which is useful for expanding the choice of material combinations and simplifying the process.

  On the other hand, in the semiconductor device 6, since the capacitance per unit area is approximately equal between the pixel capacitor portion and the wiring intersection portion, a larger capacitance required for the pixel capacitance portion and a smaller capacitance required for the wiring intersection portion are provided. It becomes difficult to achieve both. In particular, a semiconductor device as a display panel substrate is required to cope with an increase in size, a high-speed drive, and a high definition. For a large size and a high definition, it is important to reduce the capacitance at the wiring intersection. It is a problem, and for high definition, it is important to secure a sufficiently large pixel capacity in a limited pixel region. That is, in the configuration of Comparative Example 1, it is very disadvantageous that it is difficult to achieve both a high capacitance of the pixel capacitance portion and a low capacitance of the wiring intersection portion.

(Comparative Example 2)
FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor device 7 as the comparative example 2.

  In order to eliminate the disadvantage of the semiconductor device 6, the semiconductor device 7 has a configuration in which the film body of the second insulating material is removed at the pixel capacitor portion and maintained at the wiring intersection.

  Unlike the conventional semiconductor device 9, the pixel capacitor portion of the semiconductor device 7 does not have an electrode made of a semiconductor material, so that the capacitance characteristic variation due to electrode deterioration does not occur. Therefore, according to the semiconductor device 7, higher reliability than the conventional one can be obtained. In addition, since the capacitance per unit area of the pixel capacitor portion can be configured to be larger than the capacitance per unit area of the wiring intersection portion, it is possible to easily achieve both a higher capacitance of the pixel capacitance portion and a lower capacitance of the wiring intersection portion.

  On the other hand, in the semiconductor device 7, since it is necessary to use a material having selectivity in etching for the first insulating material and the second insulating material, the first insulating material and the second insulating material are used. The options for combination with materials are limited, and the benefits of process unification and simplification are lost.

(Comparative Example 3)
FIG. 3 is a cross-sectional view showing an example of the structure of the semiconductor device 8 as Comparative Example 3.

  In the pixel capacitor portion of the semiconductor device 8, as in the conventional semiconductor device 9, a MIS capacitor is formed by a laminated structure including the lower electrode 11, the first insulating layer 12, the first upper electrode 13, and the second upper electrode 15. ing.

  The first upper electrode 13 and the channel 33 are both made of a semiconductor material such as an oxide semiconductor, for example, and are formed in the same layer by patterning a film body of the semiconductor material.

  A second inter-wiring insulating layer 24 made of an insulating material is provided at the wiring intersection of the semiconductor device 8 in order to make the capacitance smaller than that of the pixel capacitor.

  According to the semiconductor device 8, if the second inter-wiring insulating layer 24 is installed sufficiently wider than the scanning line 21 at the wiring intersection, for example, when the semiconductor layer 23 is an N-type semiconductor, the potential of the scanning line 21 becomes the data line. Even if a channel is induced in the semiconductor layer 23 in the vicinity of the scanning line at a potential sufficiently higher than 25, the distance between the connection portion between the channel portion and the data line is long, so that the channel of the semiconductor layer 23 at the wiring intersection portion is long. The connection resistance between the scanning line 21 and the data line 25 can be substantially reduced.

  On the other hand, as compared with the semiconductor device 6 and the semiconductor device 7, the semiconductor device 8 requires an additional pattern region for forming the second inter-wiring insulating layer 24, which is disadvantageous in terms of high definition. It is.

(Aspect of the Invention)
In view of the above-described problems of a semiconductor device having a conventional structure and a plurality of semiconductor devices studied as comparative examples, a semiconductor device that is less likely to cause a change in capacitance characteristics and highly reliable, and such a semiconductor device will be described below. Several embodiments of the manufacturing method are disclosed.

  One aspect of the semiconductor device according to the present disclosure is a semiconductor device in which a plurality of capacitive elements are arranged on a substrate, and each of the capacitive elements has a lower electrode, a first insulating layer, a semiconductor on the substrate. A first upper electrode made of a material and a second upper electrode are stacked in this order, and an end of the first upper electrode is covered with a second insulating layer, and an end of the second upper electrode is formed. The part is disposed on the second insulating layer.

  According to this aspect, the MIS capacitor is formed by the laminated structure including the lower electrode, the first insulating layer, the first upper electrode, and the second upper electrode. The end of the first upper electrode is covered with the second insulating layer, and the end of the second upper electrode is formed on the second insulating layer so that the entire circumference of the cross section of the first upper electrode 13 is , In contact with at least one of the first insulating layer 12, the second insulating layer 14, and the second upper electrode 15.

  Therefore, in this aspect, unlike the conventional semiconductor device, for example, hydrogen radicals generated in the passivation layer or the like are blocked by at least one of the first insulating layer, the second insulating layer, and the second upper electrode, and the first upper portion Does not enter the electrode. As a result, deterioration due to hydrogen radicals in the first upper electrode and fluctuations in capacitance characteristics are suppressed, so that higher reliability can be obtained compared to conventional semiconductor devices.

  In one aspect of the semiconductor device according to the present disclosure, the semiconductor material may be an oxide semiconductor.

  According to this aspect, an oxide semiconductor excellent in mobility can be used as the first upper electrode.

  In one aspect of the semiconductor device according to the present disclosure, the first upper electrode may be disposed in a region included in the lower electrode when viewed from the stacking direction.

  According to this aspect, light incident from below the substrate is blocked by the lower electrode and does not reach the first upper electrode 13. As a result, deterioration of the first upper electrode due to light and capacitance characteristic fluctuation are suppressed, so that higher reliability can be obtained as compared with a conventional semiconductor device.

  In one aspect of the semiconductor device according to the present disclosure, the second upper electrode may be disposed in a region including the first upper electrode when viewed from the stacking direction.

  According to this aspect, light incident from above the substrate is blocked by the second upper electrode and does not reach the first upper electrode 13. As a result, deterioration of the first upper electrode due to light and capacitance characteristic fluctuation are suppressed, so that higher reliability can be obtained as compared with a conventional semiconductor device.

  In one aspect of the semiconductor device according to the present disclosure, the film capacity of the first insulating layer may be larger than the film capacity of the second insulating layer, and the film thickness of the first insulating layer may be It may be thinner than the film thickness of the second insulating layer.

  According to this aspect, in the pixel capacitor portion, the MIS capacitor is formed by the laminated structure including the lower electrode, the first insulating layer, the first upper electrode, and the second upper electrode, and at the wiring intersection, the first insulating layer is formed. In addition, for example, when the scanning line and the data line intersect with each other with the second insulating layer interposed, the capacitance per unit area of the pixel capacitor portion can be made larger than the capacitance per unit area of the wiring intersection portion. Therefore, it is possible to easily achieve both a high capacity of the pixel capacity section and a low capacity of the wiring intersection.

  In one aspect of the semiconductor device according to the present disclosure, the first insulating layer and the second insulating layer may be made of a material containing the same element.

  This aspect is useful for simplifying material selection and processes.

  In one aspect of the semiconductor device according to the present disclosure, the end surface and the upper surface of the first upper electrode may be entirely covered with the second insulating layer and the second upper electrode.

  According to this aspect, since the entire end face and upper surface of the first upper electrode are covered with the second insulating layer and the second upper electrode, for example, hydrogen radicals generated in the passivation layer or the like are generated in the second insulating layer. And at least one of the second upper electrode and does not enter the first upper electrode. As a result, deterioration of the first upper electrode due to hydrogen radicals and capacitance characteristic fluctuations are suppressed, so that higher reliability can be obtained compared to a conventional semiconductor device.

  One aspect of the semiconductor device according to the present disclosure further includes a plurality of scanning lines and a plurality of data lines intersecting each other at a plurality of wiring intersections, and each of the wiring intersections is formed on the substrate. One of the scanning line and the data line formed in the same layer as the lower electrode, the first inter-wiring insulating layer formed in the same layer as the first insulating layer, and the same layer as the second insulating layer The second inter-wiring insulating layer and the other of the scanning line and the data line formed in the same layer as the second upper electrode may have a structure in which they are stacked in this order.

  According to this aspect, the reliability of the semiconductor device including the MIS capacitor and the wiring intersection can be improved.

  One aspect of the semiconductor device according to the present disclosure further includes a plurality of thin film transistors, each of the plurality of thin film transistors being formed on the substrate in the same layer as the lower electrode, and the first insulation. A gate insulating layer formed in the same layer as the first layer, a channel formed in the same layer as the first upper electrode, a channel etching stopper formed in the same layer as the second insulating layer, and the same as the second upper electrode The source / drain electrodes formed in the layer have a structure laminated in this order, and the channel etching stopper is disposed excluding the channel contact portion on the channel, and the channel is formed in the channel contact portion, It may be directly connected to the source / drain electrode.

  This aspect can improve the reliability of the semiconductor device including the MIS capacitor and the TFT portion.

  One aspect of a method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device in which a plurality of capacitive elements are arranged on a substrate, each of the plurality of capacitive elements including a lower electrode and a first insulation. A layer, a first upper electrode made of a semiconductor material, and a second upper electrode are stacked in this order. A first conductive film is formed on the substrate, and the first conductive film is patterned. Thus, a first step of forming the lower electrode, a second step of forming a first insulating film covering at least the lower electrode as the first insulating layer, and forming a semiconductor film on the first insulating film A third step of forming the first upper electrode by patterning the semiconductor film, a fourth step of forming a second insulating film covering at least the first upper electrode, and the second insulating film. By patterning A fifth step of exposing a portion other than the end portion of the first upper electrode, a sixth step of forming a second conductive film covering at least the exposed portion of the first upper electrode, and the second step. Patterning a conductive film to form a second upper electrode having an end portion disposed on the second insulating film, and in the fifth step, etching the second insulating film The insulating film is patterned by performing etching under the condition that the rate is higher than the etching rate of the semiconductor film.

  According to this aspect, a highly reliable semiconductor device having an MIS capacitor can be manufactured.

  In one aspect of the method of manufacturing a semiconductor device according to the present disclosure, the semiconductor device further includes a plurality of scanning lines, a plurality of data lines, and a plurality of thin film transistors that intersect with each other at a plurality of wiring intersections. Each of the wiring intersections includes a first inter-wiring insulating layer formed on one of the scanning line and the data line formed on the substrate and on the same layer as the first insulating layer. A structure in which the second inter-wiring insulating layer formed in the same layer as the second insulating layer, and the other of the scanning line and the data line formed in the same layer as the second upper electrode are stacked in this order. Each of the plurality of thin film transistors includes a gate electrode formed on the substrate in the same layer as the lower electrode, a gate insulating layer formed in the same layer as the first insulating layer, and the first upper portion. Same as electrode A channel formed in the layer, a channel etching stopper formed in the same layer as the second insulating layer, and a source / drain electrode formed in the same layer as the second upper electrode are stacked in this order. The manufacturing method further forms the one of the scan line and the data line and the gate electrode by patterning the first conductive film in the first step, and in the second step, In the third step, the first insulating film is formed as the first inter-wiring insulating layer and the gate insulating layer so as to cover the one of the scanning line and the data line, and the gate electrode. By patterning the semiconductor film, the channel is formed and the semiconductor film at the wiring intersection is removed, and the fourth process is performed. In the fifth step, the second insulating film is further formed as the second inter-wiring insulating layer and the channel etching stopper so as to cover the first inter-wiring insulating layer and the channel. Patterning the second insulating film to further expose a part of the channel, and in the sixth step, to form the second conductive film so as to cover the exposed part of the channel; In the seventh step, the second conductive film may be patterned to form the other of the scanning line and the data line, and a source / drain electrode.

  According to this aspect, a highly reliable semiconductor device including the MIS capacitor, the wiring intersection portion, and the TFT portion can be manufactured.

(Embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to one embodiment of the present invention will be specifically described with reference to the drawings.

  Note that each of the embodiments described below shows a specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connecting forms of the constituent elements, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

  The semiconductor device according to the embodiment of the present invention is, for example, a semiconductor device that can be used as a display panel substrate provided with a plurality of pixel portions.

  FIG. 4 is a cross-sectional view illustrating an example of the structure of the pixel capacitor portion, the wiring intersection portion, and the TFT portion included in each of the plurality of pixel portions of the semiconductor device 1. In the following, the same components as those in the semiconductor device 6, the semiconductor device 7, and the semiconductor device 8 according to the comparative example described above are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Differences from the comparative example Mainly explained.

  The pixel capacitor portion of the semiconductor device 1 has a structure in which a lower electrode 11, a first insulating layer 12, a first upper electrode 13, and a second upper electrode 15 are stacked in this order on a substrate 10. A MIS capacitor is formed by a laminated structure including the lower electrode 11, the first insulating layer 12, the first upper electrode 13, and the second upper electrode 15.

  Considering the application in which light is irradiated from below the substrate 10, in order to avoid the characteristic fluctuation due to light of the first upper electrode 13 made of a semiconductor, the first upper electrode 13 is a lower electrode as viewed from the stacking direction. 11 is preferably disposed in a region included in the area 11.

  The end portion of the first upper electrode 13 is covered with the second insulating layer 14, and the end portion of the second upper electrode 15 is disposed on the second insulating layer 14. The first upper electrode 13 may be made of a semiconductor material such as an oxide semiconductor, for example.

  The wiring crossing portion of the semiconductor device 1 includes a scanning line 21 formed on the same layer as the lower electrode 11 on the substrate 10, a first inter-wiring insulating layer 22 formed on the same layer as the first insulating layer 12, a second A second inter-wiring insulating layer 24 formed in the same layer as the insulating layer 14 and a data line 25 formed in the same layer as the second upper electrode 15 are stacked in this order.

  Note that the scanning line 21 and the data line 25 may be interchanged at the wiring intersection. That is, although not shown, the data line 25 may be arranged in a lower layer close to the substrate 10 and the scanning line 21 may be arranged in an upper layer far from the substrate 10. Further, wirings other than the scanning lines 21 and the data lines 25 may intersect at the wiring intersections.

  The TFT portion of the semiconductor device 1 includes a gate electrode 31 formed on the same layer as the lower electrode 11, a gate insulating layer 32 formed on the same layer as the first insulating layer 12, and the first upper electrode 13 on the substrate 10. A channel 33 formed in the same layer, a channel etching stopper 34 formed in the same layer as the second insulating layer 14, and a source / drain electrode 35 formed in the same layer as the second upper electrode 15 are laminated in this order. Have a structure.

  The channel etching stopper 34 is disposed excluding the channel contact portion 39 on the channel 33, and the channel 33 is directly connected to the source / drain electrode 35 in the channel contact portion 39.

  The semiconductor device 1 having such a structure is manufactured by the following method, for example.

  (First Step) A first conductive film is formed on the substrate 10, and the first conductive film is patterned to form the lower electrode 11, the scanning line 21, and the gate electrode 31.

  (Second Step) A first insulating film covering at least the lower electrode 11, the scanning line 21, and the gate electrode 31 is formed as the first insulating layer 12, the first inter-wiring insulating layer 22, and the gate insulating layer 32.

  (Third Step) A semiconductor film is formed on the first insulating film, and the semiconductor film is patterned, thereby forming the first upper electrode 13 and removing the semiconductor film at the wiring intersection. If necessary, the first upper electrode 13 may be formed in a region included in the lower electrode 11 when viewed from the stacking direction.

  (Fourth Step) The second insulating film covering at least the first upper electrode 13, the first inter-wiring insulating layer 22, and the channel 33 is replaced with the second insulating layer 14, the second inter-wiring insulating layer 24, and the channel etching stopper. 34 is formed.

  (Fifth Step) By patterning the second insulating film, a part other than the end of the first upper electrode 13 is exposed in the pixel capacitor part, and a part of the channel 33 is exposed. In this step, the second insulating film is patterned without deforming the semiconductor film pattern by performing etching under the condition that the etching rate of the second insulating film is faster than the etching rate of the semiconductor film.

  (Sixth Step) A second conductive film is formed to cover at least the exposed part of the first upper electrode 13 and the exposed part of the channel 33.

  (Seventh Step) By patterning the second conductive film so that at least the end of the second upper electrode 15 is disposed on the second insulating film, the second upper electrode 15, the data line 25, and the source / drain The electrode 35 is formed.

  FIG. 5 is a diagram for explaining the effect of the semiconductor device 1.

  FIG. 5 shows a passivation layer 16 serving as a hydrogen radical generation source in addition to the cross-sectional structure of FIG.

  In the semiconductor device 1, the end portion of the first upper electrode 13 is covered with the second insulating layer 14, and the end portion of the second upper electrode 15 is disposed on the second insulating layer 14. Due to such a shape, the entire circumference of the cross section of the first upper electrode 13 is in contact with at least one of the first insulating layer 12, the second insulating layer 14, and the second upper electrode 15. In other words, the entire end surface and upper surface of the first upper electrode 13 are covered with the second insulating layer 14 and the second upper electrode 15.

  Therefore, in the semiconductor device 1, unlike the conventional semiconductor device 9 and the semiconductor device 8 according to the comparative example 3, hydrogen radicals from the passivation layer 16 are generated in at least one of the second insulating layer 14 and the second upper electrode 15. It is blocked and does not enter the first upper electrode 13.

  As a result, according to the semiconductor device 1, changes in the characteristics of the first upper electrode 13 due to hydrogen radicals, that is, fluctuations in the characteristics of the MIS capacitance are suppressed, so that the conventional semiconductor device 9 and the semiconductor device 8 according to Comparative Example 3 are suppressed. Higher reliability can be obtained than

  Further, in the semiconductor device 1, in consideration of an application in which light is irradiated from below the substrate 10, the first upper electrode 13 is viewed from the stacking direction in order to avoid characteristic fluctuations of the first upper electrode 13 due to light. Therefore, it is desirable to arrange in a region encompassed by the lower electrode 11. Due to such a shape, light incident from below the substrate 10 is blocked by the lower electrode 11 and does not reach the first upper electrode 13.

  In the semiconductor device 1, the second upper electrode 15 may be disposed in a region including the first upper electrode 13 when viewed from the stacking direction. According to such a shape, light incident from above the substrate 10 is blocked by the second upper electrode 15 and does not reach the first upper electrode 13.

  As a result, deterioration of the first upper electrode 13 due to light and capacitance characteristic fluctuation are suppressed, so that the semiconductor device 1 is more in comparison with the conventional semiconductor device 9 and the semiconductor device 8 according to the comparative example 3. High reliability is obtained.

  In the semiconductor device 1, the film capacity of the first insulating layer 12 may be larger than the film capacity of the second insulating layer 14, and the film thickness of the first insulating layer 12 is the film thickness of the second insulating layer 14. It may be thinner. Here, the film capacity is a capacity per unit area and is a value obtained by dividing the dielectric constant by the film thickness.

  According to such a shape, even when the same material is used for the first insulating layer 12 and the second insulating layer 14, the capacitance per unit area of the pixel capacitor portion is reduced per unit area of the wiring intersection portion. Since it can be configured larger than the capacitance, it is possible to easily achieve both higher pixel capacitance and lower wiring intersection.

  In the semiconductor device 1, the first insulating layer 12 and the second insulating layer 14 may be made of a material containing the same element. For example, the first insulating layer 12 and the second insulating layer 14 may be any combination of silicon nitride and silicon oxide. Such a configuration is useful for simplifying material selection and processes.

  FIG. 6 is a functional block diagram showing an example of the configuration of the display device 100 using the semiconductor device 1 according to the embodiment. The display device 100 is a device that displays images and videos, and includes a display unit 102, a controller 103, a scanning line driver 104, a data line driver 105, and a power source 107.

  The display unit 102 is configured by a display panel such as an organic EL display panel or a liquid crystal display panel, and the semiconductor device 1 is used as a substrate of the display panel. The semiconductor device 1 is provided with a plurality of pixel portions 106, at least a plurality of scanning lines SCAN and a plurality of data lines DATA for controlling the plurality of pixel portions 106. The power source 107 emits at least the organic ELs individually arranged in the plurality of pixel units 106 and operates the controller 103, the scanning line driver 104, and the data line driver 105 with a low potential side power source VDD and a low power source VDD. The potential side power supply VSS is output.

  The controller 103 controls the scanning line driver 104 and the data line driver 105 based on the received video signal. The scan line driver 104 and the data line driver 105 output a signal for driving the display unit 102 to the scan line SCAN and the data line DATA under the control of the controller 103. The display unit 102 displays an image represented by the image signal according to signals supplied from the scanning line SCAN and the data line DATA.

  FIG. 7A is a circuit diagram illustrating an example of the configuration of the pixel unit 106, and FIG. 7B is a waveform diagram illustrating an example of a signal for driving the pixel unit 106.

  The pixel unit 106 is the most basic example of the pixel unit used in the organic EL display panel, and includes a selection transistor T1, a drive transistor TD, a storage capacitor Cs, and a light emitting element EL. A scan line SCAN and a data line DATA are extended in the pixel portion 106.

  A part, B part, and C part of the pixel part 106 shown in FIG. 7A correspond to the pixel capacitor part, the wiring intersection part, and the TFT part shown in FIG. 4, respectively.

  Here, the function of the storage capacitor Cs will be described with reference to FIGS. 7A and 7B.

  A parasitic capacitance Cp exists structurally between the gate electrode, the source electrode, and the drain electrode of the selection transistor T1. That is, the intra-pixel node N varies by ΔV (N) from the written data voltage at the fall of the scanning line SCAN. This phenomenon is a penetration due to the fluctuation of the scanning line SCAN and the parasitic capacitance Cp of the selection transistor T1, and the magnitude of ΔV (N) is approximately ΔV (SCAN) × Cp / (Cp + Cs). That is, the larger the storage capacitor Cs, the smaller the fluctuation of the data voltage written in the pixel and the more stable the image quality. The effect of stabilizing the image quality is particularly remarkable in a display device that writes data voltages of opposite polarity in an even frame and an odd frame such as an LCD (Liquid Crystal Display).

  Further, when a leakage current Ileak occurs between the source and drain of the selection transistor T1 during the non-conduction period of the selection transistor T1, one frame has elapsed since the writing of the data voltage from the data line is completed (time t = 0). Later (time t = t1F), the fluctuation amount of the intra-pixel node N is Ileak × t1F / Cs. That is, the larger the storage capacitor Cs, the smaller the fluctuation of the data voltage written in the pixel and the more stable the image quality.

  Furthermore, in the case of a display device that controls the current flowing through a current drive element such as an organic EL by a drive transistor TD, particularly in the case of a large-screen display device, a wiring for supplying a low-voltage power supply VSS A significant voltage drop occurs due to the resistance and the drive current of the organic EL element EL. That is, voltage distribution occurs in the low voltage side power supply VSS. This influence causes nonuniformity of the pixel current Ipix due to the parasitic capacitance that is structurally present between the gate electrode, the source electrode, and the drain electrode in the driving transistor TD. The non-uniformity of Ipix is generally suppressed as (Cs + Cp_gs) / Cpara increases. Here, Cp_gs is a parasitic capacitance between the gate electrode and the source electrode of the driving transistor TD, and Cpara is a gate electrode of the driving transistor TD including a parasitic capacitance between the gate electrode and the drain electrode of the driving transistor TD. All connected capacity.

  As described above, increasing the capacitance value of the storage capacitor Cs is important for improving display quality.

  FIG. 8 is an external view of a television receiver which is an example of the display device 100 configured using the semiconductor device 1. By using the semiconductor device 1, the display device 100 with excellent reliability can be realized.

  Although the semiconductor device according to one or more aspects of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. Unless it deviates from the gist of the present invention, one or more of the present invention may be applied to various modifications that can be conceived by those skilled in the art, or forms constructed by combining components in different embodiments. It may be included within the scope of the embodiments.

  The present invention can be applied to a video display device such as an organic EL display device.

DESCRIPTION OF SYMBOLS 1, 6-9 Semiconductor device 10 Board | substrate 11 Lower electrode 12 1st insulating layer 13 1st upper electrode 14 2nd insulating layer 15 2nd upper electrode 16 Passivation layer 21 Scan line 22 Between 1st wiring insulating layers 24 Between 2nd wiring Insulating layer 25 Data line 31 Gate electrode 32 Gate insulating layer 33 Channel 34 Channel etching stopper 35 Source / drain electrode 39 Channel contact portion 90 Substrate 91 Lower electrode 92 Dielectric layer 93 Semiconductor layer 94 Wiring layer 96 Protective layer 97 Flattening layer 98 Pixel Electrode 100 Display device 102 Display unit 103 Controller 104 Scan line driver 105 Data line driver 106 Pixel unit 107 Power supply

Claims (12)

A semiconductor device in which a plurality of capacitive elements are arranged on a substrate,
Each of the capacitive elements has a structure in which a lower electrode, a first insulating layer, a first upper electrode made of a semiconductor material, and a second upper electrode are stacked in this order on the substrate.
The end of the first upper electrode is covered with a second insulating layer,
An end of the second upper electrode is disposed on the second insulating layer,
Semiconductor device. The semiconductor material is an oxide semiconductor.
The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the first upper electrode is disposed in a region included in the lower electrode when viewed from the stacking direction. The semiconductor device according to claim 1, wherein the second upper electrode is disposed in a region including the first upper electrode when viewed from the stacking direction. The semiconductor device according to claim 1, wherein a film capacity of the first insulating layer is larger than a film capacity of the second insulating layer. The semiconductor device according to claim 1, wherein a film thickness of the first insulating layer is thinner than a film thickness of the second insulating layer. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are made of a material containing the same element. The semiconductor device according to claim 1, wherein all of an end surface and an upper surface of the first upper electrode are covered with the second insulating layer and the second upper electrode. The semiconductor device further includes a plurality of scanning lines and a plurality of data lines intersecting each other at a plurality of wiring intersections,
Each of the wiring intersections has a first inter-wiring insulation formed on one of the scanning line and the data line formed on the same layer as the lower electrode on the substrate. A second inter-wiring insulating layer formed in the same layer as the second insulating layer, and the other of the scanning line and the data line formed in the same layer as the second upper electrode are stacked in this order. The semiconductor device according to claim 1, having a structure. The semiconductor device further includes a plurality of thin film transistors,
Each of the plurality of thin film transistors includes a gate electrode formed on the substrate in the same layer as the lower electrode, a gate insulating layer formed in the same layer as the first insulating layer, and the same layer as the first upper electrode. A channel formed in the first insulating layer, a channel etching stopper formed in the same layer as the second insulating layer, and a source / drain electrode formed in the same layer as the second upper electrode are stacked in this order,
The semiconductor device according to claim 1, wherein the channel etching stopper is disposed excluding a channel contact portion on the channel, and the channel is directly connected to the source / drain electrode in the channel contact portion. A method of manufacturing a semiconductor device in which a plurality of capacitive elements are arranged on a substrate,
Each of the plurality of capacitive elements has a structure in which a lower electrode, a first insulating layer, a first upper electrode made of a semiconductor material, and a second upper electrode are stacked in this order,
Forming a first conductive film on the substrate and patterning the first conductive film to form the lower electrode;
A second step of forming a first insulating film covering at least the lower electrode as the first insulating layer;
A third step of forming the first upper electrode by forming a semiconductor film on the first insulating film and patterning the semiconductor film;
A fourth step of forming a second insulating film covering at least the first upper electrode;
A fifth step of exposing a part other than an end of the first upper electrode by patterning the second insulating film;
A sixth step of forming a second conductive film covering at least the exposed part of the first upper electrode;
Patterning the second conductive film to form a second upper electrode having an end portion disposed on the second insulating film, and a seventh step,
The method of manufacturing a semiconductor device, wherein in the fifth step, the second insulating film is patterned by performing etching under a condition that an etching rate of the second insulating film is faster than an etching rate of the semiconductor film. The semiconductor device further includes a plurality of scanning lines, a plurality of data lines, and a plurality of thin film transistors that intersect each other at a plurality of wiring intersections,
Each of the wiring intersections has a first inter-wiring insulation formed on one of the scanning line and the data line formed on the same layer as the lower electrode on the substrate. A second inter-wiring insulating layer formed in the same layer as the second insulating layer, and the other of the scanning line and the data line formed in the same layer as the second upper electrode are stacked in this order. Has a structure,
Each of the plurality of thin film transistors includes a gate electrode formed on the substrate in the same layer as the lower electrode, a gate insulating layer formed in the same layer as the first insulating layer, and the same layer as the first upper electrode. A channel formed in the first insulating layer, a channel etching stopper formed in the same layer as the second insulating layer, and a source / drain electrode formed in the same layer as the second upper electrode are stacked in this order,
The manufacturing method includes:
In the first step, by patterning the first conductive film, the one of the scanning line and the data line, and the gate electrode are formed,
In the second step, the first insulating film is formed as the first inter-wiring insulating layer and the gate insulating layer so as to cover the one of the scanning line and the data line, and the gate electrode,
In the third step, by patterning the semiconductor film, the channel is further formed, and the semiconductor film at the wiring intersection is removed,
In the fourth step, the second insulating film is further formed as the second inter-wiring insulating layer and the channel etching stopper so as to cover the first inter-wiring insulating layer and the channel,
In the fifth step, by patterning the second insulating film, further exposing a part of the channel,
In the sixth step, the second conductive film is further formed to cover the exposed part of the channel,
The method of manufacturing a semiconductor device according to claim 11, wherein in the seventh step, the second conductive film is patterned to form the other of the scanning line and the data line, and a source / drain electrode.

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