CN103293790B - Pixel cell and preparation method thereof, array base palte, display device - Google Patents
Pixel cell and preparation method thereof, array base palte, display device Download PDFInfo
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- CN103293790B CN103293790B CN201310200428.6A CN201310200428A CN103293790B CN 103293790 B CN103293790 B CN 103293790B CN 201310200428 A CN201310200428 A CN 201310200428A CN 103293790 B CN103293790 B CN 103293790B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Abstract
The invention provides a kind of pixel cell and preparation method thereof, array base palte, display device, belong to display technique field, its area occupied that can solve the memory capacitance of existing double-layer structure is large, the problem that aperture opening ratio is low.Pixel cell of the present invention comprises memory capacitance, and described memory capacitance comprises the first electrode and the second electrode; Described first electrode comprises the sandwich construction of electrical connection, described second electrode comprises the sandwich construction of electrical connection, each Rotating fields of two electrodes is disposed alternately at different layers, and all Rotating fields are overlapping at least partly, and the first electrode is identical with the Rotating fields number of the structure of the second electrode; Described memory capacitance is being the pixel electrode of pixel cell away from the most top level structure on the direction of substrate.The electric capacity of pixel cell of the present invention is sandwich construction, reduces capacitor size, and then improves aperture opening ratio.
Description
Technical field
The invention belongs to technical field of liquid crystal display, be specifically related to a kind of pixel cell and preparation method thereof, array base palte, display device.
Background technology
The aperture opening ratio (aperture) of liquid crystal indicator is defined as the area of pixel cell light-permeable part and the ratio of the pixel cell total area (comprising the area of lightproof part).In order to improve aperture opening ratio, the area of lightproof part must be reduced as much as possible; Meanwhile, also to ensure that pixel cell total area minimizes, to ensure resolution high as far as possible.
In a pixel cell, lighttight part is thin film transistor (TFT) (TFT), signal line, data line, memory capacitance (Cs), black matrix material mainly, and these area summations determine the aperture opening ratio of a pixel.
In the design of separate, stored electric capacity, storage capacitor electrode is served as by pixel electrode in one end, wherein pixel electrode material is transparent metal oxide, as ITO(tin indium oxide), the other end adopts light tight metal material to make another electrode of memory capacitance, namely this memory capacitance is double-layer structure, and two-layer relative area determines the electric capacity of memory capacitance; Wherein, ITO pixel electrode can printing opacity, and metal material is light tight.
Inventor finds that in prior art, at least there are the following problems: in the memory capacitance of existing double-layer structure, the area of light tight metal material electrode needs larger with the relative area ensureing memory capacitance two electrode (thus ensureing electric capacity), and this meeting causes impact to a certain degree to aperture opening ratio.
Summary of the invention
Technical matters to be solved by this invention comprises, area for the memory capacitance of existing pixel cell is larger, cause the problem that aperture opening ratio declines, provide a kind of memory capacitance area to reduce, pixel cell that aperture opening ratio is high and preparation method thereof, array base palte, display device.
The technical scheme that solution the technology of the present invention problem adopts is a kind of pixel cell, and comprise memory capacitance, described memory capacitance comprises the first electrode and the second electrode; Described first electrode comprises the multiple Rotating fields be electrically connected to each other, described second electrode comprises the multiple Rotating fields be electrically connected to each other, each Rotating fields of two electrodes is disposed alternately at different layers, and all Rotating fields are overlapping at least partly, and the first electrode is equal with the number of plies of the structure of the second electrode; Described memory capacitance is being the pixel electrode of pixel cell away from the most top level structure on the direction of substrate.
The memory capacitance of pixel cell of the present invention adopts sandwich construction, and then the area (area namely occupied in substrate of memory capacitance is reduced when total relative area constant (namely electric capacity is constant) of two electrodes of guarantee memory capacitance, namely lighttight area), therefore it effectively can improve the aperture opening ratio of pixel cell.
Preferably, away from the direction of substrate, described memory capacitance comprises ground floor structure, second layer structure, third layer structure, four-layer structure successively, and described four-layer structure is overlapping at least partly;
The four-layer structure of described memory capacitance is the pixel electrode of pixel cell, and is electrically connected with the second layer structure of memory capacitance, forms the first electrode of memory capacitance;
The ground floor structure of described memory capacitance is electrically connected with third layer structure, forms the second electrode of memory capacitance.
Further preferably, above-mentioned pixel cell also comprises the thin film transistor (TFT) of top gate structure;
The active area of described thin film transistor (TFT) and the ground floor structure of memory capacitance are located in same layer, the active area of the first insulation course cover film transistor and the ground floor structure of memory capacitance;
The grid of described thin film transistor (TFT) and the second layer structure of memory capacitance are located on the first insulation course, the grid of the second insulation course cover film transistor and the second layer structure of memory capacitance;
The third layer structure of the source electrode of described thin film transistor (TFT), drain electrode and memory capacitance is located on the second insulation course, the third layer structure of the source electrode of the 3rd insulation course cover film transistor, drain electrode and memory capacitance, wherein,
The ground floor structure of described memory capacitance is electrically connected by the via hole run through in the first insulation course and the second insulation course with between third layer structure;
Described pixel electrode is located on the 3rd insulation course, wherein,
Be electrically connected by the via hole run through in the second insulation course and the 3rd insulation course between described pixel electrode with the second layer structure of memory capacitance.
Further preferably, the material of the active area of described thin film transistor (TFT) is metal-oxide semiconductor (MOS).
Further preferably, the ground floor structure of described memory capacitance comprises the metal oxide semiconductor layer synchronously formed with thin film transistor (TFT) active area, and the metal oxide semiconductor layer of described ground floor structure is provided with metal level.
Again further preferably, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
The technical scheme that solution the technology of the present invention problem adopts is a kind of preparation method of pixel cell, and described pixel cell is above-mentioned pixel cell, comprises the steps:
In substrate, the figure comprising each Rotating fields of memory capacitance is formed successively by patterning processes.
Preferably, the memory capacitance of described pixel cell is the memory capacitance of four-layer structure, comprises the steps:
Substrate is formed the ground floor structure of memory capacitance;
The substrate completing above-mentioned steps is formed the first insulation course;
On the first insulation course, the figure of the second layer structure comprising memory capacitance is formed by patterning processes;
The substrate completing above-mentioned steps is formed the second insulation course, by patterning processes memory capacitance ground floor structure do not form with the upper of the second layer Structural superposition via hole running through the first insulation course and the second insulation course;
The substrate completing above-mentioned steps is formed by patterning processes and comprises the figure of the third layer structure of memory capacitance, and the third layer structure of memory capacitance is by the ground floor anatomical connectivity of the via hole and memory capacitance that run through the first insulation course and the second insulation course;
In the substrate completing above-mentioned steps formed the 3rd insulation course, by patterning processes memory capacitance second layer structure do not form with the upper of third layer Structural superposition the via hole running through the second insulation course and the 3rd insulation course;
In the substrate completing above-mentioned steps, logical patterning processes forms the figure comprising the four-layer structure of memory capacitance, and the four-layer structure of memory capacitance is by the second layer anatomical connectivity of the via hole and memory capacitance that run through the second insulation course and the 3rd insulation course.
Further preferably, described pixel cell also comprises the thin film transistor (TFT) of top gate structure, and the preparation method of described plain unit specifically comprises the steps:
Substrate is formed the ground floor structure of memory capacitance, forms the active area of thin film transistor (TFT) simultaneously;
The substrate completing above-mentioned steps is formed the first insulation course, and formed the figure of the second layer structure of memory capacitance on the first insulation course by patterning processes while, forms the figure comprising thin-film transistor gate;
The substrate completing above-mentioned steps is formed the second insulation course, memory capacitance ground floor structure do not form with the upper of the second layer Structural superposition via hole running through the first insulation course and the second insulation course while source on the active area of thin film transistor (TFT), drain region form the via hole running through the first insulation course and the second insulation course;
Formed while the substrate completing above-mentioned steps is formed by patterning processes the figure of the third layer structure of memory capacitance and comprise the figure of thin film transistor (TFT) source electrode, drain electrode, and the source of described thin film transistor (TFT), draining is connected with thin film transistor (TFT) active area by via hole;
In the substrate completing above-mentioned steps formed the 3rd insulation course, memory capacitance third layer structure do not form with the upper of the second layer Structural superposition via hole running through the second insulation course and the 3rd insulation course while on thin film transistor (TFT) drains, form the via hole running through the 3rd insulation course;
The substrate completing above-mentioned steps is formed by patterning processes the figure comprising the four-layer structure of memory capacitance, and the four-layer structure of described memory capacitance is connected with the drain electrode of thin film transistor (TFT) by the via hole running through the 3rd insulation course.
Further have choosing, the described 101. ground floor structures forming memory capacitance in substrate, form the active area of thin film transistor (TFT) simultaneously, specifically comprise the steps:
Substrate is prepared metal oxide semiconductor material layer, and photoresist layer is applied on metal oxide semiconductor material layer, photoresist is exposed, develops, wherein the remaining photoresist thickness being positioned at active area is greater than the photoresist thickness in memory capacitance district, and the photoresist in the photoresist of active area and memory capacitance district disconnects;
Exposed metal oxide semiconductor material layer is removed by etching;
The photoresist of memory capacitance district residual thickness is removed by development;
In the metal-oxide semiconductor (MOS) district of the ground floor structure of memory capacitance, metal level is formed by chemical plating process
Peel off and remove residue photoresist.
Further preferably, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
Further preferably, described exposure photoresist comprises:
By intermediate tone mask plate or gray level mask plate, photoresist is exposed.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and described array base palte comprises above-mentioned pixel cell.
Because this array base palte comprises above-mentioned pixel cell, therefore its aperture opening ratio is high.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display device, and described display device comprises above-mentioned array base palte.
Because this display device comprises above-mentioned array base palte, therefore its picture effect is better.
Accompanying drawing explanation
Fig. 1 is the structural representation of the pixel cell of embodiments of the invention 1,2,3,4;
Fig. 2 a is that the ground floor configuration steps 1011 of the memory capacitance of the formation pixel cell of embodiments of the invention 4 is intended to;
Fig. 2 b is ground floor configuration steps 1012 schematic diagram of the memory capacitance of the formation pixel cell of embodiments of the invention 4;
Fig. 2 c is ground floor configuration steps 1013 schematic diagram of the memory capacitance of the formation pixel cell of embodiments of the invention 4;
Fig. 2 d is ground floor configuration steps 1014 schematic diagram of the memory capacitance of the formation pixel cell of embodiments of the invention 4;
Fig. 2 e is ground floor configuration steps 1015 schematic diagram of the memory capacitance of the formation pixel cell of embodiments of the invention 4;
Fig. 3 be embodiments of the invention 4 prepare in the method for pixel cell, the structural representation of the pixel cell after completing steps 102; And
Fig. 4 be embodiments of the invention 4 prepare in the method for pixel cell, the structural representation of pixel cell after completing step 104;
Wherein Reference numeral is: 101, substrate; 102, the ground floor structure of memory capacitance; 103, active area; 104, metal-oxide semiconductor (MOS) rete; 105, photoresist; 201, the first insulation course; 202, the second layer structure of memory capacitance; 203, grid; 301, the second insulation course; The third layer structure of 302 memory capacitance; 303, source electrode; 304, drain; 3051, the first via hole; 3052, the second via hole 3053, the 3rd via hole; 3054, the 4th via hole; 3055, the 5th via hole; 401 the 3rd insulation courses; 402, the four-layer structure (pixel electrode) of memory capacitance.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of pixel cell, comprises memory capacitance, and described memory capacitance comprises the first electrode and the second electrode; Described first electrode comprises the multiple Rotating fields be electrically connected to each other, described second electrode comprises the multiple Rotating fields be electrically connected to each other, each Rotating fields of two electrodes is disposed alternately at different layers, and all Rotating fields are overlapping at least partly, and the first electrode is equal with the number of plies of the structure of the second electrode; Described memory capacitance is being the pixel electrode of pixel cell away from the most top level structure on the direction of substrate.
First electrode and second electrode of the memory capacitance of the pixel cell of the present embodiment include sandwich construction, therefore it is little compared with the area of existing memory capacitance, effectively can improve aperture opening ratio.
Embodiment 2
Shown in diagram 1, the present embodiment provides a kind of pixel cell, and it comprises the electric capacity of four-layer structure, also comprises the thin film transistor (TFT) of top gate structure simultaneously.
Wherein, the active area 103 of described thin film transistor (TFT) is located in same layer (being namely directly arranged in suprabasil layer) with the ground floor structure 102 of memory capacitance, the active area 103 of the first insulation course 201 cover film transistor and the ground floor structure 102 of memory capacitance.
The grid 203 of described thin film transistor (TFT) is located on the first insulation course 201 with the second layer structure 202 of memory capacitance, the grid 203 of the second insulation course 301 cover film transistor and the second layer structure 202 of memory capacitance.
The third layer structure 302 of the source electrode 303 of described thin film transistor (TFT), drain electrode 304 and memory capacitance is located on the second insulation course 301, the third layer structure 302 of the source electrode 303 of the 3rd insulation course 401 cover film transistor, drain electrode 304 and memory capacitance, wherein,
The ground floor structure 102 of described memory capacitance is electrically connected by the first via hole 3051 running through the first insulation course 201 and the second insulation course 301 with between third layer structure 302, the source electrode 303 of described thin film transistor (TFT), drain electrode 304 respectively by running through three via hole 3053 of the first insulation course 201 with the second insulation course 301, the 4th via hole 3054 is connected with the active area 103 of thin film transistor (TFT).
Described pixel electrode 402 is located on the 3rd insulation course 401, wherein, be electrically connected by the second via hole 3052 running through the second insulation course 301 and the 3rd insulation course 401 between described pixel electrode 402 with the second layer structure 202 of memory capacitance, simultaneously pixel electrode 402 is drained by the 5th via hole 3055 that runs through the 3rd insulation course 401 above thin film transistor (TFT) drain electrode 304 and thin film transistor (TFT) and 304 to be electrically connected.
Wherein, the ground floor structure 102 of memory capacitance and the active area 103 of thin film transistor (TFT) are arranged at same layer, second layer structure 202 and the grid 203 of thin film transistor (TFT) are arranged at same layer, the source electrode 303 of third layer structure 302 and thin film transistor (TFT) and drain and 304 be arranged at same layer, also just can when making and the spacer structure of thin film transistor (TFT) formed respectively by a patterning processes, that is processing step need not be increased, also can be cost-saving.
Certainly, each Rotating fields of memory capacitance also can lay respectively in different layers from the structure of thin film transistor (TFT), need each Rotating fields making thin film transistor (TFT) and memory capacitance respectively like this, but its memory capacitance is compared with existing memory capacitance, area still reduces, and also effectively can improve aperture opening ratio.
Preferably, the material of the active area 103 of described thin film transistor (TFT) is metal-oxide semiconductor (MOS).
Preferably, the ground floor structure 102 of described memory capacitance comprises the metal oxide semiconductor layer that formed synchronous with thin film transistor (TFT) active area 103, the metal oxide semiconductor layer of described ground floor structure 102 is provided with metal level, wherein, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
When active area 103 material is metal-oxide semiconductor (MOS), the storage capacitor construction that formed synchronous with it is also metal oxide semiconductor material, therefore non-conductive, directly as electrode, therefore at this moment also can not will form the metal level for conducting electricity thereon.
Certainly the pixel cell in this enforcement is just for the thin film transistor (TFT) of the memory capacitance and top gate type that comprise four-layer structure, the memory capacitance of certain pixel cell also can be six layers, the memory capacitance of eight layers and more multi-layered structure (Rotating fields number is even number), the type of thin film transistor (TFT) also can be (bottom gate thin film transistor) of other type, as long as reduce the area (area namely occupied in substrate of memory capacitance when total relative area constant (namely electric capacity is constant) of two electrodes of guarantee memory capacitance, namely lighttight area), the pixel cell of this structure is just in protection scope of the present invention.
Embodiment 3
The present embodiment provides a kind of preparation method of pixel cell for the pixel cell described in embodiment 1,2, comprises the steps:
Substrate is formed the figure comprising the sandwich construction of the memory capacitance of pixel cell.
Wherein, after often forming a Rotating fields of memory capacitance, just on this Rotating fields, form a layer insulating, the part underlapped in adjacent two layers structure forms the via hole running through the insulation course that this double-layer structure covers, for two odd-level electrical connections and the electrical connection of two even levels, form the first electrode and second electrode of memory capacitance respectively, and the number of plies of the first electrode is identical with the number of plies of the second electrode.
Certainly, pixel cell also comprises thin film transistor (TFT), while the memory capacitance forming pixel cell, also form thin film transistor (TFT).
Embodiment 4
Shown in composition graphs 1,2,3,4, the present embodiment provides a kind of preparation method of pixel cell for the pixel cell of embodiment 2, specifically comprises the steps:
The 101. ground floor structures 102 forming memory capacitance in substrate 101, form the active area 103 of thin film transistor (TFT), as shown in Figure 2 simultaneously.
Wherein step 101 specifically comprises:
As shown in Figure 2 a, 1011. utilize metal oxide semiconductor material to form the figure including active layer and ground floor structure respectively by patterning processes in substrate 101, first concrete forms metal-oxide semiconductor (MOS) rete 104 in substrate 101, and photoresist 105 is formed on metal-oxide semiconductor (MOS) rete 104, photoresist 105 is exposed, developed, wherein remaining photoresist 105 thickness being positioned at active area 103 is greater than photoresist 105 thickness in memory capacitance district, and the photoresist 105 of active area 103 disconnects with the photoresist 105 in memory capacitance district.
Preferably, described exposure photoresist 105 comprises:
By intermediate tone mask plate or gray level mask plate, photoresist 105 is exposed.
As shown in Figure 2 b, 1012. exposed metal-oxide semiconductor (MOS) rete 104 is removed by etching.
As shown in Figure 2 c, 1013. by etching the photoresist 105 removing memory capacitance district residual thickness.
1014. in the metal-oxide semiconductor (MOS) district of the ground floor structure 102 of memory capacitance, form metal level by chemical plating process as shown in Figure 2 d.
Chemical plating process is simple, and cost is low; And due to the complexing agent in the chemical liquids that uses in the chemical plating process in this programme be tartrate, it can make metal and metal oxide surface modification, and change can not be caused to surfaces such as SiO, SiN, therefore its meeting forms metal level (because thin film transistor (TFT) active area 103 is now still covered by photoresist in the metal-oxide semiconductor (MOS) district of the ground floor structure 102 of exposed memory capacitance, therefore can not metal level be formed), and the performance of top gate type thin film transistor is not affected.
Preferably, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
To form the example of Mo layer as chemical plating process: at the temperature between room temperature to 100 DEG C, being coated on by electroless plating molybdenum liquid has in the substrate 101 of structure as shown in Figure 2 c, treat its structure that can obtain as shown in Fig. 2 d, Fig. 2 e that reacts completely, clean afterwards, dry, carry out subsequent step.Wherein, the composition of electroless plating molybdenum liquid can comprise: the molybdenum trisulfate of 0.1 ~ 0.3mol/L; The sodium sulphide (stabilizing agent) of 0.05 ~ 0.15mol/L, it is for ensureing the stable of molybdenum ion; The sodium acetate (buffering agent) of 0.1 ~ 1mol/L; The tartrate (complexing agent) of 0.1 ~ 1mol/L, it can be used for making the polarity of molybdenum ion to increase, and makes the coating crystallization of gained careful smooth, can also stablize plating solution simultaneously; The water of surplus.Certainly, be more than an object lesson of electroless plating molybdenum liquid, its composition can have difference, such as, wherein also can contain other materials such as accelerator, pH value regulator, and the selection of the concentration of each existing component, material also can be different.
Because the technique being formed conductive layer by electroless plating is known, therefore no longer it is described in detail at this.
Certainly, if do not use chemical plating process, and to adopt patterning processes directly to form metal level be also feasible, it needs increase patterning processes like this, but its scope of application is also wider, such as can be used for the thin film transistor (TFT) of bottom gate type, and the material of active area may not be metal-oxide semiconductor (MOS).
As shown in Figure 2 e, 1015. removal residue photoresist 105 is peeled off.
102. form the first insulation course 201 in the substrate 101 completing above-mentioned steps, and formed the figure of the second layer structure 202 of memory capacitance on the first insulation course 201 by patterning processes while, form the figure comprising thin-film transistor gate, obtain structure as shown in Figure 2.
103. form the second insulation course 301 in the substrate 101 completing above-mentioned steps, and the source while the upper that ground floor structure 102 and the second layer structure 202 of memory capacitance are underlapped forms the first via hole 3051 running through the first insulation course 201 and the second insulation course 301 on the active area 103 of thin film transistor (TFT), drain region form the 3rd via hole 3053 and the 4th via hole 3054 that run through the first insulation course 201 and the second insulation course 301.
104. comprise the figure of thin film transistor (TFT) source electrode 303, drain electrode 304 by formation while the figure of the third layer structure 302 of patterning processes formation memory capacitance in the substrate 101 completing above-mentioned steps, and the source of described thin film transistor (TFT), drain electrode 304 are connected with thin film transistor (TFT) active area 103 with the 4th via hole 3054 respectively by the 3rd via hole 3053, obtain structure as shown in Figure 3.
105. form the 3rd insulation course 401 in the substrate 101 completing above-mentioned steps, drain on 304 at thin film transistor (TFT) while the upper that the third layer structure 302 of memory capacitance is underlapped with second layer structure 202 forms the second via hole 3052 running through the second insulation course 301 and the 3rd insulation course 401 and form the 5th via hole 3055 running through the 3rd insulation course 401, obtain structure shown in Fig. 4.
106. form by patterning processes the figure comprising the four-layer structure 402 of memory capacitance in the substrate 101 completing above-mentioned steps, and the four-layer structure 402 of described memory capacitance is connected with the drain electrode 304 of thin film transistor (TFT) by the second via hole 3052 running through the 3rd insulation course 401, obtains structure as shown in Figure 1.
Certainly; according to the difference of thin-film transistor structure; the concrete preparation method of memory capacitance is also various (such as can be 6 layers, 8 layers etc.), describe no longer one by one, but as long as its sandwich construction (even level structure) that can form memory capacitance just belongs to protection scope of the present invention at this.
Embodiment 5
Present embodiments provide a kind of array base palte, this array base palte comprises above-mentioned pixel cell.
Certainly, in array base palte, also should have other the known structure such as data line, sweep trace, be not described in detail at this.
Array base palte due to the present embodiment has above-mentioned pixel cell, therefore its aperture opening ratio is higher.
Embodiment 6
Present embodiments provide a kind of display device, this display device comprises the array base palte described in embodiment 5.This display device can be: any product or parts with Presentation Function such as mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Have the array base palte in embodiment 5 in the display device of the present embodiment, therefore it has better aperture opening ratio, visual effect is better.
Certainly, other conventional structures can also be comprised in the display device of the present embodiment, as power supply unit, display driver unit etc.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (14)
1. a pixel cell, comprises memory capacitance, it is characterized in that, described memory capacitance comprises the first electrode and the second electrode;
Described first electrode comprises the multiple Rotating fields be electrically connected to each other, described second electrode comprises the multiple Rotating fields be electrically connected to each other, each Rotating fields of two electrodes is disposed alternately at different layers, and all Rotating fields are overlapping at least partly, and the first electrode is identical with the Rotating fields number of the second electrode;
Described memory capacitance is being the pixel electrode of pixel cell away from the most top level structure on the direction of substrate.
2. pixel cell according to claim 1, is characterized in that, away from the direction of substrate, described memory capacitance comprises ground floor structure, second layer structure, third layer structure, four-layer structure successively;
The four-layer structure of described memory capacitance is the pixel electrode of pixel cell, and is electrically connected with the second layer structure of memory capacitance, forms the first electrode of memory capacitance;
The ground floor structure of described memory capacitance is electrically connected with third layer structure, forms the second electrode of memory capacitance.
3. pixel cell according to claim 2, is characterized in that, also comprises the thin film transistor (TFT) of top gate structure,
The active area of described thin film transistor (TFT) and the ground floor structure of memory capacitance are located in same layer, the active area of the first insulation course cover film transistor and the ground floor structure of memory capacitance;
The grid of described thin film transistor (TFT) and the second layer structure of memory capacitance are located on the first insulation course, the grid of the second insulation course cover film transistor and the second layer structure of memory capacitance;
The third layer structure of the source electrode of described thin film transistor (TFT), drain electrode and memory capacitance is located on the second insulation course, the third layer structure of the source electrode of the 3rd insulation course cover film transistor, drain electrode and memory capacitance, wherein,
The ground floor structure of described memory capacitance is electrically connected by the via hole run through in the first insulation course and the second insulation course with between third layer structure;
Described pixel electrode is located on the 3rd insulation course, wherein,
Be electrically connected by the via hole run through in the second insulation course and the 3rd insulation course between described pixel electrode with the second layer structure of memory capacitance.
4. pixel cell according to claim 3, is characterized in that, the material of the active area of described thin film transistor (TFT) is metal-oxide semiconductor (MOS).
5. pixel cell according to claim 4, it is characterized in that, the ground floor structure of described memory capacitance comprises the metal oxide semiconductor layer synchronously formed with thin film transistor (TFT) active area, and the metal oxide semiconductor layer of described ground floor structure is provided with metal level.
6. pixel cell according to claim 5, is characterized in that, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
7. as weighed a preparation method for the pixel cell in 1 to 6 as described in any one, it is characterized in that, comprising the steps:
In substrate, the figure comprising each Rotating fields of memory capacitance is formed successively by patterning processes.
8. the preparation method of pixel cell according to claim 7, is characterized in that, described memory capacitance is the memory capacitance of four-layer structure, and the preparation method of described pixel cell comprises the steps:
Substrate is formed the ground floor structure of memory capacitance;
The substrate completing above-mentioned steps is formed the first insulation course;
On the first insulation course, the figure of the second layer structure comprising memory capacitance is formed by patterning processes;
The substrate completing above-mentioned steps is formed the second insulation course, by patterning processes memory capacitance ground floor structure do not form with the upper of the second layer Structural superposition via hole running through the first insulation course and the second insulation course;
The substrate completing above-mentioned steps is formed by patterning processes and comprises the figure of the third layer structure of memory capacitance, and the third layer structure of memory capacitance is by the ground floor anatomical connectivity of the via hole and memory capacitance that run through the first insulation course and the second insulation course;
In the substrate completing above-mentioned steps formed the 3rd insulation course, by patterning processes memory capacitance second layer structure do not form with the upper of third layer Structural superposition the via hole running through the second insulation course and the 3rd insulation course;
In the substrate completing above-mentioned steps, logical patterning processes forms the figure comprising the four-layer structure of memory capacitance, and the four-layer structure of memory capacitance is by the second layer anatomical connectivity of the via hole and memory capacitance that run through the second insulation course and the 3rd insulation course.
9. the preparation method of pixel cell according to claim 8, is characterized in that, described pixel cell also comprises the thin film transistor (TFT) of top gate structure, and the preparation method of described plain unit specifically comprises the steps:
Substrate is formed the ground floor structure of memory capacitance, forms the active area of thin film transistor (TFT) simultaneously;
The substrate completing above-mentioned steps is formed the first insulation course, and is formed on the first insulation course by patterning processes and comprise the second layer structure of memory capacitance and the figure of thin-film transistor gate;
The substrate completing above-mentioned steps is formed the second insulation course, form at not underlapped with the second layer structure upper of the ground floor structure of memory capacitance the via hole running through the first insulation course and the second insulation course by patterning processes, simultaneously in the source of thin film transistor (TFT), drain region forms the via hole running through the first insulation course and the second insulation course;
The substrate completing above-mentioned steps is formed by patterning processes the figure comprising the third layer structure of memory capacitance and thin film transistor (TFT) source electrode, drain electrode, and the source of described thin film transistor (TFT), draining is connected with thin film transistor (TFT) active area by via hole;
The substrate completing above-mentioned steps forms the 3rd insulation course, while the third layer structure of memory capacitance and the underlapped upper of second layer structure form the via hole running through the second insulation course and the 3rd insulation course, on thin film transistor (TFT) drains, forms the via hole running through the 3rd insulation course;
The substrate completing above-mentioned steps is formed by patterning processes the figure comprising the four-layer structure of memory capacitance, and the four-layer structure of described memory capacitance is connected with the drain electrode of thin film transistor (TFT) by the via hole running through the 3rd insulation course.
10. the preparation method of pixel cell according to claim 9, is characterized in that, the described ground floor structure forming memory capacitance in substrate, forms the active area of thin film transistor (TFT) simultaneously, specifically comprise the steps:
Substrate is prepared metal oxide semiconductor material layer, and photoresist layer is applied on metal oxide semiconductor material layer, photoresist is exposed, develops, wherein the remaining photoresist thickness being positioned at active area is greater than the photoresist thickness in memory capacitance district, and the photoresist in the photoresist of active area and memory capacitance district disconnects;
Exposed metal oxide semiconductor material layer is removed by etching;
The photoresist of memory capacitance district residual thickness is removed by etching;
On the metal oxide semiconductor layer of the ground floor structure of memory capacitance, metal level is formed by chemical plating process;
Peel off and remove residue photoresist.
The preparation method of 11. pixel cells according to claim 10, is characterized in that, described metal level is made up of at least one in molybdenum, copper, aluminium, tungsten.
The preparation method of 12. pixel cells according to claim 10, is characterized in that, described exposure photoresist comprises:
By intermediate tone mask plate or gray level mask plate, photoresist is exposed.
13. 1 kinds of array base paltes, is characterized in that, comprise the pixel cell in claim 1 ~ 6 described in any one.
14. 1 kinds of display device, is characterized in that, comprise array base palte according to claim 13.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310200428.6A CN103293790B (en) | 2013-05-27 | 2013-05-27 | Pixel cell and preparation method thereof, array base palte, display device |
| PCT/CN2013/085280 WO2014190657A1 (en) | 2013-05-27 | 2013-10-16 | Pixel unit, manufacturing method thereof, array substrate, and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310200428.6A CN103293790B (en) | 2013-05-27 | 2013-05-27 | Pixel cell and preparation method thereof, array base palte, display device |
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| CN103293790A CN103293790A (en) | 2013-09-11 |
| CN103293790B true CN103293790B (en) | 2016-01-06 |
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| WO (1) | WO2014190657A1 (en) |
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| CN103293790B (en) * | 2013-05-27 | 2016-01-06 | 京东方科技集团股份有限公司 | Pixel cell and preparation method thereof, array base palte, display device |
| CN104716154B (en) * | 2013-12-11 | 2018-12-18 | 昆山国显光电有限公司 | A kind of organic light-emitting display device and preparation method thereof |
| US9443876B2 (en) * | 2014-02-05 | 2016-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module |
| CN103943634A (en) * | 2014-03-17 | 2014-07-23 | 京东方科技集团股份有限公司 | Array substrate, display device and capacitor structure of array substrate |
| CN104965362A (en) * | 2015-06-04 | 2015-10-07 | 京东方科技集团股份有限公司 | Array base plate, preparation method of same and display apparatus |
| CN105116585A (en) * | 2015-09-16 | 2015-12-02 | 深圳市华星光电技术有限公司 | Touch panel, array substrate and manufacturing method of array substrate |
| TWI575732B (en) * | 2016-05-25 | 2017-03-21 | 友達光電股份有限公司 | Pixel structure and display device |
| CN105914229B (en) | 2016-06-24 | 2017-12-15 | 京东方科技集团股份有限公司 | A kind of AMOLED display base plates and preparation method thereof, display device |
| CN107579083A (en) * | 2017-09-30 | 2018-01-12 | 京东方科技集团股份有限公司 | Array base palte and preparation method and display device |
| US10804411B2 (en) * | 2017-11-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of forming the same |
| CN108257977B (en) * | 2018-01-10 | 2021-01-01 | 京东方科技集团股份有限公司 | Display back plate and manufacturing method thereof, display panel and display device |
| CN108878453A (en) * | 2018-06-29 | 2018-11-23 | 上海天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN108957884B (en) * | 2018-07-23 | 2021-07-27 | Tcl华星光电技术有限公司 | Array substrate, liquid crystal panel and array substrate manufacturing method |
| CN110164870A (en) | 2019-05-14 | 2019-08-23 | 深圳市华星光电半导体显示技术有限公司 | Backsheet constructions containing capacitor |
| CN115995470A (en) * | 2019-08-23 | 2023-04-21 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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