TW201742170A - Semiconductor packages and methods of manufacturing the same - Google Patents

Abstract

Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

Description

Semiconductor package and method of manufacturing same

The disclosed concept relates to a semiconductor package and a method of fabricating the same, and more particularly to a solder ball of a semiconductor package and a method of fabricating the same.

Semiconductor packages are provided to make integrated circuit chips suitable for use in electronic appliances. Generally, in a semiconductor package, a semiconductor wafer is mounted on a printed circuit board (PCB), and the semiconductor wafer is electrically connected to the printed circuit board using bonding wires or bonding bumps. With the development of the electronics industry, electronic products have increasingly required high performance, high speed, and compact size. To cope with this trend, numerous stacking methods have been developed, such as stacking multiple semiconductor wafers on a single substrate or stacking packages on another package.

Embodiments of the inventive concept provide a semiconductor package with increased reliability and a method of fabricating the same.

Embodiments of the inventive concept provide a simplified method of fabricating a semiconductor package.

According to an exemplary embodiment, the disclosed concept relates to a method of fabricating a semiconductor package, the method comprising: providing an interconnect substrate on a carrier substrate; forming a first solder ball on the interconnect substrate; Providing a semiconductor wafer on the carrier substrate, the semiconductor wafer being spaced apart from the interconnect substrate; forming a polymer layer on the interconnect substrate and the semiconductor wafer, the polymer layer covering the first solder ball And forming an opening in the polymer layer to expose the first solder ball.

According to an exemplary embodiment, the present invention is directed to a semiconductor package including: a substrate; a semiconductor wafer disposed on the substrate; and an interconnect substrate spaced apart from the semiconductor wafer on the substrate, The interconnect substrate includes a conductive member; a solder ball disposed on the interconnect substrate and electrically connected to the conductive member; a polymer layer disposed on the interconnect substrate and the semiconductor wafer, The polymer layer includes an opening through which the solder ball is exposed; and polymer particles formed in the solder ball and containing the same material as the polymer layer, wherein the polymer particles At least some are formed in the top half of the solder ball.

According to an exemplary embodiment, the present invention is directed to a method of fabricating a semiconductor package, the method comprising: providing an interconnect substrate on a carrier substrate; forming a solder pad on the interconnect substrate; forming a a solder bump; providing a semiconductor wafer on the carrier substrate, the semiconductor wafer being spaced apart from the interconnect substrate; forming a polymer layer on the interconnect substrate and the semiconductor wafer, the polymer layer Covering the first solder bump; and forming an opening in the polymer layer to expose a portion of the first solder bump, wherein the first solder bump is disposed on the solder pad and contacts Said solder pad.

The various pads of the devices described herein can be conductive terminals that are connected to the internal wiring of the device, and can transmit signals and/or supply voltages between internal wiring of the device and/or internal circuitry and external sources. For example, a wafer pad of a semiconductor wafer can be electrically connected to an integrated circuit of the semiconductor wafer and a device connected to the semiconductor wafer, and a power supply voltage and/or signal is transmitted between the integrated circuit and the device. The various pads may be disposed on or near the outer surface of the device, and may generally have a flat surface area (typically greater than a corresponding surface area of the internal wiring connected to the various pads) to facilitate A connection of a terminal (such as a solder bump or solder ball) and/or external wiring.

As used herein, various items that are described as "electrically connected" are configured such that electrical signals can be transmitted from one item to another. Thus, a passive conductive component that is physically connected to a passive electrical insulation component (eg, a prepreg layer of a printed circuit board, an electrically insulating adhesive that joins two devices, an electrically insulating underfill layer, or an electrically insulating mold layer, etc.) For example, wires, pads, internal wires, etc.) are not electrically connected to the assembly. In addition, individual items that are "directly electrically connected" to each other are electrically connected by one or more passive components (eg, for example, wires, pads, internal wires, perforations, etc.). As such, the directly electrically connected components do not include components that are electrically connected by active components such as transistors or diodes. The directly electrically connected components can be physically connected and directly electrically connected.

Hereinafter, a method of manufacturing a semiconductor package will be explained in accordance with an exemplary embodiment.

FIG. 1A is a plan view illustrating a first package 10, according to an exemplary embodiment. 1B to 1F, 1K, and 1M are cross-sectional views for explaining a method of fabricating a semiconductor package, according to an exemplary embodiment. 1B to 1F, FIG. 1I, FIG. 1K, and FIG. 1M correspond to a cross-sectional view taken along line II' shown in FIG. 1A. 1G and 1H are enlarged cross-sectional views of a portion II shown in Fig. 1F. 1J, 1L, and 1N are enlarged cross-sectional views of a portion II shown in Figs. 1I, 1K, and 1M, respectively.

Referring to FIGS. 1A and 1B, an interconnect substrate 200 may be provided on the carrier substrate 100. A carrier glue layer 110 may be provided to adhere the interconnection substrate 200 to the carrier substrate 100. For example, a printed circuit board (PCB) can be used as the interconnect substrate 200, which can be bonded to the carrier substrate 100 by the carrier glue layer 110. The interconnect substrate 200 may include a base layer 210 and a conductive member 220 located in the base layer 210. The base layer 210 may comprise a non-conductive material (eg, a non-electrically conductive material). For example, the base layer 210 may comprise a carbonaceous material (eg, graphite, graphene, etc.), a ceramic, or a polymer (eg, nylon, polycarbonate, high-density polyethylene, HDPE, etc.) ). Each of the conductive members 220 may include a first pad 221, a line pattern 222, and a via 223. The first pad 221 may be disposed on the bottom surface 200b of the interconnect substrate 200 above the carrier glue layer 110. The via 223 can penetrate the base layer 210. The line pattern 222 may be sandwiched between the respective base layers 210 and connected to the via 223. Conductive member 220 can comprise copper, nickel, aluminum, gold, silver, stainless steel, or alloys thereof. Conductive member 220 can have a melting point of about 1100 °C. In certain embodiments, the electrically conductive member 220 can have a melting point above about 450 °C.

A solder pad 300 may be provided on the top surface 200a of the interconnect substrate 200, and the solder pad 300 may be electrically connected to one of the vias 223. The solder pad 300 may comprise copper, nickel, aluminum, gold, silver, stainless steel, or alloys thereof. The solder pad 300 may have a high melting point. For example, solder pad 300 can have a melting point of about 1100 °C. In certain embodiments, solder pad 300 can have a melting point above about 450 °C.

A mask pattern 150 may be formed on the top surface 200a of the interconnect substrate 200. The interconnect substrate 200 may include a mask opening 151 through which the solder pad 300 is exposed.

A solder bump may be formed on the solder pad 300, which may be, for example, a solder ball (eg, the first solder ball SB1), and thus the first solder ball SB1 may be electrically connected to the conductive member 220. For example, solder paste (not shown) may be provided on the solder pad 300 in the mask opening 151. The solder paste may be reflowed such that a first solder ball SB1 may be formed on the solder pad 300 in the mask opening 151. The first solder ball SB1 may be formed at a temperature lower than the melting point of the conductive member 220 and the melting point of the solder pad 300. For example, the first solder ball SB1 may be formed at a temperature lower than 450 °C. In some embodiments, the first solder ball SB1 can be formed at a temperature of from about 170 ° C to about 230 ° C. The solder pad 300 can thus be in a solid state during formation of the first solder ball SB1 without being melted. The first solder ball SB1 may have a melting point of less than about 450 °C. In certain embodiments, the first solder ball SB1 can have a melting point from about 170 °C to about 230 °C. The first solder ball SB1 may include, for example, tin (Sn), lead (Pb), indium (In), or an alloy thereof. After the solder paste is reflowed, the first solder ball SB1 may be placed at room temperature (for example, about 15 ° C to about 25 ° C), and the first solder ball SB1 may be in a solid state. The mask pattern 150 can be removed.

Referring to FIGS. 1A and 1C, a hole 290 may be formed in the interconnect substrate 200. For example, the interconnect substrate 200 can be partially removed to form the holes 290. The holes 290 may be formed on a central portion of the interconnect substrate 200 when viewed in a plan view.

Referring to FIGS. 1A and 1D, a first semiconductor wafer 400 and a first polymer layer 500 may be provided on a carrier substrate 100. The first semiconductor wafer 400 may be disposed in the hole 290 of the interconnect substrate 200 and may be surrounded by the interconnect substrate 200 along its periphery when viewed in a plan view. In some embodiments, there may be a gap between the semiconductor wafer 400 and the interconnected interconnect substrate 200. The first semiconductor wafer 400 can include one or more wafer pads 410 on its bottom surface.

A first polymer layer 500 may be formed on the interconnect substrate 200 and the first semiconductor wafer 400. The first polymer layer 500 may cover the first solder ball SB1. The first polymer layer 500 may be disposed in a gap between the interconnect substrate 200 and the first semiconductor wafer 400. The first polymer layer 500 can comprise an insulating polymer such as, for example, an epoxy based polymer. The first polymer layer 500 can be used as a mold layer. For example, a polymer sheet can be used to form the first polymer layer 500, but the embodiment is not limited thereto. Thereafter, the carrier substrate 100 and the carrier paste layer 110 may be removed to expose the bottom surface of the first semiconductor wafer 400 and the bottom surface of the interconnect substrate 200 and disposed in the gap between the interconnect substrate 200 and the first semiconductor wafer 400. The bottom surface of the first polymer layer 500.

Referring to FIGS. 1A and 1E, an insulating pattern 610 and a redistribution member 621 and a redistribution member 622 may be formed on the bottom surface of the first semiconductor wafer 400 and the bottom surface 200b of the interconnect substrate 200, thereby forming the first substrate 600. The first substrate 600 may be a redistribution substrate. The redistribution member 621 and the redistribution member 622 may include a conductive pattern 621 disposed between the respective insulation patterns 610 and a conductive via 622 penetrating the insulation pattern 610. The redistribution member 621 and the redistribution member 622 may include a metal such as copper or aluminum, and may have a melting point of about 1100 °C. In some embodiments, the redistribution member 621 and the redistribution member 622 can have a melting point above about 450 °C. The redistribution member 621 and the redistribution member 622 may be in contact with the wafer pad 410 of the first semiconductor wafer 400 and the first pad 221 of the interconnection substrate 200. A protective layer 630 may be formed on the bottom surface of the first substrate 600. The protective layer 630 may comprise an insulating material. For example, the protective layer 630 can comprise the same material as the first polymer layer 500. Alternatively, the protective layer 630 can be omitted. In some embodiments, since the redistribution substrate is used as the first substrate 600, the first substrate 600 may have a small thickness.

Referring to FIGS. 1A and 1F, an opening 550 may be formed in the first polymer layer 500, and thus the first solder ball SB1 may be exposed through the opening 550. In some embodiments, a portion of the first solder ball SB1 may be exposed via an opening 550 formed in the first polymer layer 500. For example, a drilling process can be performed to remove the first polymer layer 500 such that the opening 550 can be formed. In some embodiments, the drilling process can be performed using laser drilling. Hereinafter, the formation of the opening 550 can be discussed in further detail with reference to FIGS. 1G and 1H. It should be noted that although only one opening 550 is discussed in this example as shown in FIG. 1F, a plurality of openings may be formed.

1G and 1H are cross-sectional views corresponding to an enlarged cross-sectional view of a portion II shown in FIG. 1F, illustrating a forming procedure of the opening 550 according to an exemplary embodiment.

Referring to FIG. 1G, the opening 550 may expose the first solder ball SB1 to air, and thus the oxide layer 700 may be formed on the first solder ball SB1. After the oxide layer 700 is formed, the first polymer layer 500 shown in FIG. 1D may be formed, or the opening 550 shown in FIG. 1F may be formed before the oxide layer 700 is formed. Although not shown, in some embodiments, the oxide layer 700 can be more sandwiched between the first solder ball SB1 and the first polymer layer 500. The oxide layer 700 can have a variety of shapes and thicknesses, and is not limited to the shapes and thicknesses illustrated. When the opening 550 is formed, a portion of the polymer 500 may not be removed, but may remain to form a residue 501 on the first solder ball SB1. The residue 501 may remain on the first solder ball SB1 and may cover the oxide layer 700. Alternatively, in some embodiments, the oxide layer 700 may not be sandwiched between the residue 501 and the first solder ball SB1. Residue 501 can have a variety of shapes, but is not limited to the shapes illustrated. Residue 501 can comprise the same material as first polymer layer 500.

If the first solder ball SB1 in FIG. 1F is formed after the opening 550 is formed, the opening 550 may expose the solder pad 300, and the residue of the first polymer layer 500 may remain on the solder pad 300. Since the solder pad 300 has a high melting point, the solder pad 300 can be not melted by the heat generated from the drilling process, but can be kept in a solid state. The residue of the first polymer layer 500 can thus form a layer (not shown) that covers the solder pad 300. In this example, the first solder ball SB1 may be formed on the residue of the first polymer layer 500. Since the formation of the first solder ball SB1 is performed at a temperature lower than the melting point of the solder pad 300, the residue of the first polymer layer 500 may remain between the solder pad 300 and the first solder ball SB1. In this case, poor electrical characteristics may be achieved between the solder pad 300 and the first solder ball SB1. If a removal process is performed to remove the residue of the first polymer layer 500 on the solder pad 300, the removal process may increase the number of process steps of the semiconductor package. Additionally, the solder pad 300 and/or the first polymer layer 500 may be damaged during the removal process for removing residues of the first polymer layer 500.

In some embodiments, when the opening 550 is formed after the first solder ball SB1 is formed, the residue 501 may not be formed on the solder pad 300. The first solder ball SB1 can thus be satisfactorily connected to the solder pad 300 to allow a good electrical connection between the first solder ball SB1 and the solder pad 300 to be achieved.

Referring to FIG. 1G and FIG. 1H in sequence, the drilling process can generate heat. The heat can be transferred to the first solder ball SB1. Since the first solder ball SB1 has a relatively low melting point, the heat may melt at least a portion of the first solder ball SB1. For example, the upper portion of the first solder ball SB1 may be melted into a liquid state. Residue 501 can flow into first solder ball SB1 as indicated by the arrows in Figure 1G such that polymer particles 502 can be formed as shown in Figure 1H. The oxide layer 700 may hardly affect the inflow of the residue 501, so that the residue 501 can flow into the first solder ball SB1 substantially unimpeded. The polymer particles 502 may be dispersed in the first solder ball SB1. Polymer particles 502 can have a variety of shapes such as, for example, a circular or elliptical shape. For example, polymer particles 502 can have an average diameter of less than about 2 microns. In certain embodiments, polymer particles 502 can have an average diameter of less than about 1 micron. After the drilling process, the first solder ball SB1 may be placed at room temperature (for example, about 15 ° C to about 25 ° C), and the melted portion of the first solder ball SB1 may become a solid state. In some embodiments, the first solder ball SB1 may have a portion of the residue 501 that does not flow into the first solder ball SB1 on the first solder ball SB1. Alternatively, in other embodiments, there may be no residue 501 remaining on the first solder ball SB1.

As illustrated in FIG. 1H, in certain embodiments, polymer particles 502 may be formed on the first solder ball SB1, and when the opening 550 is formed, the polymer particles 502 may be dispersed in the first solder ball SB1. The polymer particles 502 dispersed in the first solder balls SB1 may be located above the bottom of the first solder balls SB1. For example, at least some of the polymer particles 502 formed in the first solder ball SB1 may be located in the top half of the first solder ball SB1, and at least some of the polymer particles 502 may be located in the first solder In the middle part of the ball SB1.

Returning to FIG. 1F, an external terminal 650 may be formed on the bottom surface of the first substrate 600. For example, the lower opening 631 may be formed in the protective layer 630, and thus the redistribution member 621 and the redistribution member 622 may be exposed through the lower opening 631. The external terminal 650 may be formed in the lower opening 631 and connected to the redistribution member 621 and the redistribution member 622. The external terminal 650 may include metal and have a shape of a solder ball. Each of the external terminals 650 may be electrically connected to the first solder ball SB1 by the redistribution member 621 and the redistribution member 622 and the conductive member 220. The external terminal 650 may be misaligned with the first solder ball SB1 in the third direction D3. For example, the external terminal 650 may be offset with respect to the first solder ball SB1 when viewed from a plan view (eg, the third direction D3). The number of external terminals 650 may be different from the number of solder pads 300. The first package 10 can be fabricated by the foregoing examples. The first package 10 can be fabricated in a wafer level process.

Referring to FIGS. 1A, 1I, and 1J, the oxide layer 700 illustrated in FIGS. 1G and 1H can be removed by performing a cleaning process on the first solder ball SB1. The cleaning process can be performed using a soldering fluid. For example, the soldering solution may contain a halogen element. In this step, residue 501 can also be removed along with oxide layer 700. Since the residue 501 is removed without performing a separate process, the fabrication of the first package 10 can be simplified. After the cleaning process is completed, in some embodiments, a portion of the residue 501 may not be removed but may remain on the first solder ball SB1. Alternatively, in other embodiments, no residue 501 remains on the first solder ball SB1 at the end of the cleaning process.

Referring to FIGS. 1K and 1L, a second package 20 may be provided on the first package 10. The second package 20 can include a second substrate 800, a second semiconductor wafer 810, and a mold layer 820. The second substrate 800 can be a printed circuit board or a redistributed substrate. The second semiconductor wafer 810 can be disposed on the second substrate 800 and can be electrically connected to the second substrate 800 by, for example, bonding wires 811. The second semiconductor wafer 800 can have various numbers, mounting methods, arrangements, and constituent elements and/or features. A second solder ball SB2 may be provided on the bottom surface of the second substrate 800. The second solder ball SB2 may be electrically connected to the second semiconductor wafer 810. A broken line in the second substrate 800 may roughly represent an example of electrical connection of the second substrate 800. The second package 20 may be disposed on the first package 10 to align the second solder ball SB2 with the first solder ball SB1.

Referring to FIGS. 1M and 1N and FIG. 1L, a reflow process may be performed to couple or bond the second solder ball SB2 to the first solder ball SB1 such that the interconnect solder SB may be formed in the first semiconductor package 1. The interconnect solder SB may be formed between the solder pad 300 and the second substrate 800. The reflow process may be performed at a temperature equal to or higher than the melting point of the first solder ball SB1 and the melting point of the second solder ball SB2 and lower than the melting point of the conductive member 220 and the melting point of the solder pad 300. For example, the reflow process can be performed at a temperature of less than about 450 °C. In certain embodiments, the reflow process can be performed at a temperature from 170 ° C to about 230 ° C. The conductive member 220 and the solder pad 300 may not be melted in the reflow process, but may remain in a solid form. The conductive member 220 and the solder pad 300 may not be damaged during the reflow process.

Although a portion of the residue 501 remains on the first solder ball SB1 in the reflow process, the residue 501 may flow into the interconnect solder SB as shown in FIGS. 1G and 1L, and as shown in FIGS. 1M and 1N. Polymer particles 502 are formed in the interconnect solder SB. The polymer particles 502 can be dispersed in the interconnect solder SB such that the polymer particles 502 can hardly affect the electrical characteristics of the interconnect solder SB. Therefore, the second package 20 can be successfully electrically connected to the first package 10 by interconnecting the solder SB. The first semiconductor package 1 can have enhanced reliability. In some embodiments, the cleaning process illustrated in FIGS. 1I and 1J can be performed prior to the reflow process, and residual residue 501 can be advantageously reduced in the reflow process. Therefore, the second solder ball SB2 can be satisfactorily connected to the first solder ball SB1, and the first semiconductor package 1 can have significantly enhanced reliability.

FIG. 2A is a plan view illustrating a first package, according to an exemplary embodiment. 2B through 2G are cross-sectional views for explaining a method of fabricating a semiconductor package, according to an exemplary embodiment. 2B to 2E correspond to a cross-sectional view taken along line III-III' shown in Fig. 1A. The same contents as those described above will not be described again below.

Referring to FIGS. 2A and 2B, an interconnect substrate 200, a first semiconductor wafer 400, and a first polymer layer 500 may be provided on the carrier substrate 100. The description provided with reference to FIGS. 1B through 1D can also be applied to form the interconnect substrate 200, the first semiconductor wafer 400, and the first polymer layer 500. A plurality of second pads 240 may be disposed on the top surface 200a of the interconnect substrate 200, and the plurality of second pads 240 may be electrically connected to the vias 223. A first polymer layer 500 may be formed on the interconnect substrate 200 and the first semiconductor wafer 400.

An interconnect via 900 can be formed in the first polymer layer 500. The interconnect via 900 can be disposed on the second pad 240 and connected to the second pad 240. For example, each of the second pads 240 can be connected to a corresponding interconnect via 900 in the interconnect via 900. The interconnect via 900 can comprise copper, nickel, aluminum, gold, silver, stainless steel, or alloys thereof. Interconnect via window 900 can have a melting point of about 1100 °C. In some embodiments, interconnect via 900 can have a melting point greater than about 450 °C.

An interconnect pattern 910 and a plurality of solder pads 300' may be formed on the first polymer layer 500. The interconnect pattern 910 may extend along a top surface of the first polymer layer 500 and be electrically connected to the interconnect via 900 and the solder pad 300 ′. The solder pad 300 ′ can be electrically connected to the interconnect via 900 by the interconnect pattern 910 . At least one of the solder pads 300' may not be aligned with the conductive member 220 to which it is connected in the third direction D3. The bottom surface 200b of the interconnect substrate 200 may be parallel to the first direction D1 and the second direction D2 that may perpendicularly intersect each other. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. A solder pad 300' may be formed on the first semiconductor wafer 400 and on the interconnect substrate 200. Since the interconnection pattern 910 is provided, the solder pad 300' may have an increased degree of arrangement freedom. For example, the provision of interconnect patterns 910 may allow for various arrangements of solder pads 300' to be achieved. Solder pad 300' and interconnect pattern 910 may comprise copper, nickel, aluminum, gold, silver, stainless steel, or alloys thereof. Solder pad 300' and interconnect pattern 910 each may have a melting point of about 1000 °C. In some embodiments, solder pad 300' and interconnect pattern 910 can each have a melting point above about 450 °C.

The first solder balls SB1 may be provided in plurality (ie, a plurality of first solder balls SB1). A first solder ball SB1 may be formed on the solder pad 300'. The first solder ball SB1 can be formed by a process substantially the same as that described in connection with FIG. 1B. The first solder ball SB1 may have the same melting point and material as the melting point and material of the embodiment described in FIG. 1B. The first solder ball SB1 may be electrically connected to the solder pad 300'. For example, each of the first solder balls SB1 can be electrically connected to a corresponding one of the solder pads 300'. The first solder ball SB1 may be formed on the first semiconductor wafer 400 and on the interconnect substrate 200.

Referring to FIGS. 2A and 2C, a second polymer layer 510 may be formed on the first polymer layer 500, and the second polymer layer 510 may cover the first solder balls SB1 and the interconnect pattern 910. The second polymer layer 510 can comprise an insulating polymer such as, for example, an epoxy based polymer. The second polymer layer 510 may be a molded layer, but the second polymer layer 510 may not be limited thereto. Thereafter, the carrier substrate 100 and the carrier paste layer 110 may be removed to expose the bottom surface of the first semiconductor substrate 400 and the bottom surface 200b of the interconnect substrate 200.

Referring to FIGS. 2A and 2D, an insulating pattern 610 and a redistribution member 621 and a redistribution member 622 may be formed on the bottom surface of the first semiconductor substrate 400 and the bottom surface 200b of the interconnect substrate 200, thereby forming the first substrate 600. In some embodiments, a protective layer 630 may be formed on the bottom surface of the first substrate 600. Alternatively, in other embodiments, the protective layer 630 may not be formed.

Referring to FIGS. 2A and 2E and FIGS. 1G and 1H, a drilling process (eg, laser drilling) may be performed to form a plurality of openings 550' in the second polymer layer 510. The opening 550' may expose the first solder balls SB1, respectively. For example, each of the openings 550' may expose a portion of a corresponding one of the first solder balls SB1. When the second polymer 510 is removed, a residue 501' of the second polymer layer 510 may be formed on the first solder ball SB1. The first solder ball SB1 may be melted by heat generated from the drilling process, and the residue 501' may flow into the first solder ball SB1 to form polymer particles 502'. After the drilling process, a portion of the residue 501' may remain on the first solder ball SB1. The external terminal 650 may be formed on the bottom surface of the first substrate 600, and thus the first package 11 may be fabricated.

Referring to FIGS. 2A and 2F and FIG. 1J, the residue 501' may be removed by performing a cleaning process on the first solder ball SB1. In this step, the oxide layer 700 of FIG. 1H of the first solder ball SB1 may be removed together with the residue 501'. A portion of the residue 501' may not be removed but remains on the first solder ball SB1.

Referring to FIGS. 2A and 2G, the second package 21 may be disposed on the first package 11 to align the second solder ball SB2 with the first solder ball SB1. Since the first solder ball SB1 is disposed on the first semiconductor wafer 400, the second solder ball SB2 and the circuit pattern (not shown) in the second substrate 800 may have an increased degree of arrangement freedom.

In some embodiments, bumps 812 can be provided to mount the second semiconductor wafer 810 on the second substrate 800 in a flip-chip manner. Alternatively, in other embodiments, the second semiconductor wafer 810 can be bonded directly to the second substrate 800. For example, the bumps 812 can be omitted such that the wafer pads 813 of the second semiconductor wafer 810 can contact the pads 803 disposed on the top surface of the second substrate 800. The third semiconductor wafer 815 can be stacked on the second semiconductor wafer 810, and the third semiconductor wafer 815 can be electrically connected to the second substrate 800 by the vias 814 formed in the second semiconductor wafer 810. The number, arrangement, and mounting method of semiconductor wafer 810 and semiconductor wafer 815 can be varied in a variety of ways.

Referring to FIGS. 2A and 2H, a reflow process may be performed to couple the second solder ball SB2 to the first solder ball SB1 such that a plurality of interconnect solder SBs may be formed. Although the residue 501' shown in FIG. 2F partially remains on the first solder ball SB1, the residue 501' may flow into the interconnect solder SB in the reflow process, and thus the interconnect solder SB as described in connection with FIG. 1N. Polymer particles 502' may be formed therein. Since the polymer particles 502' are dispersed in the interconnecting solder SB, the polymer particles 502' may not deteriorate the electrical characteristics of the semiconductor package 2.

FIG. 3A is a plan view illustrating a first package, according to an exemplary embodiment. Fig. 3B is a cross-sectional view taken along line IV-IV' shown in Fig. 3A.

Referring to FIGS. 3A and 3B , the first package 12 may include a first substrate 600 , a first semiconductor wafer 400 , a first polymer layer 500 , a solder pad 300 , and a first solder ball SB1 . The first package 12 may further include an interconnect substrate 201 having structural features different from those of the interconnect substrate 200 described with reference to FIGS. 1A and 1F. The interconnect substrate 201 will be discussed in detail later. The explanations made with reference to FIGS. 1B through 1F may also be substantially equally applicable to forming the first substrate 600, the first semiconductor wafer 400, the solder pad 300, and the first solder ball SB1.

The interconnect substrate 201 may be provided in plurality (for example, a plurality of interconnect substrates 201). As shown in FIG. 3A, the interconnect substrate 201 may surround the first semiconductor wafer 400. As shown in FIG. 3B, each of the interconnect substrates 201 may include a base layer 210 and a conductive member 220. Unlike the interconnect substrate 200 described in connection with FIGS. 1A and 1F, in some embodiments, the base layer 210 can be configured as a single (eg, one base layer 210), and the line pattern 222 can be omitted. The via 223 can penetrate the base layer 210 and can contact the first pad 221 and the solder pad 300, respectively. For example, each of the vias 223 may directly contact a corresponding one of the first pads 221 of the first pads 221 and a corresponding one of the solder pads 300.

Polymer particles 502 may be formed in the first solder ball SB1. As described in FIG. 1H, polymer particles 502 can be the residue of first polymer layer 500 that is formed when opening 550 is formed. Polymer particles 502 can comprise the same material as first polymer layer 500. In some embodiments, residue 501 can remain on solder ball SB1. Alternatively, in other embodiments, residue 501 may be left.

FIG. 3C is a cross-sectional view illustrating a semiconductor package in accordance with an exemplary embodiment. The same contents as those described above will not be described again below.

Referring to FIG. 3C, the semiconductor package 3 can be fabricated by mounting the second package 20 on the first package 12 shown in FIGS. 3A and 3B. The second package 20 can be mounted on the first package 12 by substantially the same method as described in connection with FIGS. 1K and 1N. For example, a reflow process can be performed to couple or bond the second solder ball SB2 to the first solder ball SB1 such that the interconnect solder SB can be formed. Before the second package 20 is mounted on the first package 12, a cleaning process may be performed on the first solder balls SB1 to remove the residue 501.

According to certain embodiments disclosed, a first solder ball may be formed prior to forming an opening in the polymer layer. Since the melting point of the first solder ball is low, the residue of the polymer layer may flow into the first solder ball when the opening is formed, so that polymer particles may be formed. The residue of the polymer layer can be further flowed into the first solder ball or interconnect solder during the reflow process. The polymer particles can be dispersed in the first solder ball. Thus, the polymer particles can have minimal impact on the electrical properties of the first solder ball or interconnect solder. A cleaning process can be performed on the first solder balls to effectively remove residues of the polymer layer. Semiconductors can therefore have enhanced reliability.

Although the inventive concept has been described in connection with the embodiments illustrated in the drawings, the inventive concept is not limited thereto. It will be appreciated by those skilled in the art that various substitutions, modifications, and variations can be made without departing from the scope and spirit of the invention.

1‧‧‧First semiconductor package
2, 3‧‧‧ semiconductor package
10, 11, 12‧‧‧ First package
20, 21‧‧‧ Second package
100‧‧‧ Carrier substrate
110‧‧‧Carrier layer
150‧‧‧ mask pattern
151‧‧‧Mask opening
200, 201‧‧‧ interconnection substrate
200a‧‧‧ top surface
200b‧‧‧ bottom surface
210‧‧‧Basic layer
220‧‧‧Electrical components
221‧‧‧First pad
222‧‧‧ line pattern
223‧‧‧ via window
240‧‧‧second pad
290‧‧‧ hole
300, 300'‧‧‧ solder pads
400‧‧‧First semiconductor wafer/semiconductor wafer
410, 813‧‧‧ wafer pad
500‧‧‧First polymer layer/polymer layer
501‧‧‧Residues
502, 502'‧‧‧ polymer particles
510‧‧‧Second polymer layer
550, 550' ‧ ‧ openings
600‧‧‧First substrate
610‧‧‧Insulation pattern
621‧‧‧Rewiring members/conductive patterns
622‧‧‧Rewiring members/conductive vias
630‧‧ ‧ protective layer
631‧‧‧ Lower opening
650‧‧‧External terminals
700‧‧‧Oxide layer
800‧‧‧second substrate
803‧‧‧ pads
810‧‧‧Second semiconductor wafer
811‧‧‧ bonding line
812‧‧‧Bumps
814‧‧‧Perforation
815‧‧‧ Third semiconductor wafer
820‧‧‧Molded layer
900‧‧‧Interconnected vias
910‧‧‧Interconnection pattern
D1‧‧‧ first direction
D2‧‧‧ second direction
D3‧‧‧ third direction
Lines I-I', III-III', IV-IV'‧‧
Section II‧‧‧
SB‧‧‧Interconnect Solder
SB1‧‧‧First solder ball/solder ball
SB2‧‧‧second solder ball

FIG. 1A is a plan view illustrating a package in accordance with an exemplary embodiment. 1B to 1F, FIG. 1I, FIG. 1K, and FIG. 1M correspond to a cross-sectional view taken along line II' shown in FIG. 1A, and are cross-sectional views for explaining a method of fabricating a semiconductor package in accordance with an exemplary embodiment. . 1G and 1H are cross-sectional views corresponding to an enlarged cross-sectional view of a portion II shown in FIG. 1F, illustrating a forming procedure of an opening according to an exemplary embodiment. Fig. 1J is a cross-sectional view corresponding to an enlarged cross-sectional view of a portion II shown in Fig. 1I, illustrating a forming procedure of an opening according to an exemplary embodiment. Fig. 1L is a cross-sectional view corresponding to an enlarged cross-sectional view of a portion II shown in Fig. 1K, illustrating a forming procedure of an opening according to an exemplary embodiment. 1N is a cross-sectional view corresponding to an enlarged view of a portion II shown in FIG. 1M, illustrating a forming procedure of an opening according to an exemplary embodiment. FIG. 2A is a plan view illustrating a first package, according to an exemplary embodiment. 2B through 2H are cross-sectional views for explaining a method of fabricating a semiconductor package, according to an exemplary embodiment. FIG. 3A is a plan view illustrating a package in accordance with an exemplary embodiment. Fig. 3B is a cross-sectional view taken along line IV-IV' shown in Fig. 3A. FIG. 3C is a cross-sectional view illustrating a semiconductor package in accordance with an exemplary embodiment.

3‧‧‧Semiconductor package

12‧‧‧ First package

20‧‧‧ Second package

201‧‧‧Interconnect substrate

210‧‧‧Basic layer

220‧‧‧Electrical components

221‧‧‧First pad

223‧‧‧ via window

300‧‧‧ solder pads

400‧‧‧First semiconductor wafer/semiconductor wafer

500‧‧‧First polymer layer/polymer layer

502‧‧‧ polymer particles

600‧‧‧First substrate

610‧‧‧Insulation pattern

621‧‧‧Rewiring members/conductive patterns

622‧‧‧Rewiring members/conductive vias

630‧‧ ‧ protective layer

650‧‧‧External terminals

800‧‧‧second substrate

810‧‧‧Second semiconductor wafer

811‧‧‧ bonding line

820‧‧‧Molded layer

D1‧‧‧ first direction

D3‧‧‧ third direction

SB‧‧‧Interconnect Solder

Claims (20)

A method of fabricating a semiconductor package, the method comprising: providing an interconnect substrate on a carrier substrate; forming a first solder ball on the interconnect substrate; providing a semiconductor wafer on the carrier substrate, the semiconductor wafer and Interconnecting substrates are spaced apart; forming a polymer layer on the interconnect substrate and the semiconductor wafer, the polymer layer covering the first solder ball; and forming an opening in the polymer layer to expose The first solder ball is taken out. The method of claim 1, further comprising: forming a solder pad on the interconnect substrate, wherein the first solder ball is disposed on the solder pad and contacts the solder pad, and wherein the The melting point of the first solder ball is lower than the melting point of the solder pad. The method of claim 1, further comprising: forming polymer particles in the first solder ball, wherein the polymer particles comprise the same material as the polymer layer. The method of claim 3, wherein the polymer particles are formed when the opening is formed. The method of claim 1, wherein forming the opening comprises: removing a portion of the polymer layer by laser drilling. The method of claim 1, further comprising: providing a second package, the second package including a second solder ball on a bottom surface thereof; and the first solder ball and the second solder The ball is reflowed. The method of claim 6, wherein when the opening is formed, a residue of the polymer layer remains on the first solder ball, wherein the method further comprises using a soldering liquid pair The first solder ball performs a cleaning process to remove the residue of the polymer layer prior to the reflow. The method of claim 1, wherein the providing the interconnect substrate comprises: providing a base layer and a conductive member located in the base layer, wherein the first solder ball is electrically connected to the Conductive member. The method of claim 1, further comprising: removing the carrier substrate to expose a bottom surface of the semiconductor wafer and a bottom surface of the interconnect substrate; and at the semiconductor wafer A rewiring substrate is formed on the bottom surface and the bottom surface of the interconnect substrate. A semiconductor package comprising: a substrate; a semiconductor wafer disposed on the substrate; an interconnect substrate spaced apart from the semiconductor wafer on the substrate, the interconnect substrate comprising a conductive member; a solder ball disposed on the substrate The interconnect substrate is electrically connected to the conductive member; a polymer layer disposed on the interconnect substrate and the semiconductor wafer, the polymer layer including an opening through which the solder ball passes And exposing; and polymer particles formed in the solder ball and comprising the same material as the polymer layer, wherein at least some of the polymer particles are formed in a top half of the solder ball. The semiconductor package of claim 10, further comprising: a solder pad disposed between the interconnect substrate and the solder ball, wherein a melting point of the solder ball is lower than a melting point of the solder pad. The semiconductor package of claim 10, further comprising: a residue formed on the solder ball, wherein the residue comprises the same material as the polymer layer. The semiconductor package of claim 10, wherein the polymer layer is disposed in a gap between the semiconductor wafer and the interconnect substrate. The semiconductor package of claim 10, wherein the interconnect substrate comprises a hole penetrating the inside of the interconnect substrate, and the semiconductor wafer is disposed in the hole of the interconnect substrate. The semiconductor package of claim 10, wherein the solder ball has a melting point lower than a melting point of the conductive member. A method of fabricating a semiconductor package, the method comprising: providing an interconnect substrate on a carrier substrate; forming a solder pad on the interconnect substrate; forming a first solder bump on the solder pad; on the carrier substrate Providing a semiconductor wafer spaced apart from the interconnect substrate; forming a polymer layer on the interconnect substrate and the semiconductor wafer, the polymer layer covering the first solder bump; and An opening is formed in the polymer layer to expose a portion of the first solder bump, wherein the first solder bump is disposed on the solder pad and contacts the solder pad. The method of claim 16, further comprising: forming polymer particles in the first solder bump, wherein the polymer particles comprise the same material as the polymer layer. The method of claim 16, further comprising: providing a second package, the second package including a second solder bump on a bottom surface thereof; and by opposing the first solder bump The second solder bump is reflowed to form a reflow soldering solder. The method of claim 18, further comprising: performing a cleaning process on the first solder bump to remove the remaining solder bumps when forming the reflow solder solder Residues of the polymer layer on the first solder bump. The method of claim 16, wherein the providing the interconnect substrate comprises: providing a base layer comprising a conductive member, wherein the first solder bump is electrically connected to the conductive member.