TW201737423A - 半導體封裝裝置 - Google Patents
半導體封裝裝置 Download PDFInfo
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- TW201737423A TW201737423A TW106102394A TW106102394A TW201737423A TW 201737423 A TW201737423 A TW 201737423A TW 106102394 A TW106102394 A TW 106102394A TW 106102394 A TW106102394 A TW 106102394A TW 201737423 A TW201737423 A TW 201737423A
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- die pad
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- 239000004065 semiconductor Substances 0.000 title description 44
- 239000000463 material Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000001427 coherent effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Abstract
電子裝置包含:一載體及複數個電子組件。該載體包含一引線框架及一封裝體。該載體具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁。該載體具有一圓形空腔,其自該載體之該開放之上表面朝該封閉之下表面延伸。該載體包含該引線框架,其具有一晶粒銲墊及複數個引線。該等引線藉由至少一間隙與該晶粒銲墊實體上隔離。該封裝體部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露。該等引線所暴露之部分係沿著該晶粒銲墊徑向配置。複數個電子組件係置於該晶粒銲墊上。
Description
本發明係關於一種半導體封裝裝置,且更確切地說,係關於一種具有發光組件之半導體封裝裝置。
發光二極體(LED)或雷射二極體係廣泛地用於各種應用中。半導體發光裝置可包含一LED晶片,其具有一或多個半導體層。當該半導體層受激發時,其可經組態以發射同調及/或非同調之光線。在製造過程中,大量的LED半導體晶粒可被製造於半導體晶圓上,該晶圓可藉由探測或測試以精確地識別各晶粒之特定顏色特徵(如色溫)。接著,可將該晶圓切割成複數個晶片。該等LED晶片通常被封裝以提供:外部電連接、散熱、透鏡或導光件、環境保護及/或其他特徵。製造LED晶片封裝之方法包含如晶粒貼合、打線、模封、測試及其他製程。 部分LED控制電路係用於產生恆定的直流電,並控制一串給定數目之LED。若欲個別地控制每個LED,則需要大面積之電路板以實施更複雜之電路。在部分情況下,可使用具有大量引線之引線框架作為電連接。 此外,在部分發光裝置中,多個LED及控制器單獨地封裝,接著安裝在一主機板上,其會增加製造成本及發光裝置之總面積。
根據本發明之部分實施例,電子裝置包含:一載體及複數個電子組件。該載體包含一引線框架及一封裝體。該載體具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁。該載體具有一圓形空腔,其自該載體之該開放之上表面朝該封閉之下表面延伸。該載體包含該引線框架,其具有一晶粒銲墊及複數個引線。該等引線藉由至少一間隙與該晶粒銲墊實體上隔離。該封裝體部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露。該等引線所暴露之部分係沿著該晶粒銲墊徑向配置。複數個電子組件係置於該晶粒銲墊上。 根據本發明之部分實施例,一載體包含一引線框架及封裝體。該引線框架具有一晶粒銲墊及複數個引線。該等引線藉由至少一間隙與該晶粒銲墊實體上隔離。該封裝體部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露。該封裝體具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁。該封裝體具有一圓形空腔,其自該開放之上表面朝該封閉之下表面延伸。該等引線所暴露之部分係沿著該晶粒銲墊徑向配置。 根據本發明之部分實施例,一電子模組包含:一第一載體。該第一載體具有複數個置於其上之封裝。各封裝包含一第二載體。一外罩覆蓋該等封裝。該第二載體具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁。該第二載體具有一圓形空腔,其自該第二載體之該開放之上表面朝該封閉之下表面延伸。該第二載體包含一引線框架、一封裝體及複數個電子組件。該引線框架具有一晶粒銲墊及複數個引線。該等引線藉由至少一間隙與該晶粒銲墊實體上隔離。該封裝體部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露。該等引線所暴露之部分係沿著該晶粒銲墊徑向配置。複數個電子組件係置於該晶粒銲墊上。
圖1A說明根據本發明之部分實施例之半導體封裝裝置1之透視圖。半導體封裝裝置1包括載體及複數個電子組件13、14。 載體10具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁。該載體10具有或定義一圓形空腔10a,其自該載體10之開放之上表面朝封閉之下表面延伸。如圖1A所示,該載體10包含引線框架12及封裝體11。 該引線框架12為預鑄模之引線框架,其具有一晶粒銲墊12a及複數個引線12b。該引線框架12可由銅、銅合金或其他合適之材料或合金組成。在部分實施例中,該引線框架12可包含下列之一或下列之組合:鐵/鐵合金、鎳/鎳合金或其他金屬/金屬合金。在部分實施例中,該引線框架12塗覆銀層。 該晶粒銲墊12a具有第一區域12a1及第二區域12a2。在部分實施例中,該晶粒銲墊之第一區域12a1實質上為弧形或圓形。舉例而言,該晶粒銲墊12a之第一區域12a1可為圓形、橢圓形或其他弧形。在部分實施例中,該晶粒銲墊12a之第一區域12a1可為圓形、橢圓形或其他弧形之一部分。在部分實施例中,該晶粒銲墊12a為散熱墊(如具有承受熱能之合適材料),其可承受由置於其上之電子組件13、14所產生之熱能。 該等引線12b沿著晶粒銲墊12a成徑向(或輻射狀)配置。例如,該等引線12b配置之方向係自晶粒銲墊12a之中心朝向晶粒銲墊12a之外邊緣。該等引線12b與該晶粒銲墊12a分離。亦即,該等引線12b與該晶粒銲墊12a之間具有至少一間隙。在部分實施例中,該至少一間隙由該封裝體11所填滿。在部分實施例中,該晶粒銲墊12a之邊緣與各引線12b之端點或至少兩個引線之端點之間的距離實質上相同。在部分實施例中,該間隙之寬度約為0.15微米(μm)至0.2 μm。在部分實施例中,該晶粒銲墊12a之邊緣與各引線12b之端點共形(conformal)。在部分實施例中,該引線框架12具有13個引線。在其他實施例中,該引線框架12可根據半導體封裝裝置之需求選擇任何數目之引線。 封裝體11置於該引線框架12上,並覆蓋一部分之引線框架12。例如:該封裝體11覆蓋該晶粒銲墊12a之第二區域12a2之一部分及各引線12b之一部分。在部分實施例中,該封裝體11包含環氧樹脂,其具有填充物(filler)散布其中。 該封裝體11具有圓形空腔10a,其自該封裝體11之上表面延伸至該封裝體11之下表面。該空腔10a暴露一部分之晶粒銲墊12a及一部分之引線12b。該空腔10a之側壁11a可由包含反射性材質的材料所組成。在部分實施例中,該空腔10a之側壁11a可作為反射面。由於電子組件13及電子組件14係整合至一單一半導體封裝裝置1,其需要使該半導體封裝裝置微小化。封裝體11之形狀有助於減小半導體封裝裝置1之總尺寸。舉例而言,封裝體11可具有凹槽11r以容納更多組件或暴露更多引線。在部分實施例中,該凹槽11r形成於封裝體11之側壁中。 電子組件13(包含13a、13b、13c)係置於該晶粒銲墊12a之第二區域12a2上。在部分實施例中,電子組件13a、13b、13c為LED。LED 13a、13b、13c可安置為彼此互相鄰近。在部分實施例中(例如用於三原色(RGB)裝置中),LED 13a、13b、13c可分別為紅光LED、綠光LED及藍光LED(如:發射紅色可見光頻譜、綠色可見光頻譜及藍色可見光頻譜),且可安置為彼此互相鄰近以增強混色以避免盲區(blind zone)出現。 電子組件14置於該晶粒銲墊12a之第一區域12a1上。在部分實施例中,該電子組件14為控制器。該電子組件14可為或可包含積體電路(IC)。該電子組件14可為具有通用處理器(general purpose processor)、微處理器、微控制器或其他可程式化組件(如現場可程式化邏輯閘陣列(Field Programmable Gate Array, FPGA)或其他如特殊應用積體電路(Application-specific integrated circuit, ASIC)之控制器)。 電子組件14藉由導線15與LED 13a、13b、13c電連接,並經組態以透過至少一導線15控制LED 13a、13b、13c。在部分實施例中,電子組件14可藉由其他導線15與引線12b連接。相較於直接將LED 13a、13b、13c與引線12b連接,先將LED 13a、13b、13c與電子組件14連接再將電子組件與引線12b連接可降低導線之長度。如此可避免導線15之短路。此外,使用較短長度之導線15亦可降低製造成本。 為了個別地或集體地控制LED,載體或將具有或呈載複雜的電路,如此將需要大量的引線以用於地連接。在部分實施例中,載體具有空腔,其會限制引線之數目及佈局,且因引線與電子組件之連接銲墊間的距離不同,其亦會阻礙電子組件及引線之間導線之結合。圖1揭示一圓形空腔10a,其中引線12b與圓形晶粒銲墊12a之邊緣共形,如此有助於增加適用於該半導體封裝裝置1之引線之數目。此外,由於各引線12b暴露於該封裝體11外之形狀及尺寸實質上相同,其可簡化電子組件14與引線之間的導線之連接,藉此可降低製造成本及時間。 圖1B說明根據本發明之部分實施例之半導體封裝裝置1之下視圖。如圖1B所示,一部分之晶粒銲墊12a及一部分之引線12b被該封裝體11所覆蓋。該晶粒銲墊12a及引線12b所暴露之部分實質上與該封裝體11之下表面共平面。 圖1C說明根據本發明之部分實施例之半導體封裝裝置1之示意圖。如圖1C所示,各引線12具有被該封裝體11所包覆或覆蓋之第一部分及暴露於該封裝體11外之第二部分。 各引線12之寬度在朝著該晶粒銲墊12a之方向上減少。即使各引線12之總長度可能不同,但各引線12之第二部分之長度實質上相同。在部分實施例中,由於各引線12之長度不同,故可於第一部分12b1及第二部分12b2之間形成斷差12b3,俾使各引線12所暴露部分(如第二部分12b2)之長度相同。 圖2說明根據本發明之部分實施例之半導體封裝裝置2之示意圖。該半導體封裝裝置2與圖1C所示之半導體封裝裝置1相似,除了在半導體封裝裝置2中,各引線所暴露部分之長度並不完全相同。例如,引線22b1所暴露部分之長度小於引線22b2所暴露部分之長度。在部分實施例中,部分引線(如引線22b3)會被封裝體11完全包覆或覆蓋。因此,各引線與晶粒銲墊12a間的距離並非完全相同,其將增加電子組件14與引線間導線連接之困難度。相較之下,由於圖1C中各引線12b暴露於該封裝體11外之形狀及尺寸實質上相同,其可簡化電子組件14與引線12b之間的導線之連接,藉此可降低製造成本及時間。 圖3說明根據本發明之部分實施例之半導體封裝裝置3之示意圖。除了以下差異,該半導體封裝裝置3與圖1C所示之半導體封裝裝置1相似:在半導體封裝裝置3中,各引線所暴露部分之長度並不完全相同;載體30具有矩形空腔30a自其開放之上表面朝封閉之下表面延伸;及晶粒銲墊32a為矩形。該矩形之空腔30a會限制引線之數目及佈局,且由於各導線與電子組件之連接銲墊間的距離不同,其亦將妨礙電子組件與引線間之導線之連接。相較之下,藉由使用如圖1C所示之圓形空腔10a,引線12b可與圓形晶粒銲墊12a之邊緣共形,其可增加適用於該半導體封裝裝置之引線之數目。此外,如圖3所示,各引線與晶粒銲墊32a間的距離不同,其會使電子組件34與引線之間的導線連接較為困難。相較之下,如圖1C所示,由於各引線12b暴露於該封裝體11外之形狀及尺寸實質上相同,其可簡化電子組件14與引線12b之間的導線15之連接,藉此可降低製造成本及時間。 圖4說明根據本發明之部分實施例之半導體封裝裝置4之示意圖。該半導體封裝裝置4與圖1C所示之半導體封裝裝置1相似,除了在圖4中,晶粒銲墊42a之第一區域42a1與第二區域42a2 互相分離。該晶粒銲墊42a之第一區域42a1及第二區域42a2之間存在間隙。該間隙之寬度約為0.15μm至0.2 μm。 LED 13a、13b、13c係放置於該晶粒銲墊42a之第二區域42a2上。電子組件14係放置於該晶粒銲墊42a之第二區域42a1上。藉由分離晶粒銲墊42a之第一部分42a1及第二部分42a2,LED 13a、13b、13c所產生之熱能對電子組件14較不可能產生不利之影響。 圖5說明根據本發明之部分實施例之電子裝置5之上視圖。在部分實施例中,在部分實施例中,電子裝置5為可調式LED模組。如圖5所示,電子裝置5具有複數個如圖1A所示之半導體封裝裝置1。在部分實施例中,該電子裝置5具有複數個如圖2-4所示之半導體封裝裝置2、3或4,或其組合(包含與半導體封裝裝置1之組合)。在部分實施裡中,該電子裝置5可具有任何數目之半導體封裝裝置。 如本文中所使用,術語「實質上」、「實質的」、「大約」及「約」用以描述及考慮小變化。當與事件或情形結合使用時,該等術語可以指其中事件或情形明確發生之情況以及其中事件或情形極近似於發生之情況。舉例而言,該等術語可以指小於或等於±10%,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%。術語「實質上共平面」可指兩表面沿著同一平面具有微米以內之差異,如40μm內、30μm內、20μm內、10μm內或1μm內。當術語「實質上」、「大約」、「約」用於一事件或情況時,其可指該事件或該情況準確地發生,亦可指該事件或該情況接近一近似值。 在部分實施例之敘述中,一組件位於另一組件之「上」可包含該組件直接位於另一組件之上(如實體接觸),亦可指該組件與另一組件之間具有其他組件。 另外,有時在本文中按範圍格式呈現量、比率及其他數值。應理解,此範圍格式係出於便利及簡潔起見,且應靈活地理解,不僅包含明確地指定為範圍限制之數值,而且包含涵蓋於彼範圍內之所有個別數值或子範圍,如同明確地指定每一數值及子範圍一般。 雖然已參考本發明之特定實施例描述及說明本發明,但這些描述及說明並不限制本發明。熟習此項技術者應理解,在不脫離如由所附申請專利範圍界定之本發明之真實精神及範疇的情況下,可作出各種改變且可取代等效物。該等說明可未必按比例繪製。歸因於製造製程及容限,本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明之本發明之其他實施例。應將本說明書及圖式視為說明性的而非限制性的。可作出修改,以使特定情況、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此等修改意欲在所附申請專利範圍之範疇內。雖然本文中所揭示之方法已參考按特定次序執行之特定操作加以描述,但應理解,可在不脫離本發明之教示的情況下組合、細分或重新排序這些操作以形成等效方法。因此,除非本文中特別指示,否則操作之次序及分組並非本發明之限制。
1‧‧‧半導體封裝裝置
10‧‧‧載體
10a‧‧‧空腔
11‧‧‧封裝體
11a‧‧‧側壁
11r‧‧‧凹槽
12‧‧‧引線框架
12a‧‧‧晶粒銲墊
12a1‧‧‧第一區域
12a2‧‧‧第二區域
12b3‧‧‧斷差
12b‧‧‧引線
13‧‧‧電子組件
13a‧‧‧發光二極體
13b‧‧‧發光二極體
13c‧‧‧發光二極體
14‧‧‧電子組件
15‧‧‧導線
2‧‧‧半導體封裝裝置
22b1‧‧‧引線
22b2‧‧‧引線
22b3‧‧‧引線
3‧‧‧半導體封裝裝置
30‧‧‧載體
30a‧‧‧空腔
32a‧‧‧晶粒銲墊
34‧‧‧電子組件
4‧‧‧半導體封裝裝置
42a‧‧‧晶粒銲墊
42a1‧‧‧第一區域
42a2‧‧‧第二區域
5‧‧‧電子裝置
10‧‧‧載體
10a‧‧‧空腔
11‧‧‧封裝體
11a‧‧‧側壁
11r‧‧‧凹槽
12‧‧‧引線框架
12a‧‧‧晶粒銲墊
12a1‧‧‧第一區域
12a2‧‧‧第二區域
12b3‧‧‧斷差
12b‧‧‧引線
13‧‧‧電子組件
13a‧‧‧發光二極體
13b‧‧‧發光二極體
13c‧‧‧發光二極體
14‧‧‧電子組件
15‧‧‧導線
2‧‧‧半導體封裝裝置
22b1‧‧‧引線
22b2‧‧‧引線
22b3‧‧‧引線
3‧‧‧半導體封裝裝置
30‧‧‧載體
30a‧‧‧空腔
32a‧‧‧晶粒銲墊
34‧‧‧電子組件
4‧‧‧半導體封裝裝置
42a‧‧‧晶粒銲墊
42a1‧‧‧第一區域
42a2‧‧‧第二區域
5‧‧‧電子裝置
圖1A說明根據本發明之部分實施例之半導體封裝裝置之透視圖。 圖1B說明根據本發明之部分實施例之半導體封裝裝置之下視圖。 圖1C說明根據本發明之部分實施例之半導體封裝裝置之示意圖。 圖2說明根據本發明之部分實施例之半導體封裝裝置之上視圖。 圖3說明根據本發明之部分實施例之半導體封裝裝置之上視圖。 圖4說明根據本發明之部分實施例之半導體封裝裝置之示意圖。 圖5說明根據本發明之部分實施例之電子裝置之上視圖。 貫穿圖式及詳細描述使用共同參考數字以指示相同或類似元件。自以下結合附圖作出之詳細描述,本發明將會更顯而易見。
1‧‧‧半導體封裝裝置
10‧‧‧載體
10a‧‧‧空腔
11‧‧‧封裝體
11a‧‧‧側壁
11r‧‧‧凹槽
12‧‧‧引線框架
12a‧‧‧晶粒銲墊
12a1‧‧‧第一區域
12a2‧‧‧第二區域
12b‧‧‧引線
13‧‧‧電子組件
13a‧‧‧發光二極體
13b‧‧‧發光二極體
13c‧‧‧發光二極體
14‧‧‧電子組件
15‧‧‧導線
Claims (27)
- 一種電子裝置,其包含: 一載體,其具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁,該載體具有一圓形空腔,其自該載體之該開放之上表面朝該封閉之下表面延伸,該載體包含: 一引線框架(leadframe),其具有一晶粒銲墊及複數個引線,該等引線藉由至少一間隙與該晶粒銲墊實體上隔離; 一封裝體,其部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露,其中該等引線所暴露之部分係沿著該晶粒銲墊徑向配置;及 複數個電子組件,其置於該晶粒銲墊上。
- 如請求項1之電子裝置,其中該至少一間隙被該封裝體所填滿。
- 如請求項1之電子裝置,其中該晶粒銲墊之邊緣與各引線之一端點共形(conformal)。
- 如請求項3之電子裝置,其中該晶粒銲墊之邊緣與各引線之該端點之間的距離實質上相同。
- 如請求項3之電子裝置,其中該晶粒銲墊之邊緣為弧形。
- 如請求項3之電子裝置,其中該至少一間隙之寬度約為0.15微米(μm)至0.2 μm。
- 如請求項1之電子裝置,其中該晶粒銲墊進一步包含一第一電子組件置於其上之一中央部分及一第二電子組件置於其上之一邊緣部分。
- 如請求項7之電子裝置,其中該中央部分與該邊緣部分藉由該晶粒銲墊之一間隙實體上互相隔離。
- 如請求項7之電子裝置,其中該第一電子組件為一控制器且該第二電子組件為一發射器。
- 如請求項1之電子裝置,其中該載體之該圓形空腔之側壁包含一反射性材料。
- 一載體,其包含: 一引線框架,其具有一晶粒銲墊及複數個引線,該等引線藉由至少一間隙與該晶粒銲墊實體上隔離; 一封裝體,其部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露,該封裝體具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁,該封裝體具有一圓形空腔,其自該封裝體之該開放之上表面朝該封閉之下表面延伸,該等引線所暴露之部分係沿著該晶粒銲墊徑向配置。
- 如請求項11之載體,其中該至少一間隙被該封裝體所填滿。
- 如請求項11之載體,其中該晶粒銲墊之邊緣與各引線之一端點共形。
- 如請求項13之載體,其中該晶粒銲墊之邊緣與各引線之該端點之間的距離實質上相同。
- 如請求項13之載體,其中該晶粒銲墊之邊緣為弧形。
- 如請求項11之載體,其中該至少一間隙之寬度約為0.15μm至0.2 μm。
- 如請求項11之載體,其中該封裝體之該圓形空腔之側壁包含一反射性材料。
- 一第一載體,其具有複數個封裝置於其上,各封裝包含: 一第二載體,其具有一開放之上表面、一封閉之下表面及在該開放之上表面與該封閉之下表面之間延伸之側壁,該第二載體具有一圓形空腔,其自該載體之該開放之上表面朝該封閉之下表面延伸,該第二載體包含: 一引線框架,其具有一晶粒銲墊及複數個引線,該等引線藉由至少一間隙與該晶粒銲墊實體上隔離; 一封裝體,其部分地包覆該引線框架,俾使該晶粒銲墊之一上表面之一部分及各引線之一部分自該封裝體暴露,其中該等引線所暴露之部分係沿著該晶粒銲墊徑向配置;及 複數個電子組件,其置於該晶粒銲墊上;及 一外罩,其覆蓋該等封裝。
- 如請求項18之電子模組,其中該至少一間隙被該封裝體所填滿。
- 如請求項18之電子模組,其中該晶粒銲墊之邊緣與各引線之一端點共形。
- 如請求項20之電子模組,其中該晶粒銲墊之邊緣與各引線之該端點之間的距離實質上相同。
- 如請求項20之電子模組,其中該晶粒銲墊之邊緣為弧形。
- 如請求項18之電子模組,其中該至少一間隙之寬度約為0.15微米μm至0.2 μm。
- 如請求項18之電子模組,其中該晶粒銲墊進一步包含一第一電子組件置於其上之一中央部分及一第二電子組件置於其上之一邊緣部分。
- 如請求項24之電子模組,其中該中央部分與該邊緣部分藉由該晶粒銲墊之一間隙實體上互相隔離。
- 如請求項24之電子模組,其中該第一電子組件為一控制器且該第二電子組件為一發射器。
- 如請求項18之電子模組,其中該第二載體之該圓形空腔之側壁包含一反射性材料。
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