TW201733137A - Power diode device - Google Patents

Power diode device Download PDF

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TW201733137A
TW201733137A TW105107768A TW105107768A TW201733137A TW 201733137 A TW201733137 A TW 201733137A TW 105107768 A TW105107768 A TW 105107768A TW 105107768 A TW105107768 A TW 105107768A TW 201733137 A TW201733137 A TW 201733137A
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layer
electric field
power diode
surface electric
isolation structure
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TW105107768A
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TWI583004B (en
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羅梓源
曾清秋
許志維
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敦南科技股份有限公司
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Abstract

A power diode device is provided. The power diode device includes a substrate, an epitaxial layer, a RESURF layer, a highly-doped contact region, and an isolation structure. The epitaxial layer disposed on the substrate has the same conductivity type as the substrate. The RESURF layer disposed on the epitaxial layer and having a top surface defines an active region. The highly-doped contact region having the same conductivity type as the RESURF layer is formed in the active region of the RESURF region and exposed at the top surface. The isolation structure is formed in the RESURF layer and surrounds the active region. A continuous PN junction among the RESURF layer, the epitaxial layer, and the isolation structure is formed.

Description

功率二極體元件 Power diode component

本發明是關於一種半導體元件,且特別是關於一種用於整流的功率二極體元件。 The present invention relates to a semiconductor component, and more particularly to a power diode component for rectification.

功率二極體為一用途相當廣泛的電子元件,亦為構成電子電路之重要成分。一個良好的功率二極體須具備有低導通電壓、高切換速度及高崩潰電壓等特性。 A power diode is a widely used electronic component and an important component of an electronic circuit. A good power diode must have low turn-on voltage, high switching speed, and high breakdown voltage.

請參照圖1,顯示習知的功率二極體的剖面示意圖。習知的功率二極體元件1包括基材10、半絕緣層11、玻璃鈍化層12以及電極層13。具體而言,基材10內分別具有一p型摻雜區101與n型摻雜區102,以在基材10內形成PN接面,其中p型摻雜區101會暴露於基材10的頂面。電極層13位於基材10的頂面上,以電性接觸p型摻雜區101。 Referring to Figure 1, a schematic cross-sectional view of a conventional power diode is shown. A conventional power diode element 1 includes a substrate 10, a semi-insulating layer 11, a glass passivation layer 12, and an electrode layer 13. Specifically, the substrate 10 has a p-type doping region 101 and an n-type doping region 102 respectively to form a PN junction in the substrate 10, wherein the p-type doping region 101 is exposed to the substrate 10 Top surface. The electrode layer 13 is located on the top surface of the substrate 10 to electrically contact the p-type doping region 101.

此外,基材10的側邊會被局部地蝕刻,而使基材10的上半部形成一平台(mesa),並使PN接面裸露於平台的兩側表面。半絕緣層11覆蓋於平台的兩側表面上,以保護PN接面。另外,玻璃鈍化層12覆蓋於半絕緣層11上。 In addition, the sides of the substrate 10 are partially etched such that the upper portion of the substrate 10 forms a mesa and the PN junctions are exposed to both side surfaces of the platform. A semi-insulating layer 11 covers both side surfaces of the platform to protect the PN junction. In addition, a glass passivation layer 12 is overlaid on the semi-insulating layer 11.

由於上述的功率二極體1會經過蝕刻製程,以形成立體結構,但在蝕刻製程中,蝕刻液對基材10不同位置的蝕刻速率不一定能夠完全保持一致,從而使得在平台的側表面的梯度也無法被精確控制。然而平台的側表面的梯度會影響功率二極體1的崩潰電壓,也因此造成所測得的崩潰電壓不如預期。此外,在通過黃光微影製程形成半絕緣層11與玻璃鈍化層12以及電極層13時,對位的精準度也會受到影響。 Since the power diode 1 described above is subjected to an etching process to form a three-dimensional structure, in the etching process, the etching rate of the etching liquid to different positions of the substrate 10 may not be completely uniform, thereby making the side surface of the platform Gradient cannot be precisely controlled. However, the gradient of the side surface of the platform affects the breakdown voltage of the power diode 1, and thus the measured breakdown voltage is not as expected. In addition, when the semi-insulating layer 11 and the glass passivation layer 12 and the electrode layer 13 are formed by the yellow lithography process, the alignment accuracy is also affected.

接著,請參照圖2,顯示習知技術另一功率二極體的剖面示意圖。另一習知的功率二極體2包括基材20、保護層21、上電極層22與下電極層23。上電極層22與下電極層23分別位於基材20的上表面及下表面上。 Next, referring to FIG. 2, a schematic cross-sectional view of another power diode of the prior art is shown. Another conventional power diode 2 includes a substrate 20, a protective layer 21, an upper electrode layer 22, and a lower electrode layer 23. The upper electrode layer 22 and the lower electrode layer 23 are respectively located on the upper surface and the lower surface of the substrate 20.

另外,基材20內具有用於和下電極層23形成歐姆接觸的n型重摻雜區201、和上電極層22形成歐姆接觸的p型重摻雜區203以及位於n型重摻雜區201與p型重摻雜區203之間的n型輕摻雜區202。當功率二極體2被施加逆向偏壓時,為了使電場橫向延展,以增加功率二極體2的崩潰電壓,在p型重摻雜區203的周圍具有多條環型的p型摻雜區,以形成多個防護環(guard ring)204。 In addition, the substrate 20 has an n-type heavily doped region 201 for forming an ohmic contact with the lower electrode layer 23, a p-type heavily doped region 203 for forming an ohmic contact with the upper electrode layer 22, and an n-type heavily doped region. An n-type lightly doped region 202 between the 201 and the p-type heavily doped region 203. When the power diode 2 is applied with a reverse bias, in order to laterally extend the electric field to increase the breakdown voltage of the power diode 2, there are a plurality of ring-shaped p-type dopings around the p-type heavily doped region 203. Zones to form a plurality of guard rings 204.

然而,想要提高功率二極體2的崩潰電壓,需增加防護環的數量。因此,防護環所占的面積比例也會增加,這會不利於元件體積縮小化。此外,由於防護環通常具有較窄的線寬,在利用黃光微影以及蝕刻等線寬製程製備防護環時,製程潔淨度以及線寬製程限制皆容易影響功率二極體2的良率。 However, in order to increase the breakdown voltage of the power diode 2, it is necessary to increase the number of guard rings. Therefore, the proportion of the area occupied by the guard ring also increases, which is disadvantageous for the size reduction of the component. In addition, since the guard ring usually has a narrow line width, when the guard ring is prepared by a line width process such as yellow lithography and etching, the process cleanliness and the line width process limitation easily affect the yield of the power diode 2.

據此,開發一種製程簡易,又可具有較大崩潰電壓的功率二極體,仍為本領域的技術人員致力於研究的目標。 Accordingly, the development of a power diode with a simple process and a large breakdown voltage is still a goal of research by those skilled in the art.

本發明提供一種功率二極體元件,通過降低表面電場層來降低功率二極體元件的表面電場,從而可提高功率二極體元件的崩潰電壓。 The invention provides a power diode element, which reduces the surface electric field of the power diode element by reducing the surface electric field layer, thereby improving the breakdown voltage of the power diode element.

本發明其中一實施例提供一種功率二極體元件,其包括基底、磊晶層、降低表面電場層、重摻雜接觸區以及隔離結構。磊晶層位於基底上,並具有和基底相同的導電型。降低表面電場層位於磊晶層上,並具有一頂面,其中所述降低表面電場層定義出一主動區。重摻雜接觸區形成於降低表面電場層的主動區內,並暴露於頂面,其中重摻雜接觸區和所述降低表面電場層具有相同的導電型。隔離結構形成於降 低表面電場層內並環繞主動區,其中降低表面電場層與磊晶層及隔離結構之間形成一連續的PN接面。 One embodiment of the present invention provides a power diode component including a substrate, an epitaxial layer, a reduced surface electric field layer, a heavily doped contact region, and an isolation structure. The epitaxial layer is on the substrate and has the same conductivity type as the substrate. The reduced surface electric field layer is located on the epitaxial layer and has a top surface, wherein the reduced surface electric field layer defines an active region. The heavily doped contact region is formed in the active region of the reduced surface electric field layer and exposed to the top surface, wherein the heavily doped contact region and the reduced surface electric field layer have the same conductivity type. Isolation structure formed in the lower The low surface electric field layer surrounds the active region, wherein a reduced PN junction is formed between the surface electric field layer and the epitaxial layer and the isolation structure.

綜上所述,本發明所提供的功率二極體元件,通過設置降低表面電場層,使功率二極體元件的耐壓控制可由降低表面電場層的厚度來決定。除此之外,降低表面電場層、磊晶層以及隔離結構之間形成PN接面,當功率二極體元件被施加逆向偏壓時,可使表面電場橫向延伸,從而提高功率二極體元件的崩潰電壓。另外,由於本發明所提供的功率二極體元件不需要設置防護環,也不具有立體結構,因此相較於習知技術,本發明實施例的功率二極體元件的製程較為簡易,且容易控制。 In summary, the power diode element provided by the present invention can reduce the surface electric field layer so that the withstand voltage control of the power diode element can be determined by reducing the thickness of the surface electric field layer. In addition, the PN junction is formed between the surface electric field layer, the epitaxial layer and the isolation structure, and when the power diode element is reversely biased, the surface electric field can be laterally extended, thereby improving the power diode component. The breakdown voltage. In addition, since the power diode element provided by the present invention does not need to be provided with a guard ring and does not have a three-dimensional structure, the power diode device of the embodiment of the present invention is simpler and easier to manufacture than the prior art. control.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.

1、2‧‧‧習知功率二極體 1, 2‧‧‧Learning power diodes

10、20‧‧‧基材 10, 20‧‧‧ substrate

101‧‧‧p型摻雜區 101‧‧‧p-doped region

102‧‧‧n型摻雜區 102‧‧‧n-doped region

11‧‧‧半絕緣層 11‧‧‧Semi-insulating layer

12‧‧‧玻璃鈍化層 12‧‧‧ glass passivation layer

13‧‧‧電極層 13‧‧‧Electrode layer

21‧‧‧保護層 21‧‧‧Protective layer

22‧‧‧上電極層 22‧‧‧Upper electrode layer

23‧‧‧下電極層 23‧‧‧ lower electrode layer

201‧‧‧n型重摻雜區 201‧‧‧n type heavily doped area

203‧‧‧p型重摻雜區 203‧‧‧p type heavily doped area

202‧‧‧n型輕摻雜區 202‧‧‧n type lightly doped area

204‧‧‧防護環 204‧‧‧ guard ring

3‧‧‧功率二極體元件 3‧‧‧Power diode components

30‧‧‧基底 30‧‧‧Base

30a‧‧‧上表面 30a‧‧‧ upper surface

30b‧‧‧背面 30b‧‧‧back

31‧‧‧磊晶層 31‧‧‧Elevation layer

32‧‧‧降低表面電場層 32‧‧‧Reducing the surface electric field layer

321‧‧‧頂面 321‧‧‧ top surface

AR‧‧‧主動區 AR‧‧‧Active Area

33‧‧‧重摻雜接觸區 33‧‧‧ heavily doped contact area

34‧‧‧隔離結構 34‧‧‧Isolation structure

35‧‧‧鈍化層 35‧‧‧ Passivation layer

36‧‧‧正電極層 36‧‧‧ positive electrode layer

37‧‧‧背電極層 37‧‧‧Back electrode layer

S1‧‧‧第一PN接面 S1‧‧‧ first PN junction

S2‧‧‧第二PN接面 S2‧‧‧ second PN junction

351‧‧‧電中性絕緣層 351‧‧‧Electrical neutral insulation

352‧‧‧硬質保護層 352‧‧‧hard protective layer

D‧‧‧預定距離 D‧‧‧Predetermined distance

DR‧‧‧空乏區 DR‧‧‧ Vacant Zone

P1、P2‧‧‧峰值 Peak P1, P2‧‧‧

L1~L4‧‧‧位置 L1~L4‧‧‧ position

圖1 繪示習知的功率二極體的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional power diode.

圖2 繪示習知的另一功率二極體的剖面示意圖。 2 is a schematic cross-sectional view of another conventional power diode.

圖3 繪示本發明實施例的功率二極體元件的俯視示意圖。 3 is a top plan view of a power diode component in accordance with an embodiment of the present invention.

圖4 繪示圖3中的功率二極體元件沿線IV-IV的剖面示意圖。 4 is a cross-sectional view of the power diode component of FIG. 3 taken along line IV-IV.

圖5 繪示圖4中的功率二極體元件的局部放大圖。 FIG. 5 is a partial enlarged view of the power diode element of FIG. 4.

圖6 繪示圖5中的功率二極體元件沿線X-X的電場強度曲線圖。 FIG. 6 is a graph showing electric field intensity along the line X-X of the power diode element of FIG. 5.

圖7 繪示圖5中的功率二極體元件沿線Y-Y的電場強度曲線圖。 FIG. 7 is a graph showing the electric field intensity along the line Y-Y of the power diode element of FIG. 5.

請參照圖3及圖4。圖3繪示本發明實施例的功率二極體元件的俯視示意圖,而圖4繪示圖3中的功率二極體元件沿線IV-IV的剖面示意圖。 Please refer to FIG. 3 and FIG. 4. 3 is a schematic top view of a power diode component according to an embodiment of the invention, and FIG. 4 is a cross-sectional view of the power diode component of FIG. 3 taken along line IV-IV.

本發明實施例的功率二極體元件3包括基底30、磊晶層31、降低表面電場層32、重摻雜接觸區33、隔離結構34、鈍化層35、正電極層36以及背電極層37。 The power diode element 3 of the embodiment of the present invention includes a substrate 30, an epitaxial layer 31, a reduced surface electric field layer 32, a heavily doped contact region 33, an isolation structure 34, a passivation layer 35, a positive electrode layer 36, and a back electrode layer 37. .

在本實施例中,基底30為半導體材料,可以是矽(Si)、氮化 鎵(GaN)、砷化鎵(GaAs)、氮化鋁(AlN)、碳化矽(SiC)、磷化銦(InP)、硒化鋅(ZnSe)或其他VI族、III-V族或II-VI族半導體材料。基底30並具有高濃度的第一型導電性雜質,可以是N型或P型導電性雜質。假設基底30為矽基底,N型導電性雜質為五價元素離子,例如磷離子或砷離子,而P型導電性雜質為三價元素離子,例如硼離子、鋁離子或鎵離子。 In this embodiment, the substrate 30 is a semiconductor material, which may be germanium (Si) or nitrided. Gallium (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), tantalum carbide (SiC), indium phosphide (InP), zinc selenide (ZnSe) or other Group VI, III-V or II- Group VI semiconductor materials. The substrate 30 has a high concentration of the first type of conductive impurities and may be an N-type or P-type conductive impurity. It is assumed that the substrate 30 is a germanium substrate, the N-type conductive impurities are pentavalent element ions such as phosphorus ions or arsenic ions, and the P-type conductive impurities are trivalent element ions such as boron ions, aluminum ions or gallium ions.

另外,基底30具有上表面30a及與上表面30a相對的背面30b。磊晶層(epitaxial layer)31位於基底30的上表面30a上,並具有低濃度的第一型導電性雜質。在本實施例中,基底30為高濃度的N型摻雜(N+),而磊晶層31則為低濃度的N型摻雜(N-)。 Further, the substrate 30 has an upper surface 30a and a back surface 30b opposed to the upper surface 30a. An epitaxial layer 31 is located on the upper surface 30a of the substrate 30 and has a low concentration of first type conductivity impurities. In the present embodiment, the substrate 30 is a high concentration of N-type doping (N+), and the epitaxial layer 31 is a low concentration of N-type doping (N-).

基底30的背面30b則電性接觸背電極層37。在本實施例中,具有N型摻雜的基底30的阻值範圍小於0.01ohm.cm,以和背電極層37之間形成歐姆接觸。並且,當基底30為N型摻雜時,背電極層37是陰極電極層,並電性連接至外部控制電路。 The back surface 30b of the substrate 30 is in electrical contact with the back electrode layer 37. In this embodiment, the substrate 30 having the N-type doping has a resistance range of less than 0.01 ohm. Cm to form an ohmic contact with the back electrode layer 37. Also, when the substrate 30 is N-type doped, the back electrode layer 37 is a cathode electrode layer and is electrically connected to an external control circuit.

降低表面電場層32位於磊晶層31上,並具有和磊晶層31相反的導電型。在本實施例中,磊晶層31具有低濃度的N型摻雜區,則降低表面電場層32具有低濃度的P型摻雜區。在一實例中,降低表面電場層32即為P型磊晶層。因此,降低表面電場層32與磊晶層31之間會形成第一PN接面S1。 The reduced surface electric field layer 32 is located on the epitaxial layer 31 and has a conductivity type opposite to that of the epitaxial layer 31. In the present embodiment, the epitaxial layer 31 has a low concentration of the N-type doped region, and the surface electric field layer 32 is lowered to have a low concentration of the P-type doped region. In one example, the reduced surface electric field layer 32 is a P-type epitaxial layer. Therefore, the first PN junction S1 is formed between the surface electric field layer 32 and the epitaxial layer 31.

須說明的是,磊晶層31以及降低表面電場層32的厚度以及摻雜濃度會影響功率二極體元件3的崩潰電壓,因此,磊晶層31以及降低表面電場層32的厚度以及摻雜濃度,可根據預設的崩潰電壓來調整。 It should be noted that the thickness of the epitaxial layer 31 and the reduced surface electric field layer 32 and the doping concentration affect the breakdown voltage of the power diode element 3, and therefore, the thickness of the epitaxial layer 31 and the surface electric field reducing layer 32 and the doping. The concentration can be adjusted according to the preset breakdown voltage.

在本發明實施例中,預設崩潰電壓為200V至1000V,則磊晶層31的厚度是介於10至65μm之間,電阻值介於5至25ohm.cm之間。另外,降低表面電場層32的厚度是介於10至45μm之間,電阻值介於15至75ohm.cm之間。須說明的是,通常降低表面電場層32的厚度與磊晶層31的厚度大致相同。在一實施例中,降低表面電場層32的厚度與磊晶層31的厚度差值小於10μm。 In the embodiment of the present invention, the preset breakdown voltage is 200V to 1000V, and the thickness of the epitaxial layer 31 is between 10 and 65 μm, and the resistance value is between 5 and 25 ohms. Between cm. In addition, the thickness of the surface electric field reducing layer 32 is between 10 and 45 μm, and the resistance value is between 15 and 75 ohms. Between cm. It should be noted that the thickness of the surface electric field layer 32 is generally reduced to be substantially the same as the thickness of the epitaxial layer 31. In one embodiment, the difference between the thickness of the reduced surface electric field layer 32 and the thickness of the epitaxial layer 31 is less than 10 [mu]m.

另外,降低表面電場層32具有一頂面321,並定義出一主動區AR。重摻雜接觸區33形成於降低表面電場層32的主動區AR內,並暴露於頂面321上。詳細而言,重摻雜接觸區33具有和降低表面電場層32具有相同的導電型,但重摻雜接觸區33的摻雜濃度是大於降低表面電場層32的摻雜濃度。另外,重摻雜接觸區33的深度小於降低表面電場層32的厚度。 In addition, the reduced surface electric field layer 32 has a top surface 321 and defines an active area AR. The heavily doped contact region 33 is formed in the active region AR of the reduced surface electric field layer 32 and is exposed on the top surface 321. In detail, the heavily doped contact region 33 has the same conductivity type as the reduced surface electric field layer 32, but the doping concentration of the heavily doped contact region 33 is greater than the doping concentration of the reduced surface electric field layer 32. Additionally, the depth of the heavily doped contact region 33 is less than the thickness of the reduced surface electric field layer 32.

如此,當功率二極體元件3被施加逆向偏壓時,空乏區DR的範圍可盡可能地被侷限在降低表面電場層32內,並可避免重摻雜接觸區33內的載子被耗盡。 Thus, when the power diode element 3 is applied with a reverse bias, the range of the depletion region DR can be confined as much as possible within the reduced surface electric field layer 32, and the carrier in the heavily doped contact region 33 can be avoided. Do it.

請參照圖3,由俯視圖中可以看出,隔離結構34形成於降低表面電場層32內,並環繞主動區AR。另外,如圖4中所示,隔離結構34由降低表面電場層32的頂面321向下延伸至磊晶層31內。 Referring to FIG. 3, it can be seen from the top view that the isolation structure 34 is formed in the reduced surface electric field layer 32 and surrounds the active area AR. Additionally, as shown in FIG. 4, the isolation structure 34 extends downwardly from the top surface 321 of the reduced surface electric field layer 32 into the epitaxial layer 31.

詳細而言,隔離結構34是通過離子佈植或是熱擴散製程而形成於降低表面電場層32內的一隔離摻雜區,且隔離摻雜區具有和磊晶層31相同的導電型,而和降低表面電場層32具有相反的導電型。因此,降低表面電場層32與隔離結構34之間形成一第二PN接面S2。 In detail, the isolation structure 34 is formed by an ion implantation or a thermal diffusion process in an isolated doped region in the reduced surface electric field layer 32, and the isolation doped region has the same conductivity type as the epitaxial layer 31, and The reduced surface electric field layer 32 has an opposite conductivity type. Therefore, a second PN junction S2 is formed between the reduced surface electric field layer 32 and the isolation structure 34.

另外,隔離結構34的擴散深度會大於降低表面電場層32的厚度,而使隔離結構34延伸至磊晶層31內。因此,前述降低表面電場層32與磊晶層31之間所形成的第一PN接面S1,和降低表面電場層32與隔離結構34之間所形成的第二PN接面S2會相互連接。也就是說,降低表面電場層32、磊晶層31與隔離結構34之間會形成一連續的PN接面。 In addition, the diffusion depth of the isolation structure 34 may be greater than the thickness of the surface electric field layer 32, and the isolation structure 34 is extended into the epitaxial layer 31. Therefore, the first PN junction S1 formed between the surface electric field reducing layer 32 and the epitaxial layer 31 and the second PN junction S2 formed between the surface electric field layer 32 and the isolation structure 34 are connected to each other. That is to say, a continuous PN junction is formed between the surface electric field layer 32, the epitaxial layer 31 and the isolation structure 34.

在本發明實施例中,隔離結構34的濃度會大於降低表面電場層32的摻雜濃度。在本實施例中,隔離結構34的摻雜濃度大於1019cm-3。除此之外,隔離結構34和重摻雜接觸區33之間相互分隔一預定距離D。須說明的是,前述隔離結構34和重摻雜接觸區33之間的預定距離D若太小,無法有效達到舒緩表面電場的效果,而有可能使功率二極體元件3在接近表面(也就是頂面321)的地方被擊穿,也無法有效提高 功率二極體元件3的崩潰電壓。 In an embodiment of the invention, the concentration of the isolation structure 34 may be greater than the reduction of the doping concentration of the surface electric field layer 32. In the present embodiment, the doping concentration of the isolation structure 34 is greater than 10 19 cm -3 . In addition to this, the isolation structure 34 and the heavily doped contact regions 33 are separated from each other by a predetermined distance D. It should be noted that if the predetermined distance D between the foregoing isolation structure 34 and the heavily doped contact region 33 is too small, the effect of soothing the surface electric field cannot be effectively achieved, and it is possible to make the power diode element 3 close to the surface (also It is the place where the top surface 321) is broken, and the breakdown voltage of the power diode element 3 cannot be effectively improved.

因此,隔離結構34和重摻雜接觸區33之間的預定距離D可根據功率二極體元件3的崩潰電壓來設計。當所需承受的崩潰電壓越高,預定距離D需要越大。在一實施例中,預定距離D至少大於降低表面電場層32的厚度以及磊晶層31的厚度總和。在一實施例中,若預設崩潰電壓為200V至1000V,則磊晶層31與降低表面電場層32的總厚度可介於20至105μm之間。 Therefore, the predetermined distance D between the isolation structure 34 and the heavily doped contact region 33 can be designed according to the breakdown voltage of the power diode element 3. The higher the breakdown voltage that is required to withstand, the greater the predetermined distance D needs to be. In an embodiment, the predetermined distance D is at least greater than the sum of the thickness of the reduced surface electric field layer 32 and the thickness of the epitaxial layer 31. In an embodiment, if the preset breakdown voltage is 200V to 1000V, the total thickness of the epitaxial layer 31 and the reduced surface electric field layer 32 may be between 20 and 105 μm.

在一實施例中,當崩潰電壓為200V時,磊晶層31與降低表面電場層32的總厚度介於20至40μm之間,而當崩潰電壓為1000V時,磊晶層31與降低表面電場層32的總厚度是介於85至105μm之間。預定距離D即可根據所預設的崩潰電壓值,以及磊晶層31與降低表面電場層32的總厚度來調整。 In one embodiment, when the breakdown voltage is 200V, the total thickness of the epitaxial layer 31 and the reduced surface electric field layer 32 is between 20 and 40 μm, and when the breakdown voltage is 1000 V, the epitaxial layer 31 and the surface electric field are lowered. The total thickness of layer 32 is between 85 and 105 μm. The predetermined distance D can be adjusted according to the preset breakdown voltage value and the total thickness of the epitaxial layer 31 and the reduced surface electric field layer 32.

請參照圖3與圖4,鈍化層35形成於降低表面電場層32的頂面321上,覆蓋暴露於頂面321的第二PN接面S2。另外,鈍化層35具有一連接於重摻雜接觸區33的開口350。鈍化層35覆蓋暴露於頂面321的第二PN接面S2,並通過開口350暴露出位於主動區AR的重摻雜接觸區33。如圖3所示,鈍化層35是圍繞主動區AR周圍而覆蓋於降低表面電場層32的頂面321上。 Referring to FIGS. 3 and 4, a passivation layer 35 is formed on the top surface 321 of the reduced surface electric field layer 32 to cover the second PN junction S2 exposed to the top surface 321. Additionally, passivation layer 35 has an opening 350 that is coupled to heavily doped contact region 33. The passivation layer 35 covers the second PN junction S2 exposed to the top surface 321 and exposes the heavily doped contact region 33 located in the active region AR through the opening 350. As shown in FIG. 3, the passivation layer 35 is over the top surface 321 of the reduced surface electric field layer 32 around the active area AR.

詳細而言,鈍化層35具有依序堆疊於頂面321上的電中性絕緣層351以及硬質保護層352。電中性絕緣層351例如是硼磷矽玻璃(BPSG)或半絕緣性多晶矽膜(SIPOS),可避免電子(electron)或電洞(hole)累積於功率二極體元件3的表面,並可避免當功率二極體元件3被施加偏壓時,累積的電子或電洞產生漏電流,而影響功率二極體元件3的電性表現。硬質保護層352例如是氮化物等較緻密的絕緣層,可用以隔絕水氣或汙染。 In detail, the passivation layer 35 has an electrically neutral insulating layer 351 and a hard protective layer 352 which are sequentially stacked on the top surface 321 . The electrically neutral insulating layer 351 is, for example, a borophosphorus bismuth glass (BPSG) or a semi-insulating polycrystalline germanium film (SIPOS), which prevents electrons or holes from accumulating on the surface of the power diode element 3, and It is avoided that when the power diode element 3 is biased, the accumulated electrons or holes generate leakage current, which affects the electrical performance of the power diode element 3. The hard protective layer 352 is, for example, a dense insulating layer such as nitride, which can be used to insulate moisture or contamination.

另外,正電極層36設置於降低表面電場層32的頂面321,並通過鈍化層35的開口電性接觸重摻雜接觸區33。在本實施例中,正電極層36可與重摻雜接觸區33形成歐姆接觸,並作為功率二極體元件 3的陽極,以連接至外部的控制電路。 In addition, the positive electrode layer 36 is disposed on the top surface 321 of the surface electric field reducing layer 32, and electrically contacts the heavily doped contact region 33 through the opening of the passivation layer 35. In this embodiment, the positive electrode layer 36 can form an ohmic contact with the heavily doped contact region 33 and function as a power diode component. The anode of 3 is connected to an external control circuit.

請參照圖5,圖5繪示圖4中的功率二極體元件的局部放大圖。當功率二極體元件3被施加逆向偏壓時,在降低表面電場層32、磊晶層31以及隔離結構34之間形成空乏區DR。值得說明的是,由於隔離結構34含有高濃度摻雜的第一導電型雜質,而降低表面電場層32含有低濃度摻雜的第二導電型雜質,因此可使降低表面電場層32內的載子完全被耗盡(depleted),而使空乏區DR可被橫向擴展至重摻雜接觸區33。在靠近功率二極體元件3表面所形成的空乏區DR可舒緩電場分布,從而增加功率二極體元件3的崩潰電壓。 Please refer to FIG. 5. FIG. 5 is a partial enlarged view of the power diode component of FIG. 4. When the power diode element 3 is reversely biased, a depletion region DR is formed between the reduced surface electric field layer 32, the epitaxial layer 31, and the isolation structure 34. It should be noted that since the isolation structure 34 contains a high concentration doped first conductivity type impurity and the surface electric field reduction layer 32 contains a low concentration doped second conductivity type impurity, the load in the surface electric field layer 32 can be reduced. The sub-depletion is completely depleted, and the depletion region DR can be laterally extended to the heavily doped contact region 33. The depletion region DR formed near the surface of the power diode element 3 can relieve the electric field distribution, thereby increasing the breakdown voltage of the power diode element 3.

請先參照圖6及圖7。圖6繪示圖5中的功率二極體元件沿線X的電場強度曲線圖,圖7則繪示圖5中的功率二極體元件沿線Y的電場強度曲線圖。圖6與圖7是對本發明實施例的功率二極體元件施加逆向偏壓750V的條件下,所模擬出的電場分布圖。 Please refer to FIG. 6 and FIG. 7 first. 6 is a graph showing the electric field intensity along the line X of the power diode element of FIG. 5, and FIG. 7 is a graph showing the electric field intensity along the line Y of the power diode element of FIG. 5. 6 and 7 are diagrams showing the electric field distribution simulated under the condition that a reverse bias voltage of 750 V is applied to the power diode element of the embodiment of the present invention.

圖6的位置L1是對應於圖5的L1的位置,位置L2是對應於圖5的L2的位置。相似地,圖7的位置L3是對應於圖5的L3的位置,位置L4是對應於圖5的L4的位置。 The position L1 of Fig. 6 corresponds to the position of L1 of Fig. 5, and the position L2 is the position corresponding to L2 of Fig. 5. Similarly, the position L3 of FIG. 7 is the position corresponding to L3 of FIG. 5, and the position L4 is the position corresponding to L4 of FIG.

由圖6中可以看出,降低表面電場層32可舒緩原本集中於隔離結構34與重摻雜接觸區33的電場。在圖6中,電場強度的最大值P1為1.6×105牛頓/庫倫。請參照圖7,在圖7中顯示電場強度的最大值P2為2.3×105牛頓/庫倫,且電場強度最大值P2的位置是對應於第一PN接面S1的位置。也就是說,當繼續施加更大的逆向偏壓至功率二極體元件3時,崩潰區域會大致上位於磊晶層31與降低表面電場層32之間所形成的第一PN接面S1,而不會位於功率二極體元件3的表層。 As can be seen in FIG. 6, the reduced surface electric field layer 32 can relieve the electric field originally concentrated on the isolation structure 34 and the heavily doped contact region 33. In Fig. 6, the maximum value P1 of the electric field strength is 1.6 × 10 5 Newtons / Coulomb. Referring to FIG. 7, the maximum value P2 of the electric field intensity is shown in FIG. 7 to be 2.3×10 5 Newtons/Coulomb, and the position of the electric field intensity maximum value P2 is the position corresponding to the first PN junction S1. That is, when a larger reverse bias is continuously applied to the power diode element 3, the collapsed region will be substantially located at the first PN junction S1 formed between the epitaxial layer 31 and the reduced surface electric field layer 32, It is not located on the surface of the power diode element 3.

請參照下表1,顯示本發明實施例的功率二極體元件(實施例1及實施例2)與習知的功率二極體(比較例1、比較例2)在施加600V的逆向偏壓下的電性表現。習知的功率二極體的結構如圖1所示。 Referring to Table 1 below, the power diode elements (Embodiment 1 and Embodiment 2) of the embodiment of the present invention and the conventional power diodes (Comparative Example 1, Comparative Example 2) are applied with a reverse bias of 600 V. Electrical performance under. The structure of a conventional power diode is shown in FIG.

如表1所示,相較於比較例1、2,實施例1與實施例2可被應用在175℃的高溫下,並具有較高的單脈衝崩潰能量(EAS)。除此之外,相較於比較例1及2,實施例1及實施例2具有更小的漏電流,特別是超過125℃之後,相較於比較例1、2而言,實施例1及實施例2的漏電流的增加幅度並不大。 As shown in Table 1, Example 1 and Example 2 can be applied at a high temperature of 175 ° C and have a high single pulse collapse energy (EAS) compared to Comparative Examples 1 and 2. In addition, Example 1 and Example 2 have smaller leakage currents than Comparative Examples 1 and 2, and in particular, after more than 125 ° C, Example 1 and Comparative Examples 1 and 2 The increase in leakage current of Embodiment 2 is not large.

綜上所述,綜上所述,本發明所提供的功率二極體元件,在降低表面電場層、磊晶層以及隔離結構之間形成連續PN接面,當功率二極體元件被施加逆向偏壓時,可使表面電場橫向延伸,從而提高功率二極體元件的崩潰電壓。經由上述測試結果,可明顯看出本發明實施例所提供的功率二極體元件相較於習知的功率二極體而言,具有更好的電性表現。 In summary, in summary, the power diode device provided by the present invention forms a continuous PN junction between the surface electric field layer, the epitaxial layer and the isolation structure, and the power diode element is reversely applied. When biased, the surface electric field can be laterally extended to increase the breakdown voltage of the power diode component. Through the above test results, it is apparent that the power diode element provided by the embodiment of the present invention has better electrical performance than the conventional power diode.

另外,由於本發明所提供的功率二極體元件不需要設置防護環,也不具有立體結構,因此相較於習知技術,本發明實施例的功率二極 體元件的製程較為簡易,且容易控制。 In addition, since the power diode element provided by the present invention does not need to be provided with a guard ring and does not have a three-dimensional structure, the power diode of the embodiment of the present invention is compared with the prior art. The process of the body components is relatively simple and easy to control.

雖然本發明之實施例已揭露如上,然本發明並不受限於上述實施例,任何所屬技術領域中具有通常知識者,在不脫離本發明所揭露之範圍內,當可作些許之更動與調整,因此本發明之保護範圍應當以後附之申請專利範圍所界定者為準。 Although the embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and those skilled in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

3‧‧‧功率二極體元件 3‧‧‧Power diode components

30‧‧‧基底 30‧‧‧Base

30a‧‧‧上表面 30a‧‧‧ upper surface

30b‧‧‧背面 30b‧‧‧back

31‧‧‧磊晶層 31‧‧‧Elevation layer

32‧‧‧降低表面電場層 32‧‧‧Reducing the surface electric field layer

321‧‧‧頂面 321‧‧‧ top surface

AR‧‧‧主動區 AR‧‧‧Active Area

33‧‧‧重摻雜接觸區 33‧‧‧ heavily doped contact zone

34‧‧‧隔離結構 34‧‧‧Isolation structure

35‧‧‧鈍化層 35‧‧‧ Passivation layer

36‧‧‧正電極層 36‧‧‧ positive electrode layer

37‧‧‧背電極層 37‧‧‧Back electrode layer

S1‧‧‧第一PN接面 S1‧‧‧ first PN junction

S2‧‧‧第二PN接面 S2‧‧‧ second PN junction

351‧‧‧電中性絕緣層 351‧‧‧Electrical neutral insulation

352‧‧‧硬質保護層 352‧‧‧hard protective layer

D‧‧‧預定距離 D‧‧‧Predetermined distance

Claims (10)

一種功率二極體元件,包括:一基底;一磊晶層,位於所述基底上,並具有和所述基底相同的導電型;一降低表面電場層,位於所述磊晶層上,並具有一頂面,其中所述降低表面電場層定義出一主動區;一重摻雜接觸區,形成於所述降低表面電場層的所述主動區內,並暴露於所述頂面,其中所述重摻雜接觸區和所述降低表面電場層具有相同的導電型;以及一隔離結構,形成於所述降低表面電場層內並環繞所述主動區,其中所述降低表面電場層與所述磊晶層及所述隔離結構之間形成一連續的PN接面。 A power diode component comprising: a substrate; an epitaxial layer on the substrate and having the same conductivity type as the substrate; a reduced surface electric field layer on the epitaxial layer and having a top surface, wherein the reduced surface electric field layer defines an active region; a heavily doped contact region is formed in the active region of the reduced surface electric field layer and exposed to the top surface, wherein the weight The doped contact region and the reduced surface electric field layer have the same conductivity type; and an isolation structure formed in the reduced surface electric field layer and surrounding the active region, wherein the reduced surface electric field layer and the epitaxial layer A continuous PN junction is formed between the layer and the isolation structure. 如請求項1所述的功率二極體元件,更包括一設置於所述頂面上的鈍化層,其中所述鈍化層具有一連接所述重摻雜接觸區的開口。 The power diode component of claim 1, further comprising a passivation layer disposed on the top surface, wherein the passivation layer has an opening connecting the heavily doped contact regions. 如請求項2所述的功率二極體元件,更包括一設置於所述頂面上的正電極層,其中所述正電極層通過所述開口以電性接觸所述重摻雜接觸區。 The power diode component of claim 2, further comprising a positive electrode layer disposed on the top surface, wherein the positive electrode layer electrically contacts the heavily doped contact region through the opening. 如請求項2所述的功率二極體元件,其中所述鈍化層包括一位於所述頂面的電中性絕緣層及一位於所述電中性絕緣層上的硬質保護層。 The power diode component of claim 2, wherein the passivation layer comprises an electrically neutral insulating layer on the top surface and a hard protective layer on the electrically neutral insulating layer. 如請求項1所述的功率二極體元件,其中所述隔離結構為形成於所述降低表面電場層內的一隔離摻雜區,且所述隔離摻雜區的摻雜濃度大於所述降低表面電場層的摻雜濃度。 The power diode device of claim 1, wherein the isolation structure is an isolation doping region formed in the reduced surface electric field layer, and a doping concentration of the isolation doping region is greater than the reduction The doping concentration of the surface electric field layer. 如請求項1所述的功率二極體元件,其中所述隔離結構由所述頂 面延伸至所述磊晶層內。 The power diode component of claim 1, wherein the isolation structure is from the top The face extends into the epitaxial layer. 如請求項1所述的功率二極體元件,其中所述隔離結構與所述重摻雜接觸區之間相互分隔一預定距離。 The power diode component of claim 1, wherein the isolation structure and the heavily doped contact regions are separated from each other by a predetermined distance. 如請求項7所述的功率二極體元件,其中所述預定距離至少大於所述磊晶層的厚度與所述降低表面電場層的厚度的總和。 The power diode component of claim 7, wherein the predetermined distance is at least greater than a sum of a thickness of the epitaxial layer and a thickness of the reduced surface electric field layer. 如請求項1所述的功率二極體元件,更包括一背電極層,設置於所述基底的一背面上。 The power diode component of claim 1, further comprising a back electrode layer disposed on a back surface of the substrate. 如請求項1所述的功率二極體元件,其中所述重摻雜接觸區的深度小於所述降低表面電場層的厚度。 The power diode component of claim 1, wherein the heavily doped contact region has a depth less than a thickness of the reduced surface electric field layer.
TW105107768A 2016-03-14 2016-03-14 Power diode device TWI583004B (en)

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