TW201732793A - Semiconductor memory apparatus - Google Patents

Abstract

A big peak current IDDP of a refreshing semiconductor apparatus is reduced, and a sense amplifier margin of bit lines is ensured to be above a predetermined value. In the semiconductor apparatus, memory cells are respectively at each intersection of a plurality of word lines and a plurality of bit lines. The semiconductor apparatus includes sense amplifiers and sense amplifier latch circuits. The semiconductor apparatus reads data from a plurality of data lines of the plurality of memory cells. The sense amplifier latch circuits has a first transistor latching data from the plurality of data lines. The plurality of sense amplifiers of the same column lines in parallel with the plurality of word lines are divided into a plurality of sense amplifier circuit groups. The divided sense amplifier circuit group includes a second transistor. The second transistor latches a read out data according to a latch signal delaying from an active beginning of the word line of reading data.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device such as a dynamic access memory (hereinafter referred to as DRAM).

The DRAM has a volatile memory element that must be refreshed in order to maintain the data stored in the volatile memory element. Here, the DRAM renews itself with auto refresh and self refresh. The new is to activate a larger number of sense amplifiers than the usual read and write operations. Prior art literature

Patent Document 1: U.S. Patent No. 5,997,471, Patent Document 2: U.S. Patent No. 7,535,785, Patent Document 3: U.S. Patent No. 6,084,811, Patent Document 4: U.S. Patent No. 5,251,176, Patent Document 5: U.S. Patent No. 4,912,678 [Problems to be solved by the invention]

The renewed large peak current will generate unnecessary noise on the power bus of the DRAM, thereby renewing the DRAM or operating on the system side. Make an impact. In order to reduce the renewed peak current, the following two methods are known.

(Conventional Example 1) The DRAM is divided into a plurality of memory cells. (Conventional Example 2) The sense amplifier circuit of one memory cell of the DRAM is divided into a plurality of groups.

1A is a block diagram showing a configuration example of a DRAM divided into four memory cells B0 to B3 in Conventional Example 1. FIG. 1B is a timing chart showing an operation example when four memory cells B0 to B3 are simultaneously activated in the DRAM of FIG. 1A. FIG. 1C is a sequence diagram showing an operation example when each of the memory cells B0 to B3 is activated in the DRAM of FIG. 1A.

In FIG. 1A, the DRAM is divided into four memory cells B0 to B3, for example, and a sense amplifier circuit SA is connected to each of the memory cells B0 to B3. Here, WL0 to WL3 are word lines, and NS0/PS0 to NS3/PS3 are sense amplifier active signals. As shown in FIG. 1B, when four memory cells B0 to B3 are simultaneously activated in the DRAM of FIG. 1A, a large peak current IDDP flows when renewed in the power source current IDD flowing through the power supply terminal VDD. Further, in the DRAM of FIG. 1A, when each of the memory cells B0 to B3 is activated, as shown in FIG. 1C, the power source current IDD is lowered to 1/4.

However, in this case, there is a problem in that the renewed peak current IDDP of each of the memory cells B0 to B3 cannot be lowered, and as will be described later, the sensing margin of the sense amplifier cannot be sufficiently maintained.

2A is a block diagram showing a configuration example of a DRAM divided into four memory cells B0 to B3 in Conventional Example 2. FIG. 2B is a timing chart showing an operation example when four memory cells B0 to B3 are simultaneously activated in the DRAM of FIG. 2A. 2C is a timing chart showing an operation example when the sense amplifier circuit is divided into two groups in the DRAM of FIG. 2A, and each of the memory cells B0 to B3 is activated.

In the conventional example 2 of FIG. 2A, the DRAM is divided into, for example, four memory cells B0 to B3, and the sense amplifier circuit connected to each of the memory cells B0 to B3 is divided into two sense amplifier circuit groups. Group SA, SAa. In FIG. 2A, WL0 to WL3 are word lines, and NS0/PS0 to NS3/PS3 are sense amplifier enable signals for the first sense amplifier circuit group SA, and NS0a/PS0a to NS3a/PS3a are for the second sense. The sense amplifier enable signal of the amp circuit group SAa.

As is clear from FIG. 2B, in the DRAM of FIG. 2A, when four memory cells B0 to B3 are simultaneously activated, a large peak current IDDP is generated. Next, FIG. 2C shows that the sense amplifier circuit is divided into two groups, and each of the memory cells B0 to B3 is activated. In FIG. 2C, 101 indicates activation of the first sense amplifier circuit group SA for the memory cells B0 to B3, and 102 indicates activation of the second sense amplifier circuit group SAa for the memory cells B0 to B3. As is clear from FIG. 2C, although the peak current IDDP can be lowered to 1/8, there is a problem that the sensing voltage tolerance of the second sense amplifier circuit group SAa cannot be maintained sufficiently.

Fig. 3A is a circuit diagram showing a detailed configuration example of the DRAM of Fig. 2A. In FIG. 3A, the DRAM is provided with an X decoder 11, a word line driver circuit 12, a memory region including two sense amplifier circuit groups BG0 to BG1, and a sense amplifier. The control circuit 10 of the signals PS0, NS0, PS0a, and NS0a is activated. A memory cell as a volatile memory element is connected to an intersection of each of the word lines WL0 to WLn and each of the bit lines BL_0(0) to BL_m(0) and BL_0(1) to BL_m(1) (memory cell) MC.

In the sense amplifier circuit group BG0, a sense amplifier SA, a plurality of sense amplifiers SA, are connected to each of each of BL_0(0) to BL_m(0) and /BL_0(0) to /BL_m(0) Connected to the sense amplifier latch circuit SLA0 via data lines DL00, DL01. The sense amplifier latch circuit SLA0 is composed of a P channel metal oxide semiconductor (MOS) transistor Ptr0 and an N channel MOS transistor Ntr0, and the data line DL00 is via the MOS transistor Ptr0. Connected to the power supply voltage VDD, the data line DL01 is connected to the ground voltage VSS via the MOS transistor Ntr0. The sense amplifier enable signals PS0, NS0 from the control circuit 10 are applied to the gates of the MOS transistors Ptr0, Ntr0, respectively.

In the sense amplifier circuit group BG1, a sense amplifier SAa, a plurality of sense amplifiers SAa, are connected to each of each of BL_0(1) to BL_m(1) and /BL_0(1) to /BL_m(1) The sense amplifier latch circuit SLA1 is connected via the data lines DL10, DL11. The sense amplifier latch circuit SLA1 is configured to include a P-channel MOS transistor Ptr0a and an N-channel MOS transistor Ntr0a. The data line DL10 is connected to the power supply voltage VDD via the MOS transistor Ptr0a, and the data line DL11 is connected via the MOS transistor Ntr0a. At ground voltage VSS. The sense amplifier enable signals PS0a, NSOa from the control circuit 10 are applied to the respective gates of the MOS transistors Ptr0a, Ntr0a, respectively.

FIG. 3B is a timing chart showing an operation example of the memory cell B0 for explaining the first problem of the DRAM of FIGS. 2A and 3A. In FIG. 3B, one memory cell is divided into two sense amplifier circuit groups BG0 and BG1, and in the case of sequentially starting in accordance with each memory cell B0 to B3 as shown in FIG. 2C, it must be relatively small. The voltage is maintained until the voltage difference DV between the different data of the bit line voltage until the start of the next sense amplifier circuit group, but if there is a leakage current in the bit lines BL, /BL, the voltage difference DV will Further reduction becomes DVd, which may cause a new failure of the memory cell MC of the DRAM.

4 is a timing chart showing an operation example of the sense amplifier circuit groups BG0 to BG1 for explaining the second problem of the DRAM of FIGS. 2A and 3A. If the data of the bit lines BLm(0), /BLm(0) and the data of the bit lines BL0(1), /BL0(1) are inverted, for example, the bit lines BL0(1), /BL0(1) The voltage difference DV between the two is shown in Fig. 4. During the sensing of the bit lines BLm(0) and /BLm(0), the coupling from the bit lines BLm(0), /BLm(0) (coupling) The DV of the bit lines BL0(1), /BL0(1) is reduced, whereby there is a problem that the sense amplifier tolerance of the bit lines BL0(1), /BL0(1) becomes small. Further, the same problems are also caused in Patent Documents 1 to 5.

An object of the present invention is to solve the above problems and to provide a semiconductor memory device capable of reducing a large peak current IDDP when a semiconductor memory device such as a DRAM is renewed, and ensuring that a sense amplifier tolerance of a bit line is equal to or greater than a predetermined value. [Means for solving the problem]

The semiconductor memory device of the present invention has memory cells at respective intersections of a plurality of word lines and a plurality of bit lines, and has a sense amplifier for reading data from a plurality of data lines from a plurality of memory cells. And a sense amplifier latch circuit having a first transistor that latches data from a plurality of data lines, the semiconductor memory device characterized by a plurality of identical line lines parallel to the plurality of word lines The sense amplifiers are divided into a plurality of sense amplifier circuit groups, and the divided sense amplifier circuit groups further include a second transistor, and the second transistors are based on word lines when read from data. A latch signal that starts to delay is started to latch the read data.

In the semiconductor memory device, the sense amplifiers of all of the divided sense amplifier circuit groups are simultaneously activated by the shared latch signal.

Further, in the semiconductor memory device, the driving ability of the second transistor is configured to be weaker than the driving ability of the first transistor.

Further, in the semiconductor memory device, the memory region of the semiconductor memory device is divided into a plurality of memory cell groups, and a plurality of sense amplifiers of the same row line parallel to the plurality of word line lines Divided into a plurality of sense amplifier circuit groups corresponding to each of the divided memory cell groups.

Further, in the semiconductor memory device, the data reading is a renewed time of the memory cell.

Furthermore, in the semiconductor memory device, a dummy dummy bit line is formed between the divided sense amplifier circuit groups adjacent to each other. (Effect of the invention)

Therefore, according to the semiconductor memory device of the present invention, the large peak current IDDP at the time of renewing can be reduced, and the sense amplifier tolerance of the bit line can be ensured to be a predetermined value or more.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

(Embodiment 1) FIG. 5A is a block diagram showing a configuration example of a DRAM according to Embodiment 1 of the present invention. 5B is a circuit diagram showing a detailed configuration example of the DRAM of FIG. 5A. In FIGS. 5A and 5B, the DRAM of the first embodiment differs from the DRAM of FIGS. 2A and 3A in the conventional example in the following points. (1) In place of the control circuit 10, the control circuit 10A is further provided, and the control circuit 10A further generates latch signals PSA and NSA for latching data in the first predetermined short time of data sensing. Data of lines DL00, DL01, DL10, DL11. Here, the latch signals PSA, NSA are delayed by a predetermined time after the start of the word line at the time of data sensing, and the sense amplifiers in the different sense amplifier circuit groups BG0, BG1 are simultaneously activated. (2) A sense amplifier latch circuit SLA0A is provided instead of the sense amplifier latch circuit SLA0. The sense amplifier latch circuit SLA0A is provided with a P-channel MOS transistor PtrA for latching the data line DL00 based on the latch signal PSA. And the N-channel MOS transistor NtrA, which latches the data of the data line DL01 based on the latch signal NSA. (3) A sense amplifier latch circuit SLA1A is provided instead of the sense amplifier latch circuit SLA1. The sense amplifier latch circuit SLA1A is provided with a P-channel MOS transistor PtrA for latching the data line DL10 based on the latch signal PSA. And the N-channel MOS transistor NtrA, which latches the data of the data line DL11 based on the latch signal NSA.

Further, the plurality of sense amplifiers of the same row line parallel to the plurality of word line lines WL0 to WLn are divided into a plurality of sense amplifier circuit groups, for example, corresponding to each of the memory cell groups B0 to B3. Further, in FIG. 5A, only the memory cell B0 is illustrated, but the memory cells B1 to B3 are also configured in the same manner.

In FIG. 5B, the DRAM of the present embodiment includes an X decoder 11, a word line driver circuit 12, a memory region including two sense amplifier circuit groups BG0 to BG1, and a sense amplifier enable signal PS0. The control circuit 10A of NS0, PS0a, NS0a, PSA, and NSA is configured. Each of the word lines WL0 to WLn and each of the bit lines BL_0(0) to BL_m(0), /BL_0(0) to /BL_m(0), BL_0(1) to BL_m(1), /BL_0(1), At the intersection of /BL_m(1), a memory cell MC as a volatile memory element is connected.

In the sense amplifier circuit group BG0, a sense amplifier SA, a plurality of sense amplifiers SA, are connected to each of each of BL_0(0) to BL_m(0) and /BL_0(0) to /BL_m(0) It is connected to the sense amplifier latch circuit SLA0A via the data lines DL00 and DL01. The sense amplifier latch circuit SLA0A is configured to include P-channel MOS transistors Ptr0 and PtrA and N-channel MOS transistors Ntr0 and NtrA. The data line DL00 is connected to the power supply voltage VDD via the MOS transistors Ptr0 and PtrA, and the data line DL01 is connected via the data line DL01. The MOS transistors Ntr0 and NtrA are connected to the ground voltage VSS. The sense amplifier enable signals PS0, NS0 from the control circuit 10A are applied to the respective gates of the MOS transistors Ptr0, Ntr0, respectively. Further, the latch signals PSA, NSA from the control circuit 10A are applied to the respective gates of the MOS transistors PtrA, NtrA, respectively.

In the sense amplifier circuit group BG1, a sense amplifier SAa, a plurality of sense amplifiers SAa, are connected to each of each of BL_0(1) to BL_m(1) and /BL_0(1) to /BL_m(1) The sense amplifier latch circuit SLA1A is connected via the data lines DL10, DL11. The sense amplifier latch circuit SLA1A includes P-channel MOS transistors Ptr0a and PtrA and N-channel MOS transistors Ntr0a and NtrA. The data line DL10 is connected to the power supply voltage VDD via the MOS transistors Ptr0a and PtrA, and the data line DL11 is connected via the MOS transistor Ptr0a and PtrA. The MOS transistors Ntr0a and NtrA are connected to the ground voltage VSS. The sense amplifier enable signals PS0a, NSOa from the control circuit 10A are applied to the respective gates of the MOS transistors Ptr0a, Ntr0a, respectively. Further, the latch signals PSA, NSA from the control circuit 10A are applied to the respective gates of the MOS transistors PtrA, NtrA, respectively.

Further, in the MOS transistors of the sense amplifier latch circuits SLA0A and SAL1A, the driving ability of the MOS transistors PtrA and NtrA latched based on the latch signals PSA and NSA is preferably configured as compared with the conventional example. The driving ability of the MOS transistors Ptr0, Ptr0a, Ntr0, and Ntr0a is weak. Specifically, the difference in driving ability is made by making the sizes of the respective transistors different. This is because the transistors PtrA and NtrA that operate according to the latch signals PSA and NSA are auxiliary transistors, and the overall efficiency can be reduced. Consumption of electricity.

Fig. 5C is a timing chart showing an operation example of the DRAM of Fig. 5B. In the present embodiment, for example, four or four or more memory cell groups are divided, and each memory cell group is divided into two sense amplifier circuit groups. As is clear from FIG. 5C, the data of the data lines DL00 to DL11 are latched by the MOS transistors PtrA and NtrA, respectively, based on the latch signals PSA and NSA. Therefore, at the beginning of the data sensing, a known example can be obtained. The voltage difference DV between the data of the large individual lines (111, 112 of Fig. 5C), and a predetermined voltage difference DV can be maintained for sensing (113 of Fig. 5C).

As described above, according to the present embodiment, even if divided into a plurality of sense amplifier circuit groups, the re-new operation is not affected, the peak current IDDP for the re-operation can be reduced, and the bit can be secured. The sense amplifier tolerance of the line is above the specified value.

(Embodiment 2) FIG. 6A is a circuit diagram showing a detailed configuration example of a DRAM according to Embodiment 2 of the present invention. 6A is characterized in that, in the circuit of FIG. 3A of the conventional example, a dummy bit line 13 connected to the ground voltage VSS is additionally formed in a region between the adjacent sense amplifier circuit groups BG0 and BG1. The other structure is the same as that of Fig. 3A.

Fig. 6B is a timing chart showing an operation example of the DRAM of Fig. 6A. It can be clarified according to FIG. 6B that there is no coupling between the bit lines BL_m-1(0), /BL_m-1(0) and the bit lines BL_1(1), /BL_1(1) in the data sensing. Initially, a voltage difference DV between the data of the bit lines larger than the conventional example can be obtained, and a predetermined voltage difference DV can be maintained for sensing.

In the above embodiment, the dummy bit line 13 is added to the circuit of FIG. 3A of the conventional example. However, the present invention is not limited thereto, and the dummy bit line 13 may be added to the circuit of FIG. 5B of the first embodiment. . Thereby, the effects of both the first embodiment and the second embodiment are obtained.

The present invention differs from Patent Document 1 to Patent Document 5. (1) Patent Document 1 Patent Document 1 discloses that a sense amplifier is divided into a plurality of sense amplifier circuit groups, and only the divided sense amplifiers are disclosed. The circuit group is activated by the sense amplifier enable signal. However, the split sense amplifier circuit groups are not simultaneously enabled, and the dummy bit lines between the divided sense amplifier circuit groups are not disclosed.

(2) Patent Document 2 In Patent Document 2, a sense amplifier is divided into a plurality of sense amplifier circuit groups. Only each of the divided sense amplifier circuit groups is activated by the sense amplifier enable signal. However, the divided sense amplifier circuit groups are not simultaneously activated.

(3) Patent Document 3 In Patent Document 3, a sense amplifier is divided into a plurality of sense amplifier circuit groups. Among them, only the sense amplifier circuit group for reading is activated to reduce the data read current, thereby improving the read margin, but the self-renewed peak current does not change. Here, first, after one sense amplifier circuit group of the read data is activated, the remaining sense amplifier groups are simultaneously activated.

(4) Patent Document 4 Patent Document 4 has the feature that the sense amplifiers of the same row line are not divided into the same sense amplifier circuit group.

(5) Patent Document 5 Patent Document 5 has a feature that the sense amplifiers of the same row line are not divided into a plurality of sense amplifier circuit groups. [Industrial availability]

As described in detail above, according to the semiconductor memory device of the present invention, the large peak current IDDP at the time of renewing can be reduced, and the sense amplifier tolerance of the bit line can be ensured to be a predetermined value or more.

10, 10A‧‧‧ control circuit
11‧‧‧X decoder
12‧‧‧Word line driver circuit
13‧‧‧Digital bit line
101, 102‧‧‧ start
111, 112, 113‧‧‧ time points
B0～B3‧‧‧ storage unit
BG0～BG1‧‧‧Sense Amplifier Circuit Group
BL_0(0) to BL_m(0), BL_0(1) to BL_m(1), /BL_0(0) to /BL_m(0), /BL_0(1) to /BL_m(1), BL0(0), / BL0(0), BL0(1), /BL0(1), BLm(0), /BLm(0)‧‧‧ bit lines
DL00～DL11‧‧‧ data line
IDD‧‧‧Power supply current
IDDP‧‧‧ Peak current
MC‧‧‧ memory cell
NS0～NS3, NS0a～NS3a, PS0～PS3, PS0a～PS3a‧‧‧Sense amplifier start signal
NSA, PSA‧‧‧ latch signal
Ptr0, Ptr0a, Ntr0, Ntr0a, PtrA, NtrA‧‧‧MOS transistors
SA, SAa‧‧‧ sense amplifier
SLA0, SLA1, SLA0A, SLA1A‧‧‧ sense amplifier latch circuit
t‧‧‧Time
VDD‧‧‧Power terminal (power supply voltage)
VSS‧‧‧ Grounding voltage
WL0~WLn‧‧‧ character line
DV, DVd‧‧‧ voltage difference

1A is a block diagram showing a configuration example of a DRAM divided into four memory cells B0 to B3 in Conventional Example 1. FIG. 1B is a timing chart showing an operation example when four memory cells B0 to B3 are simultaneously activated in the DRAM of FIG. 1A. FIG. 1C is a sequence diagram showing an operation example when each of the memory cells B0 to B3 is activated in the DRAM of FIG. 1A. 2A is a block diagram showing a configuration example of a DRAM divided into four memory cells B0 to B3 in Conventional Example 2. FIG. 2B is a timing chart showing an operation example when four memory cells B0 to B3 are simultaneously activated in the DRAM of FIG. 2A. 2C is a timing chart showing an operation example when the sense amplifier circuit is divided into two sense amplifier circuit groups in the DRAM of FIG. 2A, and each of the memory cells B0 to B3 is activated. Fig. 3A is a circuit diagram showing a detailed configuration example of the DRAM of Fig. 2A. FIG. 3B is a timing chart showing an operation example of the memory cell B0 for explaining the first problem of the DRAM of FIGS. 2A and 3A. 4 is a timing chart showing an operation example of the sense amplifier circuit groups BG0 to BG1 for explaining the second problem of the DRAM of FIGS. 2A and 3A. FIG. 5 is a block diagram showing a configuration example of a DRAM according to Embodiment 1 of the present invention. Fig. 5B is a circuit diagram showing a detailed configuration example of the DRAM of Fig. 5A. Fig. 5C is a timing chart showing an operation example of the DRAM of Fig. 5B. Fig. 6 is a circuit diagram showing a detailed configuration example of a DRAM according to a second embodiment of the present invention. Fig. 6B is a timing chart showing an operation example of the DRAM of Fig. 6A.

111, 112, 113‧‧‧ time points

BL0(0), /BL0(0), BL0(1), /BL0(1)‧‧‧ bit lines

IDD‧‧‧Power supply current

NS0, NS0a, PS0, PS0a‧‧‧ sense amplifier start signal

NSA, PSA‧‧‧ latch signal

t‧‧‧Time

WL0‧‧‧ character line

ΔV‧‧‧voltage difference

Claims (6)

A semiconductor memory device having memory cells at respective intersections of a plurality of word lines and a plurality of bit lines, and having sensing for reading data from a plurality of data lines from the plurality of memory cells An amplifier, and a sense amplifier latch circuit having a first transistor that latches data from the plurality of data lines, the semiconductor memory device characterized by the same row line parallel to the plurality of word lines The plurality of sense amplifiers are divided into a plurality of sense amplifier circuit groups, and the divided sense amplifier circuit group further includes a second transistor, and the second transistor is based on characters when read from the data. The line starts to delay the latched signal to latch the read data. The semiconductor memory device of claim 1, wherein the sense amplifiers of all of the divided sense amplifier circuit groups are simultaneously activated by the shared latch signal. The semiconductor memory device according to claim 1 or 2, wherein the driving ability of the second transistor is weaker than the driving ability of the first transistor. The semiconductor memory device according to claim 1 or 2, wherein the memory region of the semiconductor memory device is divided into a plurality of memory cell groups, and the same row parallel to the plurality of word lines A plurality of sense amplifiers of the line are divided into a plurality of sense amplifier circuit groups corresponding to each of the divided memory cell groups. The semiconductor memory device according to claim 1 or 2, wherein the data reading is a renewed time of the memory cell. The semiconductor memory device according to claim 1 or 2, wherein a grounded dummy bit line is formed between the group of the sense amplifier circuits which are divided and adjacent to each other.