TW201730966A - Ultrahigh selective polysilicon etch with high throughput - Google Patents

Abstract

Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60 DEG C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.

Description

Ultra-high selectivity polysilicon etch with high throughput

The present disclosure generally relates to the etching of polysilicon on a wafer, and more particularly to the etching of a plasma based polycrystalline silicon on a wafer with high selectivity.

The etching of the plasma base can be an important processing step in the production of semiconductor components and integrated circuits.

Typically, the removal of polysilicon can be performed using a wet or dry reactive ion etching (RIE) process. However, the wet etch process used to remove the polysilicon may result in a low polysilicon etch rate, which results in low throughput. Furthermore, the wet etch process to remove polysilicon may not achieve the same selectivity for other materials as the dry etch process. Dry RIE processes can result in higher costs, at least in part due to the use of external biases to control the complexity of the ion direction and energy. In addition, the use of a dry RIE process can damage surrounding structures due to exposure to ion and photon flux. The surrounding structure can be a sidewall made of, for example, exposed nitride and/or oxide. Such surrounding structures may include low-k dielectric materials, tantalum nitride (Si ₃ N ₄ ), titanium nitride (TiN), and tantalum oxide (SiO ₂ ) including hot tantalum oxide.

Moreover, the presence of native oxide layers on the surface of many materials, including semiconductor wafers containing germanium and metal, can adversely affect the patterning of such materials. This may be an important part of the production of semiconductor wafers, memory components, and logic components. For example, a native oxide layer on a polysilicon can substantially inhibit and reduce the uniformity of polysilicon etch. When the cerium-containing surface is exposed to ambient conditions or oxygen, a native oxide layer may be formed.

Typically, native oxide removal can be performed using a wet process, such as treating the native oxide with dilute hydrofluoric acid (HF). However, such wet etching processes for removing native oxides can be expensive, can cause serious safety problems, may not achieve high selectivity for other materials, and may cause additional exposure to environmental conditions to allow for native oxidation. The material re-grows before etching the polysilicon. Wet processes can also be problematic for components involving high aspect ratio features.

The present disclosure relates to a method of removing a polysilicon layer from a wafer. The method includes providing a wafer having a polycrystalline germanium layer, flowing an etchant comprising a hydrogen-based species and a fluorine-based species to a remote plasma source (where the concentration of the hydrogen-based species is greater than a concentration of the fluorine-based species), at the distal plasma A remote plasma is generated in the source (where the distal plasma includes radicals of a hydrogen-based species and a fluorine-based species), and the wafer is exposed to a remote plasma to remove the polysilicon layer (where the wafer is maintained at a temperature range) Inside, the wafer is substantially free of residues of solid by-products during exposure to the remote plasma.

In some embodiments, the wafer includes exposed nitrides and/or oxides. In some embodiments, the selectivity of the polysilicon to the exposed nitride and/or oxide structure during the removal of the polysilicon layer is greater than about 500:1. In some embodiments, the hydrogen-based species include hydrogen or ammonia, and the fluorine-based species includes nitrogen trifluoride or carbon tetrafluoride. In some embodiments, the temperature range is less than about 60 °C. In some embodiments, the wafer is exposed to a distal plasma in a chamber having a pressure of less than about 5 Torr. In some embodiments, the wafer is supported on an electrostatic chuck having a plurality of hot zones that are configured to define a plurality of different temperatures on the wafer. In some embodiments, the polysilicon layer is removed at an etch rate greater than about 2000 Å per minute. In some embodiments, the concentration of the fluorine-based species is between about 0.7% and about 10% by volume, and wherein the concentration of the hydrogen-based species is greater than about 50% by volume. In some embodiments, the etchant further comprises a modified gas species other than a fluorine-based species, wherein the modified gas species comprises at least one of nitrogen trifluoride, carbon tetrafluoride, fluoromethane, and sulfur hexafluoride. In some embodiments, the wafer is supported on the electrostatic chuck and further includes a native oxide layer, and the method further includes applying a bias to the electrostatic chuck to create at least between the remote plasma source and the electrostatic chuck. The fluorine-based etchant capacitively couples the plasma, and exposes the wafer to a capacitively coupled plasma to remove the native oxide layer, wherein the removal of the native oxide layer and the removal of the polysilicon layer are performed in situ.

The disclosure also relates to an apparatus for removing a polysilicon layer from a wafer. The apparatus includes a plasma etch chamber, wherein the plasma etch chamber includes a remote plasma source and a wafer support for supporting the wafer and outside the remote plasma source, wherein the wafer includes a polysilicon layer and an oxide layer At least one of the layers with the nitride. The apparatus further includes a controller configured to provide instructions for performing: (a) flowing an etchant comprising a hydrogen-based species and a fluorine-based species to a remote plasma source, wherein the concentration of the hydrogen-based species is greater than the fluorine-based species The concentration of the species, (b) the generation of far-end plasma in the remote plasma source, where the far-end plasma includes radicals of hydrogen-based species and fluorine-based species, and (c) exposes the wafer to the far-end plasma To remove the polysilicon layer, wherein the wafer is maintained within a temperature range such that the wafer is substantially free of residues of solid byproducts during exposure to the remote plasma.

In some embodiments, the apparatus further includes a showerhead between the wafer support and the remote plasma source, wherein the plasma etch chamber is configured to generate an inductively coupled plasma in the remote plasma source, and The plasma etch chamber is configured to create a capacitively coupled plasma between the wafer support and the showerhead. In some embodiments, the wafer support includes a plurality of thermal zones configured to define a plurality of different temperatures across the wafer range. In some embodiments, the temperature range is less than about 60 °C. In some embodiments, the etchant further comprises a modified gas species other than a fluorine-based species, wherein the modified gas species comprises at least one of nitrogen trifluoride, carbon tetrafluoride, fluoromethane, and sulfur hexafluoride. In some embodiments, the wafer includes a native oxide layer on the polysilicon layer, and the controller is further configured with instructions to apply a bias to the wafer support for remote plasma source and wafer support A capacitive coupling plasma of at least a fluorine-based etchant is generated between the pieces, and the wafer is exposed to a capacitively coupled plasma to remove the native oxide layer, wherein the removal of the native oxide layer and the removal of the polysilicon layer are performed in situ .

These and other embodiments are further described below with reference to the drawings.

[Preface] In the following description, numerous specific details are set forth to provide a thorough understanding of the concepts illustrated. The concepts shown may be implemented in the absence of some or all of these specific details. On the other hand, well-known process operations are not described in detail to avoid unnecessarily obscuring the concepts. Although some concepts are described in conjunction with the specific embodiments, it is understood that these embodiments are not intended to be limiting.

Plasma based etching can be used in the production of integrated circuits. For various technology nodes (as in 1x-nm or 2x-nm nodes), novel materials for structures such as memory element stacks can provide surprising benefits. Production processes, such as etching of a particular layer, may be relatively advantageous for such new materials while still being etched with high efficiency. While it may be desirable to achieve etching of certain materials (eg, polysilicon) with high efficiency for high throughput, it may also be desirable to minimize the loss of surrounding exposed materials to avoid adversely affecting device performance.

The distal or downstream plasma provides an acceptable etch rate and minimizes the loss of surrounding material. In some embodiments, for example, the material can include Si ₃ N ₄ and/or TiN. Si ₃ N ₄ can be used as a spacer, pad, and/or etch stop layer, while TiN can be used as a metal gate structure or electrode. The distal or downstream plasma can provide conditions that minimize damage caused by direct plasma exposure, including ion impact damage, charge damage, and defects due to high flux of high energy photons. [Component Structure]

Figure 1 illustrates a cross section of an example of an element structure having a polysilicon layer. In the element structure shown in FIG. 1, the polysilicon layer 100 on the bottom layer 110 may be 120, which may comprise Si ₃ N _4. The polysilicon layer 110 can also be separated by multiple vertical structures 130, each of which can include, for example, TiN and/or Si ₃ N ₄ . In some embodiments, the polysilicon layer 110 can include an annealed polysilicon. The annealed polycrystalline germanium may be more crystalline and relaxed than the unannealed polycrystalline germanium and may be etched at a different rate than the unannealed polycrystalline germanium. Those of ordinary skill in the art will appreciate that the polysilicon layer 110 can be surrounded or separated by any number of different materials.

In the example of FIG. 1, component structure 100 can be a memory component or a logic component. The underlying Si ₃ N ₄ layer 120 can serve as an etch stop layer, while the TiN and Si ₃ N ₄ vertical structures 130 can be electrodes. In some embodiments, the polysilicon layer 110 is etched and then a space between the TiN and Si ₃ N ₄ vertical structures 130 is filled with a dielectric material to create a capacitance between the TiN and Si ₃ N ₄ vertical structures 130.

In the example of FIG. 1, the thickness of the polysilicon layer 110 can be between about 1 [mu]m and about 2 [mu]m (eg, between about 1.10 [mu]m and about 1.35 [mu]m). Moreover, the TiN and Si ₃ N ₄ vertical structures 130 can be between about 1 μm and about 2 μm (eg, between about 1.10 μm and about 1.35 μm). Those of ordinary skill in the art will appreciate that the memory or logic element structure 100 can have varying thicknesses and orientations.

In the example of Figure 1, the size of the polysilicon and other features may depend on the application and technology node. In some embodiments, the removed polysilicon thickness can be about 1.3 [mu]m (which can correspond to a 2x-nm node). For a 2x-nm technology node, this may correspond to a feature below about 22 nm (eg, gate width). In some embodiments, the removed polysilicon thickness can be about 1.5 [mu]m (which can correspond to a 1 x-nm node). For a 1x-nm technology node, this may correspond to a feature below about 16 nm (eg, gate width).

Removal of polycrystalline germanium or any other germanium containing structure may be hindered by the presence of native oxides. When exposed to ambient conditions or oxygen, the native oxide layer can form on the polysilicon layer or other germanium containing layer. Figure 2 illustrates a cross section of an example of the structure of a native tantalum oxide layer on a polycrystalline germanium layer.

In FIG. 2, component structure 200 can be similar to component structure 100 provided earlier in FIG. The polysilicon layer 210 may be separated by a vertical structure 230, and each vertical structure may include TiN and/or Si ₃ N ₄ . The polysilicon layer 210 may also be disposed on the underlying layer 220 (which may include Si ₃ N ₄ ). In some embodiments, the component structure 200 can be a memory component or a logic component, wherein the lower layer 220 is an etch stop layer and the vertical structure 230 is an electrode. A native tantalum oxide layer 240 can be formed on the polysilicon layer 210. In some embodiments, an oxygen-containing layer (eg, hafnium oxynitride) can be formed on the Si ₃ N ₄ in the vertical structure 230.

The native tantalum oxide layer 240 may form when oxygen reacts with the ruthenium on the surface of the ruthenium containing structure. The native tantalum oxide layer 240 can have a thickness of between about 5 Å to about 50 Å, or between about 10 Å to about 30 Å. Since the native tantalum oxide layer 240 is not intentionally fabricated or synthesized, but is formed upon exposure to any environment containing an oxidant, the structure of the native tantalum oxide layer 240 may be non-uniform and highly amorphous.

The presence of the native tantalum oxide layer 240 may hinder the chemical reaction when attempting to perform a chemical reaction on the underlying material. In particular, the native tantalum oxide layer 240 may hinder the etching of the polysilicon layer 210, inhibiting and increasing the non-uniformity of polysilicon removal. This can adversely impact productivity and component performance.

Desirable to remove the native silicon oxide layer 240 prior to removing the polysilicon layer 210, also causing the surrounding material (e.g., vertical structure comprising TiN and / or Si ₃ N ₄ 230) of the minimal loss. In some embodiments, it is desirable to remove both the native tantalum oxide layer 240 and the polysilicon layer 210 while causing minimal loss of surrounding material.

Typically, the removal of the native tantalum oxide layer on the wafer is achieved by a wet etch process, such as immersing the wafer in a bath containing diluted HF and subsequent transfer to another chamber for further processing. room. This wet etch process may have disadvantages such as allowing native oxide to re-grow during the simultaneous transfer of wafers during the waiting time, relatively high cost of ownership, and the use of toxic, hazardous, and non-environmentally friendly solvents. In addition, wet processing can compromise the integrity of the high aspect ratio structures found in the components. However, the disclosed embodiments can alleviate at least some of the disadvantages by applying a method that removes the native tantalum oxide layer on the wafer with high selectivity and uses a dry plasma etching process. In some examples, a dry plasma etch process and a polysilicon etch process to remove the native tantalum oxide layer can be performed in situ.

3A illustrates a three-dimensional schematic of a portion of an exemplary fin field effect transistor (FinFET) structure. FinFET structure 300 can include semiconductor wafer 305. The semiconductor wafer 305 can include a plurality of fins 305a made of tantalum. A dielectric material 320, such as a shallow trench isolation (STI) oxide, is formed between adjacent fin fins 305a. Dielectric material 320 can include a low dielectric oxide material such as tantalum oxide. A plurality of polysilicon layers 310 can be formed over portions of the dielectric material 320. In some embodiments, the polysilicon layer 310 can include a vertical structure that is perpendicular to the polysilicon of the samarium fin 305a. The FinFET structure 300 can further include a tantalum nitride liner 330 formed over the dielectric material 320 and around the polysilicon layer 310. The FinFET structure 300 can further include a germanium nitride liner 330 and a mask 340 on the fin fin 305a.

FIG. 3B illustrates an enlarged view of the exemplary FinFET structure of FIG. 3A after etching the polysilicon. FIG. 3C illustrates another enlarged view of the exemplary FinFET structure of FIG. 3A after etching the polysilicon. The dry etch process selectively removes the polysilicon layer 310. The dry etch process can be highly selective for protecting the ruthenium fin 305a, the dielectric material 320, and the oxide thin layer (not shown) of the tantalum nitride liner 330. Therefore, the dry etching process can effectively remove the polysilicon and at the same time have selectivity for protecting the thin layers of tantalum, niobium oxide, and niobium nitride oxides. In FIGS. 3B and 3C, the dry etch process removes the polysilicon layer while leaving the samarium fin 305a, the dielectric material 320, and the tantalum nitride liner 330 in the absence of residue and defects. [Process conditions]

The present disclosure relates to a method of removing polysilicon at high etch rates with high selectivity to exposed nitride and/or oxide layers. The method includes providing a wafer having a polysilicon layer. In some embodiments, the wafer further includes a native oxide layer on the polysilicon layer, and at least one of a nitride layer and an oxide layer. The method further includes flowing an etchant comprising a hydrogen-based species and a fluorine-based species to a remote plasma source, wherein the concentration of the hydrogen-based species is greater than the concentration of the fluorine-based species. A distal plasma is generated in the distal plasma source, wherein the distal plasma comprises a radical of a hydrogen-based species and a fluorine-based species. The wafer is exposed to a remote plasma to remove the polysilicon layer, wherein the wafer is maintained in a temperature range such that the wafer is substantially free of residues of solid byproducts during exposure to the remote plasma. In some embodiments, the removal of the polysilicon layer is performed at an etch rate greater than about 2000 Å per minute and has a selectivity to nitride and/or oxide greater than about 500:1.

The wafer can include any semiconductor wafer, partial integrated circuit, printed circuit board, or other suitable workpiece. Process conditions can vary depending on the wafer size. Typically, many production facilities are configured for 200-nm wafers, 300-nm, or 450-nm wafers. The disclosed embodiments are configured to operate on any suitable wafer size, such as 300-nm and 450-nm wafer technology.

In some embodiments, the removal of polysilicon can be performed by a plasma processing apparatus having a remote plasma source (such as the plasma processing apparatus or plasma reactor described with respect to FIG. 10). The gas directed to the plasma reactor described in Figure 10 can vary from application to application. In some embodiments, the etching reaction can be performed using a hydrogen based etchant. The hydrogen-based etchant may include, for example, hydrogen (H ₂ ). Another example may include ammonia (NH ₃ ). In some embodiments, the etching reaction can be carried out using a combination of H ₂ and a fluorine-based species such as nitrogen trifluoride (NF ₃ ), carbon tetrafluoride (CF ₄ ), or sulfur hexafluoride (SF ₆ ). Gases such as H ₂ and NF ₃ are non-toxic and generally do not adversely affect the environment.

The use of a hydrogen-based species as an etchant can effectively etch polysilicon and at the same time act as a reducing agent that minimizes oxidation and loss of other exposed materials such as TiN, Si ₃ N ₄ , and SiO ₂ . An oxidizing agent such as oxygen can increase the etch rate of the polysilicon, but it can also oxidize and increase the loss of other exposed materials. The addition of a fluorine-based species as an etchant plus a hydrogen-based species increases the etch rate of the polysilicon, but if the concentration of the fluorine-based species exceeds a certain limit, it is also possible to increase the loss of other exposed materials.

As discussed earlier herein, a hydrogen-based species may include H ₂ or NH ₃ , while a fluorine-based species may include NF ₃ , CF ₄ , or SF ₆ . Examples of other fluorine-based species may include hexafluoroethane (C ₂ F ₆ ), trifluoromethane (CHF ₃ ), difluoromethane (CH ₂ F ₂ ), fluoromethane (CH ₃ F), octafluoropropane (C). ₃ F ₈ ), octafluorocyclobutane (C ₄ F ₈ ), octafluoro[1-]butene (C ₄ F ₈ ), octafluoro[2-]butene (C ₄ F ₈ ), octafluoroisobutylene (C ₄ F ₈ ), fluorine (F ₂ ), and the like. The plasma reactor activates hydrogen-based species and fluorine-based species to form free radicals, ions, or other plasma activated species. A plasma reactor can produce a plasma comprising a radical of a hydrogen-based species and a fluorine-based species. The plasma can be used to perform plasma etching of polycrystalline germanium, wherein the plasma etching can be a plasma etching of H ₂ /NF ₃ .

The process conditions of the plasma etch can affect the etch rate of the polysilicon and the exposed nitride and/or oxide. Various process parameters (such as surface temperature, pressure, power supply, gas flow rate, gas composition, wafer size, and associated etchant gas concentration) can affect process conditions and thus affect polysilicon and exposed nitride and/or The etch rate of the oxide. Such process parameters can be optimized in the "Process Window" to maximize the etch rate of the polysilicon while limiting the etch rate of the exposed nitride and/or oxide.

The hydrogen-based species provide an active species that is ionized or free radicalized at the distal plasma source to form a plasma. Without any theoretical limitation, the etching of polycrystalline germanium can occur by continuously adding adsorbed hydrogen atoms to germanium atoms to form a Si-H _x complex, wherein the number of chemically adsorbed hydrogen atoms is from x = 1, 2. Growth with 3 (ie, SiH, SiH ₂ , and SiH ₃ ). Such a reaction mechanism is carried out at least in the presence of pure H ₂ plasma. The addition of a hydrogen atom to SiH ₃ promotes the formation of volatile decane (SiH ₄ ), which promotes the etching of polysilicon. The following equation describes the complete Si etching reaction: Si _(s) + 4H ^* → SiH _4(g) .

Other chemical reactions promote the removal of polysilicon. The fluorine radical can react with the ruthenium atom and form volatile tetrafluorodecane (SiF ₄ ) in the following reaction: Si _(s) + 4F ^* → SiF _{4 (g)} . When hydrogen radicals and fluorine radicals react with helium atoms to form volatile decane and tetrafluorodecane, respectively, no solid by-products are formed. A process window for removing germanium atoms without the formation of solid by-products may be referred to as a "clean state."

Typically, in the plasma species with the hydrogen group of the introduced fluorine-based species formed in the gas phase reactants (e.g., HF, NH ₄ • HF, and NH ₄ F). These gas phase reactants and other plasma activated species may potentially react with deuterium atoms to form solid by-products such as ammonium hexafluoroantimonate ((NH ₄ ) ₂ SiF ₆ ). An example of such a chemical reaction can be shown in the following chemical route: Si _(s) + 4HF _(g) + 2NH ₄ F _(g) → ((SiH ₄ ) ₂ SiF ₆ ) _(g) + 2H _{2 (g)} . A process window that removes germanium atoms but involves the formation of solid by-products may be referred to as a "deposited state." The solid by-product can be sublimed at a slightly elevated temperature (e.g., a temperature greater than about 60 ° C or greater than about 75 ° C) such that the polycrystalline germanium is removed and only gaseous by-products are formed after removal of the polycrystalline germanium.

4A is a schematic cross-sectional view showing the structure of an element having a salt residue after etching a polysilicon. After etching the polysilicon (not shown), the element structure 400a includes a recess 440 between the vertical structures 430. Vertical structure 430 can include a stack of tantalum nitride and/or tantalum oxide (eg, hot tantalum oxide). The component structure 400a further includes a lower layer 420, which may include tantalum nitride and/or tantalum oxide. The polysilicon etch to form the recess 440 can occur to the underlying layer 420. In some embodiments, the lower layer 420 is an etch stop layer and the vertical structure 430 is an electrode. In FIG. 4A, salt residue 450 may be formed on the sidewalls of vertical structure 430 and the surface of underlying layer 420. Process conditions, including temperature and pressure, may kinetically favor the formation of salt residue 450 in Figure 4A. Removal of the salt residue 450 may require a temperature treatment to sublime the salt residue 450 during or after removal of the polysilicon. The presence of salt residue 450 may limit production capacity and adversely affect component performance.

4B is a schematic cross-sectional view showing the structure of an element having no salt residue after etching polycrystalline germanium. After etching the polysilicon (not shown), the element structure 400b includes a recess 440 without a salt residue 450, a vertical structure 430, and a lower layer 420. Process conditions, including temperature and pressure, may kinetically favor reactions in a clean state. As such, the throughput can be increased by etching the polysilicon in the presence of a temperature treatment step that does not require separation to sublime the salt residue 450.

As discussed above, polysilicon can be removed by at least one of the following chemical pathways: (1) Si _(s) + 4H ^* → SiH _{4 (g)} ; (2) Si _(s) + 4F ^* → SiF _{4 (g)} And (3) Si _(s) + 4HF _(g) + 2NH ₄ F _(g) → ((NH ₄ ) ₂ SiF ₆ ) _(s) + 2H _{2 (g)} . The first two chemical pathways avoid the formation of solid by-products or salts, while the final chemical pathway involves the formation of solid by-products or salts. Process conditions (such as feed gas ratio, chamber pressure, and wafer temperature) can affect reaction kinetics to favor certain chemical pathways over other chemical pathways. The reaction kinetics can be driven by the activation energy and diffusivity of the species on the surface of the wafer. Without being bound by any theory, the diffusivity of gaseous species such as NH ₄ F can be affected by wafer temperature. Wafer temperature control controls the diffusion of gaseous species such as NH ₄ F, thus limiting the formation of solid by-products such as (NH ₄ ) ₂ SiF ₆ . Thus, proper process conditions can control the choice of chemical path to etch polysilicon in a clean or deposited state.

The process conditions in the clean state can be carried out under relatively low temperature and/or low pressure conditions. In some embodiments, the temperature of the wafer can be less than about 120 ° C, or less than about 60 ° C. For example, the temperature of the wafer can be between about 20 ° C and about 120 ° C, or between about 20 ° C and about 50 ° C. In some embodiments, the chamber pressure is less than about 5 Torr, or less than about 1 Torr. For example, the chamber pressure can be between about 0.1 Torr and about 5 Torr.

In some embodiments, the removal of polysilicon can be performed at an etch rate greater than about 1000 Å per minute, and even greater than 2000 Å per minute in a clean state. In some embodiments, the wafer can include an exposed nitride and/or oxide layer, wherein the exposed nitride layer can include tantalum nitride and the exposed oxide layer can include a hot tantalum oxide. The exposed nitride and/or oxide layer may have an etch rate of less than about 5 Å per minute, or less than about 2 Å per minute, or less than about 1 Å per minute. Thus, the selectivity of the polysilicon to the exposed nitride and/or oxide can be greater than about 100:1, or greater than about 500:1. Such high selectivity can be achieved at polysilicon etch rates greater than about 2000 Å per minute.

In some embodiments, process conditions in which the wafer temperature is greater than 60 ° C may sublime the salt residue, wherein the wafer temperature at which the salt residue sublimes may represent a deposition state. Process conditions in which the wafer temperature is less than 60 ° C do not result in salt formation, wherein the wafer temperature that does not result in salt formation can represent a clean state. In some embodiments, the process conditions in the clean state can etch the polysilicon at an etch rate greater than 2000 Å per minute. Further, the selectivity of TEOS may be greater than 500: 1, and the selectivity of the Si ₃ N ₄ may be greater than 100: 1. Thus, the clean state not only avoids the deposition of excess solid by-products, but the clean state provides a higher polysilicon etch rate than the deposited state, and a greater selectivity to oxides and nitrides than the deposited state.

5A to 5C show FTIR patterns having vibration peaks for detecting (NH ₄ ) ₂ SiF ₆ in various temperature states. Detection of chemical species can be achieved by indicating the engagement of certain types of vibrational modes, such as stretching and bending. In Fig. 5A, the detection of (NH ₄ ) ₂ SiF ₆ can be achieved by indicating that the NH bond at the peak of about 3300 cm ^{-1 is} symmetrically stretched. In FIG. 5B, detection of (NH ₄ ) ₂ SiF ₆ can be achieved by indicating an NH bond that is subjected to bending (eg, shaking) at a peak of about 1425 cm ⁻¹ . In Figure 5C, detection of (NH ₄ ) ₂ SiF ₆ can be achieved by indicating a Si-F bond at a peak of about 717 cm ^-1 . In each of the FTIR patterns, the presence of (NH ₄ ) ₂ SiF ₆ was detected at the temperature of the deposition state. However, in the clean state, (NH ₄ ) ₂ SiF _{6 was} not detected. Although the wafer temperature in the deposited state (eg, above 60 ° C) results in the formation of solid by-products, the wafer is maintained in a clean state (eg, below 40 ° C) to avoid the formation of solid by-products.

Figure 6 shows a flow diagram of an exemplary process for removing polysilicon from a wafer. The operations in process 600 may be performed in different orders and/or using different, fewer, or additional operations.

Process 600 can begin at block 605 where a wafer having a polysilicon layer is provided. In some embodiments, the wafer can be a semiconductor wafer (eg, 200 mm, 300 mm, or including a germanium wafer having one or more material stacks (eg, dielectric, conductive, or semiconductor materials deposited thereon) 450mm wafer). In some embodiments, the wafer can be part of a memory element or logic element. The memory or logic elements can include those structures as shown in Figures 1, 2, and 3A through 3C. The wafer may have a polysilicon layer and at least one of a nitride and an oxide layer, wherein the nitride layer may include tantalum nitride or titanium nitride, and wherein the oxide layer may include tantalum oxide (eg, hot tantalum oxide). In some embodiments, the wafer may also include features of various topography. Such features can have an aspect ratio of height to lateral dimension of at least about 2:1, at least about 10:1, or at least about 20:1. In some embodiments, at least one of the tantalum nitride and tantalum oxide layers can be part of such a feature.

The wafer can be positioned on a wafer support in a plasma processing apparatus. In some embodiments, the wafer support can be an electrostatic chuck (ESC). In some embodiments, an electrostatic chuck can include a plurality of configurations to define a plurality of hot zones at different temperatures on the wafer. Each of the hot zones can be independently controllable. The plurality of hot zones can be radially distributed from the center to the edge on the electrostatic chuck. In this way, different wafer temperatures can be applied from the center of the wafer to the edge.

At block 610 of process 600, an etchant comprising a hydrogen-based species and a fluorine-based species is passed to a remote plasma source. In some embodiments, the concentration of the hydrogen-based species is greater than the concentration of the fluorine-based species. In some embodiments, the hydrogen-based species comprises H ₂ or NH ₃ . In some embodiments, the fluorine-based species comprises NF ₃ or CF ₄ . The addition of fluorine-based species generally increases the etch rate of polysilicon. The relative concentration of the fluorine-based species can be limited to maintain the desired selectivity on the nitride and/or oxide layer. In some embodiments, the concentration of the fluorine-based species can be less than about 50% by volume, less than about 20% by volume, or between about 0.7% and about 10% by volume. In some embodiments, the concentration of the hydrogen-based species is greater than about 50% by volume, greater than about 80% by volume, or greater than about 90% by volume.

In some embodiments, an etchant can be used to introduce an inert carrier gas. It is believed that inert carrier gas reduces the likelihood of free radical recombination in the gas phase. The inert carrier gas may affect the etch rate of the polysilicon. Examples of inert carrier gases may include inert gases such as helium (He), neon (Ne), and argon (Ar).

The etchant can be directed toward the wafer into the remote plasma source in the plasma processing apparatus. The plasma processing apparatus can include a showerhead coupled to the remote plasma source through which the etchant can be directed to the processing chamber or to an area adjacent the wafer support. The remote plasma source and showerhead can be positioned above the wafer support. Details of an exemplary remote plasma source can be described with reference to FIG.

At block 615 of process 600, a distal plasma is generated in the remote plasma source. The distal plasma can include free radicals of hydrogen-based species and fluorine-based species. Various species may be present in the far-end plasma, such as ions, electrons, free radicals, neutral species, metastable species, and other species. The far end plasma can be generated upstream of the wafer and processing chamber or outside of the area adjacent the wafer support.

When a hydrogen-based species and a fluorine-based species are introduced into a remote plasma source, power can be applied to the remote plasma source. The power supply powers the induction coil to produce a remote plasma, and the far end plasma can be an inductively coupled plasma in the remote plasma source. The distal plasma source can produce a reactive species comprising a hydrogen-based species and a plasma-activated species of a fluorine-based species (eg, free radicals). Such plasma activated species can result from the dissociation of hydrogen-based species from fluorine-based species. For example, H at the distal end of the plasma dissociation of NF ₂ and ₃ may generate a _{^{F *, N *, NF x}} *, H ^* radical and the. In some examples, radicals can recombine at the distal end to form gaseous byproducts in the plasma of HF and NH ₄ F in.

Process conditions in the remote plasma source can affect plasma generation. For example, process conditions (eg, plasma frequency, plasma power, etchant chemistry, gas mixture, gas flow rate, chamber pressure, chamber temperature, and timing) can increase or decrease the density of free radicals in the plasma. The equipment design of the remote plasma source can also affect the generation of plasma. For example, the positioning of the induction coil, the length of the induction coil, the shape of the distal plasma source, the material of the remote plasma source, the distribution of the holes in the showerhead, and the material of the showerhead can increase or decrease the freedom in the plasma. The density of the base. In some embodiments, the process conditions and equipment design of the remote plasma source can be optimized to increase the density of free radicals in the plasma. Embodiments of the device design can promote plasma recirculation in the remote plasma source to further increase the density of free radicals in the plasma. The high density of free radicals in the plasma can correspond to the high etch rate of polysilicon and the high selectivity to nitrides and/or oxides.

At block 620 of process 600, the wafer is exposed to a remote plasma to remove the polysilicon layer. The wafer is maintained within a temperature range such that the wafer is substantially free of residues of solid by-products during exposure to the remote plasma. The wafer temperature can be controlled by controlling the temperature of the wafer support. The ions generated in the far-end plasma can be filtered by a showerhead, so that the wafer can be more exposed to free radicals of hydrogen-based species and fluorine-based species. H ^* radicals and F ^* radicals (i.e., atomic hydrogen and atomic fluorine) can react with the polycrystalline germanium layer to etch polycrystalline germanium. The H ^* radical can react with hydrazine to form a gaseous by-product of decane. The F ^* radical can react with hydrazine to form a gaseous by-product of tetrafluorodecane. Therefore, the polysilicon layer can be etched not only by atomic hydrogen but also by atomic fluorine. The temperature of the wafer can be maintained at a temperature that inhibits the formation of solid by-products such as (NH ₄ ) ₂ SiF ₆ . In some embodiments, the temperature range is less than about 120 °C, less than about 60 °C, or between about 20 °C and about 50 °C. Chamber pressure can also be controlled to inhibit the formation of solid by-products. In some embodiments, the chamber pressure can be less than about 5 Torr, or less than about 1 Torr. Without being bound by any theory, controlling the wafer temperature or chamber pressure can limit the diffusivity of HF and/or NH ₄ F at the reaction surface, thereby inhibiting the chemical reaction used to form (NH ₄ ) ₂ SiF ₆ . . Controlling the wafer temperature controls the surface reaction path.

The formation of solid by-products or salts can be inhibited under certain process conditions, such as relatively low temperatures and/or relatively low pressures. This avoids or otherwise reduces excess defects in the wafer and increases throughput. Such process conditions not only avoid residues of excess solid by-products, but also increase the etch rate of the polysilicon and increase the selectivity to the nitride and/or oxide layer. In some embodiments, the polysilicon layer is removed at an etch rate greater than about 2000 Å per minute. In some embodiments, the selectivity of the polysilicon to the nitride and/or oxide layer during the removal of the polysilicon layer can be greater than about 500:1.

In some embodiments, the etch rate of the polysilicon may depend on the mixture of reactant species in the etchant. In addition to the hydrogen-based species and the fluorine-based species, the etchant may further include a modified gas species different from both the fluorine-based species and the hydrogen-based species, wherein the modified gas species include NF ₃ , CF ₄ , CH ₃ F, and At least one of SF ₆ . The concentration of the modified gas species is less than about 10% by volume. Free radicals of the modified gas species can be generated and the wafer can be exposed to such free radicals to aid in the removal of the polysilicon layer.

Figure 7 illustrates a graph showing the polysilicon etch rate as a function of temperature. The polysilicon etch rate increases with decreasing electrostatic chuck temperature until formation of salt by-products. Furthermore, when a modified gas species is added to the etchant, the sensitivity of the polysilicon etch rate to temperature changes. As shown in FIG. 7, the volume percentage of less than 10% of the added concentration of _{NF 3, CF 4, CH 3} F, SF ₆ and at least one of polysilicon etching rate increased sensitivity to temperature.

Returning to Figure 6, in an embodiment in which the wafer is supported on an electrostatic chuck having a plurality of hot zones, process 600 can further include exposing the wafer to a remote plasma to improve uniformity of polysilicon removal. During the application, a plurality of different temperatures are applied in the hot zone. The plurality of hot zones can be radially distributed such that different temperatures can be radially distributed across the wafer. The etch rate of the polysilicon from the center of the wafer to the edge can be fine tuned by applying different temperatures from the center to the edge of the electrostatic chuck of the self-supporting wafer.

Figure 8A shows the polysilicon etch uniformity on a wafer of an exemplary single zone electrostatic chuck. At a single temperature of 100 ° C applied across the electrostatic chuck, the polysilicon etch range is between 73.8 nm and 84.7 nm. The average value was 78.7 nm, the 3-sigma standard deviation was 8.9 nm (11.3%), and the range was 10.9 nm (13.9%).

Figure 8B shows the polysilicon etch uniformity on a wafer of an exemplary multi-zone electrostatic chuck. Applying a temperature of 110 ° C at the center of the electrostatic chuck, applying a temperature of 100 ° C in the first ring around the center of the electrostatic chuck, applying a temperature of 95 ° C in the second ring surrounding the first ring, and surrounding the electrostatic chuck And a temperature of 100 ° C was applied in the third ring surrounding the second ring. The range of polysilicon etch is between 83.9 nm and 88.1 nm. The average value was 86.5 nm, the 3-sigma standard deviation was 3.4 nm (3.9%), and the range was 4.2 nm (4.8%). The data shown in Figures 8A and 8B shows that the polysilicon etch uniformity on the wafer can be improved by controlling the temperature across multiple hot zones in the electrostatic chuck.

Returning to Figure 6, in an embodiment wherein the native oxide layer is formed on the polysilicon layer, the process 600 can further include applying a bias to the wafer support to create at least between the remote plasma source and the wafer support. The fluorine-based etchant capacitively couples the plasma and exposes the wafer to a capacitively coupled plasma to remove the native oxide layer. In some embodiments, the fluorine-based etchant can include CF ₄ . The removal of the native oxide layer and the removal of the polysilicon layer can be performed in situ.

The removal of polysilicon may be hindered by the presence of native oxides. When exposed to ambient conditions or oxygen, a native oxide layer (such as a native tantalum oxide layer) can be formed on the polysilicon layer (as shown in Figure 2). Exemplary wafer processing of some wafers to remove native oxides. US Patent Application No. 13/916,497, entitled "REMOVAL OF NATIVE OXIDE WITH HIGH SELECTIVITY", filed on June 12, 2013, is hereby incorporated by reference. U.S. Patent No. 9/034,773, filed on Dec. 19, 2014, and the entire contents of each of This is incorporated herein by reference.

In some embodiments, the etchant used to remove the native oxide layer can be used to flow to the wafer prior to flow using the etchant to remove the polysilicon layer. The etchant used to remove the native oxide layer may include a fluorine-based etchant (such as CF ₄ ) or a mixture of a hydrogen-based etchant and a fluorine-based etchant (such as H ₂ and NF ₃ ). An etchant to remove the native oxide layer can be provided in the region between the showerhead and the wafer support. A bias can be applied to the wafer support to create a capacitively coupled plasma between the showerhead and the wafer support, wherein the showerhead can be electrically grounded. Capacitively coupled plasmas can include ions of fluorine-based etchants, free radicals, and other plasma activated species. Exposure to a capacitively coupled plasma can remove the native oxide layer to perform a native oxide penetration step. The native oxide penetrating step can be substantially followed by the generation of the inductively coupled plasma in the remote plasma source for removing the polycrystalline germanium layer, wherein the primary oxide penetrating step and the polysilicon layer can be removed in the same plasma processing device. In progress. In other words, the removal of the native oxide through and the polysilicon layer can be performed in situ so that the wafer does not need to be transferred to a separate tool or chamber.

Figure 9 shows a flow diagram of an exemplary process for removing native oxide and polysilicon from a wafer. The operation in process 900 illustrates an example of the in situ removal of native oxide and polysilicon. The operations in process 900 can be performed in different orders and/or using different, fewer, or additional operations.

The process 900 can begin at block 905 where a wafer is provided on a multi-zone electrostatic chuck, and wherein the wafer has a polysilicon layer, at least one of a nitride layer and an oxide layer, and a native oxide on the polysilicon layer. In some embodiments, the wafer can be a semiconductor wafer (eg, a 200-mm, 300-mm, or 450-mm wafer) that includes a dielectric (eg, low) that is deposited thereon. A germanium wafer in which one or more materials of k dielectric material, conductive, or semiconductor material are stacked. In some embodiments, the wafer can be part of a memory element or logic element. Memory elements or logic elements may include those shown in Figures 1, 2, and 3A through 3C. In some embodiments, the nitride layer can include tantalum nitride or titanium nitride, and the oxide layer can include tantalum oxide (eg, hot tantalum oxide). In some embodiments, the wafer may also include features of various topography. Such features can have an aspect ratio of height to lateral dimension of at least about 2:1, at least about 10:1, or at least about 20:1. In some embodiments, at least one of the nitride and oxide layers can be part of such a feature.

The electrostatic chuck can include a plurality of thermal zones configured to provide independently controllable temperatures in each zone. The complex hot zone can be defined in a radial configuration from center to edge. The hot zone can be circular or toroidal. The hot zone can be independently controlled such that a radial temperature distribution across the wafer can be applied. An example of a multi-zone electrostatic chuck is described in U.S. Patent Application Serial No. 11/562,884, filed on November 22, 2006, entitled "ELECTROSTATIC CHUCK HAVING RADIAL TEMPERATURE CONTROL CAPABILITY" this. Polysilicon etch uniformity can be improved by independently controlling the temperature of each hot zone in the multi-zone electrostatic chuck.

At block 910 of process 900, CF _{4 is} caused to flow toward the wafer. An etchant can be provided to the area adjacent to the wafer. In some embodiments, the etchant is delivered through the showerhead to a region between the wafer support and the showerhead.

At block 915 of process 900, an RF bias is applied to the multi-zone electrostatic chuck to create a CF ₄ capacitively coupled plasma between the showerhead and the multi-zone electrostatic chuck. When the showerhead is electrically grounded, the multi-zone electrostatic chuck can be biased. Capacitively coupled plasmas can include CF ₄ ions, free radicals, and other plasma activated species. In some embodiments, CF ₄ plasma is capacitively coupled plasma in situ between the showerhead and the wafer of CF _4, wherein the bias voltage may be controlled in situ plasma is generated with respect to the increase or Reduce ion bombardment. In some embodiments, the bias voltage can be between about 100 W and about 2000 W.

At block 920 of process 900, the wafer is exposed to a capacitively coupled plasma to remove native oxide. Exposure to a capacitively coupled plasma can remove native oxide to perform a native oxide penetration step. The CF ₄ capacitively coupled plasma etches native oxide at relatively high etch rates while avoiding salt formation and polymerization chemistry. Furthermore, the capacitively coupled plasma can be selective for etching of the nitride and/or oxide layers.

In process block 925 900, so that H ₂ and NF ₃ stream to the remote plasma source, wherein the concentration of H ₂ greater than the concentration of NF _3. In some embodiments, the concentration of NF ₃ can be less than about 50% by volume, less than about 20% by volume, or between about 0.7% to about 10% by volume. In some embodiments, the concentration of H ₂ greater than about 50% by volume, greater than about 80% by volume, or greater than about 90% by volume. In some embodiments, an inert carrier gas may flow together with H ₂ and NF _3. Examples of inert carrier gases can include inert gases such as He, Ne, and Ar. In some embodiments, the modified gas species (eg, CF ₄ , CH ₃ F, and SF ₆ ) may be added with H ₂ and NF ₃ at a concentration of less than about 10% by volume to adjust the temperature of the polysilicon etch rate. Sensitivity.

930, H ₂ and NF ₃ is generated inductively coupled plasma source in a plasma in the distal end of the process block 900, wherein the inductively coupled plasma comprising hydrogen radicals and fluorine radicals. Various species can exist in the inductively coupled plasma, such as ions, electrons, free radicals, neutral species, metastable species, and other species. The power supply powers the induction coil to produce an inductively coupled plasma. Inductively coupled plasma can be generated upstream of the wafer and the exterior of the processing chamber or region adjacent to the wafer.

In some embodiments, the process conditions and the design of the remote plasma source can produce a high radical density in the inductively coupled plasma, wherein a higher radical density can correspond to a higher polysilicon etch rate and increased molecular passivation The effect can lead to higher selectivity. In some embodiments, the reduced coil voltage applied to the remote plasma source can reduce sputtering in the distal plasma source and the showerhead, which increases the radical density. In some embodiments, higher pressures can result in higher RF coupling efficiencies, which increases the radical density. The pressure can be between about 0.1 Torr and 10 Torr. Other process conditions and equipment design implementations can increase the density of free radicals in the remote plasma source.

At block 935 of process 900, the wafer is exposed to an inductively coupled plasma to remove the polysilicon layer, wherein the wafer is maintained at a temperature below 60 °C. The wafer temperature can be actively controlled by the multi-zone electrostatic chuck during plasma processing. By controlling the wafer temperature below 60 ° C, certain reaction paths can be promoted while other reaction paths can be suppressed. Specifically, the reaction pathway Si _(s) + 4H ^* → SiH _{4 (g)} and Si _(s) + 4F ^* → SiF _{4 (g) are} promoted while inhibiting the reaction pathway Si _(s) + 4HF _(g) + 2NH. ₄ F _(g) → ((NH ₄ ) ₂ SiF ₆ ) _(s) + 2H _{2 (g)} . In some embodiments, the wafer can be maintained at a temperature between about 20 ° C and about 50 ° C to avoid the formation of (NH ₄ ) ₂ SiF ₆ . The ions generated in the inductively coupled plasma can be filtered by a showerhead such that the wafer can be more exposed to hydrogen radicals and fluorine radicals. In some embodiments, the chamber pressure can be controlled to inhibit the reaction pathway used to form (NH ₄ ) ₂ SiF ₆ . For example, the chamber pressure can be less than about 5 Torr, or less than about 1 Torr.

In some embodiments, the polysilicon layer is removed at an etch rate greater than about 2000 Å per minute. In some embodiments, the selectivity of the polysilicon to the nitride and/or oxide layer may be greater than about 500:1 during removal of the polysilicon layer. [equipment]

Apparatus for performing polysilicon removal and/or native oxide removal may include a plasma processing apparatus. The plasma processing apparatus can include a plasma etch chamber. The above method can be performed in an inductively coupled plasma chamber, a capacitively coupled plasma chamber, or a combination of both. The removal of polycrystalline germanium and native oxide can be performed in the same plasma processing equipment. In some embodiments, the plasma processing apparatus can be electrically coupled to the power source used to generate the inductively coupled plasma and the bias power used to generate the capacitively coupled plasma.

Figure 10 shows a schematic diagram of a plasma processing apparatus for performing a process for removing polysilicon from a wafer. The plasma processing apparatus 1000 includes a distal plasma source 1050 and a processing chamber 1025 external to the remote plasma source 1050. The distal plasma source 1050 can be configured to generate a distal plasma 1060, wherein the distal plasma 1060 can be an inductively coupled plasma. The activated species 1004 of the distal plasma 1060 can be introduced from the distal plasma source 1050 through the showerhead 1054. The wafer 1020 can be positioned on the wafer support 1010, wherein the wafer support 1010 can hold the wafer 1020 in place by an electrostatic chuck. Other clamping mechanisms can also be used. Wafer 1020 can include those structures as shown in Figures 1, 2, and 3A through 3C.

Process gas 1002 can be supplied to remote plasma source 1050 via gas inlet 1052. In some embodiments, process gas 1002 comprises a hydrogen-based species (such as H ₂ or NH ₃ ) and a fluorine-based species (such as NF ₃ , CF ₄ , or SF ₆ ). Other carrier gas or modified gas species as described above may be introduced with the process gas 1002. The gas inlet 1052 can distribute the process gas 1002 into the remote plasma source 1050 prior to inductively coupled plasma generation. One or more valves control the introduction of process gas 1002 into remote plasma source 1050. The distal plasma source 1050 can be any suitable shape (e.g., dome shaped, conical, or cylindrical) container. In some embodiments, a container of remote plasma source 1050 can be designed to optimize plasma recirculation flow and plasma density. The gas inlet 1052 can be configured to distribute the process gas 1002 toward the sidewall of the remote plasma source 1050 or along the sidewall of the remote plasma source 1050. The sidewalls of the remote plasma source 1050 can include materials that enhance the electric field. For example, the sidewalls can include a dielectric material such as quartz, aluminum, aluminum oxide, or ceramic. In some embodiments, the sidewalls can include a ceramic coating to limit sputtering.

The coil 1056 can surround at least a portion of the container of the distal plasma source 1050. The coil 1056 can be in electrical communication with an RF power source used to generate the remote plasma 1060 in the remote plasma source 1050. In some embodiments, the coil 1056 can surround the upper portion of the container and the lower portion of the container. In some embodiments, the coil 1056 can be divided into a top coil 1056a and a bottom coil 1056b, wherein the top coil 1056a constitutes one region that is powered at a particular frequency and the bottom coil 1056b constitutes another region that is powered at a particular frequency. Although the plasma processing apparatus 1000 of FIG. 10 displays two separate RF power sources for the coil 1056, the plasma processing apparatus 1000 can be limited to a single RF power source of the coil 1056.

The arrangement of the coils 1056 can affect the coupling of the RF power to increase the density of the free radicals to the remote plasma 1060. For example, the positioning of coil 1056, the length of coil 1056, and the spacing between coil 1056 and the container can affect the coupling of RF power to remote plasma 1060. When process gas 1002 is provided in remote plasma source 1050 and coil 1056 is energized, remote plasma 1060 can be ignited to form activated species 1004 of process gas 1002. The activated species 1004 can include free radicals, ions, and other active species of the processing gas 1002. The activated species 1004 can be directed toward the wafer 1020 by the showerhead 1054. In some embodiments, activated species 1004 from remote plasma 1060 can be used to etch polysilicon on wafer 1020 at high etch rates with high selectivity. In some embodiments, the showerhead 1054 can filter out ions of the activated species 1004.

In some embodiments, wafer support 1010 can be a susceptor to support wafer 1020, which can be actively cooled or actively heated to control the temperature of wafer 1020. For example, the temperature of wafer 1020 can be maintained at a temperature range, such as less than about 120 ° C, less than about 60 ° C, or between about 20 ° C and about 50 ° C. This may limit the formation of solid byproducts during exposure of wafer 1020 to remote plasma 1060.

In some embodiments, the wafer support 1010 can include an electrostatic chuck, wherein the electrostatic chuck can include a bias electrode to apply a bias to the wafer 1020 during the etching process. When a bias is applied to the wafer 1020, the in-situ plasma 1030 can be created between the showerhead 1054 and the wafer 1020, wherein the in-situ plasma 1030 can be a capacitively coupled plasma. The gas or gas mixture 1006 can be introduced into the processing chamber 1025 external to the remote plasma source 1050. The gas or gas mixture 1006 can be introduced from the shower head 1054 or from one or more gas inlets (not shown) coupled to the processing chamber 1025. In some embodiments, the gas or gas mixture 1006 can include at least one fluorine-based etchant (such as CF ₄ ). The applied bias voltage can create an RF field for the gas or gas mixture 1006 between the showerhead 1054 and the wafer 1020. The showerhead 1054 can be electrically grounded and can be coupled to the wafer support 1010 to ignite the in-situ plasma. In some embodiments, the showerhead 1054 can be anodized. Ionization of the gas or gas mixture 1006 can ignite the in situ plasma 1030 to form an activated species of gas or gas mixture 1006. In some embodiments, the activated species of in-situ plasma 1030 can be used to etch native oxide on wafer 1020.

In some embodiments, wafer support 1010 can include a plurality of thermal zones configured to provide independently controllable temperatures in each zone. The complex hot zone can be defined in a radial configuration from center to edge. The hot zone can be circular or toroidal. The hot zone can be independently controlled such that a radial temperature distribution across the wafer 1020 can be applied. The hot zone in the wafer support 1010 can improve the etch uniformity on the wafer 1020.

</ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; This is incorporated herein by reference.

The plasma processing apparatus 1000 can include a controller 1040. Controller 1040 can be part of a system that can be part of plasma processing apparatus 1000. Such a system can include a semiconductor processing apparatus including one or more processing tools, one or more chambers, one or more processing platforms, and/or specific processing components (wafer supports, airflow systems, etc.) ). These systems can be integrated with electronics that are used to control their operation before, during, and after processing of wafer 1020. Electronic components may be referred to as "controllers" that can control different components or sub-parts of one or more systems. Depending on the processing requirements and/or system type, the controller 1040 can be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (eg, heating and/or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operational settings, in and out tools, and other wafer transfers to and from transfer tools and/or load locks that interface with a particular system.

Depending on the processing conditions and/or system type, controller 1040 can be programmed to control any of the processes disclosed herein, including gas delivery, temperature setting (eg, heating and/or cooling), pressure setting, vacuum setting, power setting, RF generation. Device settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operational settings, access to the tool and/or wafer transfer to load locks that are interfaced with or interfaced to a particular system. Controller 1040 can provide program instructions to perform the etching process described above. Program instructions control various process parameters such as RF bias power level, RF power level, current in the region of the multi-zone coil, temperature in the hot zone of the multi-zone electrostatic chuck, chamber pressure, gas flow rate , gas composition, etc. For example, controller 1040 can provide instructions to maintain the wafer within a temperature range of less than about 60 °C. Controller 1040 can provide instructions to establish a pressure in plasma processing apparatus 1000 that is less than about 5 Torr, or between about 0.1 Torr and 5 Torr, or less than about 1 Torr.

In general terms, a controller can be defined as a variety of integrated circuits, logic, memory, and/or software having a receive command, an issue command, a control operation, a cleaning operation, an endpoint measurement, and the like. Electronic parts. The integrated circuit may include a die in the form of firmware for storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and/or one of executable program instructions (eg, software) or More microprocessors or microcontrollers. Program instructions may be instructions that are transmitted to the controller in various independent settings (or program files) and define operational parameters for performing a particular process on or in a semiconductor wafer or system. In some embodiments, the operational parameters may be part of a formulation defined by a process engineer, completed during production of one or more of the stack, material, metal, surface, circuit, and/or wafer die. Or more processing steps.

In some embodiments, controller 1040 can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, controller 1040 can be in the "cloud", or part of an entire or fab host system, which can accommodate remote access to wafer processing. The computer allows remote access to the system to monitor the progress of current production operations, check the history of past production operations, check trends or performance metrics from multiple production operations, change current processing parameters, and set processing steps to Continue to process or open a new process. In some examples, a remote computer (eg, a server) can provide a process recipe to the system over a network, including a local area network or the Internet. The remote computer may include a human interface that enables entry or programmatic execution of parameters and/or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters of each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed, to the type of tool with which the controller is to interface or control. Thus, as noted above, the controller can be distributed, such as by including one or more discrete controllers that are networked and operate toward a common purpose (such as the process and control described herein). An example of a distribution controller of such a purpose may be one or more integrated circuits in the chamber that are in communication with one or more integrated circuits located at a remote location (eg, at a platform level or a portion of a remote computer). They are combined to control the process on the chamber.

Without limitation, the exemplary system may include a plasma etch chamber or module, a deposition chamber or module, a rotary cleaning chamber or module, a metal plating chamber or module, a cleaning chamber, or a mold. Group, bevel etch chamber or module, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, atomic layer deposition (ALD) chamber or module, atom Layer etching (ALD) chambers or modules, ion implantation chambers or modules, track chambers or modules, semiconductor processing systems associated with or for the production and/or manufacture of semiconductor wafers.

As mentioned above, depending on one or more process steps to be performed by the tool, the controller 1040 can be in communication with one or more other tool circuits and modules, other tool components, cluster tools, other tool interfaces, adjacent Tools, adjacent tools, tools located throughout the plant, host computer, another controller, or tools for carrying wafer containers to and from the tool location and/or loading material in a semiconductor manufacturing facility.

The plasma processing apparatus 1000 can be configured to remove the polysilicon layer from the wafer 1020. The wafer 1020 includes a polysilicon layer and at least one of an oxide layer and a nitride layer. In some embodiments, wafer 1020 further includes a native oxide layer on the polysilicon layer. The plasma processing apparatus 1000 can include a remote plasma source 1050 and a wafer support 1010 for supporting the wafer 1020 and outside of the remote plasma source 1050. The plasma processing apparatus 1000 further includes a controller 1040 configured to provide instructions to: (a) flow a process gas 1002 (eg, an etchant) comprising a hydrogen-based species to a fluorine-based species to a remote plasma source In 1050, wherein the concentration of the hydrogen-based species is greater than the concentration of the fluorine-based species; (b) generating the distal plasma 1060 in the distal plasma source 1050, wherein the distal plasma 1060 includes activation of the hydrogen-based species and the fluorine-based species Species 1004 (eg, free radicals); and (c) exposing the wafer 1020 to the remote plasma 1060 to remove the polysilicon layer, wherein the wafer 1020 is maintained within a temperature range such that the wafer 1020 is exposed to the distal end There is substantially no residue of solid by-products during the plasma 1060. In some embodiments, the nitride layer comprises at least one of a tantalum nitride layer and a titanium nitride layer, and the oxide layer comprises at least a thermal tantalum oxide layer. In some embodiments, the plasma processing apparatus 1000 further includes a showerhead 1054 between the wafer support 1010 and the remote plasma source 1050, wherein the plasma processing apparatus 1000 is configured to be in the remote plasma source 1050. An inductively coupled plasma 1060 is produced, and wherein the plasma processing apparatus 1000 is configured to create a capacitively coupled plasma 1030 between the wafer support 1010 and the showerhead 1054. In some embodiments, there may be more instructions to configure the controller 1040 to apply a bias to the wafer support 1010 to create at least one between the remote plasma source 1050 and the wafer support 1010. A capacitive coupling of the fluorine-based etchant 1030; and exposing the wafer 1020 to the capacitively coupled plasma 1030 to remove the native oxide layer, wherein the removal of the native oxide layer and the removal of the polysilicon layer are performed in situ. [lithographic patterning]

The apparatus/process described above can be used in conjunction with, for example, semiconductor components, displays, light emitting diodes, solar photovoltaic panels, lithographic patterning tools or processes for the production or manufacture of similar ones. Although not necessary, usually this tool/process will be used or performed together in a typical production facility. The lithographic patterning of the film layer typically involves some or all of the following operations, each of which can be performed with a number of possible tools: (1) the application of photoresist on the workpiece, ie using a spin-on or spray tool. a substrate; (2) curing the photoresist using a hot plate or furnace, or a UV curing tool; (3) exposing the photoresist to visible light, or ultraviolet light, or X-ray light using a tool such as a wafer stepper; 4) developing the photoresist to selectively remove the photoresist and thereby patterning it using a tool such as a wet trench; (5) transferring the photoresist pattern to the underlying layer by using a dry or plasma-assisted etching tool In the film or workpiece; and (6) the photoresist is removed using a tool such as an RF or microwave plasma photoresist stripper. [Other Embodiments]

While the illustrative embodiments and applications of the present invention have been shown and described herein, many variations and modifications are possible in the concept, scope, and spirit of the present invention, and these changes are in the field after reading this application. Usually the knowledge will become clear. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the invention

100‧‧‧Component structure
110‧‧‧Polysilicon layer
120‧‧‧Under layer
130‧‧‧Vertical structure
200‧‧‧Component structure
210‧‧‧Polysilicon layer
220‧‧‧Under layer
230‧‧‧Vertical structure
240‧‧‧Primary yttrium oxide layer
300‧‧‧finFET structure
305‧‧‧Semiconductor wafer
305a‧‧‧Fins
310‧‧‧Polysilicon layer
320‧‧‧Dielectric materials
330‧‧‧矽Nitride liner
340‧‧‧ mask
400a‧‧‧Component structure
400b‧‧‧Component structure
420‧‧‧Under layer
430‧‧‧Vertical structure
440‧‧‧ recess
450‧‧‧Salt residue
600‧‧‧Process
605‧‧‧ square
610‧‧‧ square
615‧‧‧ square
620‧‧‧ square
900‧‧‧Process
905‧‧‧ square
910‧‧‧ square
915‧‧‧ square
920‧‧‧ squares
925‧‧‧ square
930‧‧‧ square
935‧‧‧ square
1000‧‧‧ equipment
1002‧‧‧Processing gas
1004‧‧‧Activated species
1006‧‧‧ gas or gas mixture
1010‧‧‧ Wafer Supports
1020‧‧‧ wafer
1025‧‧‧Processing chamber
1030‧‧‧ Plasma
1040‧‧‧ Controller
1050‧‧‧Remote plasma source
1052‧‧‧ gas inlet
1054‧‧‧Sprinkler
1056‧‧‧ coil
1056a‧‧‧Top coil
1056b‧‧‧ bottom coil
1060‧‧‧ Plasma

1 illustrates a cross-section of an exemplary structure having a polysilicon layer on a lower layer and having multiple vertical structures.

Figure 2 illustrates a cross section of an example of the structure of a native tantalum oxide layer on a polycrystalline germanium layer and a polycrystalline germanium layer.

3A illustrates a three-dimensional schematic of a portion of an exemplary fin field effect transistor (FinFET) structure.

FIG. 3B illustrates an enlarged view of the exemplary FinFET structure of FIG. 3A after etching the polysilicon.

FIG. 3C illustrates another enlarged view of the exemplary FinFET structure of FIG. 3A after etching the polysilicon.

4A is a schematic cross-sectional view showing the structure of an element having a salt residue after etching a polysilicon.

4B is a schematic cross-sectional view showing the structure of an element having no salt residue after etching polycrystalline germanium.

5A to 5C show Fourier transform infrared spectroscopy (FTIR) patterns having vibration peaks for detecting ammonium hexafluoroantimonate ((NH ₄ ) ₂ SiF ₆ ) in various temperature states.

Figure 6 shows a flow diagram of an exemplary process for removing polysilicon from a wafer.

Figure 7 illustrates a graph showing the polysilicon etch rate as a function of temperature.

Figure 8A shows polysilicon etch uniformity on a wafer of an exemplary single zone electrostatic chuck.

Figure 8B shows polysilicon etch uniformity on a wafer of an exemplary multi-zone electrostatic chuck.

Figure 9 shows a flow diagram of an exemplary process for removing native oxide and polysilicon from a wafer.

Figure 10 shows a schematic diagram of a plasma processing apparatus for performing a process for removing polysilicon from a wafer.

1000‧‧‧ equipment

1002‧‧‧Processing gas

1004‧‧‧Activated species

1006‧‧‧ gas or gas mixture

1010‧‧‧ Wafer Supports

1020‧‧‧ wafer

1025‧‧‧Processing chamber

1030‧‧‧ Plasma

1040‧‧‧ Controller

1050‧‧‧Remote plasma source

1052‧‧‧ gas inlet

1054‧‧‧Sprinkler

1056‧‧‧ coil

1056a‧‧‧Top coil

1056b‧‧‧ bottom coil

1060‧‧‧ Plasma

Claims (25)

A method for removing a polysilicon layer from a wafer, the method comprising: providing a wafer having a polysilicon layer; flowing an etchant comprising a hydrogen species and a fluorine species to a remote plasma source, Wherein the concentration of the hydrogen-based species is greater than the concentration of the fluorine-based species; generating a distal plasma in the distal plasma source, wherein the distal plasma comprises the radical of the hydrogen-based species and the fluorine-based species; And exposing the wafer to the remote plasma to remove the polysilicon layer, wherein the wafer is maintained within a temperature range such that the wafer is substantially free of solid byproducts during exposure to the remote plasma Residues. A method of removing a polysilicon layer from a wafer as in claim 1 wherein the wafer comprises an exposed nitride and/or oxide structure. A method of removing a polysilicon layer from a wafer according to claim 2, wherein the exposed nitride structure comprises at least one of tantalum nitride and titanium nitride, and wherein the exposed oxide structure comprises at least heat Oxide. A method of removing a polysilicon layer from a wafer as in claim 2, wherein the polycrystalline germanium has a selectivity to the exposed nitride and/or oxide structure of greater than about 500:1 during removal of the polysilicon layer. A method of removing a polycrystalline germanium layer from a wafer according to claim 1, wherein the hydrogen-based species comprises hydrogen or ammonia, and wherein the fluorine-based species comprises nitrogen trifluoride or carbon tetrafluoride. A method of removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the temperature range is less than about 120 °C. A method of removing a polysilicon layer from a wafer as in claim 6 wherein the temperature range is less than about 60 °C. A method of removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the wafer is exposed to the remote plasma in a chamber having a pressure of less than about 5 Torr. A method of removing a polysilicon layer from a wafer as in claim 8 wherein the wafer is exposed to the remote plasma in a chamber having a pressure of less than about 1 Torr. The method of removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the wafer is supported on an electrostatic chuck having a plurality of hot regions configured to define a crystal A plurality of different temperatures within the circle. The method for removing a polysilicon layer from a wafer according to claim 10, further comprising: applying a plurality of different temperatures in the hot zone of the electrostatic chuck during exposing the wafer to the remote plasma To improve the uniformity of the removal of the polysilicon layer. A method of removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the polysilicon layer is removed at an etch rate of greater than about 2000 Å per minute. The method of removing a polycrystalline germanium layer from a wafer according to any one of claims 1 to 5, wherein the concentration of the fluorine-based species is between about 0.7% and about 10% by volume, and wherein the hydrogen-based species The concentration is greater than about 50% by volume. The method of removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the etchant further comprises a modified gas species different from the fluorine-based species, wherein the modified gas species comprises At least one of nitrogen trifluoride, carbon tetrafluoride, fluoromethane, and sulfur hexafluoride. A method of removing a polycrystalline germanium layer from a wafer according to claim 14 wherein the concentration of one of the modified gas species is less than about 10% by volume. The method for removing a polysilicon layer from a wafer according to any one of claims 1 to 5, wherein the wafer is supported on an electrostatic chuck, and the wafer is further included on the polysilicon layer. The primary oxide layer, the method further comprising: applying a bias voltage to the electrostatic chuck to generate a capacitive coupling plasma of at least one fluorine-based etchant between the remote plasma source and the electrostatic chuck; And exposing the wafer to the capacitively coupled plasma to remove the native oxide layer, wherein removal of the native oxide layer and removal of the polysilicon layer are performed in situ. An apparatus for removing a polysilicon layer from a wafer, the apparatus comprising: a plasma etch chamber, wherein the plasma etch chamber comprises: a remote plasma source; and a wafer support, the wafer The support member is configured to support a wafer and is outside the remote plasma source, wherein the wafer comprises a polysilicon layer and at least one of an oxide layer and a nitride layer; a controller configured to provide An instruction to: (a) flow an etchant comprising a hydrogen-based species and a monofluoro species to the remote plasma source, wherein one of the hydrogen-based species is greater than the fluorine-based species a concentration; (b) generating a distal plasma in the distal plasma source, wherein the distal plasma comprises the hydrogen-based species and the free radical of the fluorine-based species; (c) exposing the wafer to The remote plasma removes the polysilicon layer, wherein the wafer is maintained within a temperature range such that the wafer is substantially free of solid byproduct residues during exposure to the remote plasma. The apparatus for removing a polysilicon layer from a wafer according to claim 17 of the patent application, further comprising: a shower head between the wafer support and the remote plasma source, wherein the shower head is between the wafer support and the remote plasma source, wherein The plasma processing chamber is configured to generate an inductively coupled plasma in the remote plasma source, and wherein the plasma processing chamber is configured to generate a between the wafer support and the showerhead Capacitively coupled plasma. An apparatus for removing a polysilicon layer from a wafer, according to claim 17, wherein the wafer support comprises a plurality of thermal zones configured to define a plurality of different temperatures of the wafer range. An apparatus for removing a polysilicon layer from a wafer according to claim 17 wherein the nitride layer comprises at least one of a tantalum nitride layer and a titanium nitride layer, and wherein the oxide layer comprises at least one heat矽 oxide layer. An apparatus for removing a polycrystalline germanium layer from a wafer, wherein the hydrogen-based species comprises hydrogen or ammonia, and wherein the fluorine-based species comprises nitrogen trifluoride or carbon tetrafluoride, as in claim 17 of the patent application. An apparatus for removing a polysilicon layer from a wafer, according to any one of claims 17 to 21, wherein the temperature range is less than about 60 °C. An apparatus for removing a polysilicon layer from a wafer, according to any one of claims 17 to 21, wherein the pressure in the plasma etch chamber is less than about 1 Torr. The apparatus for removing a polysilicon layer from a wafer according to any one of claims 17 to 21, wherein the etchant further comprises a modified gas species different from the fluorine-based species, wherein the modified gas The species includes at least one of nitrogen trifluoride, carbon tetrafluoride, fluoromethane, and sulfur hexafluoride. The apparatus for removing a polysilicon layer from a wafer according to any one of claims 17 to 21, wherein the wafer comprises a native oxide layer on the polysilicon layer, and wherein the controller is further configured There is an instruction to: apply a bias to the wafer support to create a capacitively coupled plasma of at least one fluorine-based etchant between the remote plasma source and the wafer support; The wafer is exposed to the capacitively coupled plasma to remove the native oxide layer, wherein removal of the native oxide layer and removal of the polysilicon layer are performed in situ.