TW201729176A - Display device and control method thereof - Google Patents

Abstract

A display device is provided, which includes a timing controller. The timing controller is configured to receive and output frame data when the display device is in a normal mode, and is configured to generate virtual frame data according to a control signal when the display device enters a self-refresh mode from the normal mode and to generate and output self-refresh frame data according to the last received frame data before the display device enters the self-refresh mode. The ratio of the virtual frame data to the self-refresh frame data is less than 1, and a non-zero phase difference exists between the rising edge of the virtual frame data and the rising edge of the self-refresh frame data.

Description

Display device and control method thereof

The present invention relates to a display device, and more particularly to a display device having a power saving function and a control method thereof.

The general display device has a graphics processing unit (GPU), which is responsible for processing the image data and generating the frame data, and sending the frame data to the video playing interface, so that the video playing interface plays according to the frame data. Image. In order to make the display device have a power saving effect, a buffer may be disposed in the display device, and the buffer may store the frame material from the graphics processing unit. When the nature of the image data is a still image, the image playing interface does not receive the frame data from the graphics processing unit, but receives the stored frame data from the buffer. Until the nature of the image data is converted into a motion image, the image playback interface receives the frame data from the graphics processing unit. As can be seen from the above, the display device is provided with a buffer to reduce the power consumption when playing a still image.

However, if only a small portion of the line data is updated in the frame data, the graphics processing unit must send the entire frame data to the video play interface instead of just sending the updated line data to the video play interface. Therefore, conventional display devices equipped with buffers still have the problem of excess power consumption.

An object of the present invention is to provide a display device and a control method thereof, which are characterized in that power consumption can be reduced, and the line data can be simultaneously stored and received when the display device enters the line update mode to ensure the image played by the display device. Correctness.

One aspect of the present invention is to provide a display device including a timing controller. The timing controller is configured to receive and output the frame data when the display device is in the normal mode, and generate a virtual frame signal according to the control signal when the display device enters the self-refresh mode from the normal mode. And generating and outputting self-updating frame data according to the last received frame data before the display device enters the self-updating mode. The timing controller includes a frame control unit and a multiplex unit. The frame control unit is configured to receive the frame data when the display device is in the normal mode, and to generate the self-updating frame data according to the last received frame data before the display device enters the self-updating mode when the display device is in the self-updating mode. . The multiplex unit is coupled to the frame control unit for determining output frame data or self-updating frame data according to the control signal. The period ratio of the virtual frame data to the self-updating frame data is less than 1, and there is a non-zero phase difference between the rising edge of the virtual frame data and the rising edge of the self-updating frame data.

In one or more embodiments, the timing controller further includes a clock generation unit, wherein the pulse generation unit is coupled to the frame control unit and configured to generate a clock signal, so that the frame control unit is based on the clock signal and Displaying the last received frame data before the device enters the self-updating mode to generate self-updating The frame data and the sub-frame data are generated based on the clock signal and the virtual frame data. If the rising edge of the attached frame data is after the rising edge of the virtual frame data, the frame control unit shortens the vertical blank period of the self-updating frame data. Conversely, if the rising edge of the attached frame data is before the rising edge of the virtual frame data, the timing controller extends the vertical blank period of the self-updating frame data.

In one or more embodiments, the display device further includes a frame buffer unit coupled to the timing controller and configured to store frame data, and the frame buffer unit is configured to be in the display device In the self-updating mode, the frame data last stored before the device enters the self-updating mode is output to the timing controller.

Another aspect of the present invention is to provide a control method for a display device, the control method comprising: receiving frame data when the display device is in a normal mode; and controlling the signal when the display device enters a self-updating mode from a normal mode The virtual frame data is generated, and the self-updating frame data is generated and output according to the last received frame data before the display device enters the self-updating mode; and the output frame data or the self-updating frame data is determined according to the control signal. The period ratio of the virtual frame data to the self-updating frame data is less than 1, and there is a non-zero phase difference between the rising edge of the virtual frame data and the rising edge of the self-updating frame data.

In one or more embodiments, the control method further includes: generating a self-updating frame data according to the clock signal and the last received frame data before the display device enters the self-updating mode, and according to the clock signal and the virtual frame data. To generate the attached frame data; if the rising edge of the attached frame data After the rising edge of the virtual frame data, the vertical blank period of the self-updating frame data is shortened; and if the rising edge of the auxiliary frame data is before the rising edge of the virtual frame data, the vertical of the self-updating frame data is extended. Blank period.

Another aspect of the present invention is to provide a display device including a timing controller. The timing controller is configured to receive and output frame data when the display device is in the normal mode, and generate virtual frame data according to the control signal when the display device enters the self-updating mode from the normal mode and before the display device enters the self-updating mode. Receive frame data to generate and output self-updating frame data. The timing controller includes a frame control unit and a multiplex unit. The frame control unit is configured to receive the frame data when the display device is in the normal mode, and to generate the self-updating frame data according to the last received frame data before the display device enters the self-updating mode when the display device is in the self-updating mode. . The multiplex unit is coupled to the frame control unit, and the multiplex unit is configured to determine the output frame data or the self-updating frame data according to the control signal. The timing controller is further configured to determine whether the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value, and the next rising edge of the self-updating frame data is The vertical blank period of the self-updating frame data is adjusted under the condition that the phase difference between the next rising edges of the virtual frame data is less than the critical value.

In one or more embodiments, if the timing controller determines that the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and self-updating the frame data Next time The rising edge is earlier than the next rising edge of the virtual frame data, and the timing controller shortens the vertical blank period of the self-updating frame data.

In one or more embodiments, if the timing controller determines that the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and self-updating the frame data The next rising edge is later than the next rising edge of the virtual frame data, and the timing controller shortens the vertical blank period of the self-updating frame data.

In one or more embodiments, if the timing controller determines that the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and self-updating the frame data The next rising edge is later than the next rising edge of the virtual frame data, and the timing controller extends the vertical blank period of the self-updating frame data.

In one or more embodiments, the display device further includes a frame buffer unit coupled to the timing controller and configured to store the frame data, and configured to be in the self-updating mode of the display device The frame data last stored before the display device enters the self-updating mode is output to the timing controller.

Another aspect of the present invention is to provide a control method for a display device, the control method comprising: receiving and outputting frame data when the display device is in a normal mode; and Controlling the signal to generate virtual frame data, and generating and outputting self-updating frame data according to the last received frame data before the display device enters the self-updating mode; determining the next rising edge and virtual frame data of the self-updating frame data Whether the phase difference between the next rising edge is less than a critical value The value; and if the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than the critical value, the vertical blank period of the self-updating frame data is adjusted.

In one or more embodiments, if the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and the next rising edge of the self-updating frame data is earlier On the next rising edge of the virtual frame data, the vertical blank period of the self-updating frame data is shortened.

In one or more embodiments, if the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and the next rising edge of the self-updating frame data is late On the next rising edge of the virtual frame data, the vertical blank period of the self-updating frame data is shortened.

In one or more embodiments, if the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value and the next rising edge of the self-updating frame data is late The next rising edge of the virtual frame data extends the vertical blank period of the self-updating frame data.

100‧‧‧ display device

110‧‧‧Image Processing Unit

120‧‧‧ Panel system

122‧‧‧Sequence Controller

124‧‧‧Frame buffer unit

126‧‧‧Display unit

210‧‧‧ Receiving unit

220‧‧‧Frame Control Unit

230‧‧‧Multiple units

240‧‧‧ clock generation unit

AUX‧‧‧Subject frame information

CTRL‧‧‧ control signal

LC _C , LC _PV ‧‧‧ line count

LI (1), LI (2) ‧ ‧ line input data

LO(1), LO(2), LO'(1)‧‧‧ line output data

PI‧‧‧ input signal

PO‧‧‧ output signal

PV‧‧‧virtual frame data

SS‧‧‧ Self-updating frame data

T1, t2‧‧‧ time point

TC‧‧‧ clock signal

VB _PV , VB _SS ‧‧‧ vertical blank period

VT _PV , VT _SS ‧‧‧full cycle

For a more complete understanding of the embodiments and the advantages thereof, the following description is made with reference to the accompanying drawings, wherein: FIG. 1 is a schematic diagram showing a display device according to an embodiment of the present invention; [Figure 1] Schematic diagram of the detailed architecture of the timing controller; [Fig. 3] is a schematic diagram showing the display device of Fig. 1 entering a self-refresh mode and a line update mode; [Fig. 4] is a diagram showing the simultaneous storage of line data to the frame of Fig. 2 The buffer unit and the schematic diagram of the line data sent from the frame buffer unit of FIG. 2; FIG. 5 shows the period ratio of the virtual frame and the self-updating frame data to 2/3 and the virtual map. The rising edge of the frame data and the rising edge of the self-updating frame data have a schematic diagram of the phase difference of not 0; [Fig. 6] shows the virtual frame data and the self-updating frame data after the phase of the clock signal is changed. A schematic diagram of a phase difference between 0; [FIG. 7] is a schematic diagram showing a period of shortening the vertical blank period of the subsidiary frame data and the self-updating frame data according to an embodiment of the present invention; A schematic diagram showing a vertical blank period of extending the auxiliary frame data and the self-updating frame data according to the embodiment of the present invention; [Fig. 9] and [Fig. 10] are diagrams showing the virtual frame data and the self-updating frame of the present invention. Sample timing diagram for data And [FIG. 11] to [FIG. 13] are schematic diagrams for adjusting self-updating frame data according to an embodiment of the present invention.

Embodiments of the invention are discussed in detail below. However, it will be appreciated that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific content. The examples discussed and disclosed are illustrative only and are not intended to limit the scope of the invention.

The term "coupled" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" may also mean two or A plurality of component elements operate or operate with each other.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the invention. The display device 100 includes an image processing unit 110 and a panel system 120. The image processing unit 110 is configured to transmit the input signal PI to the panel system 120. The panel system 120 includes a timing controller 122, a frame buffer unit 124, and a display panel 126. The timing controller 122 is coupled to the image processing unit 110, and receives the input signal PI sent by the image processing unit 110, and processes the input signal PI to generate a corresponding output signal PO. The frame buffer unit 124 is coupled to the timing controller 122, which stores the frame data of the timing controller 122 and sends the stored frame data to the timing controller 122. The display panel 126 is coupled to the timing controller 122 and receives the output signal PO and displays the corresponding image.

When the display device 100 performs video playback, the image processing unit 110 determines that the frame data is a still image signal or a motion picture signal. If the frame data is a motion picture signal, the input signal PI sent by the image processing unit 110 includes frame data, and the display device 100 is in the normal mode. After receiving the input signal PI, the timing controller 122 processes the input signal PI. The output signal PO generated by the timing controller 122 includes the frame data in the input signal PI, and the timing controller 122 sends the output signal PO to the display panel 126, so that the display panel 126 plays the image corresponding to the frame material.

In contrast, if the frame data is a still image signal, the input signal PI sent by the image processing unit 110 includes a control signal, and the display device 100 enters from a normal mode to a self-refresh mode. After receiving the input signal PI, the timing controller 122 receives the frame data stored by the frame buffer unit 124 according to the control signal in the input signal PI. The output signal PO generated by the timing controller 122 includes the frame data stored by the frame buffer unit 124, and the timing controller 122 sends the output signal PO to the display panel 126, so that the display panel 126 plays the image corresponding to the frame material. The frame data received by the timing controller 122 from the frame buffer unit 124 is also referred to as self-updating frame data.

An advantage of the display device 100 of FIG. 1 is that the image processing unit 110 may not send the frame data to the panel system 120 in the self-updating mode, and the display panel 126 plays the corresponding image according to the frame data stored by the frame buffer unit 124. image. Therefore, the display device 100 has the effect of reducing power consumption.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the detailed architecture of the timing controller 122 of FIG. As shown in FIG. 2, the timing controller 122 includes a receiving unit 210, a frame control unit 220, a multiplex unit 230, and a clock generating unit 240.

The receiving unit 210 receives the input signal PI from the image processing unit 110, and sends the signal in the input signal PI to the frame control unit 220 or the multiplex unit 230. If the input signal PI includes the frame data, the receiving unit 210 receives the input signal PI from the image processing unit 110, and sends the signal in the input signal PI to the frame control unit 220 or the multiplex unit 230. If you enter the message The number PI includes the frame data and the control signal, and the receiving unit 210 sends the frame data to the frame control unit 220 and the multiplex unit 230, and sends the control signal CTRL to the multiplex unit 230. If the input signal PI only includes the control signal, the receiving unit 210 sends the control signal CTRL to the multiplex unit 230.

The frame control unit 220 is coupled to the receiving unit 210 for receiving frame data from the receiving unit 210 when the display device 100 is in the normal mode, and sending the frame data to the frame buffer unit 124 for storage. The frame control unit 220 is further configured to generate self-updating frame data according to the last received frame data before the display device 100 enters the self-updating mode in the self-updating mode, and send the self-updating frame data to the multiplex Unit 230.

The multiplexing unit 230 is coupled to the receiving unit 210 and the frame control unit 220 for determining, according to the control signal CTRL, that the output signal PO includes the frame data received from the receiving unit 210 or the self received from the frame control unit 220. Update the frame data. If the display device 100 is in the normal mode, the control signal CTRL indicates that the output signal PO of the multiplex unit 230 contains the frame material received from the receiving unit 210. In contrast, if the display device 100 is in the self-updating mode, the control signal CTRL indicates that the output signal PO of the multiplex unit 230 includes the self-updating frame data received from the frame control unit 220.

The clock generation unit 240 is coupled to the frame control unit 220 for generating the clock signal TC and sending the clock signal TC to the frame control unit 220, so that the frame control unit 220 is based on the clock signal TC and the display device. 100 enters the last stored frame data of the frame buffer unit 124 before entering the self-updating mode to generate self-updating frame data.

In addition, the timing controller 122 can generate a virtual frame signal according to the control signal in the input signal PI when the display device 100 is in the self-updating mode. The virtual frame data generated by the timing controller 122 is synchronized with the frame data received by the timing controller 122 when the display device 100 is in the normal mode, so that the display device 100 can still obtain the rate and phase of the frame data in the self-updating mode. .

FIG. 3 is a schematic diagram showing the display device 100 of FIG. 1 entering a self-updating mode and a line updating mode. As shown in FIG. 3, when the display device 100 is in the normal mode, the input signal PI sent by the image processing unit 110 includes frame data, and the output signal PO sent by the timing controller 122 includes the same frame data. After the display device 100 enters the self-updating mode from the normal mode, the input signal PI sent by the image processing unit 110 does not include the frame data, and the output signal PO sent by the timing controller 122 is included in the display device 100 to enter the self-updating mode. The frame material that was previously sent by the image processing unit 110 and stored in the frame buffer unit 124. When the image processing unit 110 detects that there is updated line data in the frame data, the input signal PI sent by the image processing unit 110 includes the updated line data, and the display device 100 temporarily enters the line update mode. As shown in FIG. 3, after receiving the line data LI(1) and LI(2), the timing controller 122 sends the line data LI(1), LI(2) to the frame buffer unit 124, and the frame buffer unit. 124 then replaces the corresponding line data in the originally stored frame data with the line data LI(1) and LI(2), and then the display device 100 returns to the self-updating mode. After the line update mode, the frame buffer The frame data sent by the element 124 to the timing controller 122 includes line data LO(1), LO(2), and the line data LO(1), LO(2), that is, the line data LI sent by the image processing unit 110 ( 1), LI (2).

However, if the timing buffer 122 sends the updated line data to the frame buffer unit 124, the frame buffer unit 124 also sends the corresponding line data in the stored frame data to the timing controller 122, which may cause A problem occurs when the frame buffer unit 124 accesses the updated line material. Taking FIG. 4 as an example, when the timing controller 122 receives the line data LI(1) and sends the line data LI(1) to the frame buffer unit 124, the frame buffer unit 124 also sets the line data LO(1). It is sent to the timing controller 122 (the line data LO(1) and LI(1) correspond to the same section). After the line update mode, the line data LO-'(1) sent to the timing controller 122 by the frame buffer unit 124 may be different from the line data LI(1), resulting in an error in the image played by the display unit 126.

In order to avoid the problem of FIG. 4, in some embodiments of the present invention, the timing controller 122 may adjust the vertical blank period of the self-updating frame data SS such that the virtual frame data PV and the self-updating frame data The period ratio of the SS is less than 1, and the phase of the self-updating frame data SS can be adjusted such that there is a phase difference of not 0 between the rising edge of the virtual frame data PV and the rising edge of the self-updating frame data SS. As shown in FIG. 5, the period ratio of the virtual frame data PV to the self-updating frame data SS is 2/3, and the rising edge of the self-updating frame data SS is later than the rising edge of the virtual frame data PV. In this way, the situation in which the frame buffer unit 124 simultaneously stores and sends the line data can be avoided. Compared with only adjusting the phase of the self-updating frame data SS, the virtual frame data PV and the self-updating frame are compared. The material SS is not synchronized, and the above embodiment further adjusts the vertical blank period of the self-updating frame data SS such that the period ratio of the virtual frame data PV to the self-updating frame data SS is less than 1, thereby reducing the display device 100 in the self-updating mode. Power loss under.

However, since the virtual frame data PV is not established by the clock signal TC generated by the clock generating signal 240 of FIG. 2, the clock signal TC generated by the clock generating signal 240 of FIG. 2 may follow The time is changed by other external factors, causing the phase of the self-updating frame data SS to change, and the rising edge of the virtual frame data PV is aligned with the rising edge of the self-updating frame data SS (ie, the virtual image) The phase difference between the frame data PV and the self-updating frame data SS is 0), which causes the frame buffer unit 124 to simultaneously store and send the line data. As shown in FIG. 6, after the time point t1, the phase of the clock signal TC generated by the clock generation signal 240 changes, so that the phase of the self-updating frame data SS also changes, resulting in a virtual time at time t2. The phase difference between the frame data PV and the self-updating frame data SS is zero.

In order to avoid the situation that the frame buffer unit 124 simultaneously stores and sends the line data due to the phase change of the clock signal TC, in some embodiments of the present invention, the frame control unit 220 can further depend on the clock signal TC and the virtual map. The frame data PV is used to generate the auxiliary frame data AUX. In the case where the phase of the clock signal TC has not changed, the generated subsidiary frame material AUX is synchronized with the virtual frame data PV. If the frame control unit 220 detects that the auxiliary frame data AUX is not synchronized with the virtual frame data PV, the phase of the clock signal TC is changed, and the frame control unit 220 can According to the phase change condition of the auxiliary frame data AUX, the vertical blank period of the self-updating frame data SS is adjusted correspondingly.

As shown in FIG. 7, if the frame control unit 220 detects that the rising edge of the auxiliary frame data AUX is after the rising edge of the virtual frame data PV, the frame control unit 220 shortens the vertical blank of the self-updating frame data SS. period. On the other hand, if the frame control unit 220 detects that the rising edge of the auxiliary frame data AUX is after the rising edge of the virtual frame data PV, the frame control unit 220 extends the self-updating frame data SS. Vertical blank period.

After the adjustment of the self-updating frame data SS by the frame control unit 220, the phase difference between the virtual frame data PV and the self-updating frame data SS can be avoided to avoid the phase change of the clock signal TC. The frame buffer unit 124 simultaneously stores and sends out line data.

In some embodiments, the frame control unit 220 may determine whether the phase of the next virtual frame data PV and the next self-updating frame data SS are similar according to the virtual frame material PV and the self-updating frame data SS. FIG. 9 is an example of the next virtual frame data PV being similar to the next self-updating frame data SS. In Figure 9, VB _PV represents the vertical blank period of the virtual frame data PV, VT _PV represents the complete period of the virtual frame data PV, VB _SS represents the vertical blank period of the self-updating frame data SS, and VT _SS represents the self-updating map. The complete period of the frame data SS, and the LC _PV represents the line count value corresponding to the rising edge of the current virtual frame data PV. The frame control unit 220 can determine whether the phase of the next virtual frame data PV and the next self-updating frame data SS is based on the vertical blank period VB _PV , VB _SS , the full period VT _PV , the VT _{SS ,} and the line count value LC _PV similar.

The frame control unit 220 determines whether the phase of the next virtual frame material PV and the next self-updating frame data SS are similar as follows. If the line count value LC _PV satisfies the formula (1), the frame control unit 220 determines that the next virtual frame data PV is similar to the phase of the next self-update frame data SS: LC _C -TH _F <LC _PV <LC _C +TH _B , (1) where TH _F and TH _B are preset thresholds, which can be adjusted according to actual design requirements, and the line count value LC _C has a corresponding definition under different conditions. As shown in FIG. 9, under the condition that the VB _{SS is} smaller than the full period VT _{PV of the} virtual frame data PV and larger than the vertical blank period VB _PV of the virtual frame data PV during the vertical blank of the self-updating frame data SS, the line meter The value LC _C is (VB _SS + VT _SS - VT _PV ) +1. In contrast, as shown in FIG. 10, under the condition that the VB _{SS is} greater than the complete period VT _PV of the virtual frame data PV during the vertical blank period of the self-updating frame data SS, the line count value LC _C is (VB _SS -VT _PV ). +1.

11 to 13 are schematic diagrams showing adjustment of self-updating frame data SS according to an embodiment of the present invention. For convenience of explanation, FIGS. 11 to 13 are exemplified by the fact that the critical values TH _F and TH _{B are} greater than 1, but they are not intended to limit the scope of the present invention.

In some embodiments, under the condition that the online count value LC _PV satisfies the formula (1) and is greater than or equal to the line count value LC _C , the frame control unit 220 shortens the vertical blank period VB _{SS of the} self-updating frame data _SS . In FIG. 11, the line count value LC _{PV is} greater than the line count value LC _C and smaller than the line count value LC _C plus the threshold TH _B , and the frame control unit 220 determines the next virtual frame data PV and the next self. The phase of the updated frame data SS is similar (ie, less than the critical value TH _B ) and the next rising edge of the self-updating frame data SS is earlier than the next rising edge of the virtual frame data PV. In this case, the frame control unit 220 sets the next count cycle of the line count value to not start from 1, thereby shortening the vertical blank period VB _{SS of the} self-updating frame data SS, and increasing the self-updating frame data SS. The phase difference between the next rising edge and the next rising edge of the virtual frame data PV. For example, as shown in FIG. 11, the frame control unit 220 sets the next counting cycle of the line count value to start with 2, and thereby shortens the vertical blank period VB _{SS of the} self-updating frame data _SS from the original 5 Is 4.

Further, in some embodiments, under the condition that the online count value LC _PV simultaneously satisfies the formula (1) and is smaller than the line count value LC _C , the frame control unit 220 extends the vertical blank period VB _{SS of the} self-updating frame data _SS . In FIG. 12, the line count value LC _{PV is} smaller than the line count value LC _C and greater than the line count value LC _C minus the threshold TH _B , and the frame control unit 220 determines the next virtual frame data PV and the next self. The phase of the updated frame data SS is similar (ie, less than the threshold TH _F ) and the next rising edge of the self-updating frame data SS is later than the next rising edge of the virtual frame data PV. In this case, the frame control unit 220 sets the next counting cycle of the line count value to start with a plurality of 1, thereby extending the vertical blank period VB _{SS of the} self-updating frame data _SS , and increasing the self-updating frame data. The phase difference between the next rising edge of the SS and the next rising edge of the virtual frame data PV. For example, as shown in FIG. 12, the frame control unit 220 sets the next counting cycle of the line count value to start with two 1, and thereby the VB _SS of the vertical blank period V of the self-updating frame data SS is from the original 5 is extended to 6.

In addition, in some embodiments, under the condition that the online count value LC _PV satisfies the formula (1) and is smaller than the line count value LC _C , if the vertical blank period VB _SS of the self-updating frame data SS is not extended, the self-updating map is made. If the rate of the frame data SS is too low, the frame control unit 220 may further select to shorten the vertical blank period VB _{SS of the} self-updating frame data _SS . In FIG. 13, the line count value LC _{PV is} smaller than the line count value LC _C and greater than the line count value LC _C minus the threshold TH _B , and the frame control unit 220 determines the next virtual frame data PV and the next self. The phase of the updated frame data SS is similar (ie, less than the threshold TH _F ) and the next rising edge of the self-updating frame data SS is later than the next rising edge of the virtual frame data PV. In this case, the frame control unit 220 sets the next count cycle of the line count value to not start from 1, thereby shortening the vertical blank period VB _{SS of the} self-updating frame data SS, and increasing the self-updating frame data SS. The phase difference between the next rising edge and the next rising edge of the virtual frame data PV. For example, as shown in FIG. 13, the frame control unit 220 sets the next counting cycle of the line count value to start with 4, and thereby shortens the vertical blank period VB _{SS of the} self-updating frame data _SS from the original 5 Is 2.

In summary, the display device of the present invention not only has the effect of reducing power consumption, but also can prevent the line material from being simultaneously stored and received when the display device enters the line update mode, thereby ensuring the correctness of the image played by the display device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art may not deviate from the essence of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims.

100‧‧‧ display device

110‧‧‧Image Processing Unit

120‧‧‧ Panel system

122‧‧‧Sequence Controller

124‧‧‧Frame buffer unit

126‧‧‧Display unit

210‧‧‧ Receiving unit

220‧‧‧Frame Control Unit

230‧‧‧Multiple units

240‧‧‧ clock generation unit

CTRL‧‧‧ control signal

PI‧‧‧ input signal

PO‧‧‧ output signal

TC‧‧‧ clock signal

Claims (14)

A display device includes: a timing controller for receiving and outputting a frame material when the display device is in a normal mode, and entering a self-updating mode from the normal mode (self- Refresh mode) generates a virtual frame signal according to a control signal and generates and outputs a self-updating frame data according to the frame data finally received before the display device enters the self-updating mode, the timing The controller includes: a frame control unit configured to receive the frame data when the display device is in the normal mode, and to be used before the display device is in the self-updating mode according to the display device entering the self-updating mode Receiving the frame data to generate the self-updating frame data; and a multiplex unit coupled to the frame control unit, the multiplex unit is configured to output the frame data or the self according to the control signal Updating the frame data; wherein the ratio of the virtual frame data to the self-updating frame data is less than 1, and the virtual frame is Having a non-zero phase difference between the rising edge of the self-renewal frit frame data rising edge. The display device of claim 1, wherein the timing controller further comprises a clock generation unit, the clock generation unit is coupled to the frame control unit, and the clock generation unit is configured to generate a clock. a signal, such that the frame control unit is based on the clock signal and the display The frame data received last before the device enters the self-updating mode to generate the self-updating frame data and generate an auxiliary frame data according to the clock signal and the virtual frame data; wherein, if the auxiliary frame data After the rising edge of the virtual frame data, the frame control unit shortens the vertical blank period of the self-updating frame data; if the rising edge of the auxiliary frame data is in the virtual frame Before the rising edge of the data, the timing controller extends the vertical blank period of the self-updating frame data. The display device of claim 1, further comprising a frame buffer unit coupled to the timing controller, wherein the frame buffer unit is configured to store the frame data, and is configured to be in the display device The frame data last stored before the display device enters the self-updating mode is output to the timing controller in the self-updating mode. A control method for a display device, comprising: receiving a frame data when the display device is in a normal mode; generating a virtual image according to a control signal when the display device enters a self-updating mode from the normal mode Blocking data, and generating and outputting a self-updating frame data according to the frame data last received before the display device enters the self-updating mode; and determining to output the frame data or the self-updating frame data according to the control signal ; The period ratio of the virtual frame data to the self-updating frame data is less than 1, and the rising edge of the virtual frame data and the rising edge of the self-updating frame data have a non-zero phase difference. The control method of claim 4, further comprising: generating the self-updating frame data according to the clock signal and the last received frame data before the display device enters the self-updating mode, and according to the time And the virtual frame data to generate an auxiliary frame data; if the rising edge of the auxiliary frame data is after the rising edge of the virtual frame data, shortening the vertical blank period of the self-updating frame data; If the rising edge of the subsidiary frame data is before the rising edge of the virtual frame data, the vertical blank period of the self-updating frame data is extended. A display device includes: a timing controller for receiving and outputting a frame data when the display device is in a normal mode, and according to the display device entering the self-updating mode from the normal mode Controlling the signal to generate a virtual frame data and generating and outputting a self-updating frame data according to the frame data finally received before the display device enters the self-updating mode, the timing controller comprising: a frame control unit, And receiving the frame data when the display device is in the normal mode, and before the display device is in the self-updating mode, according to the display device entering the self-updating mode. The frame data is finally received to generate the self-updating frame data; and a multiplex unit is coupled to the frame control unit, and the multiplex unit is configured to output the frame data according to the control signal or Self-updating the frame data; wherein the timing controller is further configured to determine whether the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value, and The vertical blank period of the self-updating frame data is adjusted under the condition that the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value. The display device of claim 6, wherein the timing controller determines that a phase difference between a next rising edge of the self-updating frame material and a next rising edge of the virtual frame data is less than the The threshold value and the next rising edge of the self-updating frame data is earlier than the next rising edge of the virtual frame data, and the timing controller shortens the vertical blank period of the self-updating frame data. The display device of claim 6, wherein the timing controller determines that a phase difference between a next rising edge of the self-updating frame material and a next rising edge of the virtual frame data is less than the The threshold value and the next rising edge of the self-updating frame data is later than the next rising edge of the virtual frame data, and the timing controller shortens the vertical blank period of the self-updating frame data. The display device of claim 6, wherein the timing controller determines that a phase difference between a next rising edge of the self-updating frame material and a next rising edge of the virtual frame data is less than the The threshold value and the next rising edge of the self-updating frame data is later than the next rising edge of the virtual frame data, and the timing controller extends the vertical blank period of the self-updating frame data. The display device of claim 6, further comprising a frame buffer unit coupled to the timing controller, wherein the frame buffer unit is configured to store the frame data and is used to be in the display device The frame data last stored before the display device enters the self-updating mode is output to the timing controller in the self-updating mode. A control method for a display device, comprising: receiving and outputting a frame data when the display device is in a normal mode; generating a frame according to a control signal when the display device enters a self-updating mode from the normal mode Virtual frame data, and generating and outputting a self-updating frame data according to the last received frame data before the display device enters the self-updating mode; determining a next rising edge of the self-updating frame data and the virtual image Whether the phase difference between the next rising edge of the frame data is less than a critical value; and if the phase difference between the next rising edge of the self-updating frame data and the next rising edge of the virtual frame data is less than a critical value The value adjusts the vertical blank period of the self-updating frame data. The control method of claim 11, wherein a phase difference between a next rising edge of the self-updating frame data and a next rising edge of the virtual frame data is less than the critical value and the self-updating The next rising edge of the frame data is earlier than the next rising edge of the virtual frame data, and the vertical blank period of the self-updating frame data is shortened. The control method of claim 11, wherein a phase difference between a next rising edge of the self-updating frame data and a next rising edge of the virtual frame data is less than the critical value and the self-updating The next rising edge of the frame data is later than the next rising edge of the virtual frame data, and the vertical blank period of the self-updating frame data is shortened. The control method of claim 11, wherein a phase difference between a next rising edge of the self-updating frame data and a next rising edge of the virtual frame data is less than the critical value and the self-updating The next rising edge of the frame data is later than the next rising edge of the virtual frame data, and the vertical blank period of the self-updating frame data is extended.