TW201727785A - 一次安裝半導體裝置之製造方法 - Google Patents

一次安裝半導體裝置之製造方法 Download PDF

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Publication number
TW201727785A
TW201727785A TW105134941A TW105134941A TW201727785A TW 201727785 A TW201727785 A TW 201727785A TW 105134941 A TW105134941 A TW 105134941A TW 105134941 A TW105134941 A TW 105134941A TW 201727785 A TW201727785 A TW 201727785A
Authority
TW
Taiwan
Prior art keywords
sheet
semiconductor device
thermosetting resin
resin sheet
solder bump
Prior art date
Application number
TW105134941A
Other languages
English (en)
Chinese (zh)
Inventor
Chie Iino
Goji Shiga
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of TW201727785A publication Critical patent/TW201727785A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW105134941A 2015-10-28 2016-10-28 一次安裝半導體裝置之製造方法 TW201727785A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015211984A JP2017084973A (ja) 2015-10-28 2015-10-28 一次実装半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW201727785A true TW201727785A (zh) 2017-08-01

Family

ID=58631510

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105134941A TW201727785A (zh) 2015-10-28 2016-10-28 一次安裝半導體裝置之製造方法

Country Status (3)

Country Link
JP (1) JP2017084973A (ja)
TW (1) TW201727785A (ja)
WO (1) WO2017073434A1 (ja)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200394A (ja) * 2002-12-18 2004-07-15 Nitto Denko Corp 半導体装置の製造方法
JP5976573B2 (ja) * 2013-03-13 2016-08-23 日東電工株式会社 補強シート及び二次実装半導体装置の製造方法

Also Published As

Publication number Publication date
JP2017084973A (ja) 2017-05-18
WO2017073434A1 (ja) 2017-05-04

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