TW201725868A - Encoding and decoding using low-density parity-check matrices - Google Patents

Abstract

Technology for a user equipment (UE) operable to encode information for transmission to an eNodeB is disclosed. The UE can acquire a block of information bits. The UE can select a modulation and coding scheme. The UE can determine a matrix prototype and a code word sub-block size based on a size of the block of information bits and the modulation and coding scheme. The UE can encode at least a portion of the block of information bits to obtain an encoded code word block. At least the portion of the block of information bits can be encoded based on the matrix prototype and the code word sub-block size. The UE can select a subset of bits from the encoded code word block. The UE can generate the subset of bits for transmission to an eNodeB.

Description

Encoding and decoding techniques using low density parity check matrix

The present invention relates to encoding and decoding techniques using low density parity check matrices.

Wireless mobile communication technologies use various standards and protocols to transfer data between a node (e.g., a transmission station) and a wireless device (e.g., a mobile device). Some wireless devices use orthogonal frequency division multiplexing multiple access (OFDMA) in one downlink (DL) transmission and single carrier frequency division multiplexing multiple access (SC-FDMA) in one uplink (UL) ) to communicate. Standards and protocols for the use of Orthogonal Frequency Division Multiplexing (OFDM) for signal transmission include 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE), industry group commonly known as WiMAX (Worldwide Interoperability for Microwave Access) The Institute of Engineers (IEEE) 702.16 standard (eg 702.16e, 702.16m), and the industry group commonly known as the IEEE 702.11 standard for WiFi.

In a 3GPP Radio Access Network (RAN) LTE system, the node may be an Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (also often referred to as an evolved Node B, an enhanced Node B, an eNodeB, or eNB) and a combination of Radio Network Controllers (RNCs) that communicate with wireless devices called a User Equipment (UE). The downlink (DL) transmission may be from one of the nodes (e.g., eNodeB) to the wireless device (e.g., UE), and the uplink (UL) transmission may be from one of the wireless devices to the node. .

In accordance with an embodiment of the present invention, a user equipment (UE) apparatus is specifically provided for encoding information for transmission to an eNodeB, the apparatus comprising one or more processors and memory, configured to be And acquiring, by the UE, an information bit block; selecting, by the UE, a modulation and write code scheme; and determining, by the UE, a matrix based on a size of the information bit block and the modulation and write code scheme a prototype and a codeword sub-block size; at the UE, encoding at least a portion of the information bit block to obtain an encoded codeword block, wherein at least the portion of the information bit block is based on the matrix prototype and the codeword The sub-block size is encoded; at the UE, a subset of bits is selected from the encoded codeword block; and at the UE, the subset of bits for transmission to an eNodeB is generated.

Before the present technology is disclosed and described, it is to be understood that the invention is not limited to the specific structures, program acts or materials described herein, but rather extended to the equivalents thereof The person will recognize it. It should also be understood that the terminology used herein is for the purpose of describing particular examples and is not intended to be limiting. The same reference symbols in different figures represent the same elements. Numerical symbols provided in the flowcharts and the procedures are provided for the purpose of clearly illustrating the acts and operations, and do not necessarily indicate a particular order or order. Illustrative embodiment

An initial overview of one of the technical embodiments is provided below, and then specific technical embodiments are described in further detail below. This initial summary is intended to assist the reader in a more rapid understanding of the technology, but is not intended to identify key features or important features of the technology, and is not intended to limit the scope of the claimed content.

Information can be transmitted from a transmitter to a receiver via a communication channel. The noise inherent in the communication channel can cause errors in the transmitted information. In order to reduce the effect of noise in the communication channel, redundancy can be included in the transmission, and this redundancy enables the receiver to accurately reconstruct the original information regardless of the noise in the communication channel. This redundancy allows the receiver to detect a limited number of errors that occur during transmission and usually corrects these errors without retransmission.

Several possible code writing schemes can be used to determine the amount of redundancy to be included in the transmitted information and its nature. This form of redundancy can be redundant bits that can be added to the transmitted information. The coding scheme can vary depending on the degree of error correction desired, the complexity of decoding, the ability to locate/correct or recover from errors, the ability to correct burst errors, and various other characteristics. In addition, a number of symbols can be used for a particular code writing scheme, wherein such symbols can vary depending on the number of information bits and the number of redundant bits (or sometimes referred to as parity bits). These symbols can be systemic or non-systematic. Regarding systemic symbols, redundant bits can be added, for example, to the end of an information bit stream. Regarding non-systematic symbols, some or all of these information bits may not exist in a transmitted bit stream.

The code writing scheme to be used and the actual symbol can be selected based on various criteria. For example, these criteria include, for example, one of the transmission system's desired block error rate (BLER), a desired BLER, one of the associated transmissions associated with a particular symbol, an amount of processing to process the symbol, and the like. Additionally, a maximum error portion (or calibratable missing bit) can be determined based on the write code scheme used, such that different write code schemes can be adapted to different conditions.

An exemplary symbol that can be used to encode and decode information in a noisy communication channel is a low density parity check (LDPC) code. The LDPC code is an error correction code (also available for forward error correction or channel code). In other words, the transmitter can encode the data in a redundant manner using an LDPC code, and the receiver can decode the data using an LDPC decoding algorithm (e.g., belief propagation) such that any errors in transmission are corrected. The LDPC code is a parity check code having a parity check matrix containing one of the binary bits 0 and 1. The parity check matrix can be defined by a matrix dimension (eg, information block length and number of parity checks), the number of rows per row, and the number of columns per column. The 1 in the parity check matrix can be randomly distributed in the parity check matrix. For efficient encoding/decoding, the parity check matrix can be formed using only a single sub-matrix per row and per column. Therefore, for a given symbol, by selecting different dimensions by such sub-matrices, a plurality of parity check matrices having different block lengths can be formed.

In the present technology, an LDPC code can be used for a 3GPP system, such as a fifth generation (5G) cellular system. The LDPC code can include a parity check matrix that supports a defined write rate. The defined code rate can indicate a ratio of useful (non-redundant) data streams. For example, if the code rate is k/n, then for every k bits of useful information, the code generator generates n bits of the total codeword, where nk bits are redundant bits or parity bits. . In a particular example, the present specification describes an LDPC code having a parity check matrix that provides a write rate of 8/9 and can support one data rate of one billion bits per second (Gbps). This equivalence check matrix can be used to support different block sizes. In addition, these parity check matrices can be specifically targeted at 5G applications, and therefore are better than simply reusing the 802.11n LDPC parity check matrix.

In one example, the 3GPP LTE standard supports adaptive modulation and coding schemes. For example, the 3GPP LTE standard supports resource allocation, modulation and coding schemes, packet size (or transport block size), and a set of rate compatible channel write codes. Such adaptive modulation and coding schemes may support turbo codes with circular buffer rate matching based on Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ).

For 256 Quadrature Amplitude Modulation (QAM), the supported spectral efficiency set can range from 0.1 bits per second per second (bps/Hz) to 7.6 bps/Hz. The modulation and coding scheme (MCS) level can be defined to correspond to approximately 1 decibel (dB) spoke. The rate compatible channel write code can be used to encode a packet or transport block (TB) at an arbitrary write rate based on a selected MCS level, and multiple redundancy versions can be defined to support HARQ operations.

In one example, the 802.11n/11ac, LDPC code design is based on a limited set of code rates and block sizes. PHY Protocol Data Unit (PPDU) encoding rules can be used to encode and transmit a packet on a channel resource. The PPDU encoding rules may include mechanisms for encoding and transmitting the packet for shortening and puncture. In this shortening mechanism, a small size packet can be padded with zeros and encoded with a parity check matrix, and this padding zero can be removed after encoding to achieve an effective lower code rate. In this breakdown mechanism, a packet can be encoded with a parity check matrix, and the equivalent bit can be broken after encoding to increase the effective bit rate.

In one example, structured LDPC codes have been adopted in wireless technology standards such as IEEE 802.11n, IEEE 802.11ac, and IEEE 802.11ad. Structured LDPC codes based on shift unit matrices can tolerate vectorization operations that facilitate high throughput encoding and decoding. In addition, the structured LDPC code provides a framework to support multiple block sizes and code rates.

In one example, an LDPC code can have a codeword length n = z∙n _b , an information block k = z∙k _b , and a shift size or sub-block size z. This LDPC code may have a code rate r = k/n = k _b /n _{b ,} where the matrix prototype of this LDPC code (as defined below) has a dimension n _b - k _b xn _b . An LDPC encoder can encode the information block i = i ₀ , i ₁ , i ₂ ... i _k-1 into a codeword of size n, c = (c ₀ , c ₁ , . . . c _k-1 , c _k ....c _n-1 ). In systematic coding, the first k bits of this codeword are typically the same as the information bits, ie c _j = i _j , where j = 0 to k-1. The codeword c satisfies the parity check equation H∙c ^T = 0, where H is a nk xn parity check matrix. In other words, the LDPC code can have a specific code rate, and for a given number of information bits, a parity check bit can be added to the information bits. The parity check bit can be obtained by solving the parity check equation (H∙c ^T = 0).

In one example, in these structured LDPC codes, each parity check matrix can be partitioned into square blocks, or sub-matrices, of size zxz, where z is an integer. These sub-matrices may be a cyclic arrangement of a unit matrix (or shift unit matrix) or a imaginary matrix. A cyclic permutation matrix P _i can be obtained from the zxz identity matrix by cyclically shifting the row to the right by i elements.

Three different exemplary sub-matrices (P ₀ , P _{4 ,} and P ₂ ) are shown below. The matrix P _{0 is} a zxz identity matrix, where z=5. The matrix P ₀ is shifted to the right by a value of zero. The matrix P ₄ represents a unit matrix shifted to the right by a value of four. In other words, the columns of the matrix P _{0 are} rotated by 4 cycles to produce P ₀ . Similarly, P ₂ is shifted to the right by a value of two. Therefore, each column of the matrix P ₀ is rotated in 2 cycles to produce P ₂ . In addition, when each element of the sub-matrix is 0, a null matrix can be used. , ,

In one example, a matrix H_r89_z96 is shown below.

The matrix H_r89_z96 is used for a write rate of 8/9 with a matrix matrix equal to 96 (or z) and a codeword length equal to 3456. In the matrix H_r89_z96, each non-negative integer i represents a cyclic permutation matrix P _i , and a negative integer item (-1) or a virtual no item (-) represents a null or zero submatrix. The matrix H_r89_z96 has 4 columns and 36 rows. In order to achieve a code rate of 8/9, the parity check matrix can encode a 32*96 information size to obtain a codeword of 36*96, where 32*96 is the information bit, and 4*96 is Code word bit. In this case, n _b = 36, k _b = 32 and n _b - k _b = 4. The first item in the matrix H_r89_z96 is 31. This 31 is similar to P ₃₁ . In other words, a 96x96 unit matrix is rotated to the right by a value of 31, and this submatrix corresponds to 31 of the matrix H_r89_z96. Similarly, the second item in the matrix H_r89_z96 is 1, which indicates that the 96x96 unit matrix is rotated to the right by a value of one, and this submatrix corresponds to one of the matrices H_r89_z96. The matrix H_r89_z96 can be referred to as a matrix prototype. This matrix prototype is essentially used as a shorthand mark.

In the case of a 5G cellular system, for a write rate of 8/9, the supported code size can be defined for different shift sizes. For example, the supported shift size (z) may include 12, 24, 36, 48, 60, 72, 84, and 96. Suppose a matrix prototype has dimensions of 4 x 36 (ie, n _b = 36 and k _b = 32), which corresponds to the codeword block size of zx 36, which is equal to 432, 864, 1296, 1728, 2160, 2592, respectively. 3024 and 3456. This 4 x 36 matrix yields a write rate of (36 – 4) / 36 or 8/9. A matrix prototype can be provided for each codeword block size. To decode each of these matrix prototypes, each column can be treated as a parity check equation. The dashed line items in the matrix prototype column can participate in the parity check equation (ie H∙c ^T = 0), while the non-dashed items in the matrix prototype column do not participate in the parity check equation.

1A to 1H respectively show a matrix prototype corresponding to a sub-block size of 8/9 and a sub-block size of 12, 24, 36, 48, 60, 72, 84 and 96.

As shown in FIG. 1A, a matrix H_r89_z12 having a sub-block size or a shift size (z) of 12 is a 4x36 matrix as follows:

As shown in FIG. 1B, a matrix H_r89_z24 having a sub-block size or a shift size (z) of 24 is a 4x36 matrix as follows:

As shown in FIG. 1C, a matrix H_r89_z36 having a sub-block size or a shift size (z) of 36 is a 4x36 matrix as follows:

As shown in FIG. 1D, a matrix H_r89_z48 having a sub-block size or a shift size (z) of 48 is a 4x36 matrix as follows:

As shown in FIG. 1E, a matrix H_r89_z60 having a sub-block size or a shift size (z) of 60 is a 4x36 matrix as follows:

As shown in FIG. 1F, the matrix H_r89_z72 having a sub-block size or a shift size (z) of 72 is a 4x36 matrix as follows:

As shown in FIG. 1G, a matrix H_r89_z84 having a sub-block size or a shift size (z) of 84 is a 4x36 matrix as follows:

As shown in FIG. 1H, a matrix H_r89_z96 having a sub-block size or a shift size (z) of 96 is a 4x36 matrix as follows:

In one example, such prototype matrices can be designed to reduce periods of length 4 and length 6 in a Tanner graph corresponding to such prototype matrices. In the construction of this prototype matrix, when assigning a shift size to each item, the algorithm can run through different candidate values and select a suitable value that minimizes the number of cycles. In general, a Tanner graph is a bipartite graph that is used to describe the state constraints or equations that specify the error correction code. In the theory of writing codes, the Tanner graph can be used to construct longer symbols from smaller symbols, and both the encoder and the decoder can use the Tanner graph. These prototype matrix reductions correspond to the number of periods of length 4 and length 6 in the Tanner graph of the prototype matrices. Therefore, the LDPC codes corresponding to the prototype matrices have favorable block error rate performance and low error bottom. .

2 illustrates an exemplary technique for encoding information using a selection matrix prototype. A transmitting device can acquire an information block for transmission. The information block can include information bits (i). The transmitting device can identify one of the modulation and writing schemes associated with the transmission. The transmitting device can determine a matrix prototype and a sub-block size based on one of the size of the information block and the modulation and writing scheme. In some cases, the matrix prototype and sub-block size to be used may be explicitly indicated by the entity requesting the transmission. The selected matrix prototype and corresponding sub-block size may be one of the matrix prototypes shown in Figures 1A through 1H. The transmitting device may encode at least a portion of the information block based on the matrix prototype and the sub-block size to obtain an encoded codeword (c). The transmitting device can select a set of bits (d) from the encoded codeword for transmission to a receiving device. For a non-limiting example, the start bit of the encoded codeword can be selected for transmission.

For example, the information block size can be 3072 bits, and the modulation and write code scheme can correspond to the spectral efficiency of 5.4 bits per Hz per symbol, which corresponds to a 5.4/6 in 64-QAM. 0.9 write rate. This code rate can be supported using a parity check matrix of 8/9 write rate, so the transmitting device can determine a matrix prototype corresponding to a sub-block size of 3072/32 = 96 (as shown in Figure 1H). ). The matrix prototype and sub-block size can be used to encode the information block and obtain the codeword bits. After obtaining the codeword bits, the transmitting device can select a set of bits from the codeword bits (eg, 3072/0.9 rounded to the nearest multiple of 6, which is the modulation order of 64-QAM) to obtain Bit for transmission. These bits may correspond to one of the 5.4 bits per symbol per Hz. The transmitting device can transmit the set of bits to the receiving device.

FIG. 3 illustrates an exemplary technique for decoding information using a selection matrix prototype. A receiving device can acquire a received bit block (y), an information block size length, and an associated modulation and write code scheme. The receiving device can receive the bit block (y) from the transmitting device. The receiving device can determine a matrix prototype and a sub-block size based on the modulation and write code scheme and the information block size. The selected matrix prototype and corresponding sub-block size may be one of the matrix prototypes shown in Figures 1A through 1H. The receiving block can decode the received bit block based on the matrix prototype and the sub-block size to obtain an estimated information block (i).

In one example, the receiving device may decode the received bit block using a layered belief propagation scheme or another decoding technique for decoding the LDPC code. For example, a hierarchical belief propagation scheme can be used to decode the parity check matrix. If there is a defined number of columns in the parity check matrix, the columns can be considered as one layer. Faith propagation can solve the parity check equation by column. The first column can handle its parity check equation and the result of the first column can be passed to the second column. The second column can use the previous result to process its parity check equation, and the second column can pass its result to the third column, and so on.

Another example provides a User Equipment (UE) function 400 that is operable to encode information for transmission to an eNodeB, as shown in FIG. The UE may include one or more processors and memory that are configured to acquire an information bit block, such as block 410, for the UE. The UE may include one or more processors and memory that are configured to: at the UE, select a modulation and write code scheme, such as block 420, for the UE. The UE may include one or more processors and memory, and is configured to: determine, according to a size of the information bit block, and the modulation and write code scheme, a matrix prototype and a codeword. Sub-block size, such as block 430. The UE may include one or more processors and memory, and is configured to: at the UE, encode at least a portion of the information bit block to obtain an encoded codeword block, wherein the information bit block includes at least The portion is encoded based on the matrix prototype and the codeword sub-block size, such as block 440. The UE may include one or more processors and memory that are configured to select a subset of bits from the encoded codeword block, such as block 450, for the UE. The UE may include one or more processors and memory that are configured to generate the subset of bits for transmission to an eNodeB, such as block 460.

Another example provides a User Equipment (UE) functionality 500 that is operable to decode information received from an eNodeB, as shown in FIG. The UE may include one or more processors and memory, and is configured to: identify, by the UE, a bit block received from the eNodeB, wherein the bit block and a block size length and a modulation The code encoding scheme is associated, such as block 510. The UE may include one or more processors and memory, and is configured to: determine, according to the block size length and the modulation and write code scheme, a matrix prototype and a codeword sub-block size, As in block 520. The UE may include one or more processors and memory, and is configured to: decode, by the UE, the bit block received from the eNodeB to obtain a decoded information bit block, where the decoded information bit The block is derived based on the matrix prototype and the codeword sub-block size, as in block 530.

Another example provides at least one machine readable storage medium having instructions 600 embodied and encoded for decoding by an eNodeB, as shown in FIG. The instructions can be executed on a machine, where the instructions are included on at least one computer readable medium or a non-transitory machine readable storage medium. The instructions, when executed, perform: identifying one of the information bit blocks for transmission from the eNodeB to a user equipment (UE), such as block 610, using one or more processors of the eNodeB. The instructions, when executed, perform: determining, by the one or more processors of the eNodeB, a low density parity check (LDPC) based on a size of the information bit block, and a modulation and write code scheme The matrix and a codeword sub-block size, such as block 620. The instructions, when executed, perform: encoding, by the one or more processors of the eNodeB, at least a portion of the information bit block to obtain an encoded codeword block, wherein the information bit block includes at least Portions are encoded based on the LDPC matrix and the codeword sub-block size, as in block 630. The instructions, when executed, perform: selecting the one-bit subset from the encoded codeword block, such as block 640, using the one or more processors of the eNodeB. The instructions, when executed, perform: using the one or more processors of the eNodeB, formatting the subset of bits for transmission to UEs in the E-UTRAN, such as block 650.

FIG. 7 provides an illustration of a user equipment (UE) device 700 and a node 720. The UE device 700 can include a wireless device, a mobile station (MS), a mobile wireless device, a mobile communication device, a tablet, a handset, or other type of wireless device. The UE device 700 may include one or more antennas that are configured to communicate with a node 720 or a transmission station, such as a base station (BS), an evolved Node B (eNB), and a baseband unit (BBU). , a remote radio head (RRH), a remote radio equipment (RRE), a relay station (RS), a radio (RE), a remote radio unit (remote radio unit) , RRU), a central processing module (CPM), or other type of wireless wide area network (WWAN) access point. Node 720 can include one or more processors 722 and memory 724. The UE device 700 can be configured to communicate using at least one wireless communication standard including 3GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi. The UE device 700 can communicate using a separate antenna of each wireless communication standard or a shared antenna of a plurality of wireless communication standards. The UE device 700 can communicate in a wireless local area network (WLAN), a wireless personal area network (WPAN), and/or a WWAN.

In some embodiments, UE device 700 can include application circuitry 702, baseband circuitry 704, radio frequency (RF) circuitry 706, front end module (FEM) circuitry 708, and/or at least coupled as shown. A plurality of antennas 710.

Application circuitry 702 can include one or more application processors. For example, application circuitry 702 can include circuitry such as, but not limited to, one or more single core or multi-core processors. This (etc.) processor can include any combination of general purpose processors and proprietary processors (graphics processors, application processors, etc.). The processors can be coupled to a storage medium and/or can include the storage medium and can be configured to execute instructions stored in the storage medium to allow various applications and/or operating systems to operate on the system. .

The baseband circuitry 704 can include circuitry such as, but not limited to, one or more single core or multi-core processors. The baseband circuitry 704 can include one or more baseband processors and/or control logic to process the received baseband signals from one of the RF circuitry 706 and transmit the signalpath to one of the RF circuitry 706. The baseband signal is generated. The baseband processing circuitry 704 can interface with the application circuitry 702 for generating and processing such baseband signals and for controlling the operation of the RF circuitry 706. For example, in some embodiments, the baseband circuitry 704 can include a second generation (2G) baseband processor 704a, a third generation (3G) baseband processor 704b, and a fourth generation (4G) baseband. Processor 704c, and/or other existing baseband processor(s) 704d (eg, fifth generation (5G), 6G, etc.) of existing generations, developments, or future generations. The baseband circuitry 704 (e.g., one or more of the baseband processors 704a through 704d) can handle various radio control functions that allow communication with one or more radio networks via the RF circuitry 706. Such radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency offset, and the like. In some embodiments, the modulation/demodulation circuitry of the baseband circuitry 704 can include Fast Fourier Transform (FFT), precoding, and/or constellation mapping/demapping functionality. In some embodiments, the encoding/decoding circuitry of the baseband circuitry 704 may include convolution, tail code cancellation convolution, turbo, Viterbi, and/or low density parity check (LDPC) encoder/decode. Function. Embodiments of modulation/demodulation and encoder/decoder functions are not limited to these examples, and other suitable functions may be included in other embodiments.

In some embodiments, baseband circuitry 704 can include an element of a protocol stack, such as, for example, an element of an Evolved Universal Terrestrial Radio Access Network (EUTRAN) protocol, including, for example, physical (PHY), media access. Control (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), and/or Radio Resource Control (RRC) elements. A central processing unit (CPU) 704e of the baseband circuitry 704 can be configured to operate elements of this protocol stack for signaling by the PHY, MAC, RLC, PDCP, and/or RRC. In some embodiments, the baseband circuitry can include one or more audio digital signal processors (DSPs) 704f. The audio DSP(s) 704f may be or may include elements for compression/decompression and echo cancellation, and may include other suitable processing elements in other embodiments. In some embodiments, the components of the baseband circuitry can be suitably combined in a single wafer, in a single wafer set, or on the same circuit board. In some embodiments, some or all of the constituent components of the baseband circuitry 704 and the application circuitry 702 can be implemented together, such as, for example, on a system single chip (SOC).

In some embodiments, baseband circuitry 704 can be used to communicate with one or more radio technologies. For example, in some embodiments, the baseband circuitry 704 can support an evolved universal terrestrial radio access network (EUTRAN) and/or other wireless metropolitan area network (WMAN), a wireless local area network ( WLAN), a wireless personal area network (WPAN) communication. Embodiments in which baseband circuitry 704 is configured to support radio communications over more than one wireless protocol may be referred to as multimode baseband circuitry.

The RF circuitry 706 can allow communication with the wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, RF circuitry 706 can include switches, filters, amplifiers, etc. to facilitate communication with the wireless network. RF circuitry 706 can include a receive signal path that can include circuitry to downconvert the RF signal received from FEM circuitry 708 and provide a baseband signal to baseband circuitry 704. RF circuitry 706 can also include a transmit signal path that can include circuitry for upconverting the baseband signal provided by baseband circuitry 704 and providing RF output signals to FEM circuitry 708 for transmission. .

In some embodiments, RF circuitry 706 can include a receive signal path and a transmit signal path. The receive signal path of RF circuitry 706 can include mixer circuitry 706a, amplifier circuitry 706b, and filter circuitry 706c. The transmit signal path of RF circuitry 706 can include filter circuitry 706c and mixer circuitry 706a. RF circuitry 706 can also include synthesizer circuitry 706d for synthesizing a frequency for use by the receive signal path and mixer circuit 706a of the transmit signal path. In some embodiments, the mixer circuit circuitry 706a of the receive signal path can be configured to downconvert the RF signal received from the FEM circuitry 708 based on the synthesized frequency provided by the synthesizer circuitry 706d. Amplifier circuitry 706b can be configured to amplify the downconverted signals, and filter circuitry 706c can be configured to remove unwanted signals from the downconverted signals to produce one of the output baseband signals. Low pass filter (LPF) or band pass filter (BPF). The baseband circuitry 704 can be provided with an output baseband signal for further processing. In some embodiments, the output baseband signals may be zero frequency baseband signals, but this is not a requirement. In some embodiments, the mixer circuit 706a that receives the signal path can include a passive mixer, although the scope of such embodiments is not limited in this respect.

In some embodiments, the transmit signal path mixer circuit 706a can be configured to upconvert the input baseband signal to generate the FEM circuitry 708 based on the synthesized frequency provided by the synthesizer circuitry 706d. The RF output signal used. These baseband signals may be provided by baseband circuitry 704 and may be filtered by filter circuitry 706c. Filter circuitry 706c may include a low pass filter (LPF), although the scope of such embodiments is not limited in this respect.

In some embodiments, the mixer circuit 706a of the receive signal path and the mixer circuit 706a of the transmit signal path may include two or more mixers and may be arranged to be used for quadrature drop respectively. Frequency conversion and / or up conversion. In some embodiments, the mixer circuit circuitry 706a that receives the signal path and the mixer circuitry 706a of the transmit signal path can include two or more mixers and can be arranged for image rejection (eg, Hartley image exclusion). In some embodiments, the mixer circuit circuitry 706a and the mixer circuitry 706a of the receive signal path can be arranged for direct down conversion and/or direct up conversion, respectively. In some embodiments, the mixer circuit 706a of the receive signal path and the mixer circuit 706a of the transmit signal path can be configured for superheterodyne operation.

In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of such embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, RF circuitry 706 can include analog-to-digital converters (ADCs) and digital analog converter (DAC) circuitry, while baseband circuitry 704 can include a means for communicating with RF circuitry 706. Digital baseband interface.

In some dual mode embodiments, a separate radio IC for processing signals may be provided for each spectrum, although the scope of such embodiments is not limited in this respect.

In some embodiments, synthesizer circuitry 706d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of such embodiments is not limited in this respect as there may be other suitable types. Frequency synthesizer. For example, synthesizer circuitry 706d can be a delta-sigma synthesizer, a multiplier, or a synthesizer that includes a phase-locked loop with one of the dividers.

Synthesizer circuitry 706d can be configured to synthesize an output frequency for use by mixer circuitry 706a of RF circuitry 706 based on a frequency input and a divider control input. In some embodiments, synthesizer circuitry 706d can be a fractional N/N+1 synthesizer.

In some embodiments, the frequency input can be provided by a voltage controlled oscillator (VCO), but this is not a requirement. The divider control input can be provided by the baseband circuitry 704 or the application processor 702, depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) can be determined via a lookup table based on a channel indicated by application processor 702.

The synthesizer circuitry 706d of the RF circuitry 706 can include a divider, a delay locked loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the divider can be a dual modulus divider (DMD) and the phase accumulator can be a digital phase accumulator (DPA). In some embodiments, the DMD can be configured to divide the input signal by N or N+1 (eg, based on a carry output) to provide a fractional allocation ratio. In some exemplary embodiments, the DLL may include a set of cascades, adjustable, delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these embodiments, the delay elements can be configured to divide a VCO period into Nd equal phase packets, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through this delay line is one VCO period.

In some embodiments, synthesizer circuitry 706d can be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency can be a multiple of the carrier frequency (eg, twice the carrier frequency) Four times this carrier frequency), and can be used in conjunction with an orthogonal generator and divider circuitry for generating a plurality of signals having a plurality of different phases from each other at the carrier frequency. In some embodiments, this output frequency can be an LO frequency (fLO). In some embodiments, RF circuitry 706 can include an IQ/polarity converter.

FEM circuitry 708 can include a receive signal path that can include being configured to operate on RF signals received from one or more antennas 710, amplify such received signals, and provide RF circuitry 706 These enlarged versions of the circuitry that have received signals for further processing. The FEM circuitry 708 can also include a transmit signal path that can include circuitry configured to amplify the transmit signals provided by the RF circuitry 706 for transmission by one or more of the one or more antennas 710. .

In some embodiments, FEM circuitry 708 can include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry can include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry can include a low noise amplifier (LNA) for amplifying the received RF signal and providing the amplified received RF signal as an output (e.g., to RF circuitry 706). The transmit signal path of FEM circuitry 708 can include a power amplifier (PA) for amplifying an input RF signal (as provided by RF circuitry 706), and one or more for generating an RF signal (eg, A filter for subsequent transmission by one or more of one or more antennas 710.

8 provides an illustration of the wireless device, such as a user equipment (UE), a mobile station (MS), a mobile wireless device, a mobile communication device, a tablet computer, a handset, or other type of wireless device. . The wireless device can include one or more antennas that are configured to communicate with a node, a macro node, a low power node (LPN), or a transmission station, such as a base station (BS), an evolved node B (eNB), a baseband processing unit (BBU), a remote radio head (RRH), a remote radio (RRE), a relay (RS), a radio (RE), or other type Wireless Wide Area Network (WWAN) access point. The wireless device can be configured to communicate using at least one wireless communication standard such as, but not limited to, 3GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi. The wireless device can communicate using a separate antenna of each wireless communication standard or a shared antenna of a plurality of wireless communication standards. The wireless device can communicate in a wireless local area network (WLAN), a wireless personal area network (WPAN), and/or a WWAN. The wireless device can also include a wireless data unit. For example, the wireless data machine can include a wireless radio transceiver and a baseband circuitry (e.g., a baseband processor). In one example, the wireless data modem can modulate signals transmitted by the wireless device via the one or more antennas and demodulate signals received by the wireless device via the one or more antennas.

Figure 8 also provides an illustration of a microphone and one or more speakers that can be used for audio input and output of the wireless device. The display screen can be a liquid crystal display (LCD) screen, or other type of display screen, such as an organic light emitting diode (OLED) display. This display screen can be combined as a touch screen. This touch screen can use capacitive, resistive, or another type of touch screen technology. An application processor and a graphics processor can be coupled to internal memory to provide processing and display functions. A non-electrical memory port can also be used to provide data input/output to a user. The non-electrical memory port can also be used to extend the memory function of the wireless device. A keyboard can be integrated with the wireless device or wirelessly connected to the wireless device to provide additional user input. You can also use this touch screen to provide a virtual keyboard. Instance

The following examples are directed to specific technical embodiments and are intended to identify particular features, elements or acts, which may be used or otherwise combined to obtain such embodiments.

Example 1 includes an apparatus operative to encode information for transmission to a user equipment (UE) of an eNodeB, the apparatus comprising one or more processors and memory, configured to: Obtaining a information bit block; selecting a modulation and write code scheme for the UE; determining, according to a size of the information bit block, and the modulation and write code scheme, determining a matrix prototype and a a codeword sub-block size; at the UE, encoding at least a portion of the information bit block to obtain an encoded codeword block, wherein at least the portion of the information bit block is based on the matrix prototype and the codeword sub-block The size is encoded; at the UE, a subset of bits is selected from the encoded codeword block; and at the UE, the subset of bits is generated for transmission to an eNodeB.

Example 2 includes the apparatus of example 1, further comprising a baseband processor operable to: determine the matrix prototype and the codeword sub-block size based on the size of the information bit block and the modulation and write code scheme And encoding the at least the portion of the information bit block to obtain the encoded codeword block; and operable to transmit the subset of bits from the UE to one of the eNodeB transceivers.

Example 3 includes the apparatus of any one of examples 1 to 2, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9.

Example 4 includes the apparatus of any of examples 1 to 3, wherein the modulation and write coding scheme corresponds to one of a spectral efficiency of about 5.4 bits per hertz per symbol.

Example 5 includes the apparatus of any one of Examples 1 to 4, wherein the codeword sub-block size is 84, and the matrix prototype is:

Example 6 includes the apparatus of any one of examples 1 to 5, wherein the codeword sub-block size is 72, and the matrix prototype is:

Example 7 includes the apparatus of any one of examples 1 to 6, wherein the codeword sub-block size is 60, and the matrix prototype is:

Example 8 includes the apparatus of any one of examples 1 to 7, wherein the codeword sub-block size is 48, and the matrix prototype is:

Example 9 includes the apparatus of any one of examples 1 to 8, wherein the codeword sub-block size is 36, and the matrix prototype is:

Example 10 includes the apparatus of any one of examples 1 to 9, wherein the codeword sub-block size is 24 and the matrix prototype is:

Example 11 includes the apparatus of any one of examples 1 to 10, wherein the codeword sub-block size is 12, and the matrix prototype is:

Example 12 includes an apparatus operative to decode information received from an eNodeB, a user equipment (UE), the apparatus comprising one or more processors and memory, configured to: identify the UE Receiving a bit block from the eNodeB, wherein the bit block is associated with a block size length and a modulation and write code scheme; based on the block size length and the modulation and write code scheme of the UE Determining a matrix prototype and a codeword sub-block size; and decoding, by the UE, the bit block received from the eNodeB to obtain a decoded information bit block, wherein the decoded information bit block is based on the matrix The prototype and the code word sub-block size are obtained.

Example 13 includes the apparatus of example 12, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9.

Example 14 includes the apparatus of any one of examples 12 to 13, wherein the modulation and write coding scheme corresponds to one of a spectral efficiency of about 5.4 bits per hertz per symbol.

Example 15 includes the apparatus of any one of embodiments 12 to 14, wherein the codeword sub-block size is 84 and the matrix prototype is:

Example 16 includes the apparatus of any one of embodiments 12 to 15, wherein the codeword sub-block size is 72, and the matrix prototype is:

Example 17 includes the apparatus of any one of embodiments 12 to 16, wherein the codeword sub-block size is 60, and the matrix prototype is:

Example 18 includes the apparatus of any one of embodiments 12 to 17, wherein the codeword sub-block size is 48, and the matrix prototype is:

Example 19 includes the apparatus of any one of examples 12 to 18, wherein the codeword sub-block size is 36, and the matrix prototype is:

Example 20 includes the apparatus of any one of embodiments 12 to 19, wherein the codeword sub-block size is 24, and the matrix prototype is:

Example 21 includes the apparatus of any one of embodiments 12 to 20, wherein the codeword sub-block size is 12, and the matrix prototype is:

Example 22 includes at least one machine-readable storage medium having instructions embodied for encoding and decoding information at an eNodeB, the instructions being executed when the following program block: using one or more processors of the eNodeB, Identifying one of the information bit blocks for transmission from the eNodeB to a user equipment (UE); the one or more processors using the eNodeB, based on a size of the information bit block, and a modulation and writing code a method for determining a low density parity check (LDPC) matrix and a codeword sub-block size; using the one or more processors of the eNodeB, encoding at least a portion of the information bit block to obtain an encoded codeword block Wherein the at least the portion of the information bit block is encoded based on the LDPC matrix and the codeword sub-block size; using the one or more processors of the eNodeB, selecting a bit from the encoded codeword block a subset; and the one or more processors using the eNodeB, formatting the subset of bits for transmission to the UE.

The example 23 includes the at least one machine-readable storage medium of the example 22, further comprising instructions for performing the following program block when executed: identifying a bit block received from the UE, wherein the bit block and a second block The size length and a second modulation are associated with the write code scheme; determining a second matrix prototype and a second codeword sub-block size based on the second block size length and the second modulation and write code scheme; And decoding the bit block to obtain a decoded information bit block, wherein the decoded information bit block is obtained based on the second matrix prototype and the second code word sub-block size.

The example 24 includes the at least one machine-readable storage medium of any one of the examples 22 to 23, wherein: the matrix prototype corresponds to a write rate of 8/9; and the modulation and write code scheme corresponds to each Hertz The symbol is about 5.4 bits of spectral efficiency.

The example 25 includes the at least one machine-readable storage medium of any one of the examples 22 to 24, wherein: the codeword sub-block size is 84, and the matrix prototype is: The codeword sub-block size is 72, and the matrix prototype is: The codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is:

Example 26 includes an apparatus operative to encode information for transmission to a user equipment (UE) of an eNodeB, the apparatus comprising one or more processors and memory, configured to: Obtaining a information bit block; selecting a modulation and write code scheme for the UE; determining, according to a size of the information bit block, and the modulation and write code scheme, determining a matrix prototype and a a codeword sub-block size; at the UE, encoding at least a portion of the information bit block to obtain an encoded codeword block, wherein at least the portion of the information bit block is based on the matrix prototype and the codeword sub-block The size is encoded; at the UE, a subset of bits is selected from the encoded codeword block; and at the UE, the subset of bits is generated for transmission to an eNodeB.

Example 27 includes the apparatus of example 26, further comprising a baseband processor operative to: determine the matrix prototype and the codeword sub-block size based on the size of the information bit block and the modulation and write code scheme And encoding the at least the portion of the information bit block to obtain the encoded codeword block; and operable to transmit the subset of bits from the UE to one of the eNodeB transceivers.

Example 28 includes the apparatus of any one of embodiments 26 to 27, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9.

Example 29 includes the apparatus of any one of embodiments 26 to 28, wherein the modulation and write coding scheme corresponds to one of a spectral efficiency of about 5.4 bits per hertz per symbol.

Example 30 includes the apparatus of any one of embodiments 26 to 29, wherein: the codeword sub-block size is 84, and the matrix prototype is: the codeword sub-block size is 84, and the matrix prototype is: The codeword sub-block size is 72, and the matrix prototype is: Wherein the codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is:

Example 31 includes an apparatus operative to decode information received from an eNodeB, a user equipment (UE), the apparatus comprising one or more processors and memory, configured to: identify the UE Receiving a bit block from the eNodeB, wherein the bit block is associated with a block size length and a modulation and write code scheme; based on the block size length and the modulation and write code scheme of the UE Determining a matrix prototype and a codeword sub-block size; and decoding, by the UE, the bit block received from the eNodeB to obtain a decoded information bit block, wherein the decoded information bit block is based on the matrix The prototype and the code word sub-block size are obtained.

Example 32 includes the apparatus of example 31, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9.

Example 33 includes the apparatus of any one of examples 31 to 32, wherein the modulation and write coding scheme corresponds to one of a spectral efficiency of about 5.4 bits per hertz per symbol.

Example 34 includes the apparatus of any one of examples 31 to 33, wherein: the codeword sub-block size is 84, and the matrix prototype is: The codeword sub-block size is 72, and the matrix prototype is: Wherein the codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is:

Example 35 includes at least one machine-readable storage medium having instructions embodied for encoding and decoding information at an eNodeB, the instructions being executed when the following program block: using one or more processors of the eNodeB, Identifying one of the information bit blocks for transmission from the eNodeB to a user equipment (UE); the one or more processors using the eNodeB, based on a size of the information bit block, and a modulation and writing code a method for determining a low density parity check (LDPC) matrix and a codeword sub-block size; using the one or more processors of the eNodeB, encoding at least a portion of the information bit block to obtain an encoded codeword block Wherein the at least the portion of the information bit block is encoded based on the LDPC matrix and the codeword sub-block size; using the one or more processors of the eNodeB, selecting a bit from the encoded codeword block a subset; and the one or more processors using the eNodeB, formatting the subset of bits for transmission to the UE.

The example 36 includes the at least one machine-readable storage medium of the embodiment 35, further comprising instructions for performing the following program block when executed: identifying a bit block received from the UE, wherein the bit block and a second block The size length and a second modulation are associated with the write code scheme; determining a second matrix prototype and a second codeword sub-block size based on the second block size length and the second modulation and write code scheme; And decoding the bit block to obtain a decoded information bit block, wherein the decoded information bit block is obtained based on the second matrix prototype and the second code word sub-block size.

The example 37 includes at least one machine-readable storage medium of any one of examples 35 to 36, wherein: the matrix prototype corresponds to a write rate of 8/9; and the modulation and write code scheme corresponds to each Hertz The symbol is about 5.4 bits of spectral efficiency.

The example 38 includes at least one machine readable storage medium of any one of examples 35 to 37, wherein: the codeword sub-block size is 84, and the matrix prototype is: the codeword sub-block size is 84, and the matrix prototype Is: The codeword sub-block size is 72, and the matrix prototype is: The codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is:

Example 39 includes an eNodeB operable to encode and decode information, the eNodeB including: means for identifying an information bit block for transmission from the eNodeB to a user equipment (UE); for using the information element based on the information bit a means for determining a low density parity check (LDPC) matrix and a codeword subblock size by one of a block size and a modulation and write scheme; for encoding at least a portion of the information bit block to obtain an encoded Means of a codeword block, wherein at least the portion of the information bit block is encoded based on the LDPC matrix and the codeword sub-block size; means for selecting a subset of bits from the encoded codeword block And means for formatting the subset of bits for transmission to the UE.

The example 40 includes the eNodeB of the example 39, further comprising: means for identifying a bit block received from the UE, wherein the bit block and a second block size length and a second modulation and write code scheme Corresponding means for determining a second matrix prototype and a second codeword sub-block size based on the second block size length and the second modulation and writing scheme; and decoding the bit block And a means for obtaining a decoded information bit block, wherein the decoded information bit block is obtained based on the second matrix prototype and the second code word sub-block size.

Example 41 includes the eNodeB of any one of Examples 39 to 40, wherein: the matrix prototype corresponds to a write rate of 8/9; and the modulation and write code scheme corresponds to approximately 5.4 bits per Hz per symbol A spectral efficiency.

The example 42 includes the eNodeB of any one of the examples 39 to 41, wherein: the codeword sub-block size is 84, and the matrix prototype is: the codeword sub-block size is 84, and the matrix prototype is: The codeword sub-block size is 72, and the matrix prototype is: The codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is:

Various techniques, or some aspects or portions thereof, may take the form of, for example, a flexible magnetic disk, a CD-ROM, a hard disk drive, a non-transitory computer readable storage medium, or any other machine. A program (ie, an instruction) embodied in a tangible medium such as a storage medium is read, wherein when a machine such as a computer loads and executes the code, the machine becomes an apparatus for practicing the various techniques. A non-transitory computer readable storage medium can be a computer readable storage medium that does not include a signal. If the code is executed on a planable computer, the computing device can include a processor, a storage medium (including electrical and non-electrical memory and/or storage components) readable by the processor, at least An input device and at least one output device. The power-dependent and non-electrical memory and/or storage component may be a random access memory (RAM), an erasable programmable read-only memory (EPROM), a flash driver, an optical driver, A magnetic hard drive, solid state drive, or other medium used to store electronic data. The node and the wireless device may also include a transceiver module (ie, a transceiver), a counter module (ie, a counter), a processing module (ie, a processor), and/or a clock module (immediate pulse) or Timer module (ie timer). In one example, the selected component of the transceiver module can be located in a cloud radio access network (C-RAN). One or more of the various techniques described or implemented herein may use an application programming interface (API), reusable controls, and the like. Such programs can be implemented as a high-level procedural or object-oriented programming language for communicating with a computer system. However, this (etc.) program can be implemented as a combination or machine language as desired. In either case, the language can be a compiled or interpreted language and combined with a hardware implementation.

The term "circuitry" as used herein may mean, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, exclusive, or group), And/or memory (shared, exclusive, or group) that performs one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry can be implemented in one or more software or firmware modules, or the functionality associated with the circuitry can be implemented by one or more software or firmware modules. In some embodiments, the circuitry can include logic that is at least partially operable in hardware.

It should be understood that many of the functional units described in this specification have been labeled as modules to more specifically emphasize the factual independence. For example, a module can be implemented as a hard-wired circuit comprising a custom ultra-large integrated body (VLSI) circuit or gate array, an off-the-shelf semiconductor such as a logic die, a transistor, or other discrete component. A module can also be implemented as a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic devices, or the like.

Modules can also be implemented as software for execution by various types of processors. An identified executable code module, for example, can include one or more computer instruction entities or logic blocks, which can be organized, for example, into an object, program, or function. However, an executable file of an identified module may not be physically located in one place, but may include different instructions stored in different locations that, when logically coupled together, include the module and achieve the stated purpose of the module.

An executable code module can be a single instruction or many instructions, and can even be distributed over several different code segments, different programs, and several memory devices. Similarly, operational data may be identified and described herein within a module, and may be embodied in any suitable form and organized in any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed in different locations, including distributed to different storage devices, and may exist as an electronic signal at least partially on a system or network. These modules can be passive or active, including agents that are operable to perform the desired function.

Reference to "an example" or "exemplary" throughout this specification means that at least one embodiment of the present technology includes a particular feature, structure, or characteristic described in connection with the example. Thus, the words "in an embodiment" or "an"

When multiple items, structured elements, component elements, and/or materials are used herein, they may be presented in a common list for convenience. However, these lists should be treated as if each member of the list was individually identified as a different and unique member. Therefore, this list should not have individual members who are considered to be physically equal to any other member of the same list because they exist in a common group and have no contralateral indication. Additionally, various embodiments and examples of the technology may be referred to herein as alternatives to various components thereof. It is understood that such embodiments, examples, and alternatives are not considered as actual equivalents of each other, but rather as distinct and autonomous representations of the present technology.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Many specific details, such as layouts, distances, network instances, etc., are provided in the following description for a thorough understanding of embodiments of the present technology. However, it will be appreciated by those of ordinary skill in the art that the present technology may be practiced without one or more of the specific details, or other methods, components, arrangements, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the technology.

Although the foregoing examples illustrate the principles of the present technology in one or more specific applications, those of ordinary skill in the art will appreciate that many modifications can be made in the form, usage and details of the embodiments, but are not required. The inventive functions are also not deviated from the principles and concepts of the technology. Therefore, it is not intended that the present technology be limited by the scope of the invention as set forth below.

400, 500‧‧‧ Functions 410~460, 510~530, 610~650‧‧‧ Program Block 600‧‧‧Instruction 700‧‧‧UE Device 702‧‧‧Application Circuit System 704‧‧‧Base Frequency Circuit System 704a ~704d‧‧‧Base frequency processor 704e‧‧‧ central processing unit 704f‧‧‧ audio digital signal processor 706‧‧‧RF circuit system 706a‧‧‧ mixer circuit system 706b‧‧‧Amplifier circuit system 706c‧ ‧‧Filter Circuit System 706d‧‧‧Synthesizer Circuit System 708‧‧FEM Circuit System 710‧‧‧Antenna 720‧‧‧Node 722‧‧‧Processor 724‧‧‧ Memory

The features and advantages of the present disclosure will be apparent from the following description of the accompanying drawings in which <RTIgt; A matrix prototype corresponding to a code rate of 8/9 and sub-block sizes of 12, 24, 36, 48, 60, 72, 84 and 96; FIG. 2 illustrates a prototype using a selection matrix according to an example. 3 is a technique for encoding information; FIG. 3 illustrates a technique for decoding information using a selected matrix prototype according to an example; FIG. 4 illustrates a function of a user equipment (UE) according to an example, where the user equipment can The operation is used to encode information for transmission to an eNodeB. FIG. 5 illustrates a function of a user equipment (UE) operable to decode information received from an eNodeB according to an example. FIG. 6 is an implementation according to an implementation. For example, a flowchart of a machine readable storage medium embodied in an instruction for encoding and decoding information of an eNodeB is illustrated. FIG. 7 illustrates a wireless device (eg, a UE) and a node according to an example (eg, a simple one of eNodeB) ; And FIG. 8 according to an example, shows a wireless device (e.g. UE), a schematic view.

Reference will now be made to the exemplary embodiments illustrated, However, it will be appreciated that it is not intended to limit the scope of the technology.

Claims (25)

A user equipment (UE) device operative to encode information for transmission to an eNodeB, the apparatus comprising one or more processors and memory, configured to: acquire an information bit block for the UE Selecting a modulation and write code scheme for the UE; determining, by the UE, a matrix prototype and a codeword sub-block size based on a size of the information bit block and the modulation and write code scheme; Transmitting, by the UE, at least a portion of the information bit block to obtain an encoded codeword block, wherein at least the portion of the information bit block is encoded based on the matrix prototype and the codeword sub-block size; The encoded codeword block selects a subset of bits; and at the UE, generates the subset of bits for transmission to an eNodeB. The equipment of claim 1, further comprising: a baseband processor operable to: determine the matrix prototype and the codeword sub-block size based on the size of the information bit block and the modulation and write code scheme; And encoding the at least the portion of the information bit block to obtain the encoded codeword block; and the transceiver operable to transmit the subset of bits from the UE to the eNodeB. The apparatus of claim 1, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9. The apparatus of claim 1, wherein the modulation and write coding scheme corresponds to a spectral efficiency of about 5.4 bits per hertz per symbol. The apparatus of claim 1, wherein the codeword sub-block size is 84, and the matrix prototype is: The apparatus of claim 1, wherein the codeword sub-block size is 72, and the matrix prototype is: The apparatus of claim 1, wherein the codeword sub-block size is 60, and the matrix prototype is: The apparatus of claim 1, wherein the codeword sub-block size is 48, and the matrix prototype is: The equipment of claim 1, wherein the codeword sub-block size is 36, and the matrix prototype is: The equipment of claim 1, wherein the codeword sub-block size is 24, and the matrix prototype is: The equipment of claim 1, wherein the codeword sub-block size is 12, and the matrix prototype is: A user equipment (UE) device operable to decode information received from an eNodeB, the apparatus comprising one or more processors and memory, configured to: receive, by the UE, one of the eNodeBs received from the eNodeB a bit block, wherein the bit block is associated with a block size length and a modulation and write code scheme; and the UE determines a matrix prototype based on the block size length and the modulation and write code scheme a codeword sub-block size; and the UE, decoding the bit block received from the eNodeB to obtain a decoded information bit block, wherein the decoded information bit block is based on the matrix prototype and the codeword Obtained from the block size. The apparatus of claim 12, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a write rate of 8/9. The apparatus of claim 12, wherein the modulation and write coding scheme corresponds to a spectral efficiency of about 5.4 bits per hertz per symbol. The apparatus of claim 12, wherein the codeword sub-block size is 84, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 72, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 60, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 48, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 36, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 24, and the matrix prototype is: The apparatus of claim 12, wherein the codeword sub-block size is 12, and the matrix prototype is: An at least one non-transitory machine readable storage medium having instructions thereon for encoding and decoding information at an eNodeB, the instructions being executed as follows: using one or more processors of the eNodeB to identify Transmitting from the eNodeB to one of the user equipment (UE) information bit blocks; using the one or more processors of the eNodeB, determining based on a size of the information bit block and a modulation and write code scheme a low density parity check (LDPC) matrix and a codeword sub-block size; using the one or more processors of the eNodeB, encoding at least a portion of the information bit block to obtain an encoded codeword block, wherein at least The information bit block of the portion is encoded based on the LDPC matrix and the codeword sub-block size; using the one or more processors of the eNodeB, selecting a one-bit subset from the encoded codeword block; And using the one or more processors of the eNodeB, formatting the subset of bits for transmission to the UE. The non-transitory machine readable storage medium of claim 22, further comprising: executing, upon execution, an instruction to: identify a bit block received from the UE, wherein the bit block and a second block size length and a second modulation is associated with the write code scheme; determining a second matrix prototype and a second codeword sub-block size based on the second block size length and the second modulation and write code scheme; and decoding the The bit block obtains a decoded information bit block, wherein the decoded information bit block is obtained based on the second matrix prototype and the second code word sub-block size. A non-transitory machine readable storage medium as claimed in claim 22, wherein: the matrix prototype corresponds to a write rate of 8/9; and the modulation and write code scheme corresponds to one of about 5.4 bits per Hz per symbol Spectral efficiency. A non-transitory machine readable storage medium as claimed in claim 22, wherein: the codeword sub-block size is 84, and the matrix prototype is: The codeword sub-block size is 72, and the matrix prototype is: The codeword sub-block size is 60, and the matrix prototype is: The codeword sub-block size is 48, and the matrix prototype is: The codeword sub-block size is 36, and the matrix prototype is: The codeword sub-block size is 24, and the matrix prototype is: The codeword sub-block size is 12, and the matrix prototype is: