TW201722080A - Bus switching circuit and portable electronic device with same - Google Patents

Bus switching circuit and portable electronic device with same Download PDF

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Publication number
TW201722080A
TW201722080A TW104135964A TW104135964A TW201722080A TW 201722080 A TW201722080 A TW 201722080A TW 104135964 A TW104135964 A TW 104135964A TW 104135964 A TW104135964 A TW 104135964A TW 201722080 A TW201722080 A TW 201722080A
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Taiwan
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bus
terminal
electrically connected
control signal
switching circuit
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TW104135964A
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Chinese (zh)
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曾峰
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群邁通訊股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

The invention relates to a bus switching circuit and portable electronic device with same. The portable electronic device includes at least one peripheral component. The bus switching circuit includes a processing unit and at least one switching unit. The processing unit includes at least one bus terminal and at least one control signal output terminal. Each control signal output terminal outputs a control signal for controlling one switching unit to turn on or off.

Description

總線切換電路及具有該總線切換電路之可攜式電子裝置Bus switching circuit and portable electronic device having the same

本發明涉及一種總線切換電路及具有該總線切換電路之可攜式電子裝置。The invention relates to a bus switching circuit and a portable electronic device having the same.

目前，行動電話等可攜式電子裝置通常包括前後兩個攝像頭，且為達到高畫質要求，通常將前後攝像頭選用同像素同型號之產品。然而，同型號之攝像頭通常具有相同之I2C(Inter-Integrated Circuit)總線位址，而處理器或者於系統可程式設計（in-system programming，ISP）晶片有時往往僅能提供一路I2C總線給某一個攝像頭專用，這樣不可避免之存於尋址衝突之問題。At present, portable electronic devices such as mobile phones usually include two cameras at the front and the rear, and in order to achieve high image quality, the front and rear cameras are usually selected from the same type of products. However, the same type of camera usually has the same I2C (Inter-Integrated Circuit) bus address, and the processor or in-system programming (ISP) chip sometimes only provides one I2C bus to some A camera is dedicated, so it is inevitable that there is a problem of addressing conflicts.

針對上述問題，有必要提供一種可避免尋址衝突之總線切換電路。In view of the above problems, it is necessary to provide a bus switching circuit that can avoid addressing conflicts.

另外，有必要提供一種具有該總線切換電路之可攜式電子裝置。In addition, it is necessary to provide a portable electronic device having the bus switching circuit.

一種總線切換電路，應用於包括至少一個周邊元件之可攜式電子裝置中，所述總線切換電路包括處理單元以及至少一開關單元，所述處理單元包括至少一總線端以及與所述至少一開關單元數量相應之控制訊號輸出端，每一開關單元均包括與所述至少一總線端數量相應之輸入端、輸出端以及控制端，所述每一開關單元中每一輸入端分別電連接至相應之總線端，每一輸出端分別電連接至相應之周邊元件之總線引腳，所述每一開關單元中之控制端電連接於一起，且分別電連接至相應之控制訊號輸出端，每一控制訊號輸出端用以輸出相應之控制訊號，以控制相應之開關單元之導通或截止。A bus switching circuit for use in a portable electronic device including at least one peripheral component, the bus switching circuit including a processing unit and at least one switching unit, the processing unit including at least one bus terminal and the at least one switch a control signal output end corresponding to the number of units, each switch unit includes an input end, an output end, and a control end corresponding to the number of the at least one bus end, and each input end of each switch unit is electrically connected to the corresponding Each of the output terminals is electrically connected to a bus pin of a corresponding peripheral component, and the control terminals of each of the switch units are electrically connected together and electrically connected to respective control signal output terminals, respectively. The control signal output is used to output a corresponding control signal to control the on or off of the corresponding switch unit.

一種可攜式電子裝置，包括至少一周邊元件以及項所述之總線切換電路。A portable electronic device includes at least one peripheral component and a bus switching circuit as described.

本發明所述之可攜式電子裝置可藉由該控制訊號輸出端輸出相應之控制訊號，以選擇對應之周邊元件，進而使得所述周邊元件共用所述總線端，而不會出現選址衝突等情況。The portable electronic device of the present invention can output a corresponding control signal by the control signal output terminal to select a corresponding peripheral component, so that the peripheral component shares the bus terminal without occurrence of an address conflict. Waiting for the situation.

圖1為本發明較佳實施例之可攜式電子裝置之整體示意圖。1 is a schematic overall view of a portable electronic device according to a preferred embodiment of the present invention.

圖2為圖1所述可攜式電子裝置另一角度下之示意圖。2 is a schematic view of the portable electronic device of FIG. 1 from another angle.

圖3為圖1所述可攜式電子裝置中總線切換電路之電路圖。3 is a circuit diagram of a bus switching circuit in the portable electronic device of FIG. 1.

請參閱圖1及圖2，本發明較佳實施例之可攜式電子裝置100可為行動電話、平板電腦等。該可攜式電子裝置100包括主體部11、顯示單元12、第一攝像頭13、第二攝像頭15以及設置於所述主體部11內部之總線切換電路17。Referring to FIG. 1 and FIG. 2, the portable electronic device 100 of the preferred embodiment of the present invention may be a mobile phone, a tablet computer, or the like. The portable electronic device 100 includes a main body portion 11 , a display unit 12 , a first camera 13 , a second camera 15 , and a bus switching circuit 17 disposed inside the main body portion 11 .

該主體部11包括第一表面111以及與第一表面111相對設置之第二表面113。所述顯示單元12設置於所述第一表面111上。於本實施例中，該第一攝像頭13為主攝像頭，其設置於所述第二表面113上。所述第二攝像頭15為副攝像頭，其設置於所述第一表面111上，即設置於該顯示單元12所在平面，用於輔助用戶實現自拍等功能。可理解，該第一攝像頭13與第二攝像頭15之位置不局限於上述所述，其亦可其他方式排設。The body portion 11 includes a first surface 111 and a second surface 113 disposed opposite the first surface 111. The display unit 12 is disposed on the first surface 111. In this embodiment, the first camera 13 is a main camera and is disposed on the second surface 113. The second camera 15 is a sub-camera disposed on the first surface 111, that is, disposed on the plane of the display unit 12, to assist the user in implementing functions such as self-timer. It can be understood that the positions of the first camera 13 and the second camera 15 are not limited to the above, and they may be arranged in other manners.

請一併參閱圖3，該第一攝像頭13包括資料引腳SDA_CAM1及時鐘引腳SCL_CAM1。第二攝像頭15包括資料引腳SDA_CAM2及時鐘引腳SCL_CAM2。Referring to FIG. 3 together, the first camera 13 includes a data pin SDA_CAM1 and a clock pin SCL_CAM1. The second camera 15 includes a data pin SDA_CAM2 and a clock pin SCL_CAM2.

於本實施例中，該總線切換電路17包括處理單元171、第一開關單元173、第二開關單元174、第一電阻R1、第二電阻R2、第一上拉電路177以及第二上拉電路178。In this embodiment, the bus switching circuit 17 includes a processing unit 171, a first switching unit 173, a second switching unit 174, a first resistor R1, a second resistor R2, a first pull-up circuit 177, and a second pull-up circuit. 178.

該處理單元171可為中央處理器（central processing unit，CPU）或在系統可程式設計（in-system programming，ISP）晶片。該處理單元171包括資料端I2C_SDA、時鐘端I2C_SCL、第一控制訊號輸出端GPIO1以及第二控制訊號輸出端GPIO2。於本實施例中，該第一控制訊號輸出端GPIO1及第二控制訊號輸出端GPIO2均為通用輸入/輸出引腳。The processing unit 171 can be a central processing unit (CPU) or an in-system programming (ISP) chip. The processing unit 171 includes a data terminal I2C_SDA, a clock terminal I2C_SCL, a first control signal output terminal GPIO1, and a second control signal output terminal GPIO2. In this embodiment, the first control signal output terminal GPIO1 and the second control signal output terminal GPIO2 are general purpose input/output pins.

所述第一開關單元173包括第一場效應管Q1及第二場效應管Q2。所述第一場效應管Q1之源極作為第一開關單元173之第一輸入端，以電連接至所述資料端I2C_SDA。所述第二場效應管Q2之源極作為所述第一開關單元173之第二輸入端，以電連接至所述時鐘端I2C_SCL。所述第一場效應管Q1之汲極作為所述第一開關單元173之第一輸出端，以電連接至所述第一攝像頭13之資料引腳SDA_CAM1。所述第二場效應管Q2之汲極作為所述第一開關單元173之第二輸出端，以電連接至所述第一攝像頭13之時鐘引腳SCL_CAM1。所述第一場效應管Q1之閘極與第二場效應管Q2之閘極分別作為所述第一開關單元173之第一控制端及第二控制端，均電連接至所述第一控制訊號輸出端GPIO1。The first switching unit 173 includes a first field effect transistor Q1 and a second field effect transistor Q2. The source of the first FET Q1 serves as a first input terminal of the first switching unit 173 to be electrically connected to the data terminal I2C_SDA. The source of the second field effect transistor Q2 serves as a second input terminal of the first switching unit 173 to be electrically connected to the clock terminal I2C_SCL. The drain of the first field effect transistor Q1 serves as a first output end of the first switching unit 173 to be electrically connected to the data pin SDA_CAM1 of the first camera 13. The drain of the second field effect transistor Q2 serves as a second output end of the first switching unit 173 to be electrically connected to the clock pin SCL_CAM1 of the first camera 13. The gate of the first FET Q1 and the gate of the second FET Q2 serve as a first control end and a second control end of the first switch unit 173, respectively, and are electrically connected to the first control Signal output GPIO1.

所述第二開關單元174包括第三場效應管Q3及第四場效應管Q4。所述第三場效應管Q3之源極作為第二開關單元174之第一輸入端，以電連接至所述資料端I2C_SDA。所述第四場效應管Q4之源極作為所述第二開關單元174之第二輸入端，以電連接至所述時鐘端I2C_SCL。所述第三場效應管Q3之汲極作為所述第二開關單元174之第一輸出端，以電連接至所述第二攝像頭15之資料引腳SDA_CAM2。所述第四場效應管Q4之汲極作為所述第二開關單元174之第二輸出端，以電連接至所述第二攝像頭15之時鐘引腳SCL_CAM2。所述第三場效應管Q3之閘極與第四場效應管Q4之閘極分別作為所述第二開關單元174之第一控制端及第二控制端，均電連接至所述第二控制訊號輸出端GPIO2。The second switching unit 174 includes a third FET Q3 and a fourth FET Q4. The source of the third field effect transistor Q3 serves as a first input terminal of the second switching unit 174 to be electrically connected to the data terminal I2C_SDA. The source of the fourth field effect transistor Q4 serves as a second input terminal of the second switching unit 174 to be electrically connected to the clock terminal I2C_SCL. The drain of the third field effect transistor Q3 serves as a first output end of the second switching unit 174 to be electrically connected to the data pin SDA_CAM2 of the second camera 15. The drain of the fourth field effect transistor Q4 serves as a second output terminal of the second switching unit 174 to be electrically connected to the clock pin SCL_CAM2 of the second camera 15. The gate of the third field effect transistor Q3 and the gate of the fourth field effect transistor Q4 are respectively used as the first control end and the second control end of the second switch unit 174, and are electrically connected to the second control Signal output GPIO2.

所述第一電阻R1之一端連接至一供電電源VCC，另一端連接至所述資料端I2C_SDA。所述第二電阻R2之一端連接至所述供電電源VCC，另一端連接至所述時鐘端I2C_SCL。One end of the first resistor R1 is connected to a power supply VCC, and the other end is connected to the data terminal I2C_SDA. One end of the second resistor R2 is connected to the power supply VCC, and the other end is connected to the clock terminal I2C_SCL.

所述第一上拉電路177包括第一上拉電阻R3及第二上拉電阻R4。所述第一上拉電阻R3之一端連接至所述供電電源VCC，另一端連接至所述第一攝像頭13之資料引腳SDA_CAM1。所述第二上拉電阻R4之一端連接至所述供電電源VCC，另一端連接至所述第一攝像頭13之時鐘引腳SCL_CAM1。The first pull-up circuit 177 includes a first pull-up resistor R3 and a second pull-up resistor R4. One end of the first pull-up resistor R3 is connected to the power supply VCC, and the other end is connected to the data pin SDA_CAM1 of the first camera 13. One end of the second pull-up resistor R4 is connected to the power supply VCC, and the other end is connected to the clock pin SCL_CAM1 of the first camera 13.

所述第二上拉電路178包括第三上拉電阻R5及第四上拉電阻R6。所述第三上拉電阻R5之一端連接至所述供電電源VCC，另一端連接至所述第一攝像頭13之資料引腳SDA_CAM2。所述第四上拉電阻R6之一端連接至所述供電電源VCC，另一端連接至所述第二攝像頭15之時鐘引腳SCL_CAM2。The second pull-up circuit 178 includes a third pull-up resistor R5 and a fourth pull-up resistor R6. One end of the third pull-up resistor R5 is connected to the power supply VCC, and the other end is connected to the data pin SDA_CAM2 of the first camera 13. One end of the fourth pull-up resistor R6 is connected to the power supply VCC, and the other end is connected to the clock pin SCL_CAM2 of the second camera 15.

可理解，於其他實施例中，所述總線切換電路17還包括第一下拉電阻R7及第二下拉電阻R8。所述第一下拉電阻R7之一端連接至所述第一控制訊號輸出端GPIO1，另一端接地。所述第二下拉電阻R8之一端連接至所述第二控制訊號輸出端GPIO2，另一端接地。It can be understood that in other embodiments, the bus switching circuit 17 further includes a first pull-down resistor R7 and a second pull-down resistor R8. One end of the first pull-down resistor R7 is connected to the first control signal output terminal GPIO1, and the other end is grounded. One end of the second pull-down resistor R8 is connected to the second control signal output terminal GPIO2, and the other end is grounded.

請一併參閱表1，所述處理單元171可藉由該第一控制訊號輸出端GPIO1及所述第二控制訊號輸出端GPIO2輸出相應之控制訊號，以控制第一開關單元173與第二開關單元174之導通或截止，進而選擇相應之第一攝像頭13或第二攝像頭15，以使得所述處理單元171藉由I2C(Inter-Integrated Circuit)總線協定對所述第一攝像頭13或第二攝像頭15進行尋址。例如，當所述第一控制訊號輸出端GPIO1輸出高電平（例如邏輯1），所述資料端I2C_SDA為輸出，且輸出高電平（例如邏輯1）時，所述第一場效應管Q1之源極與閘極之間之電壓（VGS）為0伏特（即VGS=0），所述第一場效應管Q1截止，所述第一攝像頭13之資料引腳SDA_CAM1藉由第一上拉電阻R3連接至所述供電電源VCC，進而上拉至高電平。當所述資料端I2C_SDA為輸出，且輸出低電平（例如邏輯0）時，所述第一場效應管Q1之源極與閘極之間之電壓（VGS）為1.8伏特（即VGS=1.8v），所述第一場效應管Q1飽與導通，所述第一攝像頭13之資料引腳SDA_CAM1之電壓被拉低至低電平。Referring to Table 1, the processing unit 171 can output a corresponding control signal by the first control signal output terminal GPIO1 and the second control signal output terminal GPIO2 to control the first switch unit 173 and the second switch. The unit 174 is turned on or off, and then the corresponding first camera 13 or second camera 15 is selected such that the processing unit 171 is in agreement with the first camera 13 or the second camera by an I2C (Inter-Integrated Circuit) bus protocol. 15 for addressing. For example, when the first control signal output terminal GPIO1 outputs a high level (eg, logic 1), the data terminal I2C_SDA is an output, and outputs a high level (eg, logic 1), the first field effect transistor Q1 The voltage between the source and the gate (VGS) is 0 volts (ie, VGS=0), the first field effect transistor Q1 is turned off, and the data pin SDA_CAM1 of the first camera 13 is pulled by the first pull-up The resistor R3 is connected to the power supply VCC, and is pulled up to a high level. When the data terminal I2C_SDA is an output and outputs a low level (for example, a logic 0), the voltage (VGS) between the source and the gate of the first FET Q1 is 1.8 volts (ie, VGS=1.8) v), the first field effect transistor Q1 is fully turned on, and the voltage of the data pin SDA_CAM1 of the first camera 13 is pulled low to a low level.

當所述第一控制訊號輸出端GPIO1輸出低電平（例如邏輯0），所述資料端I2C_SDA為輸出，且輸出高電平（例如邏輯1）時，所述第一場效應管Q1之源極與閘極之間之電壓（VGS）小於0伏特（即VGS<0），所述第一場效應管Q1截止，所述第一攝像頭13之資料引腳SDA_CAM1之電壓藉由所述第一上拉電阻R3連接至所述供電電源VCC，進而上拉至高電平。當所述資料端I2C_SDA為輸出，且輸出低電平（例如邏輯0）時，所述第一場效應管Q1之源極與閘極之間之電壓（VGS）為0伏特（即VGS=0），所述第一場效應管Q1截止，所述第一攝像頭13之資料引腳SDA_CAM1之電壓藉由所述第一上拉電阻R3連接至所述供電電源VCC，進而上拉至高電平。When the first control signal output terminal GPIO1 outputs a low level (for example, logic 0), the data terminal I2C_SDA is an output, and outputs a high level (for example, logic 1), the source of the first FET Q1 The voltage between the pole and the gate (VGS) is less than 0 volts (ie, VGS<0), the first field effect transistor Q1 is turned off, and the voltage of the data pin SDA_CAM1 of the first camera 13 is by the first The pull-up resistor R3 is connected to the power supply VCC, and is pulled up to a high level. When the data terminal I2C_SDA is an output and outputs a low level (for example, a logic 0), the voltage (VGS) between the source and the gate of the first FET Q1 is 0 volt (ie, VGS=0). The first FET Q1 is turned off, and the voltage of the data pin SDA_CAM1 of the first camera 13 is connected to the power supply VCC by the first pull-up resistor R3, and is pulled up to a high level.

表1 處理單元與第一攝像頭、第二攝像頭中各引腳之真值表Table 1 truth table of the processing unit and each pin in the first camera and the second camera

同樣，請一併參閱表2，當所述第一控制訊號輸出端GPIO1輸出高電平（例如邏輯1），所述資料端I2C_SDA為輸入時，當所述第一攝像頭13回應一應答訊號（Ack-knowledge訊號）而輸出高電平時，所述第一場效應管Q1之源極與閘極之間之電壓（VGS）為0伏特（即VGS=0），所述第一場效應管Q1截止，所述資料端I2C_SDA之電壓藉由所述第一上拉電路176中之第一電阻R1連接至所述供電電源VCC，進而上拉至高電平。當所述第一攝像頭13回應所述Ack-knowledge訊號而輸出低電平時，所述第一場效應管Q1藉由其內部之二極體（圖未標）將所述資料端I2C_SDA之電壓鉗位元至低電平，從而所述第一場效應管Q1中源極與閘極之間之電壓（VGS）為1.5伏特（即VGS=1.5），所述第一場效應管Q1導通，所述資料端I2C_SDA之電壓被鎖定至低電平。Similarly, please refer to Table 2, when the first control signal output terminal GPIO1 outputs a high level (for example, logic 1), and when the data terminal I2C_SDA is an input, when the first camera 13 responds with a response signal ( When the output level is high, the voltage (VGS) between the source and the gate of the first FET Q1 is 0 volts (ie, VGS=0), and the first field effect transistor Q1 The voltage of the data terminal I2C_SDA is connected to the power supply VCC by the first resistor R1 in the first pull-up circuit 176, and is pulled up to a high level. When the first camera 13 outputs a low level in response to the Ack-knowledge signal, the first FET Q1 clamps the voltage of the data terminal I2C_SDA by its internal diode (not labeled) The bit is low, so that the voltage (VGS) between the source and the gate in the first FET Q1 is 1.5 volts (ie, VGS=1.5), and the first FET Q1 is turned on. The voltage at the data terminal I2C_SDA is locked to a low level.

表2 處理單元與第一攝像頭、第二攝像頭中各引腳之真值表Table 2 truth table of the processing unit and each pin in the first camera and the second camera

顯然，從上述表1及表2可明顯看出，第一控制訊號輸出端GPIO1及第二控制訊號輸出端GPIO2可輸出相應之控制訊號，以選擇對應之攝像頭，進而實現對相應之攝像頭進行尋址。例如，當第一控制訊號輸出端GPIO1輸出為0，且第二控制訊號輸出端GPIO2輸出為0（即GPIO1&GPIO2=00）時，表示不選中任何攝像頭。當GPIO1&GPIO2=01時，表示選中第二攝像頭15，如此可實現對第二攝像頭15之尋址。當GPIO1&GPIO2=10時，表示選中第一攝像頭13，如此可實現對第一攝像頭13之尋址。GPIO1&GPIO2=11之模式被禁止，意思是不該出現此模式。Obviously, it can be clearly seen from Table 1 and Table 2 that the first control signal output terminal GPIO1 and the second control signal output terminal GPIO2 can output corresponding control signals to select the corresponding camera, thereby implementing the search for the corresponding camera. site. For example, when the output of the first control signal output terminal GPIO1 is 0, and the output of the second control signal output terminal GPIO2 is 0 (ie, GPIO1 & GPIO2 = 00), it means that no camera is selected. When GPIO1 & GPIO2 = 01, it means that the second camera 15 is selected, so that the addressing of the second camera 15 can be realized. When GPIO1 & GPIO2 = 10, it means that the first camera 13 is selected, so that the addressing of the first camera 13 can be achieved. The mode of GPIO1 & GPIO2 = 11 is disabled, meaning that this mode should not appear.

本發明項所述之可攜式電子裝置100可藉由該第一控制訊號輸出端GPIO1及第二控制訊號輸出端GPIO2輸出相應之控制訊號，以選擇對應之第一攝像頭13或第二攝像頭15，進而使得所述第一攝像頭13或第二攝像頭15共用所述資料端I2C_SDA及時鐘端I2C_SCL，而不會出現選址衝突等情況。The portable electronic device 100 of the present invention can output a corresponding control signal by the first control signal output terminal GPIO1 and the second control signal output terminal GPIO2 to select the corresponding first camera 13 or second camera 15 . In turn, the first camera 13 or the second camera 15 shares the data terminal I2C_SDA and the clock terminal I2C_SCL without occurrence of site conflicts and the like.

可理解，於其他實施例中，所述可攜式電子裝置100中攝像頭之數量不局限於本實施例項所述之兩個，其亦可為一個或多個，即所述可攜式電子裝置100包括至少一個攝像頭。對應地，所述總線切換電路17中之開關單元、上拉電路、控制訊號輸出端以及下拉電阻之數量均與攝像頭之數量保持一致。例如，當所述可攜式電子裝置100包括三個攝像頭時，所述總線切換電路17對應包括三個開關單元、三個上拉電路、三個控制訊號輸出端以及三個下拉電阻。其中，每一開關單元之第一輸入端均電連接至所述資料端，每一開關單元之第二輸入端均電連接至所述時鐘端。每一開關單元之第一輸出端及第二輸出端分別電連接至相應之攝像頭之資料引腳及時鐘引腳。每一開關單元之第一控制端及第二控制端均電連接至一相應之控制訊號輸出端。每一控制訊號輸出端用以輸出相應之控制訊號，以控制相應之開關單元之導通或截止。It is to be understood that, in other embodiments, the number of cameras in the portable electronic device 100 is not limited to the two described in the embodiment, and may also be one or more, that is, the portable electronic device. Apparatus 100 includes at least one camera. Correspondingly, the number of the switching unit, the pull-up circuit, the control signal output terminal, and the pull-down resistor in the bus switching circuit 17 are consistent with the number of cameras. For example, when the portable electronic device 100 includes three cameras, the bus switching circuit 17 correspondingly includes three switch units, three pull-up circuits, three control signal outputs, and three pull-down resistors. The first input end of each switch unit is electrically connected to the data end, and the second input end of each switch unit is electrically connected to the clock end. The first output end and the second output end of each switch unit are electrically connected to the data pins and clock pins of the corresponding cameras, respectively. The first control end and the second control end of each switch unit are electrically connected to a corresponding control signal output end. Each control signal output is used to output a corresponding control signal to control the on or off of the corresponding switch unit.

另外，每一開關單元均包括兩個場效應管，其中一個場效應管之源極作為所述第一輸入端，以電連接至所述資料端，另外一個效應管之源極作為所述第二輸入端，以電連接至所述時鐘端。所述其中一個場效應管之汲極作為所述第一輸出端，以電連接至相應之攝像頭之資料引腳，所述另外一個場效應管之汲極作為所述第二輸出端，以電連接至相應之攝像頭之時鐘引腳。兩個場效應管之閘極分別作為所述第一控制端及第二控制端，且均電連接至相應之控制訊號輸出端。In addition, each switching unit includes two FETs, one of which has a source as the first input terminal to be electrically connected to the data terminal, and another source of the effect transistor as the first Two inputs are electrically connected to the clock terminal. The drain of one of the field effect transistors serves as the first output terminal to be electrically connected to the data pin of the corresponding camera, and the drain of the other field effect transistor serves as the second output terminal to be electrically Connect to the clock pin of the corresponding camera. The gates of the two FETs serve as the first control terminal and the second control terminal, respectively, and are electrically connected to the corresponding control signal output terminals.

每一上拉電路均包括兩個上拉電阻，其中一個上拉電阻之一端電連接至一供電電源，另一端連接至相應之開關單元之第一輸出端及相應之攝像頭之資料端。另外一個上拉電阻之一端連接至所述供電電源，另一端連接至相應之開關單元之第二輸出端及相應之攝像頭之時鐘端。每一下拉電阻之一端接地，另一端則分別電連接至相應之控制訊號輸出端。Each pull-up circuit includes two pull-up resistors, one of the pull-up resistors is electrically connected to a power supply, and the other end is connected to the first output end of the corresponding switch unit and the data terminal of the corresponding camera. One of the other pull-up resistors is connected to the power supply, and the other end is connected to the second output of the corresponding switch unit and the clock end of the corresponding camera. One of the pull-down resistors is grounded, and the other end is electrically connected to the corresponding control signal output.

當然，可理解，於其他實施例中，所述可攜式電子裝置100亦不局限於本實施例項所述之攝像頭，其還可為其他之周邊元件。Of course, it can be understood that in other embodiments, the portable electronic device 100 is not limited to the camera described in the embodiment, and may be other peripheral components.

可理解，於其他實施例中，所述可攜式電子裝置100中周邊元件不局限於包括本實施例項所述之兩個總線引腳，即資料引腳SDA_CAM1、SDA_CAM2以及時鐘引腳SCL_CAM1、SCL_CAM2，其還可包括一個或多個總線引腳，即所述周邊元件包括至少一個總線引腳。對應地，所述處理單元中之總線端、開關單元中輸入端、輸出端、控制端以及上拉電路中上拉電阻之數量均與總線引腳之數量保持一致。例如，當所述周邊元件僅包括一個總線引腳時，所述處理單元僅包括一個總線端。所述開關單元僅包括一個場效應管，所述場效應管之源極作為輸入端連接至所述總線端。所述場效應管之汲極作為輸出端連接至所述周邊元件之總線引腳。所述場效應管之閘極作為控制端連接至相應之控制訊號輸出端。對應地，所述上拉電路僅包括一個上拉電阻，所述上拉電阻之一端連接至所述供電電源，另一端連接至相應之開關單元之輸出端及相應之周邊元件之總線引腳。It can be understood that in other embodiments, the peripheral components in the portable electronic device 100 are not limited to the two bus pins included in the embodiment, that is, the data pins SDA_CAM1, SDA_CAM2, and the clock pin SCL_CAM1. SCL_CAM2, which may also include one or more bus pins, ie, the peripheral components include at least one bus pin. Correspondingly, the number of bus pins in the processing unit, the input terminal, the output terminal, the control terminal, and the pull-up resistor in the pull-up circuit are consistent with the number of bus pins. For example, when the peripheral component includes only one bus pin, the processing unit includes only one bus terminal. The switching unit includes only one field effect transistor, and the source of the FET is connected as an input to the bus terminal. The drain of the FET is connected as an output to a bus pin of the peripheral component. The gate of the FET is connected as a control terminal to a corresponding control signal output terminal. Correspondingly, the pull-up circuit includes only one pull-up resistor, one end of the pull-up resistor is connected to the power supply, and the other end is connected to the output end of the corresponding switch unit and the bus pin of the corresponding peripheral component.

以上所述，僅為本發明的較佳實施例，並非是對本發明作任何形式上的限定。另外，本領域技術人員還可在本發明精神內做其它變化，當然，這些依據本發明精神所做的變化，都應包含在本發明所要求保護的範圍之內。The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. In addition, those skilled in the art can make other changes in the spirit of the present invention. Of course, the changes made in accordance with the spirit of the present invention should be included in the scope of the present invention.

100‧‧‧可攜式電子裝置100‧‧‧Portable electronic devices

11‧‧‧主體部11‧‧‧ Main body

111‧‧‧第一表面111‧‧‧ first surface

113‧‧‧第二表面113‧‧‧ second surface

12‧‧‧顯示單元12‧‧‧Display unit

13‧‧‧第一攝像頭13‧‧‧First camera

15‧‧‧第二攝像頭15‧‧‧second camera

SDA_CAM1、SDA_CAM2‧‧‧資料引腳SDA_CAM1, SDA_CAM2‧‧‧ data pin

SCL_CAM1、SCL_CAM2‧‧‧時鐘引腳SCL_CAM1, SCL_CAM2‧‧‧ clock pin

17‧‧‧總線切換電路17‧‧‧Bus switching circuit

171‧‧‧處理單元171‧‧‧Processing unit

I2C_SDA‧‧‧資料端I2C_SDA‧‧‧ data side

I2C_SCL‧‧‧時鐘端I2C_SCL‧‧‧clock end

GPIO1‧‧‧第一控制訊號輸出端GPIO1‧‧‧ first control signal output

GPIO2‧‧‧第二控制訊號輸出端GPIO2‧‧‧second control signal output

173‧‧‧第一開關單元173‧‧‧First switch unit

Q1‧‧‧第一場效應管Q1‧‧‧First field effect tube

Q2‧‧‧第二場效應管Q2‧‧‧Second FET

174‧‧‧第二開關單元174‧‧‧Second switch unit

Q3‧‧‧第三場效應管Q3‧‧‧ Third FET

Q4‧‧‧第四場效應管Q4‧‧‧Fourth effect tube

R1‧‧‧第一電阻R1‧‧‧first resistance

R2‧‧‧第二電阻R2‧‧‧second resistance

177‧‧‧第一上拉電路177‧‧‧First pull-up circuit

R3‧‧‧第一上拉電阻R3‧‧‧First pull-up resistor

R4‧‧‧第二上拉電阻R4‧‧‧Second pull-up resistor

178‧‧‧第二上拉電路178‧‧‧Second pull-up circuit

R5‧‧‧第三電阻R5‧‧‧ third resistor

R6‧‧‧第四電阻R6‧‧‧fourth resistor

R7‧‧‧第一下拉電阻R7‧‧‧First pull-down resistor

R8‧‧‧第二下拉電阻R8‧‧‧second pull-down resistor

無no

100‧‧‧可攜式電子裝置 100‧‧‧Portable electronic devices

13‧‧‧第一攝像頭 13‧‧‧First camera

15‧‧‧第二攝像頭 15‧‧‧second camera

SDA_CAM1、SDA_CAM2‧‧‧資料引腳 SDA_CAM1, SDA_CAM2‧‧‧ data pin

SCL_CAM1、SCL_CAM2‧‧‧時鐘引腳 SCL_CAM1, SCL_CAM2‧‧‧ clock pin

17‧‧‧總線切換電路 17‧‧‧Bus switching circuit

171‧‧‧處理單元 171‧‧‧Processing unit

I2C_SDA‧‧‧資料端 I2C_SDA‧‧‧ data side

I2C_SCL‧‧‧時鐘端 I2C_SCL‧‧‧clock end

GPIO1‧‧‧第一控制訊號輸出端 GPIO1‧‧‧ first control signal output

GPIO2‧‧‧第二控制訊號輸出端 GPIO2‧‧‧second control signal output

173‧‧‧第一開關單元 173‧‧‧First switch unit

Q1‧‧‧第一場效應管 Q1‧‧‧First field effect tube

Q2‧‧‧第二場效應管 Q2‧‧‧Second FET

174‧‧‧第二開關單元 174‧‧‧Second switch unit

Q3‧‧‧第三場效應管 Q3‧‧‧ Third FET

Q4‧‧‧第四場效應管 Q4‧‧‧Fourth effect tube

R1‧‧‧第一電阻 R1‧‧‧first resistance

R2‧‧‧第二電阻 R2‧‧‧second resistance

177‧‧‧第一上拉電路 177‧‧‧First pull-up circuit

R3‧‧‧第一上拉電阻 R3‧‧‧First pull-up resistor

R4‧‧‧第二上拉電阻 R4‧‧‧Second pull-up resistor

178‧‧‧第二上拉電路 178‧‧‧Second pull-up circuit

R5‧‧‧第三電阻 R5‧‧‧ third resistor

R6‧‧‧第四電阻 R6‧‧‧fourth resistor

R7‧‧‧第一下拉電阻 R7‧‧‧First pull-down resistor

R8‧‧‧第二下拉電阻 R8‧‧‧second pull-down resistor

Claims (8)

一種總線切換電路，應用於包括至少一個周邊元件之可攜式電子裝置中，其改良在於：所述總線切換電路包括處理單元以及至少一開關單元，所述處理單元包括至少一總線端以及與所述至少一開關單元數量相應之控制訊號輸出端，每一開關單元均包括與所述至少一總線端數量相應之輸入端、輸出端以及控制端，所述每一開關單元中每一輸入端分別電連接至相應之總線端，每一輸出端分別電連接至相應之周邊元件之總線引腳，所述每一開關單元中之控制端電連接於一起，且分別電連接至相應之控制訊號輸出端，每一控制訊號輸出端用以輸出相應之控制訊號，以控制相應之開關單元之導通或截止。A bus switching circuit for use in a portable electronic device including at least one peripheral component, wherein the bus switching circuit includes a processing unit and at least one switching unit, the processing unit including at least one bus terminal and a control signal output terminal corresponding to the number of at least one switch unit, each switch unit includes an input end, an output end, and a control end corresponding to the number of the at least one bus end, wherein each input end of each switch unit is respectively Electrically connected to corresponding bus terminals, each output terminal is electrically connected to a bus pin of a corresponding peripheral component, and the control terminals of each switch unit are electrically connected together and electrically connected to respective control signal outputs At the end, each control signal output terminal is used to output a corresponding control signal to control the on or off of the corresponding switch unit. 如申請專利範圍第1項所述之總線切換電路，其中所述總線端包括資料端及時鐘端，每一開關單元包括第一輸入端、第二輸入端、第一輸出端、第二輸出端、第一控制端以及第二控制端，所述第一輸入端電連接至所述資料端，所述第二輸入端電連接至所述時鐘端，所述第一輸出端電連接至所述周邊元件之資料引腳，所述第二輸出端電連接至所述周邊元件之時鐘引腳，所述第一控制端以及第二控制端電連接於一起，並均電連接至相應之控制訊號輸出端。The bus switching circuit of claim 1, wherein the bus end comprises a data end and a clock end, and each switch unit comprises a first input end, a second input end, a first output end, and a second output end. a first control terminal electrically connected to the data terminal, a second input terminal electrically connected to the clock terminal, and a first output terminal electrically connected to the a data pin of the peripheral component, the second output terminal is electrically connected to the clock pin of the peripheral component, the first control terminal and the second control terminal are electrically connected together, and are electrically connected to the corresponding control signal Output. 如申請專利範圍第1項所述之總線切換電路，其中每一開關單元均包括至少一個場效應管，每一場效應管之源極作為所述輸入端，以分別電連接至相應之總線端，每一場效應管之汲極作為所述輸出端，以電連接至相應之周邊元件之總線引腳，每一場效應管之閘極均作為所述控制端，且電連接至相應之控制訊號輸出端。The bus switching circuit of claim 1, wherein each of the switching units includes at least one field effect transistor, and the source of each field effect transistor serves as the input terminal to be electrically connected to the corresponding bus terminal, respectively. The drain of each effect transistor serves as the output terminal to electrically connect to the bus pin of the corresponding peripheral component, and the gate of each field effect transistor serves as the control terminal and is electrically connected to the corresponding control signal output terminal. . 如申請專利範圍第1項所述之總線切換電路，其中所述總線切換電路還包括與所述至少一開關單元數量相應之上拉電路，每一上拉電路包括與所述至少一總線端數量相應之上拉電阻，每一上拉電阻之一端連接至一供電電源，另一端連接至相應之開關單元之輸出端及相應之周邊元件之總線引腳。The bus switching circuit of claim 1, wherein the bus switching circuit further comprises a pull-up circuit corresponding to the number of the at least one switch unit, each pull-up circuit comprising a number of the at least one bus end Corresponding pull-up resistors, one end of each pull-up resistor is connected to a power supply, and the other end is connected to the output end of the corresponding switch unit and the bus pin of the corresponding peripheral component. 如申請專利範圍第1項所述之總線切換電路，其中所述總線切換電路還包括與所述至少一總線端數量相應之電阻，每一電阻之一端連接至一供電電源，另一端連接至相應之總線端。The bus switching circuit of claim 1, wherein the bus switching circuit further comprises a resistor corresponding to the number of the at least one bus terminal, one end of each resistor is connected to a power supply, and the other end is connected to the corresponding The bus terminal. 如申請專利範圍第1項所述之總線切換電路，其中所述總線切換電路還包括與所述控制訊號輸出端數量相應之下拉電阻，每一下拉電阻之一端接地，另一端分別電連接至相應之控制訊號輸出端。The bus switching circuit of claim 1, wherein the bus switching circuit further comprises a pull-down resistor corresponding to the number of the control signal output terminals, one end of each pull-down resistor is grounded, and the other end is electrically connected to the corresponding one. The control signal output. 一種可攜式電子裝置，包括至少一周邊元件以及如申請專利範圍第1-6項中任一項所述之總線切換電路。A portable electronic device comprising at least one peripheral component and a bus switching circuit according to any one of claims 1-6. 如申請專利範圍第7項所述之可攜式電子裝置，其中所述周邊元件為攝像頭。
The portable electronic device of claim 7, wherein the peripheral component is a camera.
TW104135964A 2015-10-28 2015-11-02 Bus switching circuit and portable electronic device with same TW201722080A (en)

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