CN204069149U - A kind of switching circuit realizing two 13M pixel camera head and switch - Google Patents
A kind of switching circuit realizing two 13M pixel camera head and switch Download PDFInfo
- Publication number
- CN204069149U CN204069149U CN201420581103.7U CN201420581103U CN204069149U CN 204069149 U CN204069149 U CN 204069149U CN 201420581103 U CN201420581103 U CN 201420581103U CN 204069149 U CN204069149 U CN 204069149U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- electric capacity
- connector
- camera
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Studio Devices (AREA)
Abstract
The utility model relates to technical field of image processing, particularly relate to a kind of switching circuit realizing two 13M pixel camera head and switch, switching circuit of the present utility model comprises the first utilizing camera interface module, second camera interface module, is that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, and the first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.Pass through switch module, the 13M pixel camera head of former and later two 4 passages is connected on the main channel of the image-signal processor of falling ISP, according to the state of control signal diverter switch, the picture signal realizing two 13M pixel camera head seizure all passes through the effect of professional ISP visual information processor process.
Description
Technical field
The utility model relates to technical field of image processing, particularly relates to a kind of switching circuit realizing two 13M pixel camera head and switch.
Background technology
The mobile phone baseband of current market main flow is all integrated with ISP visual information processor, and ISP visual information processor integrated level is high, is conducive to the miniaturization of Cell Phone Design, cost optimization.But the Mipi interface of ISP visual information processor limits, standard configuration is that main camera supports 4 passages, and front-facing camera supports 2 passages, and 13M pixel camera head is all support 4 passage usually, ISP image processor just cannot support two 13M camera, cannot meet user to the high pixel demand of autodyning.
Utility model content
The utility model provides a kind of switching circuit realizing two 13M pixel camera head and switch, and cannot meet the problem of user to the high pixel demand of autodyning to solve existing mobile phone.
A kind of switching circuit realizing two 13M pixel camera head and switch, comprise the first utilizing camera interface module, second camera interface module, be that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, described first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.
Preferably, described switching circuit also comprise power for ISP image-signal processor processor supply module, be the camera supply module that the first camera and second camera are powered, processor supply module is connected with ISP image-signal processor, camera supply module respectively, and camera supply module is connected with the first utilizing camera interface module, second camera interface module respectively.
Preferably, described switching circuit also comprises the camera filtration module that the picture signal captured for camera carries out filtering noise reduction, and camera filtration module is connected with switch module, the first utilizing camera interface module, second camera interface module respectively.
Preferably, described ISP image-signal processor comprises:
Chip U738, resistance R733-R734, electric capacity C758-C761, electric capacity C769-C785, electric capacity C797-C799, inductance L 719-L721, wherein, the model of chip U738 is THP7212_2014, the pin RD2N of described chip U738, pin RD2P, pin RD0N, pin RD0P, pin RCKN, pin RCKP, pin RD1N, pin RD1P, pin RD3N, pin RD3P is connected with switch module respectively, the pin V_CLK of chip U738 is connected with second camera interface module, the pin M_SCL of chip U738 is connected with one end of resistance R733 and second camera interface module respectively, the pin M_SDA of chip U738 is connected with one end of resistance R734 and second camera interface module respectively, the other end of resistance R733, the other end of resistance R734 is all connected with one end of inductance L 719, the other end of inductance L 719 respectively with one end of electric capacity C797, one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect, the other end of electric capacity C780, the other end of electric capacity C781, the other end of electric capacity C782, the other end of electric capacity C783 and the other end of electric capacity C784 are all connected to ground, the pin M_MSIO of chip U738, pin M_QD_HOLD, pin M_SCS is all connected with one end of inductance L 719, the pin M_QD_WPB of chip U738 is connected to ground, the pin GPIO_2 [0] of chip U738 is connected with second camera interface module, pin GPIO_2 [1] and the first utilizing camera interface model calling of chip U738, the pin VDDRX of chip U738, pin VDDREFRX, pin VDDREFTX all with one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, the other end of electric capacity C775, the other end of electric capacity C776, the other end of electric capacity C777, the other end of electric capacity C778 and the other end of electric capacity C779 are all connected to ground, the pin VDDCMOS of chip U738, VDDGPIO_0, VDDGPIO_1 is all connected with one end of inductance L 719, the pin VDDCORE of chip U738 respectively with one end of inductance L 721, one end of inductance L 720, one end of electric capacity C761, one end of electric capacity C759, one end of electric capacity C760, one end of electric capacity C758, one end of electric capacity C769, and one end of electric capacity C770 connects, the other end of electric capacity C761, the other end of electric capacity C759, the other end of electric capacity C760, the other end of electric capacity C758, the other end of electric capacity C769, and the other end of electric capacity C770 is all connected to ground, the other end of inductance L 721 respectively with one end of electric capacity C799, one end of electric capacity C785 connects, and the other end of electric capacity C785 is connected to ground, and the other end of electric capacity C799 is connected to ground, the other end of inductance L 720 respectively with one end of electric capacity C798, one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, and the other end of electric capacity C798 is connected to ground, the pin BOOT [1] of chip U738, pin VDDHOST is all connected with one end of inductance L 719, and the pin BOOT [0] of chip U738 is connected to ground, the pin TEST_IN of chip U738, pin VSS is all connected to ground, and the pin VDDPLL of chip U738 is connected with one end of electric capacity C785, the pin VDDTX of chip U738, pin VHTERMRX all with one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect.
Preferably, described switch module comprises:
Chip U1, electric capacity C766, wherein, the model of chip U1 is FSA644, the pin CLK-P of described chip U1, pin CLK-N, pin D1-P, pin D1-N, pin D2-P, pin D2-N, pin D3-P, pin D3-N, pin D4-P, the pin RCKP of pin D4-N difference correspondence and chip U738, pin RCKN, pin RD0P, pin RD0N, pin RD1P, pin RD1N, pin RD2P, pin RD2N, pin RD3N, pin RD3P connects, the pin CLKA-P of chip U1, pin CLKA-N, pin DA1-P, pin DA1-N, pin DA2-P, pin DA2-N, pin DA3-P, pin DA3-N, pin DA4-P, pin DA4-N respectively with the first utilizing camera interface model calling, the pin CLKB-P of chip U1, pin CLKB-N, pin DB1-P, pin DB1-N, pin DB2-P, pin DB2-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N is connected with second camera interface module respectively, the pin GND of chip U1, pin OE is all connected to ground, and the pin SEL of chip U1 is connected with the GPIO mouth of the CPU of described switching circuit outside, and the pin VCC of chip U1 is connected with one end of electric capacity C766, and the other end of electric capacity C766 is connected to ground.
Preferably, described first utilizing camera interface module comprises:
Connector J706, electric capacity C756, electric capacity C920-C921, electric capacity C924-C926, electric capacity C703, resistance R723, wherein, the model of connector J706 is AXT530124_2012, the pin 2 of described connector J706, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of the first camera respectively, also distinguishes pin DA3-P that is corresponding and chip U1, pin DA3-N, pin DA2-P, pin DA2-N, pin DA4-P, pin DA4-N, pin DA1-P, pin DA1-N, pin CLKA-P, pin CLKA-N connects, the pin 30 of connector J706 respectively with one end of electric capacity C756, one end of resistance R723, one end of electric capacity C926 connects, and the other end of electric capacity C756 is connected to ground, and the other end of resistance R723 is connected with second camera interface module, the pin 29 of connector J706 respectively with the pin GPIO_2 [1] of chip U738, one end of electric capacity C925 connects, and the pin 28 of connector J706 is connected with the pin V_CLK of chip U738, the pin 22 of connector J706 respectively with one end of electric capacity C703, one end of electric capacity C920 connects, and the other end of electric capacity C703 is connected to ground, the pin 21 of connector J706 respectively with camera supply module, one end of electric capacity C921 connects, the pin 18 of connector J706 is connected with the pin M_SCL of chip U738, the pin 17 of connector J706 is connected with the pin M_SDA of chip U738, and the pin 20 of connector J706 is connected with one end of electric capacity C924, the pin 27 of connector J706, pin 26, pin 24, pin 23, pin 19 all with the other end of electric capacity C920, the other end of electric capacity C921, the other end of electric capacity C924, the other end of electric capacity C925, the other end and the ground of electric capacity C926 connect.
Preferably, described second camera interface module comprises:
Connector J702, electric capacity C708-C709, electric capacity C714, resistance R722, wherein, the model of connector J702 is AXT530124_2012, the pin 2 of described connector J702, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of second camera respectively, also distinguishes pin DB1-P that is corresponding and chip U1, pin DB1-N, pin DB2-P, pin DB2-N, pin CLKB-P, pin CLKB-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N connects, and the pin 30 of connector J702 is connected with one end of resistance R722, and the other end of resistance R722 is connected with the other end of resistance R723, the pin 29 of connector J702 respectively with the pin GPIO_2 [0] of chip U738, one end of electric capacity C714 connects, the pin 28 of connector J702 is connected with the pin V_CLK of chip U738, the pin 22 of connector J702 is connected with one end of electric capacity C703, the pin 21 of connector J702 is connected with camera supply module, the pin 20 of connector J702 respectively with one end of electric capacity C708, one end of electric capacity C709 connects, the other end of electric capacity C708, the other end of electric capacity C709 is all connected to ground, and the pin 18 of connector J702 is connected with the pin M_SCL of chip U738, and the pin 17 of connector J702 is connected with the pin M_SDA of chip U738, the pin 27 of connector J702, pin 26, pin 24, pin 23, pin 19 is all connected with the other end of electric capacity C714 and ground.
Preferably, described processor supply module comprises:
Chip U788, electric capacity C765-C768, resistance R766-R768, inductance L 722, wherein, the model of chip U788 is SGM6013, the pin RUN of described chip U788 is connected with one end of resistance R768, the other end of resistance R768 is connected to ground, the pin GND of chip U788 is connected to ground, the pin FB of chip U788 respectively with one end of resistance R767, one end of resistance R766, one end of electric capacity C767 connects, the other end of resistance R767 is connected to ground, the other end of resistance R766, the other end of electric capacity C767, one end of inductance L 722, one end of electric capacity C765 all with one end of inductance L 721, one end of inductance L 720 connects, the other end of electric capacity C765 is connected to ground, the pin SW of chip U788 is connected with the other end of inductance L 722, the pin VIN of chip U788 respectively with one end of electric capacity C768, camera supply module connects, the other end of electric capacity C768 is connected to ground.
Preferably, described camera supply module comprises:
Chip U705, electric capacity C732-C733, electric capacity C704, electric capacity C755, resistance R731-R732, resistance R771, inductance L 705, the pin RUN of described chip U705 is connected with one end of resistance R771, the other end of resistance R771 is connected to ground, the pin GND of chip U705 is connected to ground, the pin FB of chip U705 respectively with one end of resistance R731, one end of resistance R732, one end of electric capacity C733 connects, the other end of electric capacity C733, the other end of resistance R732, one end of inductance L 705, one end of electric capacity C732, one end of electric capacity C704 all with the pin 21 of connector J702, the pin 21 of connector J706 connects, the pin SW of chip U705 is connected with the other end of inductance L 705, the pin VIN of chip U705 respectively with one end of electric capacity C755, the pin VIN of chip U788 connects, the other end of electric capacity C755 is connected to ground.
Preferably, described camera filtration module comprises:
Chip U704, chip U706-U709, chip U718-U720, chip U725-U726, wherein, chip U704, chip U706-U709, chip U718-U720, the model of chip U725-U726 is EXC14CE900U, the pin 1 of described chip U704 is connected with the pin CLKA-P of chip U1, the pin 2 of chip U704 is connected with the pin CLKA-N of chip U1, the pin 1 of chip U706 is connected with the pin DA1-P of chip U1, the pin 2 of chip U706 is connected with the pin DA1-N of chip U1, the pin 1 of chip U708 is connected with the pin DA2-P of chip U1, the pin 2 of chip U708 is connected with the pin DA2-N of chip U1, the pin 1 of chip U725 is connected with the pin DA3-P of chip U1, the pin 2 of chip U725 is connected with the pin DA3-N of chip U1, the pin 1 of chip U726 is connected with the pin DA4-P of chip U1, the pin 2 of chip U726 is connected with the pin DA4-N of chip U1, the pin 3 of described chip U704 is connected with the pin 9 of connector J706, the pin 4 of chip U704 is connected with the pin 8 of connector J706, the pin 3 of chip U706 is connected with the pin 3 of connector J706, the pin 4 of chip U706 is connected with the pin 2 of connector J706, the pin 3 of chip U708 is connected with the pin 6 of connector J706, the pin 4 of chip U708 is connected with the pin 5 of connector J706, the pin 3 of chip U725 is connected with the pin 12 of connector J706, the pin 4 of chip U725 is connected with the pin 11 of connector J706, the pin 3 of chip U726 is connected with the pin 15 of connector J706, the pin 4 of chip U726 is connected with the pin 14 of connector J706, the pin 1 of described chip U719 is connected with the pin DB4-P of chip U1, the pin 2 of chip U719 is connected with the pin DB4-N of chip U1, the pin 1 of chip U718 is connected with the pin DB3-P of chip U1, the pin 2 of chip U718 is connected with the pin DB3-N of chip U1, the pin 1 of chip U707 is connected with the pin DB2-P of chip U1, the pin 2 of chip U707 is connected with the pin DB2-N of chip U1, the pin 1 of chip U709 is connected with the pin DB1-P of chip U1, the pin 2 of chip U709 is connected with the pin DB1-N of chip U1, the pin 1 of chip U720 is connected with the pin CLKB-P of chip U1, the pin 2 of chip U720 is connected with the pin CLKB-N of chip U1, the pin 3 of described chip U719 is connected with the pin 15 of connector J702, the pin 4 of chip U719 is connected with the pin 14 of connector J702, the pin 3 of chip U718 is connected with the pin 12 of connector J702, the pin 4 of chip U718 is connected with the pin 11 of connector J702, the pin 3 of chip U707 is connected with the pin 6 of connector J702, the pin 4 of chip U707 is connected with the pin 5 of connector J702, the pin 3 of chip U709 is connected with the pin 3 of connector J702, the pin 4 of chip U709 is connected with the pin 2 of connector J702, the pin 3 of chip U720 is connected with the pin 9 of connector J702, the pin 4 of chip U720 is connected with the pin 8 of connector J702.
Switching circuit of the present utility model comprises the first utilizing camera interface module, second camera interface module, is that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, and the first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.Pass through switch module, the 13M pixel camera head of former and later two 4 passages is connected on the main channel of the image-signal processor of falling ISP, according to the state of control signal diverter switch, the picture signal realizing two 13M pixel camera head seizure all passes through the effect of professional ISP visual information processor process.
Accompanying drawing explanation
Fig. 1 is the frame principle figure one of the switching circuit of the two 13M pixel camera head switching of realization that the utility model embodiment provides.
Fig. 2 is the frame principle figure two of the switching circuit of the two 13M pixel camera head switching of realization that the utility model embodiment provides.
Fig. 3 is the ISP image-signal processor circuit diagram that the utility model embodiment provides.
Fig. 4 is the switch module circuit diagram that the utility model embodiment provides.
Fig. 5 is the first utilizing camera interface module circuit diagram that the utility model embodiment provides.
Fig. 6 is the second camera interface module circuit figure that the utility model embodiment provides.
Fig. 7 is the processor supply module circuit diagram that the utility model embodiment provides.
Fig. 8 is the camera supply module circuit diagram that the utility model embodiment provides.
Fig. 9 is the camera filtration module circuit diagram one that the utility model embodiment provides.
Figure 10 is the camera filtration module circuit diagram two that the utility model embodiment provides.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is described in detail further.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Fig. 1 shows a kind of frame principle figure realizing the switching circuit that two 13M pixel camera head switches that the utility model embodiment provides, and switching circuit comprises:
Comprise the first utilizing camera interface module, second camera interface module, be that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, the first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.
In the present embodiment, first camera, second camera are connected with the first utilizing camera interface module, second camera interface module respectively, and the first camera, second camera are the camera of 4 passage 13M (namely 1,300 ten thousand) pixel, first camera is post-positioned pick-up head, second camera is front-facing camera, also can exchange.
Fig. 2 shows a kind of frame principle figure realizing the switching circuit that two 13M pixel camera head switches that the utility model embodiment provides, and switching circuit comprises the whole modules in above-described embodiment, and what comprise with lower module in addition is one or more:
The processor supply module of powering for ISP image-signal processor, be the camera supply module that the first camera and second camera are powered, processor supply module is connected with ISP image-signal processor, camera supply module respectively, and camera supply module is connected with the first utilizing camera interface module, second camera interface module respectively.
The picture signal captured for camera carries out the camera filtration module of filtering noise reduction, and camera filtration module is connected with switch module, the first utilizing camera interface module, second camera interface module respectively.
Fig. 3 shows the ISP image-signal processor circuit diagram that the utility model embodiment provides, and comprising:
Chip U738, resistance R733-R734, electric capacity C758-C761, electric capacity C769-C785, electric capacity C797-C799, inductance L 719-L721, wherein, the model of chip U738 is THP7212_2014, the pin RD2N of described chip U738, pin RD2P, pin RD0N, pin RD0P, pin RCKN, pin RCKP, pin RD1N, pin RD1P, pin RD3N, pin RD3P is connected with switch module respectively, the pin V_CLK of chip U738 is connected with second camera interface module, the pin M_SCL of chip U738 is connected with one end of resistance R733 and second camera interface module respectively, the pin M_SDA of chip U738 is connected with one end of resistance R734 and second camera interface module respectively, the other end of resistance R733, the other end of resistance R734 is all connected with one end of inductance L 719, the other end of inductance L 719 respectively with one end of electric capacity C797, one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect, the other end of electric capacity C780, the other end of electric capacity C781, the other end of electric capacity C782, the other end of electric capacity C783 and the other end of electric capacity C784 are all connected to ground, the pin M_MSIO of chip U738, pin M_QD_HOLD, pin M_SCS is all connected with one end of inductance L 719, the pin M_QD_WPB of chip U738 is connected to ground, the pin GPIO_2 [0] of chip U738 is connected with second camera interface module, pin GPIO_2 [1] and the first utilizing camera interface model calling of chip U738, the pin VDDRX of chip U738, pin VDDREFRX, pin VDDREFTX all with one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, the other end of electric capacity C775, the other end of electric capacity C776, the other end of electric capacity C777, the other end of electric capacity C778 and the other end of electric capacity C779 are all connected to ground, the pin VDDCMOS of chip U738, VDDGPIO_0, VDDGPIO_1 is all connected with one end of inductance L 719, the pin VDDCORE of chip U738 respectively with one end of inductance L 721, one end of inductance L 720, one end of electric capacity C761, one end of electric capacity C759, one end of electric capacity C760, one end of electric capacity C758, one end of electric capacity C769, and one end of electric capacity C770 connects, the other end of electric capacity C761, the other end of electric capacity C759, the other end of electric capacity C760, the other end of electric capacity C758, the other end of electric capacity C769, and the other end of electric capacity C770 is all connected to ground, the other end of inductance L 721 respectively with one end of electric capacity C799, one end of electric capacity C785 connects, and the other end of electric capacity C785 is connected to ground, and the other end of electric capacity C799 is connected to ground, the other end of inductance L 720 respectively with one end of electric capacity C798, one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, and the other end of electric capacity C798 is connected to ground, the pin BOOT [1] of chip U738, pin VDDHOST is all connected with one end of inductance L 719, and the pin BOOT [0] of chip U738 is connected to ground, the pin TEST_IN of chip U738, pin VSS is all connected to ground, and the pin VDDPLL of chip U738 is connected with one end of electric capacity C785, the pin VDDTX of chip U738, pin VHTERMRX all with one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect.
In the present embodiment, in order to reach effect of better taking pictures, adopt external ISP image-signal processor, compare built-in ISP image-signal processor, external noise is less, color rendition Du Genggao, process details is more careful, in foregoing circuit, the pin RD2N of chip U738, pin RD2P, pin RD0N, pin RD0P, pin RCKN, pin RCKP, pin RD1N, pin RD1P, pin RD3N, pin RD3P is the main channel of ISP image-signal processor, for connecting valve module, switch module is respectively by the first utilizing camera interface, second camera interface and the first camera, second camera connects, by switch module switch with ISP image-signal processor and camera, resistance R733, the resistance of resistance R734 is 1K Ω, electric capacity C758-C761, the value of electric capacity C769-C785 is 100nF, the value of electric capacity C797-C799 is 10uF, the value of inductance L 719 is 2.2uH.
Fig. 4 shows the switch module circuit diagram that the utility model embodiment provides, and comprising:
Chip U1, electric capacity C766, wherein, the model of chip U1 is FSA644, the pin CLK-P of described chip U1, pin CLK-N, pin D1-P, pin D1-N, pin D2-P, pin D2-N, pin D3-P, pin D3-N, pin D4-P, the pin RCKP of pin D4-N difference correspondence and chip U738, pin RCKN, pin RD0P, pin RD0N, pin RD1P, pin RD1N, pin RD2P, pin RD2N, pin RD3N, pin RD3P connects, the pin CLKA-P of chip U1, pin CLKA-N, pin DA1-P, pin DA1-N, pin DA2-P, pin DA2-N, pin DA3-P, pin DA3-N, pin DA4-P, pin DA4-N respectively with the first utilizing camera interface model calling, the pin CLKB-P of chip U1, pin CLKB-N, pin DB1-P, pin DB1-N, pin DB2-P, pin DB2-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N is connected with second camera interface module respectively, the pin GND of chip U1, pin OE is all connected to ground, and the pin SEL of chip U1 is connected with the GPIO mouth of the CPU of described switching circuit outside, and the pin VCC of chip U1 is connected with one end of electric capacity C766, and the other end of electric capacity C766 is connected to ground.
In the present embodiment, the pin SEL of chip U1 is control pin, be connected with the GPIO mouth of switching circuit outer CPU, when CPU detects use the first camera, the signal that switch module is switched to the first camera is set by GPIO mouth, when CPU detects and uses second camera, the signal that switch module is switched to second camera is set by GPIO mouth, in foregoing circuit, the value of electric capacity C766 is 1uF.
Fig. 5 shows the first utilizing camera interface module circuit diagram that the utility model embodiment provides, and comprising:
Connector J706, electric capacity C756, electric capacity C920-C921, electric capacity C924-C926, electric capacity C703, resistance R723, wherein, the model of connector J706 is AXT530124_2012, the pin 2 of described connector J706, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of the first camera respectively, also distinguishes pin DA3-P that is corresponding and chip U1, pin DA3-N, pin DA2-P, pin DA2-N, pin DA4-P, pin DA4-N, pin DA1-P, pin DA1-N, pin CLKA-P, pin CLKA-N connects, the pin 30 of connector J706 respectively with one end of electric capacity C756, one end of resistance R723, one end of electric capacity C926 connects, and the other end of electric capacity C756 is connected to ground, and the other end of resistance R723 is connected with second camera interface module, the pin 29 of connector J706 respectively with the pin GPIO_2 [1] of chip U738, one end of electric capacity C925 connects, and the pin 28 of connector J706 is connected with the pin V_CLK of chip U738, the pin 22 of connector J706 respectively with one end of electric capacity C703, one end of electric capacity C920 connects, and the other end of electric capacity C703 is connected to ground, the pin 21 of connector J706 respectively with camera supply module, one end of electric capacity C921 connects, the pin 18 of connector J706 is connected with the pin M_SCL of chip U738, the pin 17 of connector J706 is connected with the pin M_SDA of chip U738, and the pin 20 of connector J706 is connected with one end of electric capacity C924, the pin 27 of connector J706, pin 26, pin 24, pin 23, pin 19 all with the other end of electric capacity C920, the other end of electric capacity C921, the other end of electric capacity C924, the other end of electric capacity C925, the other end and the ground of electric capacity C926 connect.
In the present embodiment, first utilizing camera interface module is connected with the first camera and camera filtration module respectively, in foregoing circuit, the value of electric capacity C920-C921, electric capacity C924-C924, electric capacity C926 is 1uF, the value of electric capacity C703, electric capacity C756 is 100nF, the value of electric capacity C925 is NC, and the resistance of resistance R723 is 0.
Fig. 6 shows the second camera interface module circuit figure that the utility model embodiment provides, and comprising:
Connector J702, electric capacity C708-C709, electric capacity C714, resistance R722, wherein, the model of connector J702 is AXT530124_2012, the pin 2 of described connector J702, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of second camera respectively, also distinguishes pin DB1-P that is corresponding and chip U1, pin DB1-N, pin DB2-P, pin DB2-N, pin CLKB-P, pin CLKB-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N connects, and the pin 30 of connector J702 is connected with one end of resistance R722, and the other end of resistance R722 is connected with the other end of resistance R723, the pin 29 of connector J702 respectively with the pin GPIO_2 [0] of chip U738, one end of electric capacity C714 connects, the pin 28 of connector J702 is connected with the pin V_CLK of chip U738, the pin 22 of connector J702 is connected with one end of electric capacity C703, the pin 21 of connector J702 is connected with camera supply module, the pin 20 of connector J702 respectively with one end of electric capacity C708, one end of electric capacity C709 connects, the other end of electric capacity C708, the other end of electric capacity C709 is all connected to ground, and the pin 18 of connector J702 is connected with the pin M_SCL of chip U738, and the pin 17 of connector J702 is connected with the pin M_SDA of chip U738, the pin 27 of connector J702, pin 26, pin 24, pin 23, pin 19 is all connected with the other end of electric capacity C714 and ground.
In the present embodiment, second camera interface module is connected with second camera and camera filtration module respectively, and in foregoing circuit, the value of electric capacity C708 is 2.2uF, and the value of electric capacity C709 is 100nF, and the value of electric capacity C714 is NC, and the resistance of resistance R722 is 0.
Fig. 7 shows the processor supply module circuit diagram that the utility model embodiment provides, and comprising:
Chip U788, electric capacity C765-C768, resistance R766-R768, inductance L 722, wherein, the model of chip U788 is SGM6013, the pin RUN of described chip U788 is connected with one end of resistance R768, the other end of resistance R768 is connected to ground, the pin GND of chip U788 is connected to ground, the pin FB of chip U788 respectively with one end of resistance R767, one end of resistance R766, one end of electric capacity C767 connects, the other end of resistance R767 is connected to ground, the other end of resistance R766, the other end of electric capacity C767, one end of inductance L 722, one end of electric capacity C765 all with one end of inductance L 721, one end of inductance L 720 connects, the other end of electric capacity C765 is connected to ground, the pin SW of chip U788 is connected with the other end of inductance L 722, the pin VIN of chip U788 respectively with one end of electric capacity C768, camera supply module connects, the other end of electric capacity C768 is connected to ground.
In the present embodiment, the value of electric capacity C765 is 2.2uF, and the value of electric capacity C767 is 18pF, and the value of electric capacity C768 is 4.7uF, and the resistance of resistance R766-R767 is 3K Ω, and the resistance of resistance R768 is 100K Ω, and the value of inductance L 722 is 2.2uH.
Fig. 8 shows the camera supply module circuit diagram that the utility model embodiment provides, and comprising:
Chip U705, electric capacity C732-C733, electric capacity C704, electric capacity C755, resistance R731-R732, resistance R771, inductance L 705, the pin RUN of described chip U705 is connected with one end of resistance R771, the other end of resistance R771 is connected to ground, the pin GND of chip U705 is connected to ground, the pin FB of chip U705 respectively with one end of resistance R731, one end of resistance R732, one end of electric capacity C733 connects, the other end of electric capacity C733, the other end of resistance R732, one end of inductance L 705, one end of electric capacity C732, one end of electric capacity C704 all with the pin 21 of connector J702, the pin 21 of connector J706 connects, the pin SW of chip U705 is connected with the other end of inductance L 705, the pin VIN of chip U705 respectively with one end of electric capacity C755, the pin VIN of chip U788 connects, the other end of electric capacity C755 is connected to ground.
In the utility model embodiment, the value of electric capacity C732 is 22uF, and the value of electric capacity C733 is 18pF, the value of electric capacity C704 is 2.2uF, and the value of electric capacity C755 is 4.7uF, and the resistance of resistance R771, resistance R731 is 100K Ω, the resistance of resistance R732 is 75K Ω, and the value of inductance L 705 is 2.2uH.
Fig. 9-10 shows the camera filtration module circuit diagram that the utility model embodiment provides, and comprising:
Chip U704, chip U706-U709, chip U718-U720, chip U725-U726, wherein, chip U704, chip U706-U709, chip U718-U720, the model of chip U725-U726 is EXC14CE900U, the pin 1 of described chip U704 is connected with the pin CLKA-P of chip U1, the pin 2 of chip U704 is connected with the pin CLKA-N of chip U1, the pin 1 of chip U706 is connected with the pin DA1-P of chip U1, the pin 2 of chip U706 is connected with the pin DA1-N of chip U1, the pin 1 of chip U708 is connected with the pin DA2-P of chip U1, the pin 2 of chip U708 is connected with the pin DA2-N of chip U1, the pin 1 of chip U725 is connected with the pin DA3-P of chip U1, the pin 2 of chip U725 is connected with the pin DA3-N of chip U1, the pin 1 of chip U726 is connected with the pin DA4-P of chip U1, the pin 2 of chip U726 is connected with the pin DA4-N of chip U1, the pin 3 of described chip U704 is connected with the pin 9 of connector J706, the pin 4 of chip U704 is connected with the pin 8 of connector J706, the pin 3 of chip U706 is connected with the pin 3 of connector J706, the pin 4 of chip U706 is connected with the pin 2 of connector J706, the pin 3 of chip U708 is connected with the pin 6 of connector J706, the pin 4 of chip U708 is connected with the pin 5 of connector J706, the pin 3 of chip U725 is connected with the pin 12 of connector J706, the pin 4 of chip U725 is connected with the pin 11 of connector J706, the pin 3 of chip U726 is connected with the pin 15 of connector J706, the pin 4 of chip U726 is connected with the pin 14 of connector J706, the pin 1 of described chip U719 is connected with the pin DB4-P of chip U1, the pin 2 of chip U719 is connected with the pin DB4-N of chip U1, the pin 1 of chip U718 is connected with the pin DB3-P of chip U1, the pin 2 of chip U718 is connected with the pin DB3-N of chip U1, the pin 1 of chip U707 is connected with the pin DB2-P of chip U1, the pin 2 of chip U707 is connected with the pin DB2-N of chip U1, the pin 1 of chip U709 is connected with the pin DB1-P of chip U1, the pin 2 of chip U709 is connected with the pin DB1-N of chip U1, the pin 1 of chip U720 is connected with the pin CLKB-P of chip U1, the pin 2 of chip U720 is connected with the pin CLKB-N of chip U1, the pin 3 of described chip U719 is connected with the pin 15 of connector J702, the pin 4 of chip U719 is connected with the pin 14 of connector J702, the pin 3 of chip U718 is connected with the pin 12 of connector J702, the pin 4 of chip U718 is connected with the pin 11 of connector J702, the pin 3 of chip U707 is connected with the pin 6 of connector J702, the pin 4 of chip U707 is connected with the pin 5 of connector J702, the pin 3 of chip U709 is connected with the pin 3 of connector J702, the pin 4 of chip U709 is connected with the pin 2 of connector J702, the pin 3 of chip U720 is connected with the pin 9 of connector J702, the pin 4 of chip U720 is connected with the pin 8 of connector J702.
The operation principle of the utility model embodiment switching circuit is as follows:
The control pin SEL of the chip U1 of switch module receive CPU by GPIO mouth send switch to the control signal of the first camera/second camera after, control switch switches corresponding utilizing camera interface module and is switched on the main channel of ISP image-signal processor, picture signal process is carried out to the picture signal that corresponding camera catches, obtains the image frame of high-quality.
Switching circuit of the present utility model comprises the first utilizing camera interface module, second camera interface module, is that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, and the first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.Pass through switch module, the 13M pixel camera head of former and later two 4 passages is connected on the main channel of the image-signal processor of falling ISP, according to the state of control signal diverter switch, the picture signal realizing two 13M pixel camera head seizure all passes through the effect of professional ISP visual information processor process.
Below know-why of the present utility model is described in conjunction with specific embodiments.These describe just in order to explain principle of the present utility model, and can not be interpreted as the restriction to the utility model protection range by any way.Based on explanation herein, those skilled in the art does not need to pay performing creative labour can associate other embodiment of the present utility model, and these modes all will fall within protection range of the present utility model.
Claims (10)
1. the switching circuit realizing two 13M pixel camera head and switch, it is characterized in that, comprise the first utilizing camera interface module, second camera interface module, be that the picture signal that the first camera and second camera catch is carried out the ISP image-signal processor of image procossing, switched the switch module of the first camera/second camera, described first utilizing camera interface module, second camera interface module, ISP image-signal processor and switch module connect mutually.
2. switching circuit as claimed in claim 1, it is characterized in that, described switching circuit also comprise power for ISP image-signal processor processor supply module, be the camera supply module that the first camera and second camera are powered, processor supply module is connected with ISP image-signal processor, camera supply module respectively, and camera supply module is connected with the first utilizing camera interface module, second camera interface module respectively.
3. switching circuit as claimed in claim 1 or 2, it is characterized in that, described switching circuit also comprises the camera filtration module that the picture signal captured for camera carries out filtering noise reduction, and camera filtration module is connected with switch module, the first utilizing camera interface module, second camera interface module respectively.
4. switching circuit as claimed in claim 1, it is characterized in that, described ISP image-signal processor comprises:
Chip U738, resistance R733-R734, electric capacity C758-C761, electric capacity C769-C785, electric capacity C797-C799, inductance L 719-L721, wherein, the model of chip U738 is THP7212_2014, the pin RD2N of described chip U738, pin RD2P, pin RD0N, pin RD0P, pin RCKN, pin RCKP, pin RD1N, pin RD1P, pin RD3N, pin RD3P is connected with switch module respectively, the pin V_CLK of chip U738 is connected with second camera interface module, the pin M_SCL of chip U738 is connected with one end of resistance R733 and second camera interface module respectively, the pin M_SDA of chip U738 is connected with one end of resistance R734 and second camera interface module respectively, the other end of resistance R733, the other end of resistance R734 is all connected with one end of inductance L 719, the other end of inductance L 719 respectively with one end of electric capacity C797, one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect, the other end of electric capacity C780, the other end of electric capacity C781, the other end of electric capacity C782, the other end of electric capacity C783 and the other end of electric capacity C784 are all connected to ground, the pin M_MSIO of chip U738, pin M_QD_HOLD, pin M_SCS is all connected with one end of inductance L 719, the pin M_QD_WPB of chip U738 is connected to ground, the pin GPIO_2 [0] of chip U738 is connected with second camera interface module, pin GPIO_2 [1] and the first utilizing camera interface model calling of chip U738, the pin VDDRX of chip U738, pin VDDREFRX, pin VDDREFTX all with one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, the other end of electric capacity C775, the other end of electric capacity C776, the other end of electric capacity C777, the other end of electric capacity C778 and the other end of electric capacity C779 are all connected to ground, the pin VDDCMOS of chip U738, VDDGPIO_0, VDDGPIO_1 is all connected with one end of inductance L 719, the pin VDDCORE of chip U738 respectively with one end of inductance L 721, one end of inductance L 720, one end of electric capacity C761, one end of electric capacity C759, one end of electric capacity C760, one end of electric capacity C758, one end of electric capacity C769, and one end of electric capacity C770 connects, the other end of electric capacity C761, the other end of electric capacity C759, the other end of electric capacity C760, the other end of electric capacity C758, the other end of electric capacity C769, and the other end of electric capacity C770 is all connected to ground, the other end of inductance L 721 respectively with one end of electric capacity C799, one end of electric capacity C785 connects, and the other end of electric capacity C785 is connected to ground, and the other end of electric capacity C799 is connected to ground, the other end of inductance L 720 respectively with one end of electric capacity C798, one end of electric capacity C775, one end of electric capacity C776, one end of electric capacity C777, one end of electric capacity C778, one end of electric capacity C779 connects, and the other end of electric capacity C798 is connected to ground, the pin BOOT [1] of chip U738, pin VDDHOST is all connected with one end of inductance L 719, and the pin BOOT [0] of chip U738 is connected to ground, the pin TEST_IN of chip U738, pin VSS is all connected to ground, and the pin VDDPLL of chip U738 is connected with one end of electric capacity C785, the pin VDDTX of chip U738, pin VHTERMRX all with one end of electric capacity C780, one end of electric capacity C781, one end of electric capacity C782, one end of electric capacity C783 and one end of electric capacity C784 connect.
5. switching circuit as claimed in claim 4, it is characterized in that, described switch module comprises:
Chip U1, electric capacity C766, wherein, the model of chip U1 is FSA644, the pin CLK-P of described chip U1, pin CLK-N, pin D1-P, pin D1-N, pin D2-P, pin D2-N, pin D3-P, pin D3-N, pin D4-P, the pin RCKP of pin D4-N difference correspondence and chip U738, pin RCKN, pin RD0P, pin RD0N, pin RD1P, pin RD1N, pin RD2P, pin RD2N, pin RD3N, pin RD3P connects, the pin CLKA-P of chip U1, pin CLKA-N, pin DA1-P, pin DA1-N, pin DA2-P, pin DA2-N, pin DA3-P, pin DA3-N, pin DA4-P, pin DA4-N respectively with the first utilizing camera interface model calling, the pin CLKB-P of chip U1, pin CLKB-N, pin DB1-P, pin DB1-N, pin DB2-P, pin DB2-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N is connected with second camera interface module respectively, the pin GND of chip U1, pin OE is all connected to ground, and the pin SEL of chip U1 is connected with the GPIO mouth of the CPU of described switching circuit outside, and the pin VCC of chip U1 is connected with one end of electric capacity C766, and the other end of electric capacity C766 is connected to ground.
6. switching circuit as claimed in claim 5, it is characterized in that, described first utilizing camera interface module comprises:
Connector J706, electric capacity C756, electric capacity C920-C921, electric capacity C924-C926, electric capacity C703, resistance R723, wherein, the model of connector J706 is AXT530124_2012, the pin 2 of described connector J706, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of the first camera respectively, also distinguishes pin DA3-P that is corresponding and chip U1, pin DA3-N, pin DA2-P, pin DA2-N, pin DA4-P, pin DA4-N, pin DA1-P, pin DA1-N, pin CLKA-P, pin CLKA-N connects, the pin 30 of connector J706 respectively with one end of electric capacity C756, one end of resistance R723, one end of electric capacity C926 connects, and the other end of electric capacity C756 is connected to ground, and the other end of resistance R723 is connected with second camera interface module, the pin 29 of connector J706 respectively with the pin GPIO_2 [1] of chip U738, one end of electric capacity C925 connects, and the pin 28 of connector J706 is connected with the pin V_CLK of chip U738, the pin 22 of connector J706 respectively with one end of electric capacity C703, one end of electric capacity C920 connects, and the other end of electric capacity C703 is connected to ground, the pin 21 of connector J706 respectively with camera supply module, one end of electric capacity C921 connects, the pin 18 of connector J706 is connected with the pin M_SCL of chip U738, the pin 17 of connector J706 is connected with the pin M_SDA of chip U738, and the pin 20 of connector J706 is connected with one end of electric capacity C924, the pin 27 of connector J706, pin 26, pin 24, pin 23, pin 19 all with the other end of electric capacity C920, the other end of electric capacity C921, the other end of electric capacity C924, the other end of electric capacity C925, the other end and the ground of electric capacity C926 connect.
7. switching circuit as claimed in claim 6, it is characterized in that, described second camera interface module comprises:
Connector J702, electric capacity C708-C709, electric capacity C714, resistance R722, wherein, the model of connector J702 is AXT530124_2012, the pin 2 of described connector J702, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 14, pin 15 is connected with each pin of second camera respectively, also distinguishes pin DB1-P that is corresponding and chip U1, pin DB1-N, pin DB2-P, pin DB2-N, pin CLKB-P, pin CLKB-N, pin DB3-P, pin DB3-N, pin DB4-P, pin DB4-N connects, and the pin 30 of connector J702 is connected with one end of resistance R722, and the other end of resistance R722 is connected with the other end of resistance R723, the pin 29 of connector J702 respectively with the pin GPIO_2 [0] of chip U738, one end of electric capacity C714 connects, the pin 28 of connector J702 is connected with the pin V_CLK of chip U738, the pin 22 of connector J702 is connected with one end of electric capacity C703, the pin 21 of connector J702 is connected with camera supply module, the pin 20 of connector J702 respectively with one end of electric capacity C708, one end of electric capacity C709 connects, the other end of electric capacity C708, the other end of electric capacity C709 is all connected to ground, and the pin 18 of connector J702 is connected with the pin M_SCL of chip U738, and the pin 17 of connector J702 is connected with the pin M_SDA of chip U738, the pin 27 of connector J702, pin 26, pin 24, pin 23, pin 19 is all connected with the other end of electric capacity C714 and ground.
8. switching circuit as claimed in claim 7, it is characterized in that, described processor supply module comprises:
Chip U788, electric capacity C765-C768, resistance R766-R768, inductance L 722, wherein, the model of chip U788 is SGM6013, the pin RUN of described chip U788 is connected with one end of resistance R768, the other end of resistance R768 is connected to ground, the pin GND of chip U788 is connected to ground, the pin FB of chip U788 respectively with one end of resistance R767, one end of resistance R766, one end of electric capacity C767 connects, the other end of resistance R767 is connected to ground, the other end of resistance R766, the other end of electric capacity C767, one end of inductance L 722, one end of electric capacity C765 all with one end of inductance L 721, one end of inductance L 720 connects, the other end of electric capacity C765 is connected to ground, the pin SW of chip U788 is connected with the other end of inductance L 722, the pin VIN of chip U788 respectively with one end of electric capacity C768, camera supply module connects, the other end of electric capacity C768 is connected to ground.
9. switching circuit as claimed in claim 8, it is characterized in that, described camera supply module comprises:
Chip U705, electric capacity C732-C733, electric capacity C704, electric capacity C755, resistance R731-R732, resistance R771, inductance L 705, the pin RUN of described chip U705 is connected with one end of resistance R771, the other end of resistance R771 is connected to ground, the pin GND of chip U705 is connected to ground, the pin FB of chip U705 respectively with one end of resistance R731, one end of resistance R732, one end of electric capacity C733 connects, the other end of electric capacity C733, the other end of resistance R732, one end of inductance L 705, one end of electric capacity C732, one end of electric capacity C704 all with the pin 21 of connector J702, the pin 21 of connector J706 connects, the pin SW of chip U705 is connected with the other end of inductance L 705, the pin VIN of chip U705 respectively with one end of electric capacity C755, the pin VIN of chip U788 connects, the other end of electric capacity C755 is connected to ground.
10. switching circuit as claimed in claim 9, it is characterized in that, described camera filtration module comprises:
Chip U704, chip U706-U709, chip U718-U720, chip U725-U726, wherein, chip U704, chip U706-U709, chip U718-U720, the model of chip U725-U726 is EXC14CE900U, the pin 1 of described chip U704 is connected with the pin CLKA-P of chip U1, the pin 2 of chip U704 is connected with the pin CLKA-N of chip U1, the pin 1 of chip U706 is connected with the pin DA1-P of chip U1, the pin 2 of chip U706 is connected with the pin DA1-N of chip U1, the pin 1 of chip U708 is connected with the pin DA2-P of chip U1, the pin 2 of chip U708 is connected with the pin DA2-N of chip U1, the pin 1 of chip U725 is connected with the pin DA3-P of chip U1, the pin 2 of chip U725 is connected with the pin DA3-N of chip U1, the pin 1 of chip U726 is connected with the pin DA4-P of chip U1, the pin 2 of chip U726 is connected with the pin DA4-N of chip U1, the pin 3 of described chip U704 is connected with the pin 9 of connector J706, the pin 4 of chip U704 is connected with the pin 8 of connector J706, the pin 3 of chip U706 is connected with the pin 3 of connector J706, the pin 4 of chip U706 is connected with the pin 2 of connector J706, the pin 3 of chip U708 is connected with the pin 6 of connector J706, the pin 4 of chip U708 is connected with the pin 5 of connector J706, the pin 3 of chip U725 is connected with the pin 12 of connector J706, the pin 4 of chip U725 is connected with the pin 11 of connector J706, the pin 3 of chip U726 is connected with the pin 15 of connector J706, the pin 4 of chip U726 is connected with the pin 14 of connector J706, the pin 1 of described chip U719 is connected with the pin DB4-P of chip U1, the pin 2 of chip U719 is connected with the pin DB4-N of chip U1, the pin 1 of chip U718 is connected with the pin DB3-P of chip U1, the pin 2 of chip U718 is connected with the pin DB3-N of chip U1, the pin 1 of chip U707 is connected with the pin DB2-P of chip U1, the pin 2 of chip U707 is connected with the pin DB2-N of chip U1, the pin 1 of chip U709 is connected with the pin DB1-P of chip U1, the pin 2 of chip U709 is connected with the pin DB1-N of chip U1, the pin 1 of chip U720 is connected with the pin CLKB-P of chip U1, the pin 2 of chip U720 is connected with the pin CLKB-N of chip U1, the pin 3 of described chip U719 is connected with the pin 15 of connector J702, the pin 4 of chip U719 is connected with the pin 14 of connector J702, the pin 3 of chip U718 is connected with the pin 12 of connector J702, the pin 4 of chip U718 is connected with the pin 11 of connector J702, the pin 3 of chip U707 is connected with the pin 6 of connector J702, the pin 4 of chip U707 is connected with the pin 5 of connector J702, the pin 3 of chip U709 is connected with the pin 3 of connector J702, the pin 4 of chip U709 is connected with the pin 2 of connector J702, the pin 3 of chip U720 is connected with the pin 9 of connector J702, the pin 4 of chip U720 is connected with the pin 8 of connector J702.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420581103.7U CN204069149U (en) | 2014-10-09 | 2014-10-09 | A kind of switching circuit realizing two 13M pixel camera head and switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420581103.7U CN204069149U (en) | 2014-10-09 | 2014-10-09 | A kind of switching circuit realizing two 13M pixel camera head and switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204069149U true CN204069149U (en) | 2014-12-31 |
Family
ID=52210586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420581103.7U Expired - Fee Related CN204069149U (en) | 2014-10-09 | 2014-10-09 | A kind of switching circuit realizing two 13M pixel camera head and switch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204069149U (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967787A (en) * | 2015-07-20 | 2015-10-07 | 广东欧珀移动通信有限公司 | Mobile terminal, camera device and control method thereof |
| CN106649167A (en) * | 2015-10-28 | 2017-05-10 | 深圳富泰宏精密工业有限公司 | Bus switching circuit and portable electronic device with bus switching circuit |
| CN106791327A (en) * | 2017-01-09 | 2017-05-31 | 广东欧珀移动通信有限公司 | CCD camera assembly, circuit board assemblies and terminal |
| CN107087115A (en) * | 2017-07-05 | 2017-08-22 | 深圳天珑无线科技有限公司 | One kind, which is taken pictures, controls circuit and method |
| CN107367332A (en) * | 2017-07-15 | 2017-11-21 | 潍坊弗莱瑞电子科技有限公司 | A kind of thermometric rises WiFi radar stealthy materials |
| WO2019205777A1 (en) * | 2018-04-28 | 2019-10-31 | Oppo广东移动通信有限公司 | Data processing method, apparatus, computer-readable storage medium, and electronic device |
| CN110832841A (en) * | 2018-04-26 | 2020-02-21 | 华为技术有限公司 | Signal switching method and terminal |
| CN111064890A (en) * | 2019-12-25 | 2020-04-24 | 安凯(广州)微电子技术有限公司 | Multi-view circuit equipment and multi-view circuit control method |
| CN112118381A (en) * | 2019-06-19 | 2020-12-22 | 深圳君正时代集成电路有限公司 | Method for controlling double cameras through single-camera controller through switch |
-
2014
- 2014-10-09 CN CN201420581103.7U patent/CN204069149U/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967787A (en) * | 2015-07-20 | 2015-10-07 | 广东欧珀移动通信有限公司 | Mobile terminal, camera device and control method thereof |
| CN104967787B (en) * | 2015-07-20 | 2018-05-04 | 广东欧珀移动通信有限公司 | Mobile terminal, camera device and its control method |
| CN106649167A (en) * | 2015-10-28 | 2017-05-10 | 深圳富泰宏精密工业有限公司 | Bus switching circuit and portable electronic device with bus switching circuit |
| CN106791327A (en) * | 2017-01-09 | 2017-05-31 | 广东欧珀移动通信有限公司 | CCD camera assembly, circuit board assemblies and terminal |
| CN107087115A (en) * | 2017-07-05 | 2017-08-22 | 深圳天珑无线科技有限公司 | One kind, which is taken pictures, controls circuit and method |
| CN107367332A (en) * | 2017-07-15 | 2017-11-21 | 潍坊弗莱瑞电子科技有限公司 | A kind of thermometric rises WiFi radar stealthy materials |
| CN110832841A (en) * | 2018-04-26 | 2020-02-21 | 华为技术有限公司 | Signal switching method and terminal |
| WO2019205777A1 (en) * | 2018-04-28 | 2019-10-31 | Oppo广东移动通信有限公司 | Data processing method, apparatus, computer-readable storage medium, and electronic device |
| US11218634B2 (en) | 2018-04-28 | 2022-01-04 | Guangdong Oppo Mobile Telecommunications Corp., Ltd. | Data processing method and apparatus, computer-readable storage medium, and electronic device |
| CN112118381A (en) * | 2019-06-19 | 2020-12-22 | 深圳君正时代集成电路有限公司 | Method for controlling double cameras through single-camera controller through switch |
| CN111064890A (en) * | 2019-12-25 | 2020-04-24 | 安凯(广州)微电子技术有限公司 | Multi-view circuit equipment and multi-view circuit control method |
| CN111064890B (en) * | 2019-12-25 | 2021-08-20 | 安凯(广州)微电子技术有限公司 | Multi-view circuit equipment and multi-view circuit control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204069149U (en) | A kind of switching circuit realizing two 13M pixel camera head and switch | |
| CN201249721Y (en) | Vehicle lane departure prewarning device | |
| CN202103758U (en) | Portable electronic device with two cameras | |
| CN202475500U (en) | USB circuit for handset and the handset | |
| CN202551195U (en) | Control device for aerial photographing and videoing | |
| CN203057540U (en) | 3G web-enabled multimedia telephone set terminal device supporting GSM/WCDMA and WIFI | |
| CN209328491U (en) | It is a kind of can integrated control LED display screen system device | |
| CN214314637U (en) | One-to-two quick-charging data line adopting TYPE-C interface input | |
| WO2017185617A1 (en) | Direct transmission device and direct transmission system for action camera | |
| CN204440854U (en) | Intelligent wireless multimedia meeting tabletop display | |
| CN204761587U (en) | City parking stall intelligent display system based on APP technique | |
| CN205071174U (en) | Double -screen display circuit of public bicycle system website controller | |
| CN102546859A (en) | Mobile phone | |
| CN102133876A (en) | Anti-deviation alarm device for automobile | |
| CN203387549U (en) | Full-angle shooting mobile phone | |
| CN206533447U (en) | Filming apparatus and mobile phone | |
| CN207150713U (en) | One kind realizes double rear camera circuits using MT6735M low sides chip | |
| CN205195807U (en) | Take clean face appearance of function of making a video recording | |
| CN205123876U (en) | Medical camera signal switchover control board | |
| CN202524472U (en) | Multifunctional camera | |
| CN203251354U (en) | Camera capable of being used for video call, storage and photographing | |
| CN203261396U (en) | Camera having light supplement lamp | |
| CN202551193U (en) | Full-high-definition high-frame-rate serial digital interface (SDI) camera | |
| CN202931459U (en) | Camera with earphone microphone | |
| CN114554084B (en) | Multi-device collaborative photographing system based on STM32 single chip microcomputer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141231 Termination date: 20171009 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |