TW201719832A - 具有高整合微電子晶粒堆疊之微電子封裝體 - Google Patents

具有高整合微電子晶粒堆疊之微電子封裝體 Download PDF

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TW201719832A
TW201719832A TW105121579A TW105121579A TW201719832A TW 201719832 A TW201719832 A TW 201719832A TW 105121579 A TW105121579 A TW 105121579A TW 105121579 A TW105121579 A TW 105121579A TW 201719832 A TW201719832 A TW 201719832A
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microelectronic
die
substrate
pillars
package
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TW105121579A
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TWI695469B (zh
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理查 裴頓
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英特爾Ｉｐ公司
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    • H—ELECTRICITY
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    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract

一種微電子封裝體可包含堆疊之微電子晶粒，其中一第一微電子晶粒係附接至一微電子基材，以及一第二微電子晶粒係堆疊在該第一微電子晶粒之至少一部份之上，其中該微電子基材包含自該微電子基材延伸之多數支柱，其中該第二微電子晶粒包含多數支柱而該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該第二微電子晶粒延伸，以及其中該等第二微電子晶粒支柱係以一附接材料附接至該等微電子基材支柱。

Description

具有高整合微電子晶粒堆疊之微電子封裝體 技術領域
本說明之實施例一般係有關於微電子封裝體製造之領域，以及，更特定地，係有關於一微電子晶粒堆疊配置而該配置減少該微電子封裝體之尺寸及高度。
背景
微電子產業係持續性力求生產較快且較小之微電子封裝體以供各種電子產品之用，包含，但不限於，電腦伺服器產品及可攜式產品，諸如可攜式電腦、電子平板、蜂巢式電話、數位相機、及類似裝置。達成此類目標之一途徑係製造其內具有堆疊微電子晶粒之微電子封裝體以導致微小側向尺寸、低封裝高度、以及微電子裝置間之高帶寬，而前述特點對行動及無線應用而言係重要考量。多種微電子晶粒堆疊配置均為習知，包含引線接合-引線接合(WBWB)堆疊、覆晶/引線接合(FCWB)堆疊、矽通孔(TSV)堆疊，以及堆疊式封裝(POP)配置。然而，此類堆疊配置可能具有顯著之缺點，而將為該等熟悉本技藝人士所習知。因此，存有一持續性努力以改善供微電子封裝體之用之微 電子晶粒堆疊。
發明概要
依據本發明之實施例，係特別提出一種微電子封裝體，包含：一微電子基材，具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；具有一主動表面及一相對之後表面之至少一第一微電子晶粒，係藉著其主動表面附接至該電子基材晶粒附接表面；以及至少一第二微電子晶粒在該至少一第一微電子晶粒之至少一部份之上延伸及具有多數支柱，該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱。
100‧‧‧微電子封裝體
110‧‧‧微電子基材
112‧‧‧晶粒附接表面
114‧‧‧外部連接表面
116‧‧‧導電路徑
122‧‧‧第一微電子晶粒附接接合墊
124‧‧‧第二微電子晶粒附接接合墊
126‧‧‧外部連接接合墊
132‧‧‧微電子基材支柱
134‧‧‧支柱-至-支柱附接材料
140‧‧‧第一微電子晶粒
140a‧‧‧第一微電子晶粒
140b‧‧‧第一微電子晶粒
142‧‧‧第一微電子晶粒主動表面
144‧‧‧第一微電子晶粒後表面
146‧‧‧第一微電子晶粒接合墊
152‧‧‧晶粒-至-基材互連件
154‧‧‧第一微電子晶粒支柱
156‧‧‧焊料凸塊
160‧‧‧第二微電子晶粒
160a‧‧‧第二微電子晶粒
160b‧‧‧第二微電子晶粒
160c‧‧‧第二微電子晶粒
160d‧‧‧第二微電子晶粒
162‧‧‧第二微電子晶粒主動表面
164‧‧‧第二微電子晶粒後表面
166‧‧‧第二微電子晶粒接合墊
172‧‧‧第二微電子晶粒支柱
174‧‧‧黏合材料
180‧‧‧鑄模材料
182‧‧‧外部附接互連件
200‧‧‧程序
202-210‧‧‧方塊
300‧‧‧計算裝置
302‧‧‧母板
304‧‧‧處理器
306A‧‧‧通訊晶片
306B‧‧‧通訊晶片
308‧‧‧DRAM
310‧‧‧ROM
312‧‧‧快閃記憶體
314‧‧‧圖形處理器/CPU
316‧‧‧晶片組
本揭示內容之標的係在本說明書之終結部份中予以特別地指出並清楚地主張。本揭示內容之前述及其他特徵將由下列說明及所附請求項，連同隨附圖式而變得更為完整地顯而易見。可理解的是隨附圖式僅說明依據本揭示內容之若干實施例以及，因此，並非被視為限制本揭示內容之範圍。本揭示內容經由隨附圖式之使用將以額外之專一性及細節加以說明，因此本揭示內容之優點可更輕易地加以確定，其中：
圖1-6係依據本說明之一實施例之用以製造圖1之一微電子封裝體之程序之一側視截面圖。
圖7-9係依據本說明之各種實施例之微電子封裝體之側視截面圖。
圖10-12係依據本說明之各種實施例之封裝前之微電子封裝體之上視圖。
圖13係依據本說明之一實施例之製造一微電子封裝體之一程序之一流程圖。
圖14係揭示依據本說明之一建置之一計算裝置。
實施例之說明
在下列詳細說明中，參考隨附圖式而該等圖式，藉由揭示，顯示特定之實施例其中所主張之標的可予以實施。此類實施例係以足夠詳細之方式加以說明以使該等熟悉本技藝人士能夠實施該標的。將理解的是各種實施例，雖然不同，但不必然相互排斥。例如，此處所說明之一特定功能、結構、或特性，雖有關於一實施例，然可在其他實施例中加以執行而不致偏離所請求標的之精神與範圍。此說明書內提及之”一(one)實施例”或”一(an)實施例”意指有關該實施例所說明之一特定功能、結構、或特性係包含在本說明中所包含之至少一建置內。因此，片語”一(one)實施例”或”在一實施例中”之使用不必然係指相同之實施例。此外，將理解的是每一揭示之實施例中之個別元件之位置或配置可加以修改而不致偏離所請求標的之精神與範圍。下列詳細說明，因此，並非以一限縮意識加以採用， 以及該標的之範圍僅藉由隨附請求項加以界定，隨同該等隨附請求項有權之完整範圍之等效物，適當地解釋。在圖式中，類似參考號碼貫穿若干視圖係指相同或類似之元件或功能，以及此處所描述之元件不必然相互符合比例，相反地，個別元件可被放大或縮小以便更容易地理解本說明之上下文中之元件。
此處所使用之術語”在...之上(over)”、”至”、”在...之間”、”在...之上(on)”可指一層相關於其他層之一相對位置。一層在另一層”之上(over)”或”之上(on)”或接合”至”另一層係可直接接觸該另一層或可具有一或多層之中間層。多數層”之間”之一層係可直接接觸該等多數層或可具有一或多層之中間層。
本說明之實施例包含一種具有堆疊微電子晶粒之微電子封裝，其中一第一微電子晶粒係附接至一微電子基材，以及一第二微電子晶粒係堆疊至該第一微電子晶粒之至少一部份之上，其中該微電子基材包含自該微電子基材延伸之多數支柱，其中該第二微電子晶粒包含多數支柱而該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該第二微電子晶粒延伸，以及其中該等第二微電子晶粒支柱係以一附接材料附接至該等微電子基材支柱。
圖1-5係揭示製造一微電子封裝體之一實施例。如圖1所示，一微電子基材110可被形成。微電子基材110可為任何適當之基材，諸如一中介層或類似物，具有一晶粒附接表面112及一相對外部連接表面114。微電子基材110可 具有多數接合墊，包含形成在微電子基材晶粒附接表面112之內或之上之至少一第一微電子晶粒附接接合墊122及至少一第二微電子晶粒附接接合墊124。微電子基材110亦可具有形成在微電子基材外部連接表面114之上或之內之多數個外部連接接合墊126。微電子基材110可包含多數介電層(未顯示)而該等介電層具有貫穿其間而形成之多數導電路徑116，其中導電路徑116可形成適當接合墊之間之連接，諸如第一微電子晶粒附接接合墊122、第二微電子晶粒附接接合墊124、及/或外部連接接合墊126。
微電子基材110可包含任何適當介電材料，包含，但不限於，液晶聚合物、環氧樹脂、雙馬來亞醯胺三氮雜苯樹脂、FR4、聚亞醯胺材料、及類似物。導電路徑116可由任何適當導電材料形成，包含，但不限於，銅、銀、金、鎳、及其合金。可理解的是微電子基材110可由任何數量之介電層所形成、可包含一硬質核心(未顯示)、以及可包含形成於其內部之主動及/或被動微電子裝置(未顯示)。可進一步理解的是導電路徑116可在微電子基材110內形成任何所期望之電氣路徑及/或具有額外之外部組件(未顯示)。亦可理解的是阻焊劑層(未顯示)可在微電子基材晶粒附接表面112及/或微電子基材外部連接表面114上使用，而將為該等熟悉本技藝人士所理解。用以形成微電子基材110之程序對於該等熟悉本技藝人士而言係習知者，以及基於簡短及簡要之故，將不在此處說明或揭示。
如圖1進一步所顯示者，一微電子基材支柱132 可附接至每一第二微電子晶粒附接接合墊124，其中微電子基材支柱132延伸至微電子基材晶粒附接表面112之上方。微電子基材支柱132可由任何適當之導電材料製成，包含，但不限於，銅、銀、金、鎳、及其合金。一支柱-至-支柱附接材料134可沉積在每一微電子基材支柱132上。在一實施例中，支柱-至-支柱附接材料134可鄰近微電子基材支柱132之一端部沉積而該端部係實質上相對其個別之第二微電子晶粒附接接合墊124。支柱-至-支柱附接材料134可為任何適當之材料，包含，但不限於，焊料諸如鉛/錫合金(例如63%錫/37%鉛焊料)或無鉛焊料，諸如一純錫或高錫含量合金(例如90%或更多之錫)，諸如錫/鉍、共熔錫/銀、三元錫/銀/銅、共熔錫/銅、及類似合金。
如圖2所示，一具有一主動表面142及一相對後表面144之第一微電子晶粒140可依一通常習知之一覆晶配置或受控崩潰晶片連接(C4)配置而以多數晶粒-至-基材互連件152附接至對應之第一微電子晶粒附接接合墊122。晶粒-至-基材互連件152可在微電子基材110之第一微電子晶粒附接接合墊122與第一微電子晶粒主動表面142上之鏡像接合墊146之間延伸以在其間形成一電氣連接。晶粒-至-基材互連件152可包含附接至第一微電子晶粒接合墊146之一第一微電子晶粒支柱154及一焊料凸塊156而該焊料凸塊係將第一微電子晶粒支柱154附接至微電子基材110之其個別第一微電子晶粒附接接合墊122。將為該等熟悉本技藝人士所理解的是，多數晶粒-至-基材互連件152可僅為在微電子基 材110之第一微電子晶粒附接接合墊122與第一微電子晶粒接合墊146之間延伸之焊料凸塊156而並無第一微電子晶粒支柱154。可理解的是第一微電子晶粒接合墊146可與第一微電子晶粒140內之積體電路(未顯示)形成電氣連通。第一微電子晶粒140可為任何適當之微電子裝置，包含，但不限於，一微處理器、一晶片組、一圖形裝置、一無線裝置、一記憶體裝置、一特定應用積體電路裝置、及類似裝置。
第一微電子晶粒支柱154可由任何適當導電材料製成，包含，但不限於，銅、銀、金、鎳、及其合金。焊料凸塊156可由任何適當材料製成，包含，但不限於，焊料諸如鉛/錫合金(例如63%錫/37%鉛焊料)或無鉛焊料，諸如一純錫或高錫含量合金(例如90%或更多之錫)，諸如錫/鉍、共熔錫/銀、三元錫/銀/銅、共熔錫/銅、及類似合金。當第一微電子晶粒140附接至微電子基材110時，焊料凸塊156係藉著熱量、壓力、及/或聲能加以回焊以固定第一微電子晶粒支柱154與第一微電子晶粒附接接合墊122間之焊料。可進一步理解的是，一電氣性絕緣可流動材料，諸如一下填材料(未顯示)，可配置在第一微電子晶粒140與微電子基材110之間，而該下填材料實質上封裝晶粒-至-基材互連件152。
如圖3所示，一具有一主動表面162及一相對後表面164之第二微電子晶粒160可附接至微電子基材110，因此第二微電子晶粒160之一部份係在第一微電子晶粒140之一部份之上延伸。第二微電子晶粒160可具有形成在第二微電 子晶粒主動表面162之內或之上之至少一接合墊166，其中第二微電子晶粒接合墊166可與微電子基材110之第二微電子晶粒附接接合墊124呈一鏡像配置。一第二微電子晶粒支柱172可附接至每一第二微電子晶粒接合墊166，其中第二微電子晶粒支柱172自第二微電子晶粒主動表面162延伸，而此舉導致第二微電子晶粒支柱172與微電子基材支柱132呈一鏡像配置。第二微電子晶粒支柱172可由任何適當之導電材料製成，包含，但不限於，銅、銀、金、鎳、及其合金。第二微電子晶粒160可以支柱-至-支柱附接材料134附接至微電子基材110。在一實施例中，支柱-至-支柱附接材料134為一焊料材料，而該支柱-至-支柱附接材料134係藉著熱量、壓力、及/或聲能加以回焊以固定微電子基材支柱132與第二微電子晶粒支柱172間之焊料。在一實施例中，支柱-至-支柱附接材料134之一部份可配置在微電子基材支柱132與第二微電子晶粒支柱172之間。
如圖3進一步所示，第二微電子晶粒主動表面162之至少一部份可以一黏合材料174任選地固定至第一微電子晶粒後表面144。
可理解的是，在附接第二微電子晶粒160以形成圖3之結構之前，支柱-至-支柱附接材料134可沉積在第二微電子晶粒支柱172上，如圖4所示，而不是將支柱-至-支柱附接材料134沉積在微電子基材支柱132上，如圖1所示。
可理解的是，第二微電子晶粒接合墊166可與第二微電子晶粒160內之積體電路(未顯示)形成電氣連通。第 二微電子晶粒160可為任何適當之微電子晶粒，包含，但不限於，一微處理器、一晶片組、一圖形裝置、一無線裝置、一記憶體裝置、一特定應用積體電路裝置、及類似裝置。
如圖5所示，在附接第二微電子晶粒160之後，一鑄模材料180可配置在第一微電子晶粒140及第二微電子晶粒160之上以形成一微電子封裝體100。在一實施例中，鑄模材料180可實質上封裝第一微電子晶粒140與第二微電子晶粒160，以及微電子基材支柱132、第二微電子晶粒支柱172、及支柱-至-支柱附接材料134。鑄模材料180可為任何適當之封裝材料，諸如一環氧樹脂及充填式環氧樹脂。鑄模材料180可藉著一習知方法形成，包含，但不限於，一鑄模下填程序或一晶片下填程序且接續一習知鑄模程序，此鑄模材料注入一模具槽，而此將為該等熟悉本技藝人士所理解。
如圖6所示，外部附接互連件182可形成在微電子基材110之外部連接接合墊126上俾將微電子封裝體100附接至任何外部組件(未顯示)，諸如一母板。在一實施例中，外部附接互連件182可包含焊料球。
可理解的是，微電子封裝體100可具有各種組件配置。在圖7所示之一實施例中，微電子封裝體100可包含多數個第一微電子晶粒(標識為元件140a及140b)。在圖8所示之另一實施例中，微電子封裝體100具有一第二微電子晶粒160而該晶粒並未在第一微電子晶粒140上完全地延伸。在圖9所示之又一實施例中，微電子封裝體100可包含多數個第二微電子晶粒(標示為元件160a及160b)。
可理解的是，微電子封裝體100可具有各種安置配置，其中圖10-12係揭示未顯示鑄模材料180之微電子封裝體100之上視平面圖。如圖10所示，微電子封裝體100可包含第一微電子晶粒140係完全地配置在微電子基材110與第二微電子晶粒160之間，此可對應於圖5。如圖11所示，微電子封裝體100可包含一對第二微電子晶粒(標示為160a及160b)而該對第二微電子晶粒兩者均跨坐第一微電子晶粒140之一部份。如圖12所示，微電子封裝體100可包含若干第二微電子晶粒(標示為160a、160b、160c及160d)，而每一第二微電子晶粒均跨坐第一微電子晶粒140之一部份。
圖13係依據本說明之一實施例之製造一微電子封裝體之一程序200之一流程圖。如方塊202中所陳述者，可形成一微電子基材具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱。可形成至少一第一微電子晶粒具有一主動表面及一相對後表面，如方塊204中所陳述者。如方塊206中所陳述者，該至少一第一微電子晶粒可藉著其主動表面附接至該微電子基材晶粒附接表面。至少一第二微電子晶粒具有多數支柱而該等支柱以一與該等多數微電子基材支柱呈一鏡像配置之方式自該第二微電子晶粒之一主動表面延伸，如方塊208中所陳述者。如方塊210中所陳述者，該至少一第二微電子晶粒係附接至該微電子基材，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱以及其中該至少一第二微電子晶粒係在該至少一第一微電子晶粒之至少 一部份之上延伸。
圖14係揭示依據本說明之一建置之一計算裝置300。計算裝置300收容一母板302。該母板可包含若干微電子組件，包含，但不限於，一處理器304、至少一通訊晶片306A、306B、依電性記憶體308(例如，DRAM)、非依電性記憶體310(例如，ROM)、快閃記憶體312、一圖形處理器或CPU 314、一數位信號處理器(未顯示)、一密碼處理器(未顯示)、一晶片組316、一天線、一顯示裝置(觸控螢幕顯示裝置)、一觸控螢幕控制器、一電池、一音頻編碼解碼器(未顯示)、一視頻編碼解碼器(未顯示)、一功率放大器(AMP)、一全球定位系統(GPS)裝置、一羅盤、一加速度計(未顯示)、一陀螺儀(未顯示)、一揚聲器(未顯示)、一照相機、以及一大量儲存裝置(未顯示)(諸如硬碟驅動機、光碟(CD)、數位多功能光碟(DVD)、等)。任何微電子組件均可實體性或電氣性耦接至母板302。在某些建置中，至少一微電子組件可為處理器304之一部份。
通訊晶片能夠促成無線通訊以供資料傳送至計算裝置及自計算裝置傳送資料之用。術語"無線"及其衍生術語可用以說明可經由一非固態媒介藉著調變電磁輻射之使用以傳送資料之電路、裝置、系統、方法、技術、通訊頻道、等。雖然在某些實施例中該等關聯裝置可能未包含線路，然而該術語並非意味該等關聯裝置未包含任何線路。該通訊晶片可執行若干無線標準或協定中之任何標準或協定，包含，但不限於，Wi-Fi(IEEE 802.11家族),WiMAX (IEEE 802.16家族),IEEE 802.20，長程演進技術(LTE),Ev-DO,HSPA+,HSDPA+,HSUPA+,EDGE,GSM,GPRS,CDMA,TDMA,DECT，藍芽，及其衍生標準或協定，以及任何其他被指定為3G、4G、5G及以上之無線協定。計算裝置可包含多數通訊晶片。例如，一第一通訊晶片可專屬於較短範圍之無線通訊諸如Wi-Fi及藍芽以及一第二通訊晶片可專屬於較長範圍之無線通訊諸如GPS,EDGE,GPRS,CDMA,WiMAX,LTE,Ev-DO，及其他無線通訊。
術語”處理器”可指任何裝置或一裝置之部份而該裝置係處理來自暫存器及/或記憶體之電子資料以將該等電子資料轉換成可儲存在暫存器及/或記憶體中之其他電子資料。
計算裝置300中之任何微電子組件均可包含具有一微電子晶粒堆疊之一微電子封裝體，如此處所說明者。
在各種建置中，計算裝置可為一膝上型電腦、一上網本型電腦、一筆記型電腦、一超薄型筆電、一智慧型手機、一平板、一個人數位助理器(PDA)、一超薄型行動個人電腦、一行動電話、一桌上型電腦、一伺服器、一印表機、一掃描器、一監視器、一機上盒、一娛樂控制單元、一數位相機、一可攜式音樂播放器、或一數位錄影機。在進一步建置中，計算裝置可為任何其他處理資料之電子裝置。
可理解的是，本說明之標的不必然受限於圖1-14中所揭示之特定應用。該標的可應用於其他微電子裝置及組合應用，如將為該等熟悉本技藝人士所理解者。
下列實例係有關進一步之實施例，其中實例1係一種微電子封裝體，包含一微電子基材具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；具有一主動表面及一相對後表面之至少一第一微電子晶粒係藉著其主動表面附接至該電子基材晶粒附接表面；以及至少一第二微電子晶粒在該至少一第一微電子晶粒之至少一部份之上延伸及具有多數支柱而該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱。
在實例2中，實例1之該標的可任選地包含該附接材料包含一焊料材料。
在實例3中，實例1之該標的可任選地包含一鑄模材料配置在該第一微電子晶粒及該第二微電子晶粒之上。
在實例4中，實例2之該標的可任選地包含該鑄模材料封裝該第一微電子晶粒；該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
在實例5中，實例1之該標的可任選地包含一黏合材料配置在該第一微電子晶粒後表面與該第二微電子晶粒主動表面之間。
在實例6中，實例1至5中之任一實例之該標的可任選地包含該微電子基材進一步包含相對於該微電子基材晶粒附接表面之一外部連接表面以及進一步包含至少一外 部附接互連件附接至該微電子基材外部連接表面。
在實例7中，實例1至5中之任一實例之該標的可任選地包含該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
在實例8中，實例1之該標的可任選地包含該微電子基材包含多數第二微電子晶粒附接接合墊以及其中該等多數微電子基材支柱係附接至該等多數第二微電子晶粒附接接合墊。
在實例9中，實例1之該標的可任選地包含該第二微電子晶粒包含多數接合墊以及其中該等多數第二微電子晶粒支柱係附接至該等多數第二微電子晶粒接合墊。
下列實例係有關進一步之實施例，其中實例10係一種製造一微電子封裝體之方法包含形成一微電子基材具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；形成至少一第一微電子晶粒具有一主動表面及一相對後表面；藉著該至少一第一微電子晶粒之該主動表面將該至少一第一微電子晶粒附接至該微電子基材晶粒附接表面；形成至少一第二微電子晶粒具有多數支柱而該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸；以及將該至少一第二微電子晶粒附接至該微電子基材，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱以及其中該至少一第二微電子晶粒在該至少一第一微電子晶粒之至少一部份之上延伸。
在實例11中，實例10之該標的可任選地包含將該等多數第二微電子晶粒支柱中之每一支柱以包含一焊料材料之一附接材料附接至一個別微電子基材支柱。
在實例12中，實例10之該標的可任選地包含將一鑄模材料配置在該第一微電子晶粒及該第二微電子晶粒之上。
在實例13中，實例12之該標的可任選地包含配置該鑄模材料以封裝該第一微電子晶粒、該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
在實例14中，實例10之該標的可任選地包含在該第一微電子晶粒後表面與該第二微電子晶粒主動表面之間配置一黏合材料。
在實例15中，實例10至14中之任一實例之該標的可任選地包含該微電子基材進一步包含相對於該微電子基材晶粒附接表面之一外部連接表面以及進一步包含在該微電子基材外部連接表面上形成至少一外部附接互連件。
在實例16中，實例10至14中之任一實例之該標的可任選地包含將該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
在實例17中，實例10之該標的可任選地包含在該微電子基材晶粒附接表面之內或之上形成多數第二微電子晶粒附接接合墊以及其中該等多數微電子基材支柱係附接至該等多數第二微電子晶粒附接接合墊。
在實例18中，實例10之該標的可任選地包含形成 該第二微電子晶粒進一步包含在該第二微電子晶粒主動表面之內或之上形成多數接合墊以及其中該等多數第二微電子晶粒支柱係附接至該等多數第二微電子晶粒接合墊。
下列實例係有關進一步之實施例，其中實例19係一種製造一電子系統之方法，包含一母板；以及在該母板上之一微電子封裝體，其中該微電子封裝體包含一微電子基材具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；具有一主動表面及一相對後表面之至少一第一微電子晶粒藉著其主動表面附接至該微電子基材晶粒附接表面；以及至少一第二微電子晶粒在該至少一第一微電子晶粒之至少一部份之上延伸以及具有多數支柱而該等支柱以一與該等多數微電子基材支柱呈一鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱。
在實例20中，實例19之該標的可任選地包含該附接材料包含一焊料材料。
在實例21中，實例19之該標的可任選地包含一鑄模材料配置在該第一微電子晶粒及該第二微電子晶粒之上。
在實例22中，實例20之該標的可任選地包含該鑄模材料封裝該第一微電子晶粒、該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
在實例23中，實例19之該標的可任選地包含一黏 合材料配置在該第一微電子晶粒後表面與該第二微電子晶粒主動表面之間。
在實例24中，實例19至23中之任一實例之該標的可任選地包含該微電子基材進一步包含相對於該微電子基材晶粒附接表面之一外部連接表面以及進一步包含至少一外部附接互連件附接至該微電子基材外部連接表面。
在實例25中，實例19至23中之任一實例之該標的可任選地包含該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
在實例26中，實例19之該標的可任選地包含該微電子基材包含多數第二微電子晶粒附接接合墊以及其中該等多數微電子基材支柱係附接至該等多數第二微電子晶粒附接接合墊。
在實例27中，實例19之該標的可任選地包含該第二微電子晶粒包含多數接合墊以及其中該等多數第二微電子晶粒支柱係附接至該等多數第二微電子晶粒接合墊。
已如此詳細說明本說明之實施例，可理解的是隨附請求項所界定之本說明並非受上述說明中所陳述之特定細節所限，因為該等特定細節之許多變化均為可能而不致偏離本說明之精神與範圍。
110‧‧‧微電子基材
112‧‧‧晶粒附接表面
114‧‧‧外部連接表面
116‧‧‧導電路徑
122‧‧‧第一微電子晶粒附接接合墊
124‧‧‧第二微電子晶粒附接接合墊
126‧‧‧外部連接接合墊
132‧‧‧微電子基材支柱
134‧‧‧支柱-至-支柱附接材料

Claims (25)

  1. 一種微電子封裝體，包含：一微電子基材，具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；具有一主動表面及一相對之後表面之至少一第一微電子晶粒，係藉著其主動表面附接至該電子基材晶粒附接表面；以及至少一第二微電子晶粒，在該至少一第一微電子晶粒之至少一部份之上延伸及具有多數支柱，該等支柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱。
  2. 如請求項1之微電子封裝體，其中該附接材料包含一焊料材料。
  3. 如請求項1之微電子封裝體，進一步包含一鑄模材料，配置在該第一微電子晶粒及該第二微電子晶粒之上。
  4. 如請求項3之微電子封裝體，其中該鑄模材料封裝該第一微電子晶粒；該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
  5. 如請求項1之微電子封裝體，進一步包括一黏合材料，配置在該第一微電子晶粒後表面與該第二微電子晶粒 主動表面之間。
  6. 如請求項1之微電子封裝體，其中該微電子基材進一步包括與該微電子基材晶粒附接表面相對之一外部連接表面，以及進一步包括至少一外部附接互連件，其附接至該微電子基材外部連接表面。
  7. 如請求項1之微電子封裝體，其中該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
  8. 如請求項1之微電子封裝體，其中該微電子基材包括多數第二微電子晶粒附接接合墊，以及其中該等多數微電子基材支柱係附接至該等多數第二微電子晶粒附接接合墊。
  9. 如請求項1之微電子封裝體，其中該第二微電子晶粒包括多數接合墊，以及其中該等多數第二微電子晶粒支柱係附接至該等多數第二微電子晶粒接合墊。
  10. 一種形成一微電子封裝體之方法，包含：形成一微電子基材，其具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；形成至少一第一微電子晶粒，其具有一主動表面及一相對之後表面；藉著該至少一第一微電子晶粒之該主動表面將該至少一第一微電子晶粒附接至該微電子基材晶粒附接表面；形成至少一第二微電子晶粒，其具有多數支柱，該等支 柱以一與該等多數微電子基材支柱呈鏡像配置之方式自該至少一第二微電子晶粒之一主動表面延伸；以及將該至少一第二微電子晶粒附接至該微電子基材，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱，以及其中該至少一第二微電子晶粒在該至少一第一微電子晶粒之至少一部份之上延伸。
  11. 如請求項10之方法，其中將該至少一第二微電子晶粒附接至該微電子基材包含將該等多數第二微電子晶粒支柱中之每一支柱以包含一焊料材料之一附接材料附接至一個別微電子基材支柱。
  12. 如請求項10之方法，進一步包含將一鑄模材料配置在該第一微電子晶粒及該第二微電子晶粒之上。
  13. 如請求項12之方法，其中配置該鑄模材料封裝該第一微電子晶粒、該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
  14. 如請求項10之方法，進一步包含在該第一微電子晶粒後表面與該第二微電子晶粒主動表面之間配置一黏合材料。
  15. 如請求項10之方法，其中該微電子基材進一步包括與該微電子基材晶粒附接表面相對之一外部連接表面，以及進一步包括在該微電子基材外部連接表面上形成至少一外部附接互連件。
  16. 如請求項10之方法，其中將該至少一第一微電子晶粒藉 著其主動表面附接至該微電子基材晶粒附接表面包含將該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
  17. 如請求項10之方法，其中形成該微電子基材進一步包含在該微電子基材晶粒附接表面之內或之上形成多數第二微電子晶粒附接接合墊，以及其中該等多數微電子基材支柱係附接至該等多數第二微電子晶粒附接接合墊。
  18. 如請求項10之方法，其中形成該第二微電子晶粒進一步包含在該第二微電子晶粒主動表面之內或之上形成多數接合墊，以及其中該等多數第二微電子晶粒支柱係附接至該等多數第二微電子晶粒接合墊。
  19. 一種電子系統，包含：一板；以及在該板上之一微電子封裝體，其中該微電子封裝體包含：一微電子基材，具有一晶粒附接表面及自該微電子基材晶粒附接表面延伸之多數支柱；具有一主動表面及一相對之後表面之至少一第一微電子晶粒，藉著其主動表面附接至該微電子基材晶粒附接表面；以及至少一第二微電子晶粒，其在該至少一第一微電子晶粒之至少一部份之上延伸以及具有多數支柱，該等支柱以一與該等多數微電子基材支柱呈一鏡像配置之方式自 該至少一第二微電子晶粒之一主動表面延伸，其中該等多數第二微電子晶粒支柱中之每一支柱均以一附接材料附接至一個別微電子基材支柱。
  20. 如請求項19之微電子封裝體，其中該附接材料包含一焊料材料。
  21. 如請求項19之微電子封裝體，進一步包含一鑄模材料，配置在該第一微電子晶粒及該第二微電子晶粒之上。
  22. 如請求項21之微電子封裝體，其中該鑄模材料封裝該第一微電子晶粒、該第二微電子晶粒、該等多數微電子基材支柱、該等多數第二微電子晶粒支柱、以及該附接材料。
  23. 如請求項19之微電子封裝體，進一步包括一黏合材料，配置在該第一微電子晶粒後表面與該第二微電子晶粒主動表面之間。
  24. 如請求項19之微電子封裝體，其中該微電子基材進一步包括與該微電子基材晶粒附接表面相對之一外部連接表面，以及進一步包括至少一外部附接互連件，其附接至該微電子基材外部連接表面。
  25. 如請求項19之微電子封裝體，其中該至少一第一微電子晶粒藉著其主動表面以至少一互連件附接至該微電子基材晶粒附接表面。
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US20210035950A1 (en) 2021-02-04
DE112015006855T5 (de) 2018-08-16
TWI695469B (zh) 2020-06-01
US20190109114A1 (en) 2019-04-11
US11527507B2 (en) 2022-12-13
US10872881B2 (en) 2020-12-22
US10622333B2 (en) 2020-04-14
WO2017039581A1 (en) 2017-03-09

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