TW201717283A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device, including: a substrate; a well region disposed in the substrate and having a first conductive type; an isolation structure disposed in the substrate and surrounding an active region in the well region; a source region disposed in the active region and in the well region; a drain region disposed in the active region and in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region, wherein the first conductive type is different from the second conductive type; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode; and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to a semiconductor device and a method of fabricating the same, and in particular to a field effect transistor and a method of fabricating the same.

Most of the junction field effect transistors are used for analog switches and signal amplifiers, and are especially used for low noise amplifiers.

For field effect transistors, the electric field close to the carrier channel is mainly changed by controlling a signal (or gate bias), which changes the nature of the channel and the current characteristics (between the source and the drain). Therefore, the field effect transistor can be used as a voltage-controlled adjustable resistor, a voltage controlled current source (VCCS), or the like. By the above principle, the channel properties and current characteristics of the junction field effect transistor can be changed by changing the width of the depletion region in the PN junction between the gate and the source/drain. Thereby, the function of the above width has an inverse relationship with the voltage.

Lowering the gate voltage increases the depletion region in the PN junction. If this gate voltage is low enough, all channels will be depleted and no current will flow from the drain to the source. The width of the channel that is completely depleted can be referred to as pinched off. The gate voltage at which this effect occurs is called a pinch-off voltage. The semiconductor device of the disclosed embodiment has a low and adjustable pinch-off voltage, and the disclosed embodiment also provides the half that can further reduce the manufacturing cost. A method of manufacturing a conductor device.

The present disclosure provides a semiconductor device comprising: a substrate; a well region disposed in the substrate and having a first conductivity type; an isolation structure disposed in the substrate and surrounding the active region in the well region; and a source region disposed on the active region In the middle and the well area; the bungee area is disposed in the active area and the well area; the second conductive type first doped area is disposed in the well area and disposed along the edge of the active area, wherein the first conductive The second conductivity type is different from the second conductivity type; the second conductivity type second doping region is disposed in the well region, and is disposed under the source region, the drain region and the second conductivity type first doping region, wherein the second The conductive second doped region is in direct contact with the second conductive type first doped region; the source electrode is electrically connected to the source region; the drain electrode is electrically connected to the drain region; and the gate electrode is electrically connected a second conductivity type first doped region.

The disclosure further provides a method for manufacturing a memory device, comprising: providing a substrate; forming a well region in the substrate, wherein the well region has a first conductivity type; forming an isolation structure in the substrate, wherein the isolation structure surrounds the active region in the well region Forming a source region in the active region and in the well region; forming a drain region in the active region and in the well region; forming a second conductivity type first doping region in the well region, wherein the second conductivity type is first The doped region is disposed along an edge of the active region, wherein the first conductive type is different from the second conductive type; the second conductive type second doped region is formed in the well region, and the second conductive type second doped region is set Under the source region, the drain region and the second conductivity type first doping region, wherein the second conductivity type second doping region is in direct contact with the second conductivity type first doping region; forming a source electrode, the source The pole electrode is electrically connected to the source region; the drain electrode is formed, the drain electrode is electrically connected to the drain region; and the gate electrode is formed, and the gate electrode is electrically connected to the second conductive type first doped region.

In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100‧‧‧Substrate

100A‧‧‧Upper surface

100B‧‧‧ lower surface

102‧‧‧Doped isolation zone

104‧‧‧ Well Area

106‧‧‧Isolation structure

108‧‧‧active area

110‧‧‧ source area

112‧‧‧Bungee Area

114‧‧‧Second Conductive Type First Doped Area

116‧‧‧Second Conductive Second Doped Region

118‧‧‧Isolated sub-well area

120‧‧‧Channel area

122‧‧‧The gate area

124‧‧‧metal telluride layer

126‧‧‧metal telluride layer

128‧‧‧metal telluride layer

130‧‧‧Source electrode

132‧‧‧汲electrode

134‧‧‧gate electrode

200‧‧‧Semiconductor device

W1‧‧‧Width

D1‧‧ depth

D2‧‧ depth

D3‧‧ depth

2A-2A’‧‧‧ Segment

3A-3A’‧‧‧ Segment

4A-4A’‧‧‧ Segment

5B-5B’‧‧‧ Segment

5C-5C’‧‧‧ Segment

1 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

2A-2B is a cross-sectional view and a top view of a semiconductor device in accordance with one of the steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

3A-3B are cross-sectional and top views of a semiconductor device in accordance with a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

4A-4B are cross-sectional and top views of a semiconductor device in accordance with a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

5A-5C are cross-sectional and top views of a semiconductor device in accordance with a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure.

Figure 6 is a graph showing the analysis of the gate voltage versus current of a semiconductor device in accordance with some embodiments of the present disclosure.

Figure 7 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

Hereinafter, the semiconductor device and the method of manufacturing the same will be described in detail. It should be understood that the following description provides many different embodiments or examples. Sub, to implement the same state of the disclosure. The specific elements and arrangements described below are merely illustrative of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It must be understood that the elements or devices of the drawings may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It will be understood that if the device of the drawing is flipped upside down, the component described on the "lower" side will become the component on the "higher" side.

Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, in the absence of specific descriptions of "about", "about" and "major", the meanings of "about", "about" and "major" may still be implied.

Understandably, although the terms "first" and "first" can be used here. 2, 3, etc., to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts are not limited by these terms, and these terms are only It is used to distinguish between different components, components, regions, layers, and/or portions. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the disclosure. section.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined herein.

The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not shown in the form of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the present disclosure. In addition, the structures and devices in the drawings are schematically illustrated in order to clearly illustrate the features of the disclosure.

In this disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. shall be understood as The orientation shown in the paragraph and related schemas. This relative term is used for convenience of description only, and does not mean that the device described therein is to be manufactured or operated in a particular orientation. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may refer to direct contact between two structures, or It means that the two structures are not in direct contact, and other structures are provided between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.

It should be noted that the term "substrate" may be used hereinafter to include formed elements on a semiconductor wafer and various film layers overlying the wafer, and any desired semiconductor elements may have been formed thereon, but here Simplified drawing, represented only by a flat substrate. In addition, the "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a germanium surface, an insulating layer, and/or metal lines.

Embodiments of the present disclosure utilize an isolated sub-well region to eliminate the need for a mask layer to form a channel and thereby reduce production costs. In addition, the semiconductor device of the embodiment of the present disclosure can have a low and adjustable pinch-off voltage by the special configuration of the source region, the drain region, the gate region and the channel.

1-5C is a cross-sectional view or a top view of each stage of the semiconductor device of the disclosed embodiment in its manufacturing method. Referring to Figure 1, a substrate 100 is provided. The substrate 100 includes an upper surface 100A and a lower surface 100B.

The substrate 100 may be an elemental semiconductor including germanium, germanium having a single crystal, polycrystalline or amorphous structure; a compound semiconductor including amorphous germanium, polycrystalline germanium, indium gallium zinc oxide, and nitriding. Gallium nitride, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide or indium sulphide (indium) Antimonide); alloy semiconductors, including germanium alloys (SiGe), phosphorus gallium arsenide alloys (GaAsP), arsenic aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (A1GaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or the like combination.

In some embodiments, the substrate 100 may further include an epitaxial layer (not shown) on the semiconductor. . The epitaxial layer may comprise ruthenium, osmium, iridium and osmium, a III-V compound or a combination thereof. The epitaxial layer can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), metal organic chemical vapor deposition (MOVPE), plasma enhanced chemical vapor deposition. (plasma-enhanced CVD), remote controlled plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), It is formed by chloride vapor phase epitaxy (Cl-VPE) or the like.

Next, a doped isolation region 102 and a well region 104 are formed in the substrate 100. This well region 104 is formed over this doped isolation region 102. The well region 104 has a first conductivity type, and the doped isolation region 102 can have a first conductivity type or a second conductivity type, and the first conductivity type is different from the second conductivity type.

This well region 104 can be formed by an ion implantation step. For example, when the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the well region 104 is to be formed to form the well region 104.

It should be noted that in the described embodiment, if not specifically referred to as "lightly doped" or "heavily doped", "doping" means a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example It is a doping concentration of about 10 ¹⁵ /cm ³ . In other words, in some embodiments, the doping concentration of the well region 104 may be a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example, about 10 ¹⁵ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "doping" can also be determined by the particular device type, technology generation, minimum component size, and the like. Thus, the definition of "doping" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

Next, Fig. 2B is a top view of the substrate 100 of the disclosed embodiment, and Fig. 2A is a cross-sectional view of the disclosed embodiment taken along line 2A-2A' of Fig. 2B. Referring to FIGS. 2A and 2B, an isolation structure 106 is formed in the substrate 100. This isolation structure 106 surrounds the active region 108 in the well region 104. The material of the isolation structure 106 can include, but is not limited to, shallow trench isolation 106.

In some embodiments, the isolation structure 106 can be formed by the following steps. First, a trench is formed in a region where the isolation structure 106 is to be formed. This trench can be formed by an etching step. This etching step includes dry etching, wet etching, or a combination thereof. This wet etch can include immersion etching, spray etching, combinations of the above, or other suitable dry etch. The dry etching step includes capacitively coupled plasma etching, inductively coupled plasma etching, spiral plasma etching, electron cyclotron resonance plasma etching, combinations of the foregoing, or other suitable dry etching. The gas used in this dry etching step may include an inert gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, a combination of the above gases, or any other suitable gas. In some embodiments, the gas used in the dry etching step includes Ar, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , C ₂ F ₆ , Cl ₂ , CHCl ₃ , CCl ₄ , HBr, CHBr ₃ , BF. _3. BCl ₃ , a combination of the above gases or any other suitable gas.

Next, an insulating material is filled in the trench to form the isolation structure 106. The insulating material may be tantalum oxide, tantalum nitride, niobium oxynitride, any other suitable insulating material formed by chemical vapor deposition (CVD), or the like. combination. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), or rapid temperature chemical vapor deposition (rapid). Thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer chemical vapor deposition (atomic layer deposition (ALD) or other commonly used methods) .

Next, Fig. 3B is a top view of the substrate 100 of the disclosed embodiment, and Fig. 3A is a cross-sectional view of the disclosed embodiment taken along line 3A-3A' of Fig. 3B. Referring to Figures 3A and 3B, source region 110 and drain region 112 are formed in active region 108 and well region 104. The source region 110 and the drain region 112 may have a first conductivity type and may be heavily doped.

In the embodiment, "heavily doped" means a doping concentration exceeding about 10 ¹⁷ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "heavily doped" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "heavily doped" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

The source region 110 and the drain region 112 can be formed by an ion implantation step. For example, when the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the source region 110 and the drain region 112 are predetermined to form the source region 110 and the drain region 112.

In addition, referring also to FIGS. 3A-3B, a second conductivity type first doped region 114 is formed in the well region 104. In addition, as shown in FIG. 3B, the second conductivity type is first Doped regions 114 are disposed along the edges of active regions 108. The second conductivity type first doping region 114 may have a second conductivity type and may be heavily doped.

The second conductivity type first doping region 114 can be formed by an ion implantation step. For example, when the second conductivity type is a P-type, boron ions, indium ions or boron trifluoride ions may be implanted in a region where the second conductivity type first doping region 114 is to be formed to form a second conductivity type first. Doped region 114.

Moreover, in some embodiments, this second conductivity type first doped region 114 directly contacts the isolation structure 106. In more detail, the second conductivity type first doping region 114 is along the four sides of the isolation structure 106 and the four sides of the isolation structure 106 when viewed from, for example, the top view of FIG. 3B. Direct contact.

In addition, the isolation structure 106 has a first depth D1, and the second conductivity type first doping region 114 has a second depth D2. The source region 110 and the drain region have a third depth D3. In some embodiments, the first depth D1 is greater than the second depth D2, and the second depth D2 is greater than the third depth D3 (D1>D2>D3).

Next, Fig. 4B is a top view of the substrate 100 of the disclosed embodiment, and Fig. 4A is a cross-sectional view of the disclosed embodiment taken along line 4A-4A' of Fig. 4B. Referring to FIG. 4A, a second conductivity type second doping region 116 is formed in the well region 104, and a second conductivity type second doping region 116 is disposed in the source region 110, the drain region 112, and the second conductivity type. Below the first doped region 114. In addition, the second conductive type second doping region 116 directly contacts the bottom of the second conductive type first doping region 114.

As shown in FIG. 4A, the second conductivity type first doping region 114 and the second conductivity type second doping region 116 collectively isolate the isolated sub-well region 118 from the well region 104. The source region 110 and the drain region 112 are This is isolated in the secondary well region 118, and the isolated secondary well region 118 includes a channel region 120 between the source region 110 and the drain region 112.

Furthermore, as shown in FIG. 4B, the isolated sub-well region 118 encloses the source region 110 and the drain region 112, and the second conductivity type first doping region 114 surrounds the isolation sub-well region 118. The second conductivity type first doping region 114 includes at least one gate region 122 adjacent to the channel region 120. For example, in some embodiments, as shown in FIG. 4B, the second conductivity type first doping region 114 includes two gate regions 122, wherein one of the gate regions 122 is disposed on the opposite side of the channel region 120, and The two gate regions 122 are adjacent to the channel region 120.

In some embodiments of the present disclosure, the production cost of the semiconductor device can be reduced due to the mask layer in the step of forming the channel region 120.

Furthermore, this channel region 120 has a width W1. In addition, lowering the gate voltage increases the depletion region in the PN junction. If this gate voltage is low enough, all channels will be depleted and no current will flow from the drain to the source. The width of the channel that is completely depleted can be referred to as pinched off. The gate voltage at which this effect occurs is called a pinch-off voltage.

By adjusting the width W1 of the channel region 120, the pinch-off voltage of the semiconductor device can be adjusted. In addition, the semiconductor device of the embodiment of the present disclosure can reduce the clip of the semiconductor device by the special configuration of the source region 110, the drain region 112, the gate region 122, and the channel region 120 as shown in FIG. 4B (top view). Pinch-off voltage. In some embodiments, the pinch-off voltage of the semiconductor device can be as low as -0.2V.

Continuing to refer to FIG. 4A, the second conductivity type second doping region 116 may have a second conductivity type. In some embodiments, the second conductivity type second doping region 116 may have a doping concentration of about 10 ¹⁴ /cm ³ to about 10 ¹⁶ /cm ³ , for example, about 10 ¹⁵ /cm ³ .

The second conductivity type second doping region 116 can be formed by an ion implantation step. For example, when the second conductivity type is a P-type, boron ions, indium ions or boron trifluoride ions may be implanted in a region where the second conductivity type second doping region 116 is to be formed to form a second conductivity type second. Doped region 116.

In addition, the source region 110 and the drain region 112 are not in direct contact with the second conductivity type second doping region 116, as shown in FIG. 4A.

It should be noted that, in addition to the embodiments shown in the above 4A-4B, the source region and the drain region of the present disclosure may also directly contact the second conductivity type second doping region. The scope of the disclosure is not limited to the embodiment shown in Figures 4A-4B. This section will be explained in detail later.

Additionally, the width of the channel region 120 is less than the width of the source region 110 and the width of the drain region 112. In detail, the width W1 of the channel region 120 is smaller than the width W2 of the source region 110 and the width W3 of the drain region 112.

5A is a top view of the semiconductor device 200 of the embodiment of the present disclosure, and FIG. 5B is a cross-sectional view of the disclosed embodiment taken along line 5B-5B' of FIG. 5A, and FIG. 5C is a diagram A cross-sectional view of the embodiment taken along line 5C-5C' of Figure 5A is disclosed.

Referring to FIGS. 5A-5C, a metal deuteration process may be selectively performed to form on the gate region 122 in the source region 110, the drain region 112, and the second conductivity type first doping region 114, respectively. Metal telluride layers 124, 126 and 128. The metal telluride layers 124, 126, and 128 can further reduce the on-resistance of the device. The materials of the metal telluride layers 124, 126 and 128 may include, but are not limited to, nickel silicide, cobalt silicide, tungsten telluride. (tungsten silicide), titanium silicide, tantalum silicide, platinum silicide, and erbium silicide. In addition, although the metal telluride layers 124, 126, and 128 are shown in FIG. 5B-5C, the metal halide layers 124, 126, and 128 are not shown in FIG. 5A for clarity of description of the disclosed embodiments.

Next, a source electrode 130 is formed on the metal telluride layer 124. The source electrode 130 is electrically connected to the source region 110. In addition, a drain electrode 132 is formed on the metal telluride layer 126, and the drain electrode 132 is electrically connected to the drain region 112. In addition, a gate electrode 134 is formed on the metal telluride layer 128, and the gate electrode 134 is electrically connected to the second conductivity type first doping region 114. In other words, the gate electrode 134 is disposed above the gate region 122. In addition, although the source electrode 130 and the drain electrode 132 are not disposed on the line segments 5B-5B', the source electrode 130 and the drain electrode 132 are still depicted in FIG. 5B to clearly describe the disclosed embodiment.

The material of the source electrode 130, the drain electrode 132 and the gate electrode 134 may include copper, aluminum, molybdenum, tungsten, titanium, tantalum, platinum, rhodium, the above alloy, the above combination or other conductive metal materials. .

The material of the source electrode 130, the drain electrode 132 and the gate electrode 134 may be by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other A suitable deposition pattern is formed. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), or rapid temperature chemical vapor deposition (rapid). Thermal chemical vapor deposition (RTCVD), plasma-assisted chemical vapor deposition (plasma enhanced chemical) Vapor deposition (PECVD), atomic layer deposition (ALD) or other commonly used methods.

Continuing to refer to FIGS. 5A-5C, the semiconductor device 200 includes a substrate 100 and a well region 104 disposed in the substrate 100. This well region 104 has a first conductivity type. The semiconductor device 200 further includes an isolation structure 106 disposed in the substrate 100, and the isolation structure 106 surrounds the active region 108 in the well region 104. The semiconductor device 200 further includes a source region 110 disposed in the active region 108 and in the well region 104, and a drain region 112 disposed in the active region 108 and in the well region 104. The semiconductor device 200 further includes a second conductive type first doped region 114 disposed in the well region 104, and the second conductive type first doped region 114 is disposed along an edge of the active region 108, wherein the first conductive type Different from the second conductivity type. The semiconductor device 200 further includes a second conductivity type second doping region 116 disposed in the well region 104 and disposed under the source region 110, the drain region 112, and the second conductivity type first doping region 114. The second conductive type second doping region 116 is in direct contact with the second conductive type first doping region 114. The semiconductor device 200 further includes a source electrode 130 electrically connected to the source region 110. The semiconductor device 200 further includes a drain electrode 132 electrically connected to the drain region 112. The semiconductor device 200 further includes a gate electrode 134 electrically connected to the first conductive type first doping region 114.

The second conductive type first doped region 114 and the second conductive type second doped region 116 are isolated from the well region 104 to isolate the isolated sub-well region 118, and the source region 110 and the drain region The pole region 112 is disposed in the isolated sub-well region 118.

As shown in FIG. 5A, the isolated sub-well region 118 surrounds the source region 110 and the drain region 112, and the second conductivity type first doping region 114 surrounds the isolation sub-well region. 118. The isolated sub-well region 118 includes a channel region 120 between the source region 110 and the drain region 112, and the width of the channel region 120 is less than the width of the source region 110 and the width of the drain region 112.

In addition, the second conductivity type first doping region 114 includes at least one gate region 122 that is adjacent to the channel region 120. The gate electrode 134 is disposed above the gate region 122.

Figure 6 is a graph showing the analysis of the gate voltage (horizontal axis) versus the drain current (vertical axis) of a semiconductor device according to some embodiments of the present disclosure. As shown in FIG. 6, the semiconductor device of the embodiment of the present disclosure can reduce the clip of the semiconductor device by the special configuration of the source region, the drain region, the gate region and the channel as shown in FIG. 5A (top view). The pinch-off voltage is -0.2V.

The semiconductor device 200 can be a junction field effect transistor (JFET) and can be applied to a switch, a current source, and an electrostatic discharge protection.

Figure 7 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. The difference between the embodiment shown in FIG. 7 and the embodiment of FIG. 5B is that the source region 110 and the drain region 112 directly contact the second conductivity type second doping region 116, as shown in FIG.

It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.

In addition, it should be noted that although in the above embodiments, the first conductivity type is N type and the second conductivity type is P type description, however, those skilled in the art can understand the first conductivity. Type can also be P type, but at this time The second conductivity type is N type.

In addition, it should be noted that those skilled in the art are well aware that the drains and sources described herein are interchangeable because their definition is related to the voltage level to which they are connected.

It should be noted that the component sizes, component parameters, and component shapes described above are not limitations of the disclosure. Those of ordinary skill in the art can adjust these settings according to different needs. Further, the semiconductor device and the method of manufacturing the same according to the present disclosure are not limited to the state illustrated in FIGS. 1-7. The disclosure may include only any one or more of the features of any one or more of the embodiments of Figures 1-7. In other words, not all illustrated features must be simultaneously implemented in the semiconductor device and method of fabricating the same.

In addition, although the doping concentrations of the various doped regions in some embodiments are set forth above. However, it will be understood by those of ordinary skill in the art that the doping concentration of each doped region can be determined according to a particular device type, technology generation, minimum component size, and the like. Thus, the doping concentration of each doped region can be re-evaluated in accordance with the technical content without being limited to the embodiments presented herein.

Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure Understand current or future developments of processes, machines, manufacturing, material compositions, devices, methods, and steps, as long as they can be implemented in the embodiments described herein The same result can be used according to the disclosure. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

100‧‧‧Substrate

106‧‧‧Isolation structure

108‧‧‧active area

110‧‧‧ source area

112‧‧‧Bungee Area

114‧‧‧Second Conductive Type First Doped Area

118‧‧‧Isolated sub-well area

120‧‧‧Channel area

122‧‧‧The gate area

130‧‧‧Source electrode

132‧‧‧汲electrode

134‧‧‧gate electrode

200‧‧‧Semiconductor device

W1‧‧‧Width

5B-5B’‧‧‧ Segment

5C-5C’‧‧‧ Segment

Claims (20)

A semiconductor device comprising: a substrate; a well region disposed in the substrate and having a first conductivity type; an isolation structure disposed in the substrate and surrounding an active region in the well region; a polar region disposed in the active region and in the well region; a drain region disposed in the active region and in the well region; a second conductive type first doped region disposed in the well region And disposed along an edge of the active region, wherein the first conductive type is different from the second conductive type; a second conductive type second doped region is disposed in the well region and disposed in the source region And the second conductive type first doped region is in direct contact with the second conductive type first doped region; a source electrode, electricity The source region is connected to the source region; a drain electrode is electrically connected to the drain region; and a gate electrode is electrically connected to the first doped region of the second conductivity type. The semiconductor device of claim 1, wherein the source region and the drain region are not in direct contact with the second conductivity type second doped region. The semiconductor device of claim 1, wherein the source region and the drain region directly contact the second conductive type second doped region. The semiconductor device of claim 1, wherein the second conductive type first doped region directly contacts the isolation structure. The semiconductor device of claim 1, wherein the second conductive type first doped region and the second conductive type second doped region together isolate an isolation sub-well region (isolated sub) -well region), where the source The polar zone and the bungee zone are located in the isolated sub-well zone. The semiconductor device of claim 5, wherein the isolated sub-well region surrounds the source region and the drain region, and the second conductivity type first doped region surrounds the isolated sub-well region. The semiconductor device of claim 5, wherein the isolated sub-well region comprises a channel region between the source region and the drain region, and the width of the channel region is less than a width of the source region With the width of the bungee zone. The semiconductor device of claim 7, wherein the second conductive type first doped region comprises at least one gate region, the gate region adjoining the channel region. The semiconductor device of claim 8, wherein the second conductive type first doped region comprises two gate regions, wherein one of the gate regions is disposed on an opposite side of the channel region, and the two The gate region is adjacent to the channel region. The semiconductor device of claim 8, wherein the gate electrode is disposed over the gate region. A method of manufacturing a memory device, comprising: providing a substrate; forming a well region in the substrate, wherein the well region has a first conductivity type; forming an isolation structure in the substrate, wherein the isolation structure surrounds the An active region in the well region; forming a source region in the active region and the well region; forming a drain region in the active region and the well region; forming a second conductivity type first doping In the well region, wherein the second conductive type first doped region is disposed along an edge of the active region, wherein the first conductive type is different from the second conductive type; Forming a second conductivity type second doping region in the well region, and the second conductivity type second doping region is disposed in the source region, the drain region, and the second conductivity type first doping a second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode is formed, the source electrode is electrically connected to the source region; The gate electrode is electrically connected to the drain region; and a gate electrode is electrically connected to the second conductive type first doped region. The method of fabricating a semiconductor device according to claim 11, wherein the source region and the drain region are not in direct contact with the second conductive type second doped region. The method of fabricating a semiconductor device according to claim 11, wherein the source region and the drain region directly contact the second conductive type second doped region. The method of fabricating a semiconductor device according to claim 11, wherein the second conductive type first doped region directly contacts the isolation structure. The method of manufacturing a semiconductor device according to claim 11, wherein the second conductive type first doped region and the second conductive type second doped region together isolate an isolation sub-well region in the well region. (isolated sub-well region), wherein the source region and the drain region are disposed in the isolated sub-well region. The method of fabricating a semiconductor device according to claim 15, wherein the isolated sub-well region surrounds the source region and the drain region, and the second conductive type first doped region surrounds the isolated sub-well region . The method of fabricating a semiconductor device according to claim 15, wherein the isolated sub-well region includes a pass between the source region and the drain region. a track zone, and the width of the channel zone is less than the width of the source zone and the width of the drain zone. The method of fabricating a semiconductor device according to claim 17, wherein the second conductive type first doped region comprises at least one gate region, the gate region adjoining the channel region. The method of fabricating a semiconductor device according to claim 18, wherein the second conductive type first doped region comprises two gate regions, wherein one of the gate regions is disposed on an opposite side of the channel region, and The two gate regions are adjacent to the channel region. The method of fabricating a semiconductor device according to claim 18, wherein the gate electrode is disposed on the gate region.