TW201714007A - Pixel array and repair method of pixel unit - Google Patents
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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Abstract
Description
本發明是有關於一種畫素陣列及畫素單元的修補方法，且特別是有關於一種利於進行暗點化的畫素陣列及畫素單元的修補方法。The invention relates to a method for repairing a pixel array and a pixel unit, and in particular to a method for repairing a pixel array and a pixel unit which are advantageous for dark spotting.
近年來，雖然平面顯示器技術已趨成熟，但顯示面板的組成元件，如主動元件陣列基板，在製造過程之中難免會產生一些點瑕疵（dot defect）。一般來說，若能通過修補方式將上述的點瑕疵修補成暗點，就可以不需要報廢丟棄這些有瑕疵的顯示面板。In recent years, although the flat panel display technology has matured, the components of the display panel, such as the active device array substrate, inevitably generate some dot defects during the manufacturing process. In general, if the above points can be repaired into dark spots by patching, it is not necessary to discard these defective display panels.
現行的畫素單元的修補方式通常是採用雷射熔接（laser welding)及雷射切割（laser cutting)的搭配來進行，以將畫素電極連接至共用電位，進而達到暗點化效果。然而，由於顯示面板的結構趨於複雜，因此畫素電極在修補後仍有可能未確實地連接至共用電位，而使得暗點化失敗。The current repair method of the pixel unit is usually carried out by using a combination of laser welding and laser cutting to connect the pixel electrodes to a common potential to achieve a dark spotting effect. However, since the structure of the display panel tends to be complicated, it is still possible that the pixel electrodes are not surely connected to the common potential after repair, and the dark spots fail.
本發明提供一種畫素陣列，其結構有利於對瑕疵畫素進行暗點化。The invention provides a pixel array, the structure of which is convenient for darkening the sputum pixels.
本發明提供另一種畫素陣列，其具有經暗點化的瑕疵畫素。The present invention provides another pixel array having dark-spotted sputum pixels.
本發明另提供一種畫素單元的修補方法，其可達到將瑕疵畫素確實暗點化之目的。The invention further provides a repairing method for a pixel unit, which can achieve the purpose of realizing dark spots of 瑕疵 素 。.
本發明的畫素陣列包括多個畫素單元，其中每一個畫素單元包括第一子畫素以及第二子畫素。第一子畫素包括第一主動元件以及與第一主動元件的汲極電性連接的第一畫素電極。第二子畫素包括第二主動元件以及與第二主動元件的汲極電性連接的第二畫素電極，其中第一畫素電極與第二主動元件的汲極具有交疊處且形成第一電容。The pixel array of the present invention includes a plurality of pixel units, wherein each pixel unit includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first active element and a first pixel electrode electrically connected to the drain of the first active element. The second sub-pixel includes a second active element and a second pixel electrode electrically connected to the drain of the second active element, wherein the first pixel electrode and the drain of the second active element have an overlap and form a A capacitor.
本發明的畫素陣列包括多個畫素單元，其中每一個畫素單元包括第一子畫素、第二子畫素、第一電極以及第二電極。第一子畫素包括第一主動元件以及與第一主動元件的汲極電性連接的第一畫素電極。第二子畫素包括第二主動元件以及與第二主動元件的汲極電性連接的第二畫素電極，其中第一畫素電極與第二主動元件的汲極的交疊處具有第一熔接點。第一畫素電極與第二畫素電極經由第一熔接點與共同電位電性連接。The pixel array of the present invention includes a plurality of pixel units, wherein each pixel unit includes a first sub-pixel, a second sub-pixel, a first electrode, and a second electrode. The first sub-pixel includes a first active element and a first pixel electrode electrically connected to the drain of the first active element. The second sub-pixel includes a second active element and a second pixel electrode electrically connected to the drain of the second active element, wherein the first pixel electrode has a first overlap with the drain of the second active element Welding point. The first pixel electrode and the second pixel electrode are electrically connected to the common potential via the first fusion point.
本發明的畫素單元的修補方法包括以下步驟。提供畫素單元，其包括第一子畫素、第二子畫素、第一電極以及第二電極。第一子畫素包括第一主動元件以及與第一主動元件的汲極電性連接的第一畫素電極。第二子畫素包括第二主動元件以及與第二主動元件的汲極電性連接的第二畫素電極，其中第一畫素電極與第二主動元件的汲極具有第一交疊處。進行雷射切割製程，切割提供訊號至第一主動元件與第二主動元件的訊號線。進行雷射熔接製程，以於第一交疊處形成第一熔接點，其中第一畫素電極與第二畫素電極經由第一熔接點與共同電位電性連接。The repair method of the pixel unit of the present invention includes the following steps. A pixel unit is provided that includes a first sub-pixel, a second sub-pixel, a first electrode, and a second electrode. The first sub-pixel includes a first active element and a first pixel electrode electrically connected to the drain of the first active element. The second sub-pixel includes a second active element and a second pixel electrode electrically connected to the drain of the second active element, wherein the first pixel electrode and the drain of the second active element have a first overlap. A laser cutting process is performed to cut the signal lines that provide signals to the first active component and the second active component. And performing a laser welding process to form a first fusion splice point at the first overlap, wherein the first pixel electrode and the second pixel electrode are electrically connected to the common potential via the first fusion splice point.
基於上述，在本發明之畫素陣列的第一與第二子畫素中，第一畫素電極與第二主動元件的汲極具有交疊處且形成電容。當畫素單元中的第一或第二子畫素發生瑕疵時，第二子畫素可以經由第一子畫素與熔接點而電性連接至共同電位，即可達到將畫素單元暗點化的目的。因此，本發明之畫素陣列的設計有利於對畫素單元進行修補，使得採用此畫素陣列的顯示面板具有良好的顯示品質。Based on the above, in the first and second sub-pixels of the pixel array of the present invention, the first pixel electrode and the drain of the second active element have overlaps and form a capacitance. When the first or second sub-pixel in the pixel unit occurs, the second sub-pixel can be electrically connected to the common potential via the first sub-pixel and the fusion point, thereby achieving the dark point of the pixel unit. Purpose. Therefore, the design of the pixel array of the present invention facilitates repair of the pixel unit, so that the display panel using the pixel array has good display quality.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A為本發明一實施例之畫素陣列的示意圖，圖1B為圖1A畫素單元的局部放大示意圖，圖1C為圖1B之畫素單元的等效電路示意圖。為了說明方便，在圖1A中是以繪示畫素陣列包括2x2個畫素單元為例，但本發明不以此為限。1A is a schematic diagram of a pixel array according to an embodiment of the present invention, FIG. 1B is a partially enlarged schematic view of the pixel unit of FIG. 1A, and FIG. 1C is an equivalent circuit diagram of the pixel unit of FIG. 1B. For convenience of description, in FIG. 1A, the illustrated pixel array includes 2×2 pixel units, but the invention is not limited thereto.
請同時參照圖1A至圖1C，畫素陣列10包括多個畫素單元100。每一個畫素單元100包括第一子畫素P1、第二子畫素P2、掃描線GL以及資料線DL。第一子畫素P1包括第一主動元件T1以及第一畫素電極PE1。第一主動元件T1例如是包括閘極G1、通道層CH1、源極S1以及汲極D1。閘極G1與掃描線GL電性連接，源極S1與資料線DL電性連接。通道層CH1例如是配置於閘極G1上方且位於源極S1與汲極D1之間。第一畫素電極PE1與汲極D1電性連接。第二子畫素P2包括第二主動元件T2以及第二畫素電極PE2。第二主動元件T2例如是包括閘極G2、通道層CH2、源極S2以及汲極D2。閘極G2與掃描線GL電性連接，源極S2與資料線DL電性連接。通道層CH2例如是配置於閘極G2上方且位於源極S2與汲極D2之間。第二畫素電極PE2與汲極D2電性連接。Referring to FIG. 1A to FIG. 1C simultaneously, the pixel array 10 includes a plurality of pixel units 100. Each pixel unit 100 includes a first sub-pixel P1, a second sub-pixel P2, a scan line GL, and a data line DL. The first sub-pixel P1 includes a first active element T1 and a first pixel electrode PE1. The first active device T1 includes, for example, a gate G1, a channel layer CH1, a source S1, and a drain D1. The gate G1 is electrically connected to the scan line GL, and the source S1 is electrically connected to the data line DL. The channel layer CH1 is disposed, for example, above the gate G1 and between the source S1 and the drain D1. The first pixel electrode PE1 is electrically connected to the drain D1. The second sub-pixel P2 includes a second active element T2 and a second pixel electrode PE2. The second active device T2 includes, for example, a gate G2, a channel layer CH2, a source S2, and a drain D2. The gate G2 is electrically connected to the scan line GL, and the source S2 is electrically connected to the data line DL. The channel layer CH2 is disposed, for example, above the gate G2 and between the source S2 and the drain D2. The second pixel electrode PE2 is electrically connected to the drain D2.
第一畫素電極PE1與第二主動元件T2的汲極D2具有第一交疊處且形成第一電容C1。在本實施例中，汲極D2包括用以電性連接至資料線DL的部分以及經由通孔與第二畫素電極PE2電性連接的部分。此外，汲極D2更包括位於第一畫素電極PE1下方以形成第一交疊處的部分。在本實施例中，與第二主動元件T2的汲極D2交疊的第一畫素電極PE1例如是位於電性連接至汲極D1的通孔附近。也就是說，第一畫素電極PE1例如是由汲極D1上方進一步延伸至第二主動元件T2的汲極D2上方。The first pixel electrode PE1 and the drain D2 of the second active device T2 have a first overlap and form a first capacitance C1. In the present embodiment, the drain D2 includes a portion for electrically connecting to the data line DL and a portion electrically connected to the second pixel electrode PE2 via the via hole. Further, the drain D2 further includes a portion located under the first pixel electrode PE1 to form a first overlap. In the present embodiment, the first pixel electrode PE1 overlapping the drain D2 of the second active device T2 is, for example, located near the through hole electrically connected to the drain D1. That is, the first pixel electrode PE1 extends, for example, from above the drain D1 to above the drain D2 of the second active device T2.
在本實施例中，畫素單元100例如是更包括第一電極E1、第二電極E2以及第三電極E3。在本實施例中，第一電極E1、第二電極E2以及第三電極E3例如是構成分享電容器。第一電極E1例如是與第一畫素電極PE1電性連接。第二電極E2例如是與第一電極E1具有第二交疊處且形成第二電容C2。第三電極E3例如是電性連接至共同電位VCS 且與第二電極E2具有第三交疊處且形成第三電容C3。在本實施例中，第三電極E3例如是經由通孔與共同線CL電性連接，但本發明不限於此，在其他實施例中，第三電極E3也可以實質上屬於共同線CL的一部分。在本實施例中，第一電極E1與第一畫素電極PE1例如是一體成形。在本實施例中，例如是更包括電容電極110，用以與共同線CL形成電容。在圖1C中，CLC1 、CLC2 表示液晶電容，CST1 、CST2 表示儲存電容，VCOM 表示彩色濾光基板側的共同電極(未繪示)的共同電位，VCS 表示畫素陣列側的共同線CL的共同電位，此為本領域所周知，於此不贅述。在本實施例中，第一畫素電極PE1與第二畫素電極PE2分別與彩色濾光基板側的共同電極(電位為VCOM )之間形成液晶電容CLC1 和CLC2 ，但不以此為限。In the embodiment, the pixel unit 100 further includes, for example, a first electrode E1, a second electrode E2, and a third electrode E3. In the present embodiment, the first electrode E1, the second electrode E2, and the third electrode E3 constitute, for example, a sharing capacitor. The first electrode E1 is electrically connected to the first pixel electrode PE1, for example. The second electrode E2 has, for example, a second overlap with the first electrode E1 and forms a second capacitance C2. The third electrode E3 is electrically connected, for example, to the common potential V CS and has a third overlap with the second electrode E2 and forms a third capacitance C3. In the present embodiment, the third electrode E3 is electrically connected to the common line CL via a through hole, for example, but the invention is not limited thereto. In other embodiments, the third electrode E3 may also substantially belong to a part of the common line CL. . In the present embodiment, the first electrode E1 and the first pixel electrode PE1 are integrally formed, for example. In this embodiment, for example, the capacitor electrode 110 is further included to form a capacitance with the common line CL. In Fig. 1C, C LC1 and C LC2 denote liquid crystal capacitors, C ST1 and C ST2 denote storage capacitors, V COM denotes a common potential of a common electrode (not shown) on the side of the color filter substrate, and V CS denotes a pixel array side. The common potential of the common line CL is well known in the art and will not be described here. In this embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 form a liquid crystal capacitors C LC1 and C LC2 respectively with the common electrode on the color filter substrate side (the potential is V COM ), but Limited.
在本實施例中，畫素單元100例如是更包括與掃描線GL平行設置的訊號線SL以及分享開關元件Tsh，其中分享開關元件Tsh例如是包括閘極Gsh、通道層CHsh、源極Ssh以及汲極Dsh。分享開關元件Tsh的閘極Gsh例如是與訊號線SL電性連接。通道層CHsh例如是配置於閘極Gsh上方且位於源極Ssh與汲極Dsh之間。在本實施例中，分享開關元件Tsh的源極Ssh例如是與第二主動元件T2的汲極D2電性連接。分享開關元件Tsh的汲極Dsh例如是與第二電極E2電性連接。在本實施例中，分享開關元件Tsh的源極Ssh與第二主動元件T2的汲極D2例如是一體成形。分享開關元件Tsh的汲極Dsh與第二電極E2例如是一體成形。In this embodiment, the pixel unit 100 further includes, for example, a signal line SL disposed in parallel with the scanning line GL and a sharing switching element Tsh, wherein the sharing switching element Tsh includes, for example, a gate Gsh, a channel layer CHsh, a source Ssh, and Bungee Dsh. The gate Gsh of the sharing switching element Tsh is electrically connected, for example, to the signal line SL. The channel layer CHsh is disposed, for example, above the gate Gsh and between the source Ssh and the drain Dsh. In this embodiment, the source Ssh of the sharing switching element Tsh is electrically connected to the drain D2 of the second active device T2, for example. The drain Dsh of the sharing switching element Tsh is electrically connected, for example, to the second electrode E2. In the present embodiment, the source Ssh of the sharing switching element Tsh and the drain D2 of the second active element T2 are integrally formed, for example. The drain Dsh of the sharing switching element Tsh and the second electrode E2 are integrally formed, for example.
如圖1C所示，在本實施例中，第一畫素電極PE1與第二主動元件T2的汲極D2形成第一電容C1，第二電極E2與第一電極E1(與第一畫素電極PE1電性連接)形成第二電容C2，電性連接至共同電位VCS 的第三電極E3與第二電極E2形成第三電容C3。因此，當第二子畫素P2發生瑕疵時，可藉由電性連接第一畫素電極PE1、第一電極E1、第二電極E2以及第三電極E3，使得第二主動元件T2的汲極D2電性連接至共同電位VCS ，以達到確實使第二子畫素P2暗點化的目的。As shown in FIG. 1C, in the embodiment, the first pixel electrode PE1 and the drain D2 of the second active device T2 form a first capacitor C1, and the second electrode E2 and the first electrode E1 (with the first pixel electrode) The PE1 is electrically connected to form a second capacitor C2, and the third electrode E3 electrically connected to the common potential V CS and the second electrode E2 form a third capacitor C3. Therefore, when the second sub-pixel P2 is chopped, the first active element T2 can be electrically connected to the first pixel E1, the first electrode E1, the second electrode E2, and the third electrode E3. D2 is electrically connected to the common potential V CS for the purpose of actually darkening the second sub-pixel P2.
應用前述的畫素陣列，針對畫素單元進行修補舉例說明如下。圖2A為對圖1B之畫素單元進行修補後的示意圖，以及圖2B為圖2A之經修補的畫素單元的等效電路示意圖。The patching of the pixel unit using the aforementioned pixel array is exemplified as follows. 2A is a schematic view showing the repair of the pixel unit of FIG. 1B, and FIG. 2B is an equivalent circuit diagram of the repaired pixel unit of FIG. 2A.
請同時參照圖2A與圖2B，當畫素單元100中的第一子畫素P1或第二子畫素P2發生瑕疵時，藉由使第二子畫素P2、第一子畫素P1及第一至第三電極E1、E2、E3彼此電性連接，可形成一連接至共同電位VCS 的路徑Pw（如粗線箭頭所示），以使得第一子畫素P1與第二子畫素P2被暗點化，詳細說明如下。首先，進行雷射切割製程，切割提供訊號至第一主動元件T1與第二主動元T2的資料線DL。也就是說，資料線DL具有一切割處CS，使得第一主動元件T1與第二主動元件T2與掃描線GL電性連接但與資料線DL經由切割處CS電性分離。接著，對第二子畫素P2的汲極D2與第一畫素電極PE1的第一交疊處進行熔接可形成第一熔接點W1，以使第二子畫素P2的汲極D2與第一子畫素P1的第一畫素電極PE1電性連接。然後，對第一電極E1與第二電極E2的第二交疊處進行熔接可形成第二熔接點W2，以經由第一電極E1使第一畫素電極PE1與第二電極E2電性連接。而後，對第二電極E2與第三電極E3的第三交疊處進行熔接可形成第三熔接點W3，以經由第二電極E2使第一電極E1電性連接至共同電位VCS 。如此一來，第二子畫素P2經由路徑Pw電性連接至共同電位VCS ，以被暗點化。Referring to FIG. 2A and FIG. 2B simultaneously, when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit 100 occurs, the second sub-pixel P2 and the first sub-pixel P1 are The first to third electrodes E1, E2, and E3 are electrically connected to each other to form a path Pw (shown by a thick line arrow) connected to the common potential V CS such that the first sub-pixel P1 and the second sub-picture The prime P2 is darkened and described in detail below. First, a laser cutting process is performed to cut the data lines DL that provide signals to the first active device T1 and the second active device T2. That is, the data line DL has a cut portion CS such that the first active device T1 and the second active device T2 are electrically connected to the scan line GL but are electrically separated from the data line DL via the cut portion CS. Then, the first overlap of the first sub-pixel P2 and the first overlap of the first pixel electrode PE1 can be formed to form the first fusion point W1, so that the second sub-pixel P2 is D2 and The first pixel electrode PE1 of a sub-pixel P1 is electrically connected. Then, the second fusion point W2 is formed by welding the second overlap of the first electrode E1 and the second electrode E2 to electrically connect the first pixel electrode PE1 and the second electrode E2 via the first electrode E1. Then, the third fusion point W3 is formed by welding the third overlap of the second electrode E2 and the third electrode E3 to electrically connect the first electrode E1 to the common potential V CS via the second electrode E2. In this way, the second sub-pixel P2 is electrically connected to the common potential V CS via the path Pw to be darkened.
在本實施例中，第二子畫素P2也有可能經由汲極D2、分享開關元件Tsh的源極Ssh、第二電極E2、第三熔接點W3以及第三電極E3的路徑而電性連接至共同電位VCS ，進而被暗點化。然而，由於此路徑需經過分享開關元件Tsh，而分享開關元件Tsh的閘極Gsh關閉會使第二子畫素P2的電容浮接，電位易受耦合影響，進而容易導致暗點化失敗。因此，本實施例藉由第一子畫素P1的第一畫素電極PE1與第二子畫素P2的汲極D2延伸而彼此重疊的設計，使第二子畫素P2能經由汲極D2、第一熔接點W1、第一子畫素P1的第一畫素電極PE1、第一電極E1、第二熔接點W2、第二電極E2、第三熔接點W3以及第三電極E3的路徑Pw電性連接至共同電位VCS 。由於此路徑Pw不須經過分享開關元件Tsh，因此能使第二子畫素P2被確實暗點化。如此一來，達到修補畫素單元100進行的目的。In this embodiment, the second sub-pixel P2 is also electrically connected to the source Ssh of the sharing switching element Tsh, the second electrode E2, the third fusion node W3, and the third electrode E3 via the drain D2. The common potential V CS is further darkened. However, since the path needs to pass through the sharing switching element Tsh, and the gate Gsh of the sharing switching element Tsh is turned off, the capacitance of the second sub-pixel P2 is floated, and the potential is susceptible to the coupling, which may easily lead to dark point failure. Therefore, in this embodiment, the second sub-pixel P2 can pass through the bungee D2 by the design that the first pixel electrode PE1 of the first sub-pixel P1 and the second D-pixel of the second sub-pixel P2 overlap each other. The first fusion node W1, the first pixel electrode PE1 of the first sub-pixel P1, the first electrode E1, the second fusion node W2, the second electrode E2, the third fusion node W3, and the path Pw of the third electrode E3 Electrically connected to a common potential V CS . Since the path Pw does not have to pass through the sharing switching element Tsh, the second sub-pixel P2 can be surely darkened. In this way, the purpose of repairing the pixel unit 100 is achieved.
圖3A為本發明一實施例之畫素陣列的示意圖，圖3B為圖3A畫素單元的局部放大示意圖，圖3C為圖3B之畫素單元的等效電路示意圖。圖3A的畫素陣列與圖1A相似，以下就不同處進行說明。在本實施例中，汲極D2與第一畫素電極PE1具有第一交疊處且形成第一電容C1。第一電極E1例如是第一畫素電極PE1的一部分，以及第二電極E2例如是共同線CL的一部分。第二電極E2與第一電極E1具有第二交疊處且形成第二電容C2。第三電極E3例如是電性連接至共同電位VCS 且與另一電極E4具有第三交疊處且形成第二電容C3。3A is a schematic diagram of a pixel array according to an embodiment of the present invention, FIG. 3B is a partially enlarged schematic view of the pixel unit of FIG. 3A, and FIG. 3C is an equivalent circuit diagram of the pixel unit of FIG. The pixel array of Fig. 3A is similar to Fig. 1A, and the differences will be described below. In the present embodiment, the drain D2 and the first pixel electrode PE1 have a first overlap and form a first capacitor C1. The first electrode E1 is, for example, a part of the first pixel electrode PE1, and the second electrode E2 is, for example, a part of the common line CL. The second electrode E2 has a second overlap with the first electrode E1 and forms a second capacitor C2. The third electrode E3 is, for example, electrically connected to the common potential V CS and has a third overlap with the other electrode E4 and forms a second capacitance C3.
圖4A為對圖3B之畫素單元進行修補後的示意圖，以及圖4B為圖4A之經修補的畫素單元的等效電路示意圖。4A is a schematic diagram of repairing the pixel unit of FIG. 3B, and FIG. 4B is an equivalent circuit diagram of the repaired pixel unit of FIG. 4A.
請參照圖4A與圖4B，當畫素單元100a中的第一子畫素P1或第二子畫素P2發生瑕疵時，藉由使第二子畫素P2、第一子畫素P1及第一電極E1與第二電極E2彼此電性連接，可形成一連接至共同電位VCS 的路徑Pw（如粗線箭頭所示），以使得第一子畫素P1與第二子畫素P2被暗點化，詳細說明如下。首先，進行雷射切割製程，切割提供訊號至第一主動元件T1與第二主動元T2的資料線DL。接著，對第二子畫素P2的汲極D2與第一畫素電極PE1的第一交疊處進行熔接可形成第一熔接點W1，以使第二子畫素P2的汲極D2與第一子畫素P1的第一畫素電極PE1電性連接。然後，對第一電極E1與第二電極E2的第二交疊處進行熔接可形成第二熔接點W2，以經由第一電極E1使第一畫素電極PE1電性連接至具有共同電位VCS 的第二電極E2。如此一來，第二子畫素P2經由路徑Pw電性連接至共同電位VCS ，以被確實暗點化。Referring to FIG. 4A and FIG. 4B, when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit 100a is 瑕疵, by the second sub-pixel P2, the first sub-pixel P1 and the first An electrode E1 and a second electrode E2 are electrically connected to each other to form a path Pw (shown by a thick line arrow) connected to the common potential V CS such that the first sub-pixel P1 and the second sub-pixel P2 are Dark spots, as detailed below. First, a laser cutting process is performed to cut the data lines DL that provide signals to the first active device T1 and the second active device T2. Then, the first overlap of the first sub-pixel P2 and the first overlap of the first pixel electrode PE1 can be formed to form the first fusion point W1, so that the second sub-pixel P2 is D2 and The first pixel electrode PE1 of a sub-pixel P1 is electrically connected. Then, the second overlapping portion W2 is welded to the second overlap of the first electrode E1 and the second electrode E2 to electrically connect the first pixel electrode PE1 to have a common potential V CS via the first electrode E1. The second electrode E2. In this way, the second sub-pixel P2 is electrically connected to the common potential V CS via the path Pw to be truly darkened.
在本實施例中，藉由第一子畫素P1的第一畫素電極PE1與第二子畫素P2的汲極D2延伸而彼此重疊的設計，使第二子畫素P2能經由汲極D2、第一熔接點W1、第一畫素電極PE1、第一電極E1、第二熔接點W2以及第二電極E2的路徑Pw電性連接至共同電位VCS ，以達到確實使第一子畫素P1與第二子畫素P2暗點化的目的，進而修補畫素單元100a。In this embodiment, the second sub-pixel P2 can pass through the bungee by the design that the first pixel electrode PE1 of the first sub-pixel P1 and the drain D2 of the second sub-pixel P2 overlap each other. D2, the first fusion contact point W1, the first pixel electrode PE1, the first electrode E1, the second fusion point W2, and the path Pw of the second electrode E2 are electrically connected to the common potential V CS to achieve the first sub-picture The pixel P1 and the second sub-pixel P2 are darkened, and the pixel unit 100a is repaired.
圖5A為本發明一實施例之畫素陣列的示意圖，圖5B為圖5A畫素單元的局部放大示意圖，圖5C為圖5B之畫素單元的等效電路示意圖。圖5A的畫素陣列與圖1A相似，不同處在於本實施例的畫素陣列不具有分享開關元件，以及本實施例的畫素陣列具有電阻調配元件(divider)以及於不同位置處形成儲存電容。因此，在圖5A的畫素陣列10b與圖1A的畫素陣列10中，使用相同或相似的標號來表示相同或相似的元件，且相關說明皆可參照前文。以下，將僅針對兩者之間的差異進行說明。5A is a schematic diagram of a pixel array according to an embodiment of the present invention, FIG. 5B is a partially enlarged schematic view of the pixel unit of FIG. 5A, and FIG. 5C is an equivalent circuit diagram of the pixel unit of FIG. 5B. The pixel array of FIG. 5A is similar to that of FIG. 1A except that the pixel array of the present embodiment does not have a sharing switching element, and the pixel array of the present embodiment has a resistance matching component and forms a storage capacitor at different positions. . Therefore, in the pixel array 10b of FIG. 5A and the pixel array 10 of FIG. 1A, the same or similar reference numerals are used to denote the same or similar elements, and the related description can be referred to the foregoing. Hereinafter, only the difference between the two will be described.
請同時參照圖5A至圖5C，在本實施例中，第一畫素電極PE1與第二主動元件T2的汲極D2具有第一交疊處且形成第一電容C1(標示於圖5C)。畫素單元100b例如是包括第一電極E1、第二電極E2以及電阻調配元件Rst。第一電極E1例如是與第一畫素電極PE1電性連接。在本實施例中，第一電極E1與第一畫素電極PE1例如是一體成形。第二電極E2例如是電性連接至共同電位VCS 且與第一電極E1具有第二交疊處且形成第二電容C2。在本實施例中，第二電極E2例如是與共同線CL一體成形。在本實施例中，第二畫素電極PE2例如是進一步延伸而與第二電極E2具交疊處且形成CST2 。電阻調配元件Rst例如是包括閘極Gst、通道層CHst、源極Sst以及汲極Dst，其中源極Sst與第一主動元件T1的汲極D1電性連接。汲極Dst例如是電性連接至共同電位VCS 。在本實施例中，源極Sst與第一主動元件T1的汲極D1例如是一體成形。在本實施例中，畫素單元100b例如是更包括電容電極110。Referring to FIG. 5A to FIG. 5C simultaneously, in the embodiment, the first pixel electrode PE1 and the drain D2 of the second active device T2 have a first overlap and form a first capacitor C1 (shown in FIG. 5C). The pixel unit 100b includes, for example, a first electrode E1, a second electrode E2, and a resistance matching element Rst. The first electrode E1 is electrically connected to the first pixel electrode PE1, for example. In the present embodiment, the first electrode E1 and the first pixel electrode PE1 are integrally formed, for example. The second electrode E2 is electrically connected to the common potential V CS and has a second overlap with the first electrode E1 and forms a second capacitance C2. In the present embodiment, the second electrode E2 is formed integrally with the common line CL, for example. In the present embodiment, the second pixel electrode PE2 is, for example, further extended to overlap the second electrode E2 and form C ST2 . The resistor matching component Rst includes, for example, a gate Gst, a channel layer CHst, a source Sst, and a drain Dst, wherein the source Sst is electrically connected to the drain D1 of the first active device T1. The drain Dst is, for example, electrically connected to a common potential V CS . In the present embodiment, the source Sst and the drain D1 of the first active element T1 are integrally formed, for example. In the present embodiment, the pixel unit 100b includes, for example, a capacitor electrode 110.
圖6A為對圖5B之畫素單元進行修補後的示意圖，以及圖6B為圖6A之經修補的畫素單元的等效電路示意圖。FIG. 6A is a schematic diagram of repairing the pixel unit of FIG. 5B, and FIG. 6B is an equivalent circuit diagram of the repaired pixel unit of FIG. 6A.
請參照圖6A與圖6B，當畫素單元100b中的第一子畫素P1或第二子畫素P2發生瑕疵時，藉由使第二子畫素P2、第一子畫素P1及第一電極E1與第二電極E2彼此電性連接，可形成一連接至共同電位VCS 的路徑Pw（如粗線箭頭所示），以使得第一子畫素P1與第二子畫素P2被暗點化，詳細說明如下。首先，進行雷射切割製程，切割提供訊號至第一主動元件T1與第二主動元T2的資料線DL。也就是說，資料線DL具有一切割處CS，使得第一主動元件T1與第二主動元件T2與掃描線GL電性連接但與資料線DL經由切割處CS電性分離。接著，對第二子畫素P2的汲極D2與第一畫素電極PE1的第一交疊處進行熔接可形成第一熔接點W1，以使第二子畫素P2的汲極D2與第一子畫素P1的第一畫素電極PE1電性連接。然後，對第一電極E1與第二電極E2的第二交疊處進行熔接可形成第二熔接點W2，以經由第二電極E2使第一電極E1電性連接至共同電位VCS 。如此一來，第二子畫素P2經由路徑Pw電性連接至共同電位VCS ，以被暗點化。Referring to FIG. 6A and FIG. 6B, when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit 100b is 瑕疵, by making the second sub-pixel P2, the first sub-pixel P1 and the first An electrode E1 and a second electrode E2 are electrically connected to each other to form a path Pw (shown by a thick line arrow) connected to the common potential V CS such that the first sub-pixel P1 and the second sub-pixel P2 are Dark spots, as detailed below. First, a laser cutting process is performed to cut the data lines DL that provide signals to the first active device T1 and the second active device T2. That is, the data line DL has a cut portion CS such that the first active device T1 and the second active device T2 are electrically connected to the scan line GL but are electrically separated from the data line DL via the cut portion CS. Then, the first overlap of the first sub-pixel P2 and the first overlap of the first pixel electrode PE1 can be formed to form the first fusion point W1, so that the second sub-pixel P2 is D2 and The first pixel electrode PE1 of a sub-pixel P1 is electrically connected. Then, welding the second overlap of the first electrode E1 and the second electrode E2 to form a second fusion splice point W2 to electrically connect the first electrode E1 to the common potential V CS via the second electrode E2. In this way, the second sub-pixel P2 is electrically connected to the common potential V CS via the path Pw to be darkened.
在本實施例中，藉由第一子畫素P1的第一畫素電極PE1與第二子畫素P2的汲極D2延伸而彼此重疊的設計，使第二子畫素P2能經由汲極D2、第一熔接點W1、第一畫素電極PE1、第一電極E1、第二熔接點W2以及第二電極E2的路徑Pw電性連接至共同電位VCS ，以達到確實使第一子畫素P1與第二子畫素P2暗點化的目的，進而修補畫素單元100b。In this embodiment, the second sub-pixel P2 can pass through the bungee by the design that the first pixel electrode PE1 of the first sub-pixel P1 and the drain D2 of the second sub-pixel P2 overlap each other. D2, the first fusion contact point W1, the first pixel electrode PE1, the first electrode E1, the second fusion point W2, and the path Pw of the second electrode E2 are electrically connected to the common potential V CS to achieve the first sub-picture The pixel P1 and the second sub-pixel P2 are darkened, and the pixel unit 100b is repaired.
圖7A為本發明一實施例之畫素陣列的示意圖，圖7B為圖7A畫素單元的局部放大示意圖，圖7C為圖7B之畫素單元的等效電路示意圖。圖7A的畫素陣列的構件與圖1A大致相同，不同處在於本實施例的第一子畫素與第二子畫素分別連接至不同的資料線，以及本實施例的畫素陣列於不同位置處形成儲存電容且不具有分享開關元件。因此，在圖7A的畫素陣列10c與圖1A的畫素陣列10中，使用相同或相似的標號來表示相同或相似的元件，且相關說明皆可參照前文。以下，將僅針對兩者之間的差異進行說明。7A is a schematic diagram of a pixel array according to an embodiment of the present invention, FIG. 7B is a partially enlarged schematic view of the pixel unit of FIG. 7A, and FIG. 7C is an equivalent circuit diagram of the pixel unit of FIG. 7B. The components of the pixel array of FIG. 7A are substantially the same as those of FIG. 1A except that the first sub-pixel and the second sub-pixel of the embodiment are respectively connected to different data lines, and the pixel array of the embodiment is different. A storage capacitor is formed at the location and does not have a shared switching element. Therefore, the same or similar reference numerals are used to denote the same or similar elements in the pixel array 10c of FIG. 7A and the pixel array 10 of FIG. 1A, and the related description can be referred to the foregoing. Hereinafter, only the difference between the two will be described.
請同時參照圖7A至圖7C，在本實施例中，畫素陣列10c包括多個畫素單元100c。每一個畫素單元100c包括第一子畫素P1、第二子畫素P2、掃描線GL、第一資料線DL1以及第二資料線DL2。其中，第一子畫素P1的第一主動元件T1的閘極G1與掃描線GL電性連接，第一主動元件T1的源極S1與第一資料線DL1電性連接。第二子畫素P2的第二主動元件T2的閘極G2與掃描線GL電性連接，第二主動元件T2的源極S2與第二資料線DL2電性連接。Referring to FIG. 7A to FIG. 7C simultaneously, in the present embodiment, the pixel array 10c includes a plurality of pixel units 100c. Each of the pixel units 100c includes a first sub-pixel P1, a second sub-pixel P2, a scanning line GL, a first data line DL1, and a second data line DL2. The gate G1 of the first active device T1 of the first sub-pixel P1 is electrically connected to the scan line GL, and the source S1 of the first active device T1 is electrically connected to the first data line DL1. The gate G2 of the second active device T2 of the second sub-pixel P2 is electrically connected to the scan line GL, and the source S2 of the second active device T2 is electrically connected to the second data line DL2.
第一畫素電極PE1與第二主動元件T2的汲極D2具有第一交疊處且形成第一電容C1。畫素單元100c例如是更包括第一電極E1與第二電極E2。第一電極E1例如是與第一畫素電極PE1電性連接。在本實施例中，第一電極E1與第一畫素電極PE1例如是一體成形。第二電極E2例如是電性連接至共同電位VCS 且與第一電極E1具有第二交疊處且形成第二電容C2。在本實施例中，第二電極E2實質上與共同線CL一體成形。在本實施例中，第二畫素電極PE2例如是進一步延伸而與第二電極E2具有交疊處且形成CST2 。The first pixel electrode PE1 and the drain D2 of the second active device T2 have a first overlap and form a first capacitance C1. The pixel unit 100c further includes, for example, a first electrode E1 and a second electrode E2. The first electrode E1 is electrically connected to the first pixel electrode PE1, for example. In the present embodiment, the first electrode E1 and the first pixel electrode PE1 are integrally formed, for example. The second electrode E2 is electrically connected to the common potential V CS and has a second overlap with the first electrode E1 and forms a second capacitance C2. In the present embodiment, the second electrode E2 is substantially integrally formed with the common line CL. In the present embodiment, the second pixel electrode PE2 is, for example, further extended to have an overlap with the second electrode E2 and form CST2 .
圖8A為對圖7B之畫素單元進行修補後的示意圖，以及圖8B為圖8A之經修補的畫素單元的等效電路示意圖。FIG. 8A is a schematic view showing the repair of the pixel unit of FIG. 7B, and FIG. 8B is an equivalent circuit diagram of the repaired pixel unit of FIG. 8A.
請參照圖8A與圖8B，當畫素單元100c中的第一子畫素P1或第二子畫素P2發生瑕疵時，藉由使第二子畫素P2、第一子畫素P1及第一電極E1與第二電極E2彼此電性連接，可形成一連接至共同電位VCS 的路徑Pw（如粗線箭頭所示），以使得第一子畫素P1與第二子畫素P2被暗點化被暗點化，詳細說明如下。首先，進行雷射切割製程，切割提供訊號至第一主動元件T1與第二主動元件T2的第一資料線DL1與第二資料線DL2。也就是說，第一資料線DL1與第二資料線DL2分別具有一切割處CS1、CS2，使得第一主動元件T1與第二主動元件T2與掃描線GL電性連接但與第一資料線DL1與第二資料線DL2經由切割處CS1、CS2電性分離。接著，對第二子畫素P2的汲極D2與第一畫素電極PE1的第一交疊處進行熔接可形成第一熔接點W1，以使第二子畫素P2的汲極D2與第一子畫素P1的第一畫素電極PE1電性連接。然後，對第一電極E1與第二電極E2的第二交疊處進行熔接可形成第二熔接點W2，以經由第二電極E2使第一電極E1電性連接至共同電位VCS 。如此一來，第二子畫素P2經由路徑Pw電性連接至共同電位VCS ，以被確實暗點化。Referring to FIG. 8A and FIG. 8B, when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit 100c is 瑕疵, by the second sub-pixel P2, the first sub-pixel P1 and the first An electrode E1 and a second electrode E2 are electrically connected to each other to form a path Pw (shown by a thick line arrow) connected to the common potential V CS such that the first sub-pixel P1 and the second sub-pixel P2 are Dark spots are darkened, as detailed below. First, a laser cutting process is performed to cut the first data line DL1 and the second data line DL2 that provide signals to the first active device T1 and the second active device T2. That is, the first data line DL1 and the second data line DL2 respectively have a cut portion CS1, CS2, such that the first active device T1 and the second active device T2 are electrically connected to the scan line GL but to the first data line DL1. It is electrically separated from the second data line DL2 via the cut places CS1, CS2. Then, the first overlap of the first sub-pixel P2 and the first overlap of the first pixel electrode PE1 can be formed to form the first fusion point W1, so that the second sub-pixel P2 is D2 and The first pixel electrode PE1 of a sub-pixel P1 is electrically connected. Then, welding the second overlap of the first electrode E1 and the second electrode E2 to form a second fusion splice point W2 to electrically connect the first electrode E1 to the common potential V CS via the second electrode E2. In this way, the second sub-pixel P2 is electrically connected to the common potential V CS via the path Pw to be truly darkened.
在本實施例中，藉由第一子畫素P1的第一畫素電極PE1與第二子畫素P2的汲極D2延伸而彼此重疊的設計，使第二子畫素P2能經由汲極D2、第一熔接點W1、第一畫素電極PE1、第一電極E1、第二熔接點W2以及第二電極E2的路徑Pw電性連接至共同電位VCS ，以達到確實使第一子畫素P1與第二子畫素P2暗點化的目的，進而修補畫素單元100c。In this embodiment, the second sub-pixel P2 can pass through the bungee by the design that the first pixel electrode PE1 of the first sub-pixel P1 and the drain D2 of the second sub-pixel P2 overlap each other. D2, the first fusion contact point W1, the first pixel electrode PE1, the first electrode E1, the second fusion point W2, and the path Pw of the second electrode E2 are electrically connected to the common potential V CS to achieve the first sub-picture The pixel P1 and the second sub-pixel P2 are darkened, and the pixel unit 100c is repaired.
由上述實施例可知，當畫素單元100、100a、100b、100c中的第一子畫素P1或第二子畫素P2發生瑕疵時，可經由第一熔接點W1電性連接至共同電位VCS ，達到將第一子畫素P1與第二子畫素P2確實暗點化的目的，如圖9A與圖9B所示。更進一步而言，當畫素單元中的第一子畫素P1或第二子畫素P2發生瑕疵時，可藉由使第二子畫素P2、第一子畫素P1及第一與第二電極E1、E2(或第一至第三電極E1、E2、E3)經由第一熔接點W1與第二熔接點W2彼此電性連接而連接至共同電位VCS ，達到將第一子畫素P1與第二子畫素P2確實暗點化的目的。因此，採用此畫素陣列10、10a、10b、10c的顯示面板具有良好的顯示品質。It can be seen from the above embodiment that when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit 100, 100a, 100b, 100c is chopped, it can be electrically connected to the common potential V via the first fusion splice point W1. CS achieves the purpose of darkening the first sub-pixel P1 and the second sub-pixel P2 as shown in FIGS. 9A and 9B. Further, when the first sub-pixel P1 or the second sub-pixel P2 in the pixel unit is 瑕疵, the second sub-pixel P2, the first sub-pixel P1, and the first and the second The two electrodes E1 and E2 (or the first to third electrodes E1, E2, and E3) are electrically connected to each other via the first fusion splice point W1 and the second fusion splice point W2 to be connected to the common potential V CS to reach the first sub-pixel. P1 and the second sub-pixel P2 are indeed darkened. Therefore, the display panel using the pixel arrays 10, 10a, 10b, and 10c has good display quality.
綜上所述，本發明之畫素陣列的第一與第二子畫素中，第一子畫素的畫素電極與第二子畫素的汲極延伸至彼此交疊以形成電容。當畫素單元中的第一子畫素或第二子畫素發生瑕疵時，可以經由切割與熔接使得第二子畫素經由第一子畫素與第一電極以及第二電極(或第一電極連接至第二電極與第三電極)電性連接至共同電位，即可達到將第一子畫素與第二子畫素確實暗點化的目的。故，本發明之畫素單元的結構有利於對子畫素進行確實暗點化，使得採用此畫素陣列的顯示面板具有良好的顯示品質。In summary, in the first and second sub-pixels of the pixel array of the present invention, the pixel electrodes of the first sub-pixel and the drain of the second sub-pixel extend to overlap each other to form a capacitance. When the first sub-pixel or the second sub-pixel in the pixel unit is chopped, the second sub-pixel can be connected to the first electrode and the second electrode (or the first via the first sub-pixel via cutting and welding) The electrode is connected to the second electrode and the third electrode to be electrically connected to a common potential, so that the first sub-pixel and the second sub-pixel are indeed darkened. Therefore, the structure of the pixel unit of the present invention facilitates the true dark spotting of the sub-pixels, so that the display panel using the pixel array has good display quality.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、10a、10b、10c‧‧‧畫素陣列
100、100a、100b、100c‧‧‧畫素單元
110‧‧‧電容電極
C1、C2、C3、CLC1、CLC2、CST1、CST2‧‧‧電容
CH1、CH2、CHsh、CHst‧‧‧通道層
CL‧‧‧共同線
CS‧‧‧切割處
D1、D2、Dsh、Dst‧‧‧汲極
DL‧‧‧資料線
DL1‧‧‧第一資料線
DL2‧‧‧第二資料線
E1‧‧‧第一電極
E2‧‧‧第二電極
E3‧‧‧第三電極
E4‧‧‧電極
G1、G2、Gsh‧‧‧閘極
GL‧‧‧掃描線
P1‧‧‧第一子畫素
P2‧‧‧第二子畫素
PE1‧‧‧第一畫素電極
PE2‧‧‧第二畫素電極
Pw‧‧‧路徑
S1、S2、Ssh‧‧‧源極
SL‧‧‧訊號線
T1‧‧‧第一主動元件
T2‧‧‧第二主動元件
Tsh‧‧‧分享開關元件
VCS、VCOM‧‧‧共同電位
W1‧‧‧第一熔接點
W2‧‧‧第二熔接點
W3‧‧‧第三熔接點10, 10a, 10b, 10c‧‧‧ pixel array
100, 100a, 100b, 100c‧‧‧ pixel units
110‧‧‧Capacitance electrode
C1, C2, C3, C LC1 , C LC2 , C ST1 , C ST2 ‧‧‧ capacitor
CH1, CH2, CHsh, CHst‧‧‧ channel layer
CL‧‧‧Common line
CS‧‧ cut section
D1, D2, Dsh, Dst‧‧‧ bungee
DL‧‧‧ data line
DL1‧‧‧ first data line
DL2‧‧‧ second data line
E1‧‧‧first electrode
E2‧‧‧second electrode
E3‧‧‧ third electrode
E4‧‧‧electrode
G1, G2, Gsh‧‧‧ gate
GL‧‧‧ scan line
P1‧‧‧ first sub-pixel
P2‧‧‧ second sub-pixel
PE1‧‧‧ first pixel electrode
PE2‧‧‧second pixel electrode
Pw‧‧‧ Path
S1, S2, Ssh‧‧‧ source
SL‧‧‧ signal line
T1‧‧‧ first active component
T2‧‧‧second active component
Tsh‧‧Share sharing switch components
V CS , V COM ‧‧‧ common potential
W1‧‧‧First fusion joint
W2‧‧‧second welding joint
W3‧‧‧ third welding joint
圖1A為本發明一實施例之畫素陣列的示意圖。 圖1B為圖1A畫素單元的局部放大示意圖。 圖1C為圖1B之畫素單元的等效電路示意圖。 圖2A為對圖1B之畫素單元進行修補後的示意圖。 圖2B為圖2A之經修補的畫素單元的等效電路示意圖。 圖3A為本發明一實施例之畫素陣列的示意圖。 圖3B為圖3A畫素單元的局部放大示意圖。 圖3C為圖3B之畫素單元的等效電路示意圖。 圖4A為對圖3B之畫素單元進行修補後的示意圖。 圖4B為圖4A之經修補的畫素單元的等效電路示意圖。 圖5A為本發明一實施例之畫素陣列的示意圖。 圖5B為圖5A畫素單元的局部放大示意圖。 圖5C為圖5B之畫素單元的等效電路示意圖。 圖6A為對圖5B之畫素單元進行修補後的示意圖。 圖6B為圖6A之經修補的畫素單元的等效電路示意圖。 圖7A為本發明一實施例之畫素陣列的示意圖。 圖7B為圖7A畫素單元的局部放大示意圖。 圖7C為圖7B之畫素單元的等效電路示意圖。 圖8A為對圖7B之畫素單元進行修補後的示意圖。 圖8B為圖8A之經修補的畫素單元的等效電路示意圖。 圖9A為本發明一實施例之畫素單元的等效電路示意圖。 圖9B為本發明一實施例之經修補的畫素單元的等效電路示意圖。1A is a schematic diagram of a pixel array according to an embodiment of the present invention. FIG. 1B is a partially enlarged schematic view of the pixel unit of FIG. 1A. FIG. 1C is an equivalent circuit diagram of the pixel unit of FIG. 1B. FIG. 2A is a schematic view showing the repair of the pixel unit of FIG. 1B. FIG. 2B is an equivalent circuit diagram of the repaired pixel unit of FIG. 2A. 3A is a schematic diagram of a pixel array in accordance with an embodiment of the present invention. FIG. 3B is a partially enlarged schematic view of the pixel unit of FIG. 3A. FIG. FIG. 3C is an equivalent circuit diagram of the pixel unit of FIG. 3B. 4A is a schematic view showing the repair of the pixel unit of FIG. 3B. 4B is an equivalent circuit diagram of the repaired pixel unit of FIG. 4A. FIG. 5A is a schematic diagram of a pixel array according to an embodiment of the invention. FIG. 5B is a partially enlarged schematic view of the pixel unit of FIG. 5A. FIG. FIG. 5C is an equivalent circuit diagram of the pixel unit of FIG. 5B. Fig. 6A is a schematic view showing the repair of the pixel unit of Fig. 5B. 6B is an equivalent circuit diagram of the repaired pixel unit of FIG. 6A. FIG. 7A is a schematic diagram of a pixel array according to an embodiment of the invention. Fig. 7B is a partially enlarged schematic view of the pixel unit of Fig. 7A. FIG. 7C is an equivalent circuit diagram of the pixel unit of FIG. 7B. Fig. 8A is a schematic view showing the repair of the pixel unit of Fig. 7B. FIG. 8B is an equivalent circuit diagram of the repaired pixel unit of FIG. 8A. FIG. 9A is a schematic diagram of an equivalent circuit of a pixel unit according to an embodiment of the invention. 9B is a schematic diagram showing an equivalent circuit of a repaired pixel unit according to an embodiment of the present invention.
100‧‧‧畫素單元 100‧‧‧ pixel unit
110‧‧‧電容電極 110‧‧‧Capacitance electrode
C1、C2、C3‧‧‧電容 C1, C2, C3‧‧‧ capacitors
CH1、CH2、CHsh‧‧‧通道層 CH1, CH2, CHsh‧‧‧ channel layer
CL‧‧‧共同線 CL‧‧‧Common line
D1、D2、Dsh‧‧‧汲極 D1, D2, Dsh‧‧‧ bungee
DL‧‧‧資料線 DL‧‧‧ data line
E1‧‧‧第一電極 E1‧‧‧first electrode
E2‧‧‧第二電極 E2‧‧‧second electrode
E3‧‧‧第三電極 E3‧‧‧ third electrode
G1、G2、Gsh‧‧‧閘極 G1, G2, Gsh‧‧‧ gate
GL‧‧‧掃描線 GL‧‧‧ scan line
P1‧‧‧第一子畫素 P1‧‧‧ first sub-pixel
P2‧‧‧第二子畫素 P2‧‧‧ second sub-pixel
PE1‧‧‧第一畫素電極 PE1‧‧‧ first pixel electrode
PE2‧‧‧第二畫素電極 PE2‧‧‧second pixel electrode
S1、S2、Ssh‧‧‧源極 S1, S2, Ssh‧‧‧ source
SL‧‧‧訊號線 SL‧‧‧ signal line
T1‧‧‧第一主動元件 T1‧‧‧ first active component
T2‧‧‧第二主動元件 T2‧‧‧second active component
Tsh‧‧‧分享開關元件 Tsh‧‧Share sharing switch components
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|---|---|
| CN105425435A (en) | 2016-03-23 |
| CN105425435B (en) | 2018-11-09 |
| TWI564645B (en) | 2017-01-01 |
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