TW201711115A - Semiconductor device manufacturing method capable of restraining the signal interference between a plurality of signal leads - Google Patents
Semiconductor device manufacturing method capable of restraining the signal interference between a plurality of signal leads Download PDFInfo
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- TW201711115A TW201711115A TW105106357A TW105106357A TW201711115A TW 201711115 A TW201711115 A TW 201711115A TW 105106357 A TW105106357 A TW 105106357A TW 105106357 A TW105106357 A TW 105106357A TW 201711115 A TW201711115 A TW 201711115A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
本申請案享有以日本專利申請案2015-181478號(申請日：2015年9月15日)為基礎申請案之優先權。本申請案係藉由參照該基礎申請案而包含基礎申請案之全部內容。 The present application has priority in the application based on Japanese Patent Application No. 2015-181478 (filing date: September 15, 2015). This application contains the entire contents of the basic application by reference to the basic application.
本發明之實施形態係關於一種半導體裝置之製造方法。 Embodiments of the present invention relate to a method of fabricating a semiconductor device.
於具備包含外引線與內引線之引線及半導體晶片之半導體裝置中，例如藉由接合線而將半導體晶片之電極墊與內引線之間電性連接。 In a semiconductor device including a lead including an outer lead and an inner lead, and a semiconductor wafer, the electrode pad of the semiconductor wafer and the inner lead are electrically connected, for example, by bonding wires.
於具備複數個信號用引線之半導體裝置中，存在根據半導體裝置之標準而並列設置2個以上之信號用引線之外引線之情形。此時，有於並列設置之信號用引線間產生信號之雜訊等干擾而引起半導體裝置之動作不良之情形。 In a semiconductor device including a plurality of signal leads, there are cases in which two or more signal leads are arranged in parallel according to the standard of the semiconductor device. At this time, there is a case where the semiconductor device is malfunctioning due to interference such as noise generated by signals between the signals arranged in parallel.
並列設置之信號用引線之間隔越窄，上述信號之干擾所致之影響越顯著。另一方面，就半導體裝置之高性能化或小型化之觀點而言，要求縮窄引線之間隔而提高引線之積體密度。 The narrower the interval between the signal leads arranged in parallel, the more significant the effect of the interference of the above signals. On the other hand, from the viewpoint of high performance or miniaturization of a semiconductor device, it is required to narrow the interval between leads to increase the integrated density of the leads.
本發明之實施形態提供一種可抑制複數個信號用引線間之信號干擾之半導體裝置之製造方法。 Embodiments of the present invention provide a method of manufacturing a semiconductor device capable of suppressing signal interference between a plurality of signal leads.
實施形態之半導體裝置之製造方法具備：對引線架實施去除配 線部之加工而將第2電源用引線之一部分、第1信號用引線之一部分及第2信號用引線之一部分分離之步驟，該引線架具備：第1電源用引線；第1信號用引線；第2信號用引線，其設置於第1電源用引線與第1信號用引線之間；第2電源用引線，其設置於第1信號用引線與第2信號用引線之間；配線部，其將第2電源用引線之一部分、第1信號用引線之一部分與第2信號用引線之一部分之間連接；及支持部，其連接於第1電源用引線之一部分、第1信號用引線之另一部分、及第2信號用引線之另一部分；且第1電源用引線以及第1及第2信號用引線各自包含內引線與外引線，第2電源用引線包含內引線；將半導體晶片搭載於引線架上之步驟；形成將第1及第2信號用引線以及第2電源用引線與半導體晶片之間分別電性連接之第1接合線、及橫跨第2信號用引線而將第1電源用引線與第2電源用引線之間電性連接之第2接合線之步驟；形成將第1及第2電源用引線以及第1及第2信號用引線各自之內引線、第2電源用引線之內引線、半導體晶片、第1及第2接合線密封之密封樹脂層之步驟；及將支持部與第1電源用引線之一部分以及第1及第2信號用引線之另一部分之間之連接部之各者切斷之步驟。 A method of manufacturing a semiconductor device according to an embodiment includes: removing a lead frame a step of separating a portion of the second power supply lead, a portion of the first signal lead, and a second signal lead by machining the line portion, the lead frame having: a first power supply lead; and a first signal lead; The second signal lead is provided between the first power supply lead and the first signal lead; the second power supply lead is provided between the first signal lead and the second signal lead; and the wiring portion One part of the second power supply lead, one part of the first signal lead, and one part of the second signal lead; and a support portion connected to one of the first power supply lead and the first signal lead And a part of the second signal lead and the first and second signal leads each include an inner lead and an outer lead, the second power supply lead includes an inner lead, and the semiconductor wafer is mounted on the lead a step of forming a first bonding wire for electrically connecting the first and second signal leads and the second power supply lead to the semiconductor wafer, and forming a first power supply for crossing the second signal lead Lead and 2nd a second bonding wire electrically connected between the power supply leads; forming an inner lead of each of the first and second power supply leads and the first and second signal leads, an inner lead of the second power supply lead, and a semiconductor a step of sealing the resin layer on the wafer, the first and second bonding wires, and a connection portion between the support portion and one of the first power supply lead and the other of the first and second signal leads The step of breaking.
1‧‧‧引線架 1‧‧‧ lead frame
2‧‧‧半導體晶片 2‧‧‧Semiconductor wafer
3‧‧‧接合線 3‧‧‧bonding line
4‧‧‧密封樹脂層 4‧‧‧ sealing resin layer
6‧‧‧有機接著層 6‧‧‧Organic layer
10‧‧‧半導體裝置 10‧‧‧Semiconductor device
11‧‧‧引線 11‧‧‧ lead
12‧‧‧支持部 12‧‧‧Support Department
13‧‧‧絕緣性帶 13‧‧‧Insulation tape
21‧‧‧電極墊 21‧‧‧electrode pads
31‧‧‧接合線 31‧‧‧bonding line
32‧‧‧接合線 32‧‧‧bonding line
33‧‧‧接合線 33‧‧‧bonding line
34‧‧‧接合線 34‧‧‧bonding line
35‧‧‧接合線 35‧‧‧bonding line
36‧‧‧接合線 36‧‧‧bonding line
100‧‧‧區域 100‧‧‧ area
101‧‧‧區域 101‧‧‧Area
102‧‧‧區域 102‧‧‧Area
111‧‧‧電源用引線 111‧‧‧Power supply leads
111a‧‧‧接合墊部 111a‧‧‧Joint pad
112‧‧‧信號用引線 112‧‧‧Signal leads
112a‧‧‧配線部 112a‧‧‧Wiring Department
113‧‧‧信號用引線 113‧‧‧Signal leads
113a‧‧‧配線部 113a‧‧‧Wiring Department
114‧‧‧電源用引線 114‧‧‧Power lead
114a‧‧‧接合墊部 114a‧‧‧Joint pad
115‧‧‧配線部 115‧‧‧Wiring Department
211‧‧‧電極墊 211‧‧‧electrode pad
212‧‧‧電極墊 212‧‧‧electrode pads
213‧‧‧電極墊 213‧‧‧electrode pads
X‧‧‧軸 X‧‧‧ axis
Y‧‧‧軸 Y‧‧‧ axis
圖1係表示引線架之構造例之俯視模式圖。 Fig. 1 is a plan view showing a configuration example of a lead frame.
圖2係表示圖1所示之引線架之一部分之放大圖。 Figure 2 is an enlarged view showing a portion of the lead frame shown in Figure 1.
圖3係表示引線架加工步驟後之引線架之一部分之放大圖。 Figure 3 is an enlarged view showing a portion of the lead frame after the lead frame processing step.
圖4係表示引線架之另一構造例之圖。 Fig. 4 is a view showing another configuration example of the lead frame.
圖5係表示半導體裝置之構造例之俯視模式圖。 Fig. 5 is a plan view showing a configuration example of a semiconductor device.
圖6係表示圖5所示之半導體裝置之一部分之放大圖。 Fig. 6 is an enlarged view showing a part of the semiconductor device shown in Fig. 5.
圖7係表示圖6所示之半導體裝置之一部分之剖面模式圖。 Fig. 7 is a cross-sectional schematic view showing a portion of the semiconductor device shown in Fig. 6.
圖8係表示圖5所示之半導體裝置之另一部分之放大圖。 Fig. 8 is an enlarged view showing another part of the semiconductor device shown in Fig. 5.
圖9係圖8所示之半導體裝置之另一部分之剖面模式圖。 Figure 9 is a cross-sectional schematic view showing another portion of the semiconductor device shown in Figure 8.
以下，參照圖式對實施形態進行說明。存在圖式中所記載之各構成要素之厚度與平面尺寸之關係、各構成要素之厚度之比率等與實物不同之情形。又，於實施形態中，對於實質上相同之構成要素標註相同之符號並適當省略說明。 Hereinafter, embodiments will be described with reference to the drawings. There is a case where the relationship between the thickness of each constituent element described in the drawing and the plane size, the ratio of the thickness of each constituent element, and the like are different from the actual one. In the embodiment, substantially the same components are denoted by the same reference numerals, and their description will be appropriately omitted.
作為半導體裝置之製造方法例，參照圖1至圖9對作為TSOP(Thin Small Outline Package：TSOP，薄型小尺寸封裝)之半導體裝置之製造方法例進行說明。半導體裝置之製造方法例具備引線架準備步驟、引線架加工步驟、晶片搭載步驟、打線接合步驟、樹脂密封步驟、鍍敷步驟、及修整成形(T/F)步驟。各步驟之順序並不限定於以上所列舉之順序。 As an example of a method of manufacturing a semiconductor device, an example of a method of manufacturing a semiconductor device as a TSOP (Thin Small Outline Package: TSOP) will be described with reference to FIGS. 1 to 9 . An example of a method of manufacturing a semiconductor device includes a lead frame preparation step, a lead frame processing step, a wafer mounting step, a wire bonding step, a resin sealing step, a plating step, and a trimming (T/F) step. The order of the steps is not limited to the order listed above.
圖1係表示引線架之構造例之俯視模式圖。圖1表示包含X軸及與X軸正交之Y軸之引線架1之X-Y平面。 Fig. 1 is a plan view showing a configuration example of a lead frame. 1 shows the X-Y plane of the lead frame 1 including the X axis and the Y axis orthogonal to the X axis.
於引線架準備步驟中，如圖1所示，準備具有複數個引線11及支持複數個引線11之支持部12之引線架1。引線架1係搭載半導體晶片等元件之金屬板。作為引線架1，例如可列舉使用銅、銅合金或42合金等鐵及鎳之合金等之引線架。 In the lead frame preparation step, as shown in FIG. 1, a lead frame 1 having a plurality of leads 11 and a support portion 12 supporting a plurality of leads 11 is prepared. The lead frame 1 is a metal plate on which components such as semiconductor wafers are mounted. As the lead frame 1, for example, a lead frame such as an alloy of iron such as copper, a copper alloy or a 42 alloy, or an alloy of nickel may be used.
複數個引線11中之至少一者係藉由貼附於半導體晶片之與搭載面為相反側之面之聚醯亞胺等絕緣性帶13而補強。於圖1中設置著複數個絕緣性帶13。 At least one of the plurality of leads 11 is reinforced by an insulating tape 13 such as polyimide which is attached to the surface of the semiconductor wafer opposite to the mounting surface. A plurality of insulating tapes 13 are provided in FIG.
作為複數個引線11，例如可列舉輸入輸出信號(IO)、資料選通信號(DQS)、讀出賦能信號(RE)、待命/忙碌信號(RB)、晶片賦能信號(CE)、位址閂賦能信號(ALE)、寫入賦能信號(WE)、寫入保護信號(RP)或零商(Zero Quotient)信號(ZQ)等信號用引線、或電源(VCC)、電源(VPP)、電源(VSS)等電源用引線等。亦可使用差動信號作為上述信號。複數個引線11亦可具有未連接(NC)之引線。各種引線之排列順序 係根據半導體裝置之標準或規格等而設定。 Examples of the plurality of leads 11 include an input/output signal (10), a data strobe signal (DQS), a read enable signal (RE), a standby/busy signal (RB), a wafer enable signal (CE), and a bit. Signal enable signal (ALE), write enable signal (WE), write protection signal (RP) or Zero Quotient signal (ZQ) signal lead, or power supply (VCC), power supply (VPP) ), power supply (VSS) and other power supply leads. A differential signal can also be used as the above signal. The plurality of leads 11 may also have unconnected (NC) leads. Arrangement of various leads It is set according to the standard or specification of a semiconductor device.
支持部12例如係以包圍複數個引線11之方式設定。支持部12連接於複數個引線11之至少一者之一部分。再者，支持部12亦可支持複數個半導體裝置之引線。 The support portion 12 is set, for example, so as to surround a plurality of leads 11. The support portion 12 is connected to a portion of at least one of the plurality of leads 11. Furthermore, the support unit 12 can also support the leads of a plurality of semiconductor devices.
圖2係表示圖1所示之引線架之一部分(區域100之一部分)之放大圖。於圖2中，圖示電源用引線111、信號用引線112、信號用引線113、電源用引線114作為複數個引線11。 Figure 2 is an enlarged view showing a portion (a portion of the region 100) of the lead frame shown in Figure 1. In FIG. 2, the power supply lead 111, the signal lead 112, the signal lead 113, and the power supply lead 114 are shown as a plurality of leads 11.
電源用引線111、信號用引線112、及信號用引線113各自包含外引線及自該外引線延伸之內引線。內引線係於樹脂密封步驟後支持於密封樹脂層之部分。外引線係連接於支持部12且於樹脂密封步驟後自密封樹脂層突出之部分。電源用引線111、信號用引線112、及信號用引線113之外引線之各者例如沿Y軸並列設置於X-Y平面。 The power supply lead 111, the signal lead 112, and the signal lead 113 each include an outer lead and an inner lead extending from the outer lead. The inner lead is supported by a portion of the sealing resin layer after the resin sealing step. The outer lead is connected to the support portion 12 and protrudes from the sealing resin layer after the resin sealing step. Each of the leads other than the power supply lead 111, the signal lead 112, and the signal lead 113 is arranged side by side on the X-Y plane along the Y axis, for example.
電源用引線111於內引線之端部具有接合墊部111a。接合墊部111a具有於與電源用引線111之長度方向交叉之方向上具有長度方向之形狀。例如，接合墊部111a之平面形狀為於Y軸方向上具有長邊之長方形。 The power supply lead 111 has a bonding pad portion 111a at the end of the inner lead. The bonding pad portion 111a has a shape having a longitudinal direction in a direction crossing the longitudinal direction of the power supply lead 111. For example, the planar shape of the joint pad portion 111a is a rectangle having a long side in the Y-axis direction.
信號用引線113設置於電源用引線111與信號用引線112之間。於半導體裝置之規格上，信號用引線112之外引線及信號用引線113之外引線係以相鄰之方式並列設置。信號用引線112之外引線與信號用引線113之外引線之間隔例如為0.5mm以下。 The signal lead 113 is provided between the power supply lead 111 and the signal lead 112. In the specification of the semiconductor device, the leads other than the signal lead wires 112 and the leads other than the signal lead wires 113 are arranged side by side in an adjacent manner. The distance between the outer leads of the signal lead wires 112 and the outer leads of the signal lead wires 113 is, for example, 0.5 mm or less.
電源用引線114設置於信號用引線112與信號用引線113之間。藉由電源用引線114設置於信號用引線112與信號用引線113之間，例如即便於使引線高密度化之情形時，亦可抑制於信號用引線112之信號與信號用引線113之信號之間產生之雜訊等干擾。 The power supply lead 114 is provided between the signal lead 112 and the signal lead 113. The power supply lead 114 is provided between the signal lead 112 and the signal lead 113. For example, even when the lead is densified, the signal of the signal lead 112 and the signal lead 113 can be suppressed. Interference caused by noise.
電源用引線114具有接合墊部114a。接合墊部114a具有於與接合墊部111a相同之方向上具有長度方向之形狀。例如，接合墊部114a之 平面形狀為於Y軸方向上具有長邊之長方形。 The power supply lead 114 has a bonding pad portion 114a. The bonding pad portion 114a has a shape having a longitudinal direction in the same direction as the bonding pad portion 111a. For example, the bonding pad portion 114a The planar shape is a rectangle having a long side in the Y-axis direction.
電源用引線114包含內引線而不包含外引線。若信號用引線112之外引線與信號用引線113之外引線之間隔較窄，則難以於信號用引線112之外引線與信號用引線113之外引線之間配置電源用引線114之外引線。 The power supply lead 114 includes an inner lead without an outer lead. When the distance between the lead other than the signal lead 112 and the lead outside the signal lead 113 is narrow, it is difficult to arrange the lead other than the power supply lead 114 between the lead outside the signal lead 112 and the lead other than the signal lead 113.
電源用引線114於打線接合步驟中電性連接於電源用引線111。即，電源用引線111之外引線具有作為電源用引線114之外引線之功能。 The power supply lead 114 is electrically connected to the power supply lead 111 in the wire bonding step. In other words, the lead other than the power supply lead 111 has a function as a lead other than the power supply lead 114.
電源用引線114較電源用引線111長。又，電源用引線111與電源用引線114之合計長度例如可較信號用引線112長且較信號用引線113短。 The power supply lead 114 is longer than the power supply lead 111. Further, the total length of the power supply lead 111 and the power supply lead 114 can be longer than the signal lead 112 and shorter than the signal lead 113, for example.
電源用引線114之信號用引線112與信號用引線113之間之部分越長，越可抑制信號用引線112與信號用引線113之間之干擾。然而，較長之引線於半導體裝置之製造過程中容易變形。若引線變形，則例如存在半導體晶片容易自引線剝落之情形或有於打線接合時於接合線與引線之間產生連接不良之情形。 The longer the portion between the signal lead 112 and the signal lead 113 of the power supply lead 114, the more the interference between the signal lead 112 and the signal lead 113 can be suppressed. However, longer leads are susceptible to deformation during the fabrication of semiconductor devices. If the lead wire is deformed, for example, there is a case where the semiconductor wafer is easily peeled off from the lead or a connection failure occurs between the bonding wire and the lead at the time of wire bonding.
如圖2所示，引線架1具有將信號用引線112、信號用引線113及電源用引線114之間連接之配線部115。此時，電源用引線114係藉由配線部115及絕緣性帶13而補強。因此，即便於電源用引線114較長之情形時，亦可抑制不必要之變形。配線部115之形狀只要為可將信號用引線112、信號用引線113及電源用引線114之間連接之形狀，則並無特別限定。再者，並不限定於配線部115，引線架1亦可具有將複數個信號用引線與電源用引線連接之其他配線部。 As shown in FIG. 2, the lead frame 1 has a wiring portion 115 that connects the signal lead 112, the signal lead 113, and the power supply lead 114. At this time, the power supply lead wire 114 is reinforced by the wiring portion 115 and the insulating tape 13. Therefore, even when the power supply lead 114 is long, unnecessary deformation can be suppressed. The shape of the wiring portion 115 is not particularly limited as long as it can connect the signal lead 112, the signal lead 113, and the power supply lead 114. Further, the wiring frame 1 is not limited to the wiring portion 115, and the lead frame 1 may have another wiring portion that connects a plurality of signal leads to a power supply lead.
圖3係表示引線架加工步驟後之引線架之一部分(區域100之一部分)之放大圖。於引線架加工步驟中，實施去除配線部115之加工而將信號用引線112之一部分、信號用引線113之一部分及電源用引線114 之一部分(接合墊部114a)分離。配線部115例如係藉由使用沖裁加工用之加工裝置對配線部115進行沖裁而去除。加工裝置例如可使用黏晶裝置。例如，於將引線架1配置(裝載)於黏晶裝置後，對配線部15進行沖裁。其後，於未將引線架1自黏晶裝置去除(卸載)之情形時將後述之半導體晶片2搭載於引線架1。於搭載半導體晶片2之後，將引線架1自黏晶裝置去除(卸載)，並執行其後之步驟、例如後述之打線接合步驟。於去除配線部115後，將接合墊部114a配置於電源用引線114之端部。又，露出部亦可殘存於信號用引線112及信號用引線113之一部分。 Figure 3 is an enlarged view showing a portion (a portion of the region 100) of the lead frame after the lead frame processing step. In the lead frame processing step, a portion of the signal lead 112, a portion of the signal lead 113, and a power supply lead 114 are removed by the process of removing the wiring portion 115. A part (joining pad portion 114a) is separated. The wiring portion 115 is removed by, for example, punching the wiring portion 115 by using a processing device for punching. For the processing device, for example, a die bonding device can be used. For example, after the lead frame 1 is placed (loaded) on the die bonding device, the wiring portion 15 is punched. Thereafter, when the lead frame 1 is not removed (unloaded) from the die bonding apparatus, the semiconductor wafer 2 to be described later is mounted on the lead frame 1. After the semiconductor wafer 2 is mounted, the lead frame 1 is removed (unloaded) from the die bonding apparatus, and a subsequent step, for example, a wire bonding step to be described later, is performed. After the wiring portion 115 is removed, the bonding pad portion 114a is disposed at the end of the power supply lead 114. Further, the exposed portion may remain in one of the signal lead 112 and the signal lead 113.
藉由改變加工裝置之沖裁構件之形狀，即便為具有與圖2不同之形狀之配線部115，亦可將其去除。圖4係表示配線部115之另一例之俯視模式圖。於圖4中，配線部115具有自信號用引線112分支之配線部112a、及自信號用引線113分支之配線部113a。 By changing the shape of the punching member of the processing apparatus, even the wiring portion 115 having a shape different from that of FIG. 2 can be removed. FIG. 4 is a schematic plan view showing another example of the wiring portion 115. In FIG. 4, the wiring portion 115 has a wiring portion 112a branched from the signal lead 112 and a wiring portion 113a branched from the signal lead 113.
配線部112a及配線部113a設置於信號用引線112與信號用引線113之間，且沿X軸方向延伸。因此，可擴大配線部115之寬度。因此，可使接合墊部114a之長邊沿Y軸方向變長至配線部112a之寬度與配線部113a之寬度之總和以上。 The wiring portion 112a and the wiring portion 113a are provided between the signal lead 112 and the signal lead 113, and extend in the X-axis direction. Therefore, the width of the wiring portion 115 can be enlarged. Therefore, the long side of the bonding pad portion 114a can be lengthened in the Y-axis direction to be greater than or equal to the sum of the width of the wiring portion 112a and the width of the wiring portion 113a.
圖5係表示可使用上述半導體裝置之製造方法製造之半導體裝置之構造例之俯視模式圖。圖5表示半導體裝置10之X-Y平面。於圖5中圖示複數個引線11、絕緣性帶13、半導體晶片2、接合線3、及密封樹脂層4。再者，於圖5中，為了便於說明，透過密封樹脂層4之內部而圖示。又，對於與圖1至圖4之共通部分，適當引用圖1至圖4之說明。 FIG. 5 is a plan view schematically showing a configuration example of a semiconductor device which can be manufactured by using the above-described semiconductor device manufacturing method. FIG. 5 shows the X-Y plane of the semiconductor device 10. A plurality of leads 11, an insulating tape 13, a semiconductor wafer 2, a bonding wire 3, and a sealing resin layer 4 are illustrated in FIG. In addition, in FIG. 5, for the convenience of description, it is illustrated by the inside of the sealing resin layer 4. Further, for the common portions with respect to FIGS. 1 to 4, the description of FIGS. 1 to 4 will be appropriately cited.
圖6係表示圖5所示之半導體裝置之一部分(區域101之一部分)之放大圖。圖7係圖6所示之半導體裝置之一部分(區域101之一部分)之剖面模式圖。圖7表示作為一例之包含電源用引線114及接合線33之剖面。圖8係表示圖5所示之半導體裝置之另一部分(區域102之一部分) 之放大圖。圖9係圖8所示之半導體裝置之另一部分(區域102之一部分)之剖面模式圖。圖9表示作為一例之包含電源用引線111、114及信號用引線112、113、以及接合線34及接合線35之剖面。 Fig. 6 is an enlarged view showing a portion (a portion of the region 101) of the semiconductor device shown in Fig. 5. Figure 7 is a schematic cross-sectional view showing a portion (a portion of the region 101) of the semiconductor device shown in Figure 6. FIG. 7 shows a cross section including the power supply lead 114 and the bonding wire 33 as an example. Figure 8 is a diagram showing another portion of the semiconductor device shown in Figure 5 (part of region 102) Magnified view. Figure 9 is a cross-sectional schematic view of another portion (portion of region 102) of the semiconductor device shown in Figure 8. FIG. 9 shows a cross section including the power supply leads 111 and 114, the signal leads 112 and 113, and the bonding wires 34 and the bonding wires 35 as an example.
於晶片搭載步驟中，將半導體晶片2搭載於複數個引線11之內引線之至少一者之上。於圖5中，半導體晶片2設置於信號用引線112、信號用引線113、及電源用引線114之內引線上，但並未設置於電源用引線111之內引線上。 In the wafer mounting step, the semiconductor wafer 2 is mounted on at least one of the inner leads of the plurality of leads 11. In FIG. 5, the semiconductor wafer 2 is provided on the inner lead of the signal lead 112, the signal lead 113, and the power supply lead 114, but is not provided on the inner lead of the power supply lead 111.
半導體晶片2具有複數個電極墊21。複數個電極墊21於半導體晶片2之表面露出。複數個電極墊21可沿半導體晶片2之一邊而設置。藉由沿半導體晶片2之一邊而設置複數個電極墊21，可縮小晶片尺寸。作為半導體晶片2，例如可列舉NAND(Not AND，反及)型快閃記憶體等記憶體元件或記憶體控制器等所使用之半導體晶片。於圖6中，圖示電極墊211至電極墊213作為複數個電極墊21。 The semiconductor wafer 2 has a plurality of electrode pads 21. A plurality of electrode pads 21 are exposed on the surface of the semiconductor wafer 2. A plurality of electrode pads 21 may be disposed along one side of the semiconductor wafer 2. By arranging a plurality of electrode pads 21 along one side of the semiconductor wafer 2, the wafer size can be reduced. The semiconductor wafer 2 is, for example, a semiconductor wafer used for a memory element such as a NAND (Not AND) type flash memory or a memory controller. In FIG. 6, the electrode pad 211 to the electrode pad 213 are illustrated as a plurality of electrode pads 21.
半導體晶片2例如係使用黏晶裝置而搭載。例如，半導體晶片2係藉由接合頭而搭載於複數個引線11之至少一者之上。如圖7所示，半導體晶片2隔著具有絕緣性之晶片黏著膜等有機接著層6而搭載於複數個引線11之一者之上。此時，複數個引線11之內引線之至少一者接著於有機接著層6。即，複數個引線11之內引線之至少一者係藉由有機接著層6及絕緣性帶13而補強，故而於其後之步驟中可抑制引線之不必要之變形。作為有機接著層6，可使用例如使用有聚醯亞胺樹脂、環氧樹脂或丙烯酸系樹脂等之熱固性樹脂或光硬化性樹脂等。半導體晶片2較佳為於去除配線部115後搭載。若於搭載半導體晶片後去除配線部115，則存在會對半導體晶片造成損害之情形。 The semiconductor wafer 2 is mounted, for example, using a die bonding device. For example, the semiconductor wafer 2 is mounted on at least one of the plurality of leads 11 by a bonding head. As shown in FIG. 7, the semiconductor wafer 2 is mounted on one of the plurality of leads 11 via an organic adhesive layer 6 such as an insulating die attach film. At this time, at least one of the inner leads of the plurality of leads 11 is followed by the organic bonding layer 6. That is, at least one of the inner leads of the plurality of leads 11 is reinforced by the organic adhesive layer 6 and the insulating tape 13, so that unnecessary deformation of the leads can be suppressed in the subsequent steps. As the organic adhesive layer 6, for example, a thermosetting resin such as a polyimide resin, an epoxy resin, or an acrylic resin, or a photocurable resin can be used. The semiconductor wafer 2 is preferably mounted after the wiring portion 115 is removed. If the wiring portion 115 is removed after the semiconductor wafer is mounted, the semiconductor wafer may be damaged.
於打線接合步驟中，形成將複數個電極墊21與複數個引線11之間電性連接之複數個接合線3。作為接合線3，可列舉例如金導線、銀導線、銅導線等。亦可利用鈀膜覆蓋銅導線之表面。接合線3係藉由打 線接合而電性連接於引線及電極墊。 In the wire bonding step, a plurality of bonding wires 3 electrically connecting a plurality of electrode pads 21 and a plurality of leads 11 are formed. Examples of the bonding wire 3 include a gold wire, a silver wire, a copper wire, and the like. The surface of the copper wire can also be covered with a palladium film. Bonding wire 3 is made by hitting The wires are bonded and electrically connected to the leads and the electrode pads.
於圖6中圖示將信號用引線112與電極墊211電性連接之接合線31、將信號用引線113與電極墊212電性連接之接合線32、將電源用引線114與電極墊213電性連接之接合線33、及將電源用引線114與其他電源用引線電性連接之接合線34。藉由利用接合線將複數個電源用引線電性連接，可使電源或接地之電位穩定或降低電源-接地間之電感。 FIG. 6 shows a bonding wire 31 electrically connecting the signal lead 112 and the electrode pad 211, a bonding wire 32 electrically connecting the signal lead 113 and the electrode pad 212, and electrically connecting the power supply lead 114 and the electrode pad 213. The bonding wires 33 of the connection and the bonding wires 34 for electrically connecting the power supply leads 114 to the other power supply leads. By electrically connecting a plurality of power supply leads by a bonding wire, the potential of the power supply or the ground can be stabilized or the inductance between the power supply and the ground can be reduced.
於圖8及圖9中圖示橫跨信號用引線113而將電源用引線111之接合墊部111a與電源用引線114之接合墊部114a電性連接之接合線35、及橫跨信號用引線112而將接合墊部114a與其他電源用引線電性連接之接合線36。接合線35與信號用引線113隔開，接合線36與信號用引線112隔開。 8 and 9, a bonding wire 35 for electrically connecting the bonding pad portion 111a of the power supply lead 111 and the bonding pad portion 114a of the power supply lead 114, and a cross-signal lead are provided across the signal lead 113. 112, a bonding wire 36 that electrically connects the bonding pad portion 114a to other power supply leads. The bonding wire 35 is spaced apart from the signal lead 113, and the bonding wire 36 is spaced apart from the signal lead 112.
藉由接合線步驟而將電源用引線114電性連接於電源用引線111。因此，即便於電源用引線114不包含外引線之情形時，亦可使電源用引線111之外引線發揮作為電源用引線114之外引線之功能。 The power supply lead 114 is electrically connected to the power supply lead 111 by a bonding wire step. Therefore, even when the power supply lead 114 does not include the outer lead, the outer lead of the power supply lead 111 can function as a lead other than the power supply lead 114.
接合線35較佳為沿接合墊部111a及接合墊部114a之長度方向延伸。若接合墊部111a及接合墊部114a於接合線35之延伸方向上較長，則容易使接合線35相對於接合墊部111a或接合墊部114a之角度較大。因此，可抑制接合線35與信號用引線113之間之短路。 The bonding wires 35 preferably extend in the longitudinal direction of the bonding pad portion 111a and the bonding pad portion 114a. When the bonding pad portion 111a and the bonding pad portion 114a are long in the extending direction of the bonding wire 35, the angle of the bonding wire 35 with respect to the bonding pad portion 111a or the bonding pad portion 114a is likely to be large. Therefore, the short circuit between the bonding wire 35 and the signal lead 113 can be suppressed.
於樹脂密封步驟中，形成將複數個引線11之內引線、半導體晶片2、及複數個接合線3密封之密封樹脂層4。於圖7及圖9中圖示將電源用引線111、信號用引線112、信號用引線113、及電源用引線114各自之內引線、半導體晶片2、接合線31至接合線36密封之密封樹脂層4。如圖7及圖9所示，密封樹脂層4係以覆蓋複數個引線11之內引線之上表面及下表面之方式設置。 In the resin sealing step, a sealing resin layer 4 that seals the inner leads of the plurality of leads 11, the semiconductor wafer 2, and the plurality of bonding wires 3 is formed. Sealing resin for sealing the inner lead of the power supply lead 111, the signal lead 112, the signal lead 113, and the power supply lead 114, the semiconductor wafer 2, the bonding wire 31 to the bonding wire 36, and the sealing resin are shown in FIG. 7 and FIG. Layer 4. As shown in FIGS. 7 and 9, the sealing resin layer 4 is provided to cover the upper surface and the lower surface of the inner lead of the plurality of leads 11.
密封樹脂層4含有SiO2等無機填充材。又，無機填充材除SiO2以 外，亦可包含例如氫氧化鋁、碳酸鈣、氧化鋁、氮化硼、氧化鈦、或鈦酸鋇等。無機填充材例如為粒狀，具有調整密封樹脂層4之黏度或硬度等之功能。密封樹脂層4中之無機填充材之含量例如為60%以上且90%以下。作為密封樹脂層4，例如可使用無機填充材與絕緣性有機樹脂材料之混合物。作為有機樹脂材料，例如可列舉環氧樹脂。 The sealing resin layer 4 contains an inorganic filler such as SiO 2 . Further, the inorganic filler may contain, for example, aluminum hydroxide, calcium carbonate, aluminum oxide, boron nitride, titanium oxide, or barium titanate in addition to SiO 2 . The inorganic filler is, for example, granular, and has a function of adjusting the viscosity or hardness of the sealing resin layer 4. The content of the inorganic filler in the sealing resin layer 4 is, for example, 60% or more and 90% or less. As the sealing resin layer 4, for example, a mixture of an inorganic filler and an insulating organic resin material can be used. As an organic resin material, an epoxy resin is mentioned, for example.
作為密封樹脂層4之形成方法，例如可列舉使用無機填充材與有機樹脂等之混合物之轉移模塑法、壓縮模塑法、注射模塑法、片狀模塑法、或樹脂點膠法等。 Examples of the method for forming the sealing resin layer 4 include transfer molding, compression molding, injection molding, sheet molding, or resin dispensing using a mixture of an inorganic filler and an organic resin. .
於鍍敷步驟中，對複數個引線11之表面實施鍍敷加工。例如使用包含錫等之焊料材料進行電場電鍍等鍍敷加工。藉由實施鍍敷加工，可抑制例如複數個引線11之氧化。 In the plating step, the surface of the plurality of leads 11 is plated. For example, plating treatment such as electric field plating is performed using a solder material containing tin or the like. By performing the plating process, for example, oxidation of a plurality of leads 11 can be suppressed.
修整成形(T/F)步驟包含將複數個引線11與支持部12之間之連接部切斷而切出半導體裝置10之步驟(修整步驟)、及使複數個引線11之外引線配合於半導體裝置10之最終形狀而變形之步驟(成形步驟)。於修整步驟中，亦將電源用引線111、信號用引線112、及信號用引線113之外引線與支持部12之間之連接部切斷。 The trimming (T/F) step includes a step of cutting the connection portion between the plurality of leads 11 and the support portion 12 to cut out the semiconductor device 10 (trimming step), and fitting the outer leads of the plurality of leads 11 to the semiconductor The step of deforming the final shape of the device 10 (forming step). In the trimming step, the power supply lead 111, the signal lead 112, and the connecting portion between the lead wire of the signal lead 113 and the support portion 12 are also cut.
藉由以上步驟，可製造出半導體裝置10。如圖5至圖9所示，半導體裝置10具備複數個引線11、搭載於複數個引線11上且具有複數個電極墊21之半導體晶片2、將複數個電極墊21與複數個引線11連接之複數個接合線3、及將複數個引線11之內引線、半導體晶片2、及複數個接合線3密封之密封樹脂層4。再者，半導體晶片2亦可搭載於與圖7所示之半導體晶片2之搭載面為相反側之複數個引線11之面。又，於X-Y平面內，自電源用引線114之接合墊部114a至密封樹脂層4之端部為止之最短距離，可短於自接合墊部114a至密封樹脂層4之中心為止之距離。進而，圖5至圖9所示之半導體裝置10為TSOP，但亦可具有其他封裝結構。 Through the above steps, the semiconductor device 10 can be manufactured. As shown in FIGS. 5 to 9, the semiconductor device 10 includes a plurality of leads 11, a semiconductor wafer 2 mounted on a plurality of leads 11 and having a plurality of electrode pads 21, and a plurality of electrode pads 21 connected to a plurality of leads 11. A plurality of bonding wires 3, and a sealing resin layer 4 for sealing the inner leads of the plurality of leads 11, the semiconductor wafer 2, and the plurality of bonding wires 3. Further, the semiconductor wafer 2 may be mounted on the surface of the plurality of leads 11 on the side opposite to the mounting surface of the semiconductor wafer 2 shown in FIG. Further, in the X-Y plane, the shortest distance from the bonding pad portion 114a of the power supply lead 114 to the end portion of the sealing resin layer 4 can be shorter than the distance from the bonding pad portion 114a to the center of the sealing resin layer 4. Further, the semiconductor device 10 shown in FIGS. 5 to 9 is TSOP, but may have other package structures.
上述實施形態係作為例子而提出者，並非意圖限定發明之範圍。該等新穎之實施形態可以其他各種方式實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變形包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明與其均等之範圍內。 The above embodiments are presented as examples and are not intended to limit the scope of the invention. The various embodiments of the invention may be embodied in a variety of other forms, and various omissions, substitutions and changes may be made without departing from the spirit of the invention. The invention or its modifications are intended to be included within the scope and spirit of the invention and are included in the scope of the invention described herein.
1‧‧‧引線架 1‧‧‧ lead frame
11‧‧‧引線 11‧‧‧ lead
12‧‧‧支持部 12‧‧‧Support Department
13‧‧‧絕緣性帶 13‧‧‧Insulation tape
100‧‧‧區域 100‧‧‧ area
X‧‧‧軸 X‧‧‧ axis
Y‧‧‧軸 Y‧‧‧ axis
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| JP2015181478A JP6352876B2 (en) | 2015-09-15 | 2015-09-15 | Manufacturing method of semiconductor device |
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| TW201711115A true TW201711115A (en) | 2017-03-16 |
| TWI581349B TWI581349B (en) | 2017-05-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4916519A (en) * | 1989-05-30 | 1990-04-10 | International Business Machines Corporation | Semiconductor package |
| JPH0750764B2 (en) * | 1989-07-05 | 1995-05-31 | 株式会社三井ハイテック | Lead frame manufacturing method |
| JP2504232B2 (en) * | 1989-11-09 | 1996-06-05 | 日本電気株式会社 | Lead frame for semiconductor device |
| JP3119544B2 (en) * | 1992-07-08 | 2000-12-25 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor integrated circuit device |
| JPH0714976A (en) * | 1993-06-24 | 1995-01-17 | Shinko Electric Ind Co Ltd | Lead frame and semiconductor device |
| JPH07307428A (en) * | 1994-05-11 | 1995-11-21 | Toppan Printing Co Ltd | Lead frame |
| JPH08148634A (en) * | 1994-11-21 | 1996-06-07 | Hitachi Ltd | Lead frame, semiconductor device using it, and manufacture thereof |
| JPH08162585A (en) * | 1994-12-06 | 1996-06-21 | Hitachi Constr Mach Co Ltd | Lead frame processing method, lead frame and semiconductor device |
| JPH1140721A (en) * | 1997-07-15 | 1999-02-12 | Matsushita Electron Corp | Lead frame, semiconductor device and manufacture thereof |
| JP3937265B2 (en) * | 1997-09-29 | 2007-06-27 | エルピーダメモリ株式会社 | Semiconductor device |
| US6515359B1 (en) * | 1998-01-20 | 2003-02-04 | Micron Technology, Inc. | Lead frame decoupling capacitor semiconductor device packages including the same and methods |
| JPH11340405A (en) * | 1998-05-22 | 1999-12-10 | Fujitsu Quantum Devices Kk | Lead frame, semiconductor device and manufacture thereof |
| KR100369393B1 (en) * | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | Lead frame and semiconductor package using it and its manufacturing method |
| US6812580B1 (en) * | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
| JP2008294278A (en) * | 2007-05-25 | 2008-12-04 | Fujitsu Microelectronics Ltd | Semiconductor device, lead frame and packaging structure of semiconductor device |
| JP4489100B2 (en) * | 2007-06-18 | 2010-06-23 | 株式会社東芝 | Semiconductor package |
| TW201019450A (en) * | 2008-11-04 | 2010-05-16 | Powertech Technology Inc | Inner-connecting structure of lead frame and its connecting method |
| US7875963B1 (en) * | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
| JP2013016666A (en) * | 2011-07-05 | 2013-01-24 | Renesas Electronics Corp | Semiconductor device |
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2015
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| CN110034086B (en) | 2024-03-01 |
| TWI581349B (en) | 2017-05-01 |
| CN110034086A (en) | 2019-07-19 |
| JP6352876B2 (en) | 2018-07-04 |
| CN106531709A (en) | 2017-03-22 |
| JP2017059613A (en) | 2017-03-23 |
| CN106531709B (en) | 2019-04-05 |
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