TW201709406A - Package structure and method of manufacture thereof - Google Patents
Package structure and method of manufacture thereof Download PDFInfo
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- TW201709406A TW201709406A TW104126960A TW104126960A TW201709406A TW 201709406 A TW201709406 A TW 201709406A TW 104126960 A TW104126960 A TW 104126960A TW 104126960 A TW104126960 A TW 104126960A TW 201709406 A TW201709406 A TW 201709406A
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- layer
- package structure
- insulating layer
- electronic component
- stop layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000463 material Substances 0.000 claims description 10
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 2
- 239000003566 sealing material Substances 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 134
- 239000004065 semiconductor Substances 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種封裝結構及其製法，特別是指一種具線路層之封裝結構及其製法。 The present invention relates to a package structure and a method of manufacturing the same, and more particularly to a package structure having a circuit layer and a method of fabricating the same.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging，簡稱WLP)的技術。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, Wafer Level Packaging (WLP) technology has been developed.
如第1A至1D圖，係為習知晶圓級半導體封裝件1之製法之剖面示意圖。 1A to 1D are schematic cross-sectional views showing the fabrication of a conventional wafer level semiconductor package 1.
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。 As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a黏著於該熱化離型膠層11上。 Next, a plurality of semiconductor elements 12 are disposed on the thermal release layer 11, the semiconductor elements 12 having opposite active and non-active surfaces 12a, each of which has a plurality of electrode pads 120, and Each of the active surfaces 12a is adhered to the thermal release adhesive layer 11.
如第1B圖所示，形成一封裝膠體13於該熱化離型膠層11上，以包覆該半導體元件12。 As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release layer 11 to coat the semiconductor element 12.
如第1C圖所示，進行烘烤製程以硬化該封裝膠體13，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之作用面12a。 As shown in FIG. 1C, the baking process is performed to harden the encapsulant 13, and at the same time, the thermal release adhesive layer 11 loses viscosity after being heated, so the thermal release adhesive layer 11 can be removed together. With the carrier 10, the active surface 12a of the semiconductor element 12 is exposed.
如第1D圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，係形成一線路重佈結構14於該封裝膠體13與該半導體元件12之作用面12a上，令該線路重佈結構14電性連接該半導體元件12之電極墊120。接著，形成一絕緣保護層15於該線路重佈結構14上，且該絕緣保護層15外露該線路重佈結構14之部分表面，以供結合如銲球之導電元件16。最後進行切單製程。 As shown in FIG. 1D, a redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulating body 13 and the active surface 12a of the semiconductor component 12, so that the line is redistributed. The structure 14 is electrically connected to the electrode pad 120 of the semiconductor component 12. Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls. Finally, the singulation process is performed.
惟，習知半導體封裝件1中，於切單過程中或切單後受到外力碰撞時，容易發生碎裂(crack)之情況，導致該線路重佈結構14損毀，進而造成產品良率過低及產品可靠度不佳等問題。 However, in the conventional semiconductor package 1, when it is subjected to an external force collision during the singulation process or after singulation, cracks are likely to occur, resulting in damage of the circuit redistribution structure 14, thereby causing the product yield to be too low. And problems such as poor product reliability.
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係提供一種封裝結構，係包括：絕緣層，係具有相對之第一側與第二側；至少一電子元件，係嵌埋於該絕緣層中；線路層，係設於該絕緣層之第一側上並電性連接該電子元件；以及止擋層，係設於該絕緣層之第一側上並圍繞該線路層。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package structure comprising: an insulating layer having opposite first and second sides; at least one electronic component embedded in the insulating layer; The layer is disposed on the first side of the insulating layer and electrically connected to the electronic component; and the stopper layer is disposed on the first side of the insulating layer and surrounds the circuit layer.
本發明亦提供一種封裝結構之製法，係包括：提供一 具有相對之第一側與第二側之絕緣層，且該絕緣層中嵌埋有至少一電子元件；以及形成線路層與止擋層於該絕緣層之第一側上，其中，該線路層電性連接該電子元件，且該止擋層係圍繞該線路層。 The invention also provides a method for manufacturing a package structure, comprising: providing a An insulating layer having a first side and a second side opposite to each other, wherein at least one electronic component is embedded in the insulating layer; and a circuit layer and a stop layer are formed on the first side of the insulating layer, wherein the circuit layer The electronic component is electrically connected, and the stop layer surrounds the circuit layer.
前述之製法中，該絕緣層係以鑄模成型或壓合方式製作。 In the above method, the insulating layer is formed by molding or pressing.
前述之封裝結構及其製法中，形成該絕緣層之材質係為模封材、乾膜、聚對二唑苯、聚醯亞胺、預浸材、Ajinomoto build-up film(ABF)、環氧樹脂或光阻材。 In the foregoing package structure and method of manufacturing the same, the material for forming the insulating layer is a mold material, a dry film, a poly-p-oxazobenzene, a polyimide, a prepreg, an Ajinomoto build-up film (ABF), an epoxy. Resin or photoresist.
前述之封裝結構及其製法中，該電子元件係外露於該絕緣層之第二側。 In the foregoing package structure and method of manufacturing the same, the electronic component is exposed on the second side of the insulating layer.
前述之封裝結構及其製法中，該止擋層係為導體。 In the foregoing package structure and method of manufacturing the same, the stop layer is a conductor.
前述之封裝結構及其製法中，該止擋層係為至少一環體，例如，該環體具有擴大部。 In the above package structure and method of manufacturing the same, the stop layer is at least one ring body, for example, the ring body has an enlarged portion.
前述之封裝結構及其製法中，該止擋層具有缺口。 In the foregoing package structure and method of manufacturing the same, the stop layer has a notch.
前述之封裝結構及其製法中，該止擋層之位置係投影於該電子元件外或該電子元件內。前述之封裝結構及其製法中，復包括形成複數導電元件於該線路層上。 In the foregoing package structure and method of manufacturing the same, the position of the stop layer is projected outside the electronic component or within the electronic component. In the foregoing package structure and method of manufacturing the same, the complex includes forming a plurality of conductive elements on the circuit layer.
前述之封裝結構及其製法中，復包括形成介電層於該絕緣層之第一側上，以令該線路層與該止擋層設於該介電層上。 In the foregoing package structure and method of fabricating the same, the dielectric layer is formed on the first side of the insulating layer such that the circuit layer and the stop layer are disposed on the dielectric layer.
由上可知，本發明之封裝結構及其製法，係於該線路層上形成該止擋層，以於切單過程中或切單後受到外力碰撞時，藉由該止擋層阻擋外力向內延伸至該線路層，故相 較於習知技術，本發明之製法能避免該線路層損毀，而能提升產品良率及產品之可靠度。 It can be seen from the above that the package structure of the present invention and the method for manufacturing the same are formed on the circuit layer to block the external force by the stopper layer during the singulation process or when the external force is collided after the singulation Extend to the circuit layer, so the phase Compared with the prior art, the method of the invention can avoid the damage of the circuit layer, and can improve the product yield and the reliability of the product.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10,20‧‧‧承載件 10,20‧‧‧Carrier
11‧‧‧熱化離型膠層 11‧‧‧heating release layer
12‧‧‧半導體元件 12‧‧‧Semiconductor components
12a,22a‧‧‧作用面 12a, 22a‧‧‧ action surface
12b,22b‧‧‧非作用面 12b, 22b‧‧‧ non-active surface
120,220‧‧‧電極墊 120,220‧‧‧electrode pads
13‧‧‧封裝膠體 13‧‧‧Package colloid
14‧‧‧線路重佈結構 14‧‧‧Line redistribution structure
15,253‧‧‧絕緣保護層 15,253‧‧‧Insulation protective layer
16,26‧‧‧導電元件 16,26‧‧‧ conductive elements
2,2’‧‧‧封裝結構 2,2’‧‧‧Package structure
200‧‧‧離形層 200‧‧‧ release layer
201‧‧‧結合層 201‧‧‧ bonding layer
21‧‧‧止擋層 21‧‧‧stop layer
210‧‧‧環體 210‧‧‧Act
22‧‧‧電子元件 22‧‧‧Electronic components
23‧‧‧絕緣層 23‧‧‧Insulation
23a‧‧‧第一側 23a‧‧‧ first side
23b‧‧‧第二側 23b‧‧‧ second side
24‧‧‧線路構造 24‧‧‧Line construction
240,250‧‧‧介電層 240, 250‧‧‧ dielectric layer
241,251,251’‧‧‧線路層 241,251,251'‧‧‧ circuit layer
25‧‧‧增層構造 25‧‧‧Building structure
251”‧‧‧凸塊底下金屬層 251"‧‧‧ Metal layer under the bump
252‧‧‧導電盲孔 252‧‧‧ Conductive blind holes
26‧‧‧導電元件 26‧‧‧Conductive components
3‧‧‧電子裝置 3‧‧‧Electronic devices
310,312‧‧‧擴大部 310,312‧‧‧Expanding Department
311‧‧‧缺口 311‧‧‧ gap
S‧‧‧切割路徑 S‧‧‧ cutting path
第1A至1D圖係為習知半導體封裝件之製法之剖面示意圖；以及第2A至2D圖係為本發明之封裝結構之製法之剖面示意圖；其中，第2B’圖係為第2B圖之局部上視圖；第2E圖係為第2D圖之另一實施例之剖面示意圖；以及第3A及3B圖係為第2B’圖之其它實施例之上視示意圖。 1A to 1D are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2D are schematic cross-sectional views showing a method of fabricating the package structure of the present invention; wherein the 2B' diagram is a part of the 2B diagram FIG. 2E is a schematic cross-sectional view of another embodiment of FIG. 2D; and FIGS. 3A and 3B are top views of other embodiments of FIG. 2B'.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關 係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Relatively Changes or adjustments to the system are considered to be within the scope of the invention, without departing from the scope of the invention.
第2A至2D圖係為本發明之封裝結構2之製法的剖面示意圖。 2A to 2D are schematic cross-sectional views showing the manufacturing method of the package structure 2 of the present invention.
如第2A圖所示，提供一具有相對之第一側23a與第二側23b之絕緣層23，且該絕緣層23中嵌埋有至少一電子元件22。 As shown in FIG. 2A, an insulating layer 23 having a first side 23a and a second side 23b is provided, and at least one electronic component 22 is embedded in the insulating layer 23.
於本實施例中，形成該絕緣層23之材質係為模封材(molding compound)、乾膜(dry film)、聚對二唑苯(Poly-p-Polybenzoxazole，簡稱PBO)、聚醯亞胺(polyimide，簡稱PI)、預浸材(prepreg，簡稱PP)、Ajinomoto build-up film(ABF)、環氧樹脂(expoxy)或光阻材。 In the present embodiment, the material forming the insulating layer 23 is a molding compound, a dry film, a poly-p-Polybenzoxazole (PBO), and a polyimine. (polyimide, referred to as PI), prepreg (PP), Ajinomoto build-up film (ABF), epoxy (expoxy) or photoresist.
再者，該電子元件22係為主動元件、被動元件或其組合者，其中，該主動元件係為半導體晶片，而該被動元件係為電阻、電容及電感。例如，該電子元件22係為半導體晶片，如電源管理晶片、動態隨機存取記憶體、應用處理器等，其具有相對之作用面22a與非作用面22b，該作用面22a具有複數電極墊220，且該電子元件22之非作用面22b齊平該絕緣層23之第二側23b。可理解地，於其它實施例中，該絕緣層23之第二側23b可覆蓋該電子元件22之非作用面22b。 Furthermore, the electronic component 22 is an active component, a passive component or a combination thereof, wherein the active component is a semiconductor wafer, and the passive component is a resistor, a capacitor and an inductor. For example, the electronic component 22 is a semiconductor wafer, such as a power management chip, a dynamic random access memory, an application processor, etc., having an opposite active surface 22a and an inactive surface 22b, the active surface 22a having a plurality of electrode pads 220 And the non-active surface 22b of the electronic component 22 is flush with the second side 23b of the insulating layer 23. It can be understood that in other embodiments, the second side 23b of the insulating layer 23 can cover the non-active surface 22b of the electronic component 22.
又，該絕緣層23與該電子元件22之製作方式繁多，例如，該絕緣層23係以鑄模成型(molding)或壓合 (Laminate)方式形成者，但並不限於此方式。具體地，可先將複數電子元件22設於支撐件(圖略)上，再形成用以包覆該些電子元件22之絕緣層23，之後將該絕緣層23之第二側23b結合於一承載件20上，才移除該支撐件。或者，先將複數電子元件22以其非作用面22b設於該承載件20上，再形成用以包覆該些電子元件22之絕緣層23。 Moreover, the insulating layer 23 and the electronic component 22 are manufactured in various ways. For example, the insulating layer 23 is molded or pressed. The (Laminate) mode is formed by, but not limited to, this method. Specifically, the plurality of electronic components 22 are first disposed on the support member (not shown), and then the insulating layer 23 for covering the electronic components 22 is formed, and then the second side 23b of the insulating layer 23 is bonded to the first layer 23b. The support member 20 is removed from the support member. Alternatively, the plurality of electronic components 22 are first disposed on the carrier 20 with their non-active surfaces 22b, and an insulating layer 23 for covering the electronic components 22 is formed.
另外，該承載件20上可依序形成有一離形層200與一結合層201，使該絕緣層23之第二側23b與該電子元件22之非作用面22b結合於該結合層201上。具體地，該離形層200係例如熱化離型膠(thermal release tape)、光感離形膜或機械離形構造，且該結合層201係如黏著材。 In addition, a release layer 200 and a bonding layer 201 are sequentially formed on the carrier 20 such that the second side 23b of the insulating layer 23 and the non-active surface 22b of the electronic component 22 are bonded to the bonding layer 201. Specifically, the release layer 200 is, for example, a thermal release tape, a photo-sensitive release film, or a mechanical release structure, and the bonding layer 201 is an adhesive material.
如第2B圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一線路構造24於該絕緣層23之第一側23a上，且該線路構造24係電性連接該電子元件22，並形成一止擋層21於該線路構造24上。 As shown in FIG. 2B, a redistribution layer (RDL) process is performed to form a line structure 24 on the first side 23a of the insulating layer 23, and the line structure 24 is electrically connected to the electron Element 22 and a stop layer 21 is formed on the line configuration 24.
於本實施例中，該線路構造24係包含一介電層240及設於該介電層240上之一線路層241，且該線路層241電性連接該電子元件22之電極墊220。 In the present embodiment, the circuit structure 24 includes a dielectric layer 240 and a circuit layer 241 disposed on the dielectric layer 240. The circuit layer 241 is electrically connected to the electrode pads 220 of the electronic component 22.
再者，該止擋層21係設於該介電層240上，且該止擋層21係為導體，使其可與該線路層241一同製作；或者，該止擋層21與該線路層241不同製程製作。因此，該止擋層21之材質與該線路層241之材質可相同或不相同。 Furthermore, the stop layer 21 is disposed on the dielectric layer 240, and the stop layer 21 is a conductor, which can be fabricated together with the circuit layer 241; or the stop layer 21 and the circuit layer 241 different process production. Therefore, the material of the stopper layer 21 and the material of the circuit layer 241 may be the same or different.
又，該止擋層21係為至少一環體210，如第2B’圖所示之兩環體210，以圍繞該線路層241，且第2B’圖所示之 虛線係用以表示該電子元件22之平面輪廓。 Moreover, the stop layer 21 is at least one ring body 210, such as the two ring body 210 shown in FIG. 2B', to surround the circuit layer 241, and is shown in FIG. 2B'. The dashed line is used to indicate the planar outline of the electronic component 22.
另外，應可理解地，該環體210之輪廓與數量不限於圖中所示之矩形，亦可為其它數量或其它形狀之輪廓。 In addition, it should be understood that the outline and number of the ring body 210 are not limited to the rectangular shape shown in the drawing, and may be other numbers or contours of other shapes.
如第2C圖所示，進行線路重佈層(RDL)製程，以形成一增層構造25於該線路構造24與該止擋層21上，且形成複數導電元件26於該增層構造25上。 As shown in FIG. 2C, a line redistribution (RDL) process is performed to form a buildup structure 25 on the line structure 24 and the stop layer 21, and a plurality of conductive elements 26 are formed on the buildup structure 25. .
於本實施例中，該增層構造25具有一絕緣保護層253、複數介電層250、形成於該些介電層250上之線路層251,251’、及設於該些介電層250中的複數導電盲孔252，且藉由該些導電盲孔252電性連接該些線路層241,251，而該絕緣保護層253係形成於最外側之介電層250與線路層251’上，以令該最外側之部分線路層251’外露於該絕緣保護層253，俾供結合該些導電元件26於該線路層251’上。 In this embodiment, the build-up structure 25 has an insulating protective layer 253, a plurality of dielectric layers 250, circuit layers 251, 251' formed on the dielectric layers 250, and the dielectric layers 250. The plurality of conductive vias 252 are electrically connected to the circuit layers 241, 251 by the conductive vias 252, and the insulating protective layer 253 is formed on the outermost dielectric layer 250 and the wiring layer 251'. The outermost portion of the wiring layer 251' is exposed to the insulating protective layer 253 for bonding the conductive elements 26 to the wiring layer 251'.
再者，該導電元件26係為銲球、金屬凸塊或金屬針等，且於形成該導電元件26前，可先於該線路層251’上形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)251”，以利於結合該導電元件26。 Furthermore, the conductive element 26 is a solder ball, a metal bump or a metal pin, etc., and before the formation of the conductive element 26, an under bump metal layer (Under Bump Metallurgy) may be formed on the circuit layer 251'. UBM) 251" to facilitate bonding of the conductive element 26.
如第2D圖所示，移除該承載板20、離形層200及該結合層201，使該電子元件22之非作用面22b係外露於該絕緣層23之第二側23b。之後，沿如第2C圖所示之切割路徑S進行切單製程，以完成該封裝結構2之製作。 As shown in FIG. 2D, the carrier 20, the release layer 200, and the bonding layer 201 are removed, and the non-active surface 22b of the electronic component 22 is exposed on the second side 23b of the insulating layer 23. Thereafter, a singulation process is performed along the dicing path S as shown in FIG. 2C to complete the fabrication of the package structure 2.
於本實施例中，可依需求佈設該止擋層21。例如，於該增層構造25之該些介電層250上，亦可形成該止擋層21於該線路層251,251’之外圍，如第2E圖所示之封裝結 構2’。 In this embodiment, the stop layer 21 can be disposed according to requirements. For example, on the dielectric layers 250 of the buildup structure 25, the stop layer 21 may be formed on the periphery of the circuit layers 251, 251', as shown in FIG. 2E. 2'.
本發明之製法係於形成該線路層241時，於該線路層241的周圍同時形成該止擋層21，故於切單過程中或切單後受到外力碰撞時，藉由該止擋層21阻擋外力向內延伸至該線路層241。因此，相較於習知技術，本發明之製法藉由該止擋層21之設計能避免該線路層241損毀，故能提升產品良率及產品之可靠度。 In the method of the present invention, when the circuit layer 241 is formed, the stopper layer 21 is simultaneously formed around the circuit layer 241, so that the stopper layer 21 is used when the external force is collided during the singulation or after singulation. The blocking external force extends inwardly to the wiring layer 241. Therefore, compared with the prior art, the method of the present invention can avoid the damage of the circuit layer 241 by the design of the stop layer 21, thereby improving the product yield and the reliability of the product.
再者，於扇出(fan out)之線路佈設中，該止擋層21之位置係投影於該電子元件22外，如第2B’圖所示；於扇入(fan in)之線路佈設中，該止擋層21之位置係投影於該電子元件22內，如第3A圖所示。 Furthermore, in the fan out line layout, the position of the stop layer 21 is projected outside the electronic component 22, as shown in FIG. 2B'; in the fan in line layout. The position of the stop layer 21 is projected into the electronic component 22 as shown in FIG. 3A.
又，如第3A圖所示，該些環體210之至少一角落處具有至少一擴大部310以阻擋較大外力向內延伸，且該些環體210之至少一邊緣具有缺口311，以於化學蝕刻製程時，蝕刻液可經由此缺口311順利向外排出，故可避免因蝕刻液殘留而過度蝕刻線路層241,251,251’或該環體210之問題。進一步地，如第3B圖所示，於受較大應力處的角落，可增設擴大部312，以強化該止擋層21。 In addition, as shown in FIG. 3A, at least one corner of the ring body 210 has at least one enlarged portion 310 to block a large external force to extend inward, and at least one edge of the ring body 210 has a notch 311. During the chemical etching process, the etching liquid can be smoothly discharged outward through the notch 311, so that the problem of over etching the wiring layer 241, 251, 251' or the ring body 210 due to the residual etching liquid can be avoided. Further, as shown in FIG. 3B, an enlarged portion 312 may be added to the corner where the stress is applied to strengthen the stopper layer 21.
另外，於後續製程中，可將該封裝結構2,2’藉由該些導電元件26結合至一如電路板之電子裝置3上，如第2E圖所示。 In addition, in the subsequent process, the package structures 2, 2' can be bonded to the electronic device 3 such as a circuit board by the conductive elements 26, as shown in FIG. 2E.
本發明提供一種封裝結構2,2’，係包括：一絕緣層23、至少一電子元件22、一止擋層21以及至少一線路層241,251,251’。 The present invention provides a package structure 2, 2' comprising: an insulating layer 23, at least one electronic component 22, a stop layer 21, and at least one wiring layer 241, 251, 251'.
所述之絕緣層23係具有相對之第一側23a與第二側23b，且形成該絕緣層23之材質係為模封材、乾膜、聚對二唑苯、聚醯亞胺、預浸材、Ajinomoto build-up film(ABF)、環氧樹脂或光阻材。 The insulating layer 23 has a first side 23a and a second side 23b opposite to each other, and the material forming the insulating layer 23 is a molding material, a dry film, a poly-p-oxazobenzene, a polyimine, and a pre-dip. Ajinomoto build-up film (ABF), epoxy or photoresist.
所述之電子元件22係嵌埋於該絕緣層23中。 The electronic component 22 is embedded in the insulating layer 23.
所述之線路層241,251,251’係設於該絕緣層23之第一側23a上並電性連接該電子元件22。 The circuit layer 241, 251, 251' is disposed on the first side 23a of the insulating layer 23 and electrically connected to the electronic component 22.
所述之止擋層21係設於該絕緣層23之第一側23a上並圍繞該線路層241,251,251’，且該止擋層係為導體。 The stop layer 21 is disposed on the first side 23a of the insulating layer 23 and surrounds the circuit layer 241, 251, 251', and the stop layer is a conductor.
於一實施例中，該電子元件22係外露於該絕緣層23之第二側23b。 In one embodiment, the electronic component 22 is exposed on the second side 23b of the insulating layer 23.
於一實施例中，該止擋層21係為至少一環體210，例如，該環體210具有至少一擴大部312。 In one embodiment, the stop layer 21 is at least one ring body 210. For example, the ring body 210 has at least one enlarged portion 312.
於一實施例中，該止擋層21之位置係投影於該電子元件22外或該電子元件22內。 In one embodiment, the position of the stop layer 21 is projected outside the electronic component 22 or within the electronic component 22.
於一實施例中，所述之封裝結構2,2’復包括至少一介電層240,250，係形成於該絕緣層23之第一側23a上，以令該線路層241,251,251’與該止擋層21設於該介電層240,250上。 In one embodiment, the package structure 2, 2' includes at least one dielectric layer 240, 250 formed on the first side 23a of the insulating layer 23 to make the circuit layer 241, 251, 251' and the stop layer 21 is disposed on the dielectric layers 240, 250.
於一實施例中，所述之封裝結構2,2’復包括形成於該線路層251’上之複數導電元件26。 In one embodiment, the package structure 2, 2' includes a plurality of conductive elements 26 formed on the circuit layer 251'.
綜上所述，本發明之封裝結構及其製法，主要藉由該止擋層之設計，以阻擋外力向內延伸至該線路層，故能避免該線路層損毀，以提升產品良率及產品之可靠度。 In summary, the package structure of the present invention and the method for manufacturing the same are mainly used to prevent the external layer from extending to the circuit layer by blocking the external force, so that the circuit layer can be prevented from being damaged, thereby improving product yield and product. Reliability.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝結構 2‧‧‧Package structure
21‧‧‧止擋層 21‧‧‧stop layer
22‧‧‧電子元件 22‧‧‧Electronic components
22a‧‧‧作用面 22a‧‧‧Action surface
22b‧‧‧非作用面 22b‧‧‧Non-active surface
220‧‧‧電極墊 220‧‧‧electrode pad
23‧‧‧絕緣層 23‧‧‧Insulation
23a‧‧‧第一側 23a‧‧‧ first side
23b‧‧‧第二側 23b‧‧‧ second side
24‧‧‧線路構造 24‧‧‧Line construction
240‧‧‧介電層 240‧‧‧ dielectric layer
241‧‧‧線路層 241‧‧‧Line layer
25‧‧‧增層構造 25‧‧‧Building structure
26‧‧‧導電元件 26‧‧‧Conductive components
Claims (21)
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| TW104126960A TWI557844B (en) | 2015-08-19 | 2015-08-19 | Package structure and method of manufacture thereof |
| CN201510540131.3A CN106469691B (en) | 2015-08-19 | 2015-08-28 | Package structure and method for fabricating the same |
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| JP2005129717A (en) * | 2003-10-23 | 2005-05-19 | Renesas Technology Corp | Semiconductor device |
| US8803290B2 (en) * | 2008-10-03 | 2014-08-12 | Qualcomm Incorporated | Double broken seal ring |
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| TW201408148A (en) * | 2012-08-06 | 2014-02-16 | Unimicron Technology Corp | Substrate structure having embedded electronic component and method of fabricating the same |
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| US9167710B2 (en) * | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
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| Publication number | Publication date |
|---|---|
| TWI557844B (en) | 2016-11-11 |
| CN106469691A (en) | 2017-03-01 |
| CN106469691B (en) | 2019-11-01 |
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