TW201709178A - Timing controller and display device comprising the same - Google Patents

Abstract

Provided are a timing controller capable of compensating for Mura defects of a display panel with high quality while reducing the size of a memory required for storing look-up table (LUT) data and a display device comprising the same. The timing controller includes a memory controller which reads compressed LUT data from an external memory, a decompressor which decompresses the compressed LUT data received from the memory controller to generate original LUT data before the compression, a line buffer which temporarily stores the original LUT data received from the decompressor, and an image signal processor which compensates for Mura defects of input image signal data by using the original LUT data stored in the line buffer.

Description

Timing controller and display device including the same

The present invention relates to a timing controller and a display device including the same.

The display device usually includes a display panel and a driving portion of the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The driving part of the display panel includes a timing controller, a gate driver and a source driver.

Typically the pixel comprises a plurality of transistors, a storage capacitor and an organic light emitting element. The difference in luminance between the pixels caused by the threshold voltage distribution of the transistor has a problem of generating a trace defect (MURA defect; hereinafter referred to as MURA defect). The panel that produces this MURA defect is called the MURA panel.

In this case, in order to compensate for the MURA defect, a look up table (LUT) may be utilized. However, recently, the resolution of the display panel becomes high, and as the number of bits used by the LUT increases, the size of the LUT also increases, thereby having a problem that a larger memory capacity is required to store the LUT. Further, in order to reduce the overall size of the LUT, when one LUT data is used for each specific unit pixel, there is a problem that the compensation quality of the trace defect is lowered.

Technical problems to be solved by the invention

The problem to be solved by the present invention is to provide a timing controller capable of reducing the memory size required for storing LUT data while compensating for MURA defects of the display panel with high quality.

Another object to be solved by the present invention is to provide a display device capable of reducing the size of a memory required to store LUT data while compensating for defects in the display panel MURA with high quality.

The subject matter to be solved by the present invention is not limited to the above-described problems, and other problems that have not yet been mentioned will be clearly understood from the following description by those skilled in the art.

Technical solution to solve the problem

An aspect of the timing controller of the present invention for solving the subject matter includes: a memory controller that reads compressed LUT data from an external memory; and decompresses the compression received from the memory controller LUT data, and a decompressor that generates raw LUT data before compression; a column buffer that temporarily stores the original LUT data received from the decompressor; and utilizes storage in the column buffer The original LUT data is an image signal processing unit that compensates for the MURA defect of the input image signal data.

In some embodiments of the present invention, the image signal processing section may include: reading the original LUT data from the column buffer, and receiving the image signal data from an external device to make the original a de-MURA controller that synchronizes the LUT data with the image signal data; and receives the synchronized original LUT data and the image signal from the de-MURA control unit, and utilizes the The original LUT data eliminates the MURA defect included in the image signal, thereby generating a de-MURA processing portion of the compensated image signal data.

In some embodiments of the invention, the MURA defect may include non-uniform contrast, luminance, or brightness values between image signals of adjacent pixels.

In some embodiments of the invention, the decompressor utilizes a lossless decompression algorithm to generate the raw LUT data from the compressed LUT data.

In some embodiments of the invention, the lossless decompression algorithm may comprise a CTW, LZ77, or LZW decompression algorithm.

In some embodiments of the invention, the image signal material includes material relating to N pixels (the N is a natural number), and the original LUT data may include compensation values corresponding to all of the N pixels.

In some embodiments of the present invention, the image signal material includes data about L*M pixels (the L and M are natural numbers), and the original LUT data may include corresponding to the L vertical lines. The compensation value, and the compensation value corresponding to the M horizontal lines.

In some embodiments of the present invention, the image signal material includes material relating to N pixels (the N is a natural number), and the original LUT data may be for every K unit pixels (the K is a ratio The N small natural number) contains a compensation value.

In some embodiments of the invention, the timing controller may be included in a semiconductor package that does not include the external memory.

The display device of the present invention for solving the above problems includes: a display panel; an external memory storing compressed LUT data; and a plurality of outputs of the display panel for a plurality of uniformity test input images An image, and using the captured plurality of output images as a basis, generating original LUT data corresponding to compensation data, and storing the compressed LUT data in the image of the external memory And compensating for MURA defects included in the image signal data input from the outside by using the compressed LUT data stored in the external memory, and providing the compensated image signal data to the display panel Timing controller.

In some embodiments of the present invention, the image capturing device may include: a controller that applies the plurality of input images for uniformity testing to the display panel; and extracts multiple outputs of the display panel a camera of an image; a processor that generates the original LUT data corresponding to the compensation material based on the plurality of captured image images; a compressor that compresses the original LUT data; and the compressed LUT The data is transmitted to the face of the external memory.

In some embodiments of the invention, the compressor utilizes a CTW, LZ77, or LZW compression algorithm to compress the original LUT data.

In some embodiments of the invention, the image capture device may be included within the timing controller.

In some embodiments of the invention, the image capture device may include a semiconductor package that is separate from the timing controller and the external memory.

In some embodiments of the present invention, the timing controller may include: a memory controller that reads compressed LUT data from the external memory; decompresses the compressed LUT data, and generates the original LUT before compression a decompressor of data; a column buffer temporarily storing the original LUT data received from the decompressor; and compensating for input image signal data using the original LUT data stored in the column buffer Image signal processing unit of MURA defect.

In some embodiments of the invention, the decompressor is capable of processing the original LUT data using an algorithm complementary to the compressor.

In some embodiments of the invention, the timing controller may include a semiconductor package that is separate from the external memory and the image capture device.

Another aspect of the display device of the present invention for solving the above problems includes: a plurality of pixels respectively disposed at intersections of a plurality of gate lines and a plurality of data lines; and a gate for driving the plurality of gate lines a driver for driving the plurality of data lines; storing external memory for compressing the LUT data; and controlling the gate driver and the source driver in response to image signal data and control signals input from the outside And compensating for the MURA defect included in the input image signal data by using the compressed LUT data stored in the external memory, and providing the compensated image signal data to the timing of the source driver Controller.

In some embodiments of the present invention, the timing controller may include: a memory controller that reads compressed LUT data from the external memory; decompresses the compressed LUT data, and generates the original LUT before compression a decompressor of data; a column buffer temporarily storing the original LUT data received from the decompressor; and compensating for input image signal data using the original LUT data stored in the column buffer Image signal processing unit of MURA defect.

In some embodiments of the present invention, the method may further include: capturing, for the plurality of uniformity test input images, a plurality of output images of the plurality of pixels, and extracting the plurality of output images On the basis of the original, the original LUT data corresponding to the compensation data is generated, and the compressed LUT data is stored in the image capturing device of the external memory.

In some embodiments of the present invention, the image capturing device may include: a control portion that applies the plurality of input images for uniformity testing to the plurality of pixels; and extracts each of the plurality of pixels a plurality of output image cameras; a processor that generates the original LUT data corresponding to the compensation material based on the plurality of captured output images; a compressor that compresses the original LUT data; and the compression The LUT data is transmitted to the face of the external memory.

In some embodiments of the invention, the timing controller may be included in a semiconductor package that is separate from the external memory.

Other specific matters of the present invention are included in the detailed description and the accompanying drawings.

Advantages, features, and methods of accomplishing the present invention will be apparent from the drawings and detailed description of the embodiments. However, the invention is not limited to the embodiments described herein, but may be embodied in other different forms. Instead, the present invention is disclosed herein to provide a more complete and complete understanding of the invention. The invention is defined by the scope of the claims. Throughout the specification, the same reference symbols denote the same elements.

The phrase "connected to" or "coupled to" to another element refers to the case where it is directly connected to another element, or the case where other elements are interposed in the middle of the connection. On the other hand, the phrase "directly connected to" or "directly coupled to" to another element refers to the case where no other elements are interposed in the middle. Throughout the specification, the same reference symbols denote the same elements. "and/or" is a combination of all involved projects and more than one.

For the purposes of illustrating various elements, elements and/or parts, it is apparent that the elements, elements and/or parts are not limited to these terms, although the terms 1st, 2nd, etc. are used. These terms are only used to distinguish one element, element, and/or part, and other elements, elements and/or parts. Therefore, the first element, the first element, or the first part mentioned in the present specification may be the second element, the second element, or the second part in the technical idea of the present invention.

The terminology used in the specification is for the purpose of illustrating the embodiments and is not intended to limit the invention. The singular expression includes a plural representation when the context does not specifically describe it. The elements, steps, acts, and/or elements referred to in the terms of "comprises" or "comprising", etc., used in the specification are not to exclude one or more other elements, steps, acts and/or components. The existence or addition.

In the absence of other definitions, all terms (including technical and scientific terms) used in the specification are the same as those understood by those of ordinary skill in the art to which the invention pertains. Also, terms defined on commonly used dictionaries are not to be construed as meanings of ideal or exaggerated form, unless otherwise defined.

Hereinafter, a timing controller and a display device including the same according to some embodiments of the present invention will be described with reference to FIGS. 1 through 10.

1 is a block diagram for explaining a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device 1000 according to a first embodiment of the present invention may employ any one of various display devices. For example, it may be an organic light emitting diode display (OLED), a liquid crystal display (LCD), a DP (plasma display panel) device, an ECD (Electrochromic Display), a DMD ( Digital Mirror Device), AMD (Actuated Mirror Device), GLV (Grating Light Value), PDP (Plasma Display Panel) or ELD (Electro Luminescent Display). Hereinafter, the display panel will be described by taking an organic light-emitting panel as an example.

Specifically, the display device 1000 includes a display panel 1100 and a display driving circuit 1201.

The display panel 1100 includes: a plurality of gate lines GL1 to GLj that transmit scan signals in a row direction; a plurality of data lines DL1 to DLk disposed in a direction intersecting with the gate lines and transmitting data signals in a column direction; and a gate A plurality of pixels PX arranged in a region where the polar lines GL1 to GLj and the data lines D1 to Dk intersect.

When the plurality of gate lines GL1 to GLj are sequentially selected, the gray scale voltage is applied to the pixels PX connected to the selected gate line through the plurality of data lines DL1 to DLk.

Each of the pixels PX may include a switching transistor Tsw, a driving transistor Tdrv, a storage capacitor Cst, and an organic light emitting diode. The gate line GL and the data line DL are connected to the gate and the source of the switching transistor Tsw, and the drain of the switching transistor Tsw and the power supply voltage VDD are respectively connected to the gate terminal and the source terminal of the driving transistor Tdrv, and the driving power is driven. The 汲 terminal of the crystal Tdrv is connected to the anode of the organic light emitting diode.

In this pixel structure, when the gate line GL is selected, the switching transistor Tsw is turned on, and the supplied gray scale voltage is applied to the gate terminal of the driving transistor Tdrv through the data line DL, according to the driving power supply voltage VDD and gray. The voltage difference of the step voltage, the driving current Idrv flows through the organic light emitting diode to emit light, thereby completing the display operation.

The display driving circuit 1201 may include a timing controller 100, a source driver 200, a gate driver 300, a voltage generator 400, a first interface circuit 500, a second interface circuit 340, and an external memory 190.

The timing controller 100 is a control signal CNT1 required to receive the first image signal data RGB and the first command CMD1 from the outside, for example, the system host on which the display device 1000 is mounted, and to provide the source driver 200 and the gate driver 300 with an operation. , CNT2 and the second image signal data RGB'.

Specifically, the timing controller 100 can control the gate driver 300 and the source driver 200 in response to image signal data and control signals input from the outside, and utilize the compression stored in the external memory 190. The LUT data compensates the MURA defect included in the input image signal data, and supplies the compensated image signal data to the source driver 200.

At this time, the timing controller 100 may include a memory controller 110, a decompressor 120, a column buffer 130, and an image signal processing unit 140. The components of the specific timing controller 100 and the operations thereof will be described later with reference to Fig. 2 .

The external memory 190 can function as a motion memory required for the timing controller 100 to operate. In some embodiments of the invention, external memory 190 may be external to timing controller 100 as shown. Specifically, the external memory 190 can be packaged in an individual PoP (Package on Package) form different from the timing controller 100. However, the invention is not limited thereto.

The source driver 200 converts the digital data applied from the timing controller 100, that is, the second image signal data RGB' into gray scale voltages, and outputs them to the data lines DL1 to DLk of the panel 1100. The gate driver 300 sequentially scans the gate lines GL1 GL GLj of the panel 1100. The gate driver 300 applies a gate-on voltage Von to the selected gate line, thereby activating the selected gate line, and the source driver 200 outputs a corresponding gray-scale voltage to the pixel connected to the startup gate line. Thus, the panel 1100 is in units of horizontal lines, that is, images can be displayed line by line.

The voltage generator 400 receives the externally applied power supply voltage (VCI), and generates voltages AVDD, Von, and Voff required for the source driver 200 and the gate driver 300.

The first interface circuit 500 is for communicating with a host (eg, an application processor). The first interface circuit 500 receives the first image signal data RGB and the first command CMD1 applied in parallel or in series by the host, and supplies the same to the timing controller 100. The first image signal data RGB and the first command CMD1 can be transmitted by the system host of the reprint display device 1000. The first interface circuit 500 can receive the first image signal data RGB and the first command CMD1 in accordance with an interface mode of the host transfer method. For example, the interface mode used in the first interface circuit 500 may be one of an RGB interface, a CPU interface, a PSI (Service provider interface), an MDDI (Mobile display digital interface), and an MIPI (Mobile industry processor interface).

The second interface circuit 340 is for communicating with another display driving circuit (that is, a second display driving circuit (not shown). The second interface circuit 340 can supply the first synchronization signal SSYNC1 generated by the timing controller 100 to the second display. a drive circuit (not shown). The first synchronization signal SSYNC1 is a signal generated in response to the end signal EXE. The second interface circuit 340 may be a different interface than the first interface circuit 500. For example, the second interface circuit 340 may be SPI (Serial Peripheral Interface), I2C (Inter Integrated Circuit), etc., but is not limited thereto.

FIG. 2 is a block diagram for explaining the timing controller shown in FIG. 1. Fig. 3 is a block diagram showing an embodiment of the image signal processing unit of Fig. 2.

Referring to FIG. 2, a timing controller (TCON) 100 according to an embodiment of the present invention may include: a memory controller 110, a decompressor 120, and a line buffer 130. Image Signal Processor 140.

The memory controller 110 can be connected to the external memory 190.

Specifically, the memory controller 110 is configured to access the external memory 190. For example, the memory controller 110 is configured to control read, write, erase, and background actions of the external memory 190. The memory controller 110 is configured to provide an interface between the external memory 190 and the timing controller 100. The memory controller 110 is configured to drive firmware that controls the external memory 190. Thus, the memory controller 110 can read the compressed LUT data from the external memory 190. Next, the memory controller 110 can transfer the read compressed LUT data to the decompressor 120.

The decompressor 120 can decompress the compressed LUT data received from the memory controller 110 to generate raw LUT data before compression. The raw LUT data may include data for compensating for MURA defects of the display panel 1100. The MURA defect may include a non-uniformity contrast, luminance, or brightness value between image signals of adjacent pixels.

Therefore, when the MURA defect is generated on the display panel 1100, a significant contrast, illuminance, or luminance value difference occurs between the first pixel and the second pixel adjacent to the first pixel. Such MURA defects may include line MURA (line MURA), black spot MURA, white spot MURA, black region MURA, white region MURA, ring MURA (ring MURA) and so on.

The decompressor 120 utilizes a lossless decompression algorithm to generate raw LUT data from the compressed LUT data. At this time, the lossless decompression algorithm may include a CTW, LZ77, or LZW decompression algorithm. The lossless decompression algorithm is a well-known technique, and a detailed description thereof will be omitted. Next, decompressor 120 can transfer the original LUT data to column buffer 130.

The column buffer 130 may temporarily store the original LUT material received from the decompressor 120. Since the size of the original LUT data is relatively large in the column buffer 130, in the decompressed compressed LUT data, in order to cause the image signal processing unit 150 to operate, the original LUT data can be temporarily stored. Thereby, the image signal processing section 150 can continuously receive the original LUT material. Moreover, the column buffer 130 can buffer the image signal processing unit 150 and the decompressor 120 in order to minimize the time delay required to decompress the compressed LUT data at the decompressor 120. However, the present invention is not limited thereto, and the column buffer 130 may be omitted when the decompressor 120 has a high data processing speed.

Referring to FIGS. 2 and 3, the image signal processing unit 150 can compensate the MURA defect of the input first image signal data RGB by using the original LUT data stored in the column buffer 130, resulting in the second Image signal data RGB'.

Specifically, the image signal processing unit 150 may include a de-MURA controller 152 (De-MURA controller) and a de-MURA processing unit 154 (De-MURA core).

The MURA control unit 152 reads the original LUT data from the column buffer 130, and after receiving the first image signal data RGB from the external device, the original LUT data and the image signal can be synchronized. The de-MURA control unit 152 can transfer the aligned LUT data and the image signal to the de-MURA processing unit 154.

The de-MURA processing unit 154 receives the synchronized original UUT data from the de-MURA control unit 152, and uses the original LUT data to eliminate the MURA defect included in the image signal. Thereby, the compensated second image signal data RGB' can be generated.

Specifically, the de-MURA processing unit 154 uses the original LUT data to change the first image signal data RGB into the second image signal data RGB' that compensates for the MURA defect. At this time, the MURA processing unit 154 compensates the first image signal data RGB into the second image signal data RGB'. For example, the MURA correction algorithm (MURA) such as a brute-force algorithm can be used. Correction algorithm). As a result, the MURA panel (MURA panel) that generates the MURA defect can be the normal operation display panel 1100. However, the raw LUT data used to initiate the MURA correction algorithm would require a relatively large memory capacity, thereby creating the burden of having a relatively large capacity memory device. Therefore, in the present invention, the compressed LUT data having a small memory capacity can be stored in the external memory 190 by compressing the original LUT data by a compression algorithm. In addition, the external memory 190 is separated in the memory controller 110, whereby the size and manufacturing cost of the memory controller 110 can be reduced.

In an embodiment of the present invention, the display device 1000 includes N (the N is a natural number) pixels, and the first image signal material RGB may have data on N pixels. Moreover, the original LUT data may include compensation values corresponding to all of the N pixels. That is, the original LUT data may have MURA defect compensation values for all of the individual pixels. In this case, the compensation processing quality for the MURA defect is high, but the memory capacity for storing the original LUT data is increased.

In another embodiment of the present invention, the display device 1000 includes N (the N is a natural number) pixels, and the first image signal material RGB may have data on N pixels. Moreover, the original LUT data may contain a compensation value for every K unit pixels (the K is a natural number smaller than the N). That is, the original LUT material may have a MURA defect compensation value for each unit pixel. In this case, the compensation processing quality for the MURA defect is slightly lower, but the memory capacity for storing the original LUT data is slightly reduced.

In still another embodiment of the present invention, the display device 1000 includes L*M (the L and M are natural numbers) pixels, and the first image signal material RGB may have data on L*M pixels. Moreover, the original LUT data may include compensation values corresponding to the L vertical lines, and compensation values corresponding to the M horizontal lines. That is, the original LUT data may have MURA defect compensation values corresponding to the vertical lines and horizontal lines of the display panel 1100, respectively. In this case, the compensation processing quality for the MURA defect is low, but the memory capacity for storing the original LUT data is significantly reduced.

In this way, the power to compensate for MURA defects, you can use LUT (Look Up Table). However, recently, the resolution of the display panel has become high, and as the number of bits used by the LUT increases, the size of the LUT also increases, and thus, a larger memory capacity is required in order to store the LUT. Moreover, in order to reduce the overall size of the LUT, the use of one LUT data per specific unit pixel reduces the compensation quality of the MURA defect. In order to solve such a problem, the display device 1000 according to an embodiment of the present invention compresses the original LUT data and stores it in the external memory 190, and uses a small memory capacity to perform high-quality compensation processing on the display panel including the MURA defect. .

In addition, the external memory 190 is separated in the memory controller 110, whereby the size and manufacturing cost of the memory controller 110 can be reduced.

As described above, considering the display device and various conditional items, some original LUT data for compensating for MURA defects can be selected. However, the invention is not limited thereto.

FIG. 4 is a block diagram for explaining a display device according to another embodiment of the present invention. FIG. 5 is a block diagram for explaining a display device according to still another embodiment of the present invention. For the sake of convenience of explanation, the same matters as those of the previously described embodiments will be omitted, and the description will be omitted.

Referring to FIGS. 4 and 5, display devices 1001, 1002 according to some embodiments of the present invention include a display panel 1100, a timing controller 100, and an external memory 190. Actually, the display devices 1001 and 1002 can perform the same operations as the display device 1000 described with reference to FIG. 1 .

The display device 1001, 1002 according to some embodiments of the present invention may further include an image capturing device 160.

The image capturing device 160 can capture an image output on the display panel 1100. Specifically, a contrast, a luminance, or a brightness value of each pixel included in the display panel 1100 can be captured. Thereby, it can be judged whether or not there is a MURA defect on the display panel 1100. When there is a MURA defect on the display panel 1100, the image capture device 160 can calculate a compensation value for the MURA defect and then generate raw LUT data containing the compensation value.

Specifically, the image capturing device 160 may capture a plurality of output images of the display panel 1100 for a plurality of series of uniform test input images, and capture the plurality of captured images. The output image is used as a basis to generate original LUT data corresponding to the compression data, and the compressed LUT data is stored in the external memory 190. Next, the timing controller 100 can compensate the MURA defect included in the image signal data input from the outside by using the compressed LUT data stored in the external memory 190, and provide the compensated image signal data to the The display panel 1100. By this compensation, the display panel 1100 (ie, the MURA panel) that outputs the MURA defect performs an operation in the normal range.

In the display device 1001 according to another embodiment of the present invention, the image capturing device 160 may include a semiconductor package that is separate from the timing controller 100 and the external memory 190. That is, it can be formed by a module separate from the timing controller 100 and the external memory 190.

However, the present invention is not limited thereto. In the display device 1002 of still another embodiment of the present invention, the image capturing device 160 may be included in the timing controller 100. In this case, however, the timing controller 100 and the image capturing device 160 may be included in a semiconductor package that is separate from the external memory 190.

Figure 6 shows a block diagram of an image capture device in accordance with some embodiments of the present invention.

Referring to FIG. 6, the image capturing device 160 according to some embodiments of the present invention may include: a camera 161, a processor 162, a compressor 163, a controller 164, and a face 165. (interface), internal memory 166 (memory) and bus 167 (bus). The camera 161, the processor 162, the compressor 163, the controller 164, the face portion 165, and the internal memory 166 can be coupled to each other through the bus bar 167. The bus 167 is equivalent to the path of the data movement.

Camera 161 can include an image sensor. The camera 161 can capture an image output on the display panel 1100. Specifically, a plurality of output images of the display panel 1100 can be captured. For example, the camera 161 can capture a contrast, luminance, or brightness value of each pixel included in the display panel 1100. However, the invention is not limited thereto. The values thus retrieved may be temporarily stored in internal memory 166 and may be utilized in the calculation of processor 162.

The processor 162 can perform the calculations required to drive the image capture device 160. In some embodiments of the invention, processor 162 may be configured as a multiple core environment that includes multiple cores. The processor 162 can generate the original LUT data corresponding to the compensation data based on the plurality of output images captured by the camera 161.

The compressor 163 can compress the original LUT data. At this time, the compressor 163 can compress the original LUT data by using a compression algorithm. The compression algorithm may be in a complementary relationship to the decompression algorithm used by the decompressor 120 of the timing controller 100. For example, compressor 163 may compress the original LUT data using a CTW, LZ77, or LZW compression algorithm. The compressed LUT data is temporarily stored in the internal memory 166 and can be transferred to the external memory 190. However, the data transfer capability based on the face portion 165 can be directly transferred to the external memory 190 without passing through the internal memory 166.

The controller 164 can control the entire action of the image capture device 160. Controller 164 can include a microprocessor, digital signal processing, a microcontroller, and at least one of logic elements capable of performing similar functions. Specifically, the controller 164 may perform an instruction to apply a plurality of series of uniform test input images to the display panel 1100, and then control the camera 161 to capture a display panel for the uniformity test. 1100 output image. However, the invention is not limited thereto. The plurality of uniformity test input images are input values for confirming whether there is a MURA defect on the display panel 1100 and generating basic data as compensation data. The plurality of uniformity test input images are transmitted to the display panel 1100 through the timing controller 100.

The interface 165 can perform the function of transmitting data to or receiving data from the communication network. The interface 165 can be in wired or wireless form. For example, the interface 165 may include an antenna or a wired wireless universal transceiver or the like. The interface portion 165 can provide an environment required for a smooth connection with an external device (for example, a motherboard). Thus, the dielectric portion 165 can be provided with a variety of channels and ports to interchange the external devices connected to the image capture device 160. The interface 165 can transfer compressed LUT data from the compressor 163 to the external memory 190.

The internal memory 166 can store data and/or instructions processed within the image capture device 160. The internal memory 166 can provide an environment required for the processor 162 to be connected to an external device for high speed operation. Moreover, the internal memory 166 can temporarily store a plurality of input image values for uniformity testing, LUT data compressed at the compressor 163, and the like. However, the invention is not limited thereto.

7 is a flow chart of a method of operation of an image capture device in accordance with some embodiments of the present invention.

Referring to FIGS. 6 and 7, first, the controller 164 of the image capturing device 160 applies the plurality of uniformity test input images to the display panel 1100. Next, the camera 161 captures a plurality of output images of the display panel 1100 for the plurality of uniformity test input images (S210).

Next, the processor 162 performs a calibration operation on the plurality of output images (S220). The calibration operation is to calibrate a plurality of images, and it is possible to calibrate the focus, tone scale, sensitivity, and the like of each image. However, the invention is not limited thereto.

Next, the processor 162 uses the calibrated plurality of output images as a basis to generate the original LUT data corresponding to the compensation material (S230). At this time, for the input for the uniformity test, compensation data may be formed based on different points of the plurality of output image data. As described above, the original LUT data may contain compensation values for all pixels, or may only contain compensation values for horizontal lines or vertical lines, or may include one compensation value per unit pixel. However, the invention is not limited thereto.

Next, the compressor 163 compresses the original LUT data to generate compressed LUT data (S240). At this time, the compressor 163 utilizes a compression algorithm, for example, the compression algorithm may include a CTW, LZ77, or LZW compression algorithm. Moreover, the algorithm can be in a complementary relationship with the decompression algorithm used by the decompressor 120.

Next, the interface 165 transmits the compressed LUT data to the external memory 190 (S250). The compressed LUT data stored in the external memory 190 can be utilized by the timing controller 100. The timing controller 100 can compensate the MURA defect included in the input image signal data by using the compressed LUT data stored in the external memory 190, and transmit the compensated image signal data to the display panel 1100. . Specifically, the timing controller 100 may include: a memory controller 110 that reads compressed LUT data from the external memory 190; decompresses the compressed LUT data, and generates a decompressor of the original LUT data before compression 120; a column buffer 130 temporarily storing the original LUT data received from the decompressor 120; and MURA for compensating the input image signal data using the original LUT data stored in the column buffer 130 Defective image signal processing unit 150.

Thereby, the display device can perform a high-quality full-frame compensation processing operation using a small amount of memory. In addition, the external memory 190 is separated in the memory controller 110, so that the size and manufacturing cost of the memory controller 110 can be reduced.

Figure 8 is a diagram of a display module in accordance with an embodiment of the present invention.

Referring to FIG. 8, the display module 2000 may include a display device 2100, a polarizing plate 2200, and a window glass 2301. The display device 2100 includes a display panel 2110, a printed circuit board 2120, and a display driving chip 2130.

The window glass 2301 is a scratch-protected display module 2000 which is usually made of a material such as acrylic or tempered glass and which is caused by external impact or repeated touch. The polarizing plate 2200 is for improving the optical characteristics of the display panel 2110. The display panel 2110 is formed by patterning on a printed circuit board 2120 with a transparent electrode. Display panel 2110 includes a plurality of pixel cells for displaying frames. According to an embodiment, the display panel 2110 may be an organic light emitting diode panel. The pixel unit includes an organic light emitting diode that emits light corresponding to the flow of current. However, it is not limited thereto, and the display panel 2110 may include various display elements. For example, the display panel 2110 may be an LCD (Liquid Crystal Display), an ECD (Electrochromic Display), a DMD (Digital Mirror Device), an AMD (Actuated Mirror Device), a GLV (Grating Light Value), a PDP (Plasma Display Panel), an ELD ( Electro Luminescent Display), LED (Light Emitting Diode) display, one of VFD (Vacuum Fluorescent Display).

The display driver chip 2130 may include the display driver circuit described above. In the present embodiment, it is represented by one wafer, but is not limited thereto. Multiple drive wafers can be mounted. Further, it can be mounted on the printed circuit board 2120 of glass material in the form of COG (Chip On Glass). However, this is only an embodiment. The display driving chip 213O can be mounted in various forms such as COF (Chip on Film), COB (chip on board), and the like.

The display module 2000 can also include a touch panel 2300 and a touch controller 2400. The touch panel 2300 is formed by patterning on a glass substrate or a PET (Polyethylene Terephthalate) film with a transparent electrode similar to ITO (Indium Tin Oxide). The touch controller 2400 detects a touch occurring on the touch panel 2300, and calculates a touch coordinate to be transmitted to a host (not shown). The touch controller 2400 can be integrated with the display drive wafer 2130 on a semiconductor wafer.

9 is a diagram of a display system in accordance with an embodiment of the present invention.

Referring to Figure 9, the display system can include a processor 3100, a display device 3200, a peripheral device 3300, and a memory 3400 that are electrically coupled to the system bus 3500.

The processor 3100 controls the data registration output of the peripheral device 3300, the memory 3400, and the display device 3200, and can perform image data processing transmitted between the devices.

The display device 3200 includes a panel 3210 and a drive circuit 3220. The image data applied by the system bus 3500 is stored in a frame memory included in the drive circuit 3220 and then displayed on the panel 3210. Display device 3200 can be display device 1000 of FIG. Therefore, the processor 3100 operates asynchronously, so that the load on the system of the processor 3100 can be reduced.

Peripheral device 3300 can be a device that converts video or still images into electrical signals, such as cameras, scanners, webcams. The image secretary obtained by the peripheral device 3300 can be stored in the memory 3400 or instantly displayed on the panel of the display device 3200.

The memory 3400 can include volatile memory elements like DRAM and/or non-volatile memory elements like flash memory. The memory 3400 can be combined with DRAM, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, NAND flash memory, and fused flash memory (eg, SRAM buffer, NAND flash memory, and NOR interface logic). Memory) and other components. The memory 3400 can store image data obtained from the peripheral device 3300 or image signals processed at the processor 3100.

A display system according to an embodiment of the present invention may include a mobile electronic product such as a smart phone. But it is not limited to this. The display system can include various electronic products that display images.

10 is a diagram of an application example of a display device being loaded on a variety of electronic products, in accordance with some embodiments of the present invention.

Display device 4000 in accordance with some embodiments of the present invention can be used on a variety of electronic products. It can be used not only on the mobile phone 4100, but also in the TV (TV) 4200, which automatically replaces the cash withdrawal ATM (Automatic Teller Machine (ATM) 4300, elevator 4400, subway station, etc., the automatic ticket vending machine 4500, portable multimedia player ( PMP) 4600, an e-book 4700, a navigation device 4800, and the like are widely used.

Display device 4000 in accordance with some embodiments of the present invention may operate asynchronously with a processor of the system. Therefore, reducing the driving load of the processor allows the processor to operate at a high speed and at a high speed, thereby improving the function of the electronic product. The display device 4000 compresses the original LUT data about the MURA panel and stores it in an external memory that is separate from the timing controller, thereby enabling high-quality compensation processing for the display panel including the MURA defect using a small memory capacity.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but those having ordinary knowledge in the technical field of the present invention can understand that the present invention can use other specific ones without changing the technical idea or basic features thereof. Form to implement. Therefore, it is to be understood that the described embodiments are in no way

100‧‧‧ timing controller
110‧‧‧ memory controller
120‧‧‧Decompressor
130‧‧‧ column buffer
150‧‧‧Image Signal Processing Department
100‧‧‧ timing controller
152‧‧‧Go to MURA Control Department
154‧‧‧Go to MURA Processing Department
160‧‧‧Image capture device
161‧‧‧Webcam
162‧‧‧ processor
163‧‧‧Compressor
164‧‧‧ Controller
165‧‧‧ face
166‧‧‧ internal memory
167‧‧‧ busbar
190‧‧‧External memory
200‧‧‧Source Driver
300‧‧‧gate driver
340‧‧‧2nd interface circuit
400‧‧‧Voltage generator
500‧‧‧1st interface circuit
1000‧‧‧ display device
1001‧‧‧ display device
1100‧‧‧ display panel
1201‧‧‧Display drive circuit
2000‧‧‧ display module
2100‧‧‧ display device
2110‧‧‧ display panel
2120‧‧‧Printed circuit board
2130‧‧‧Display driver chip
2200‧‧‧Polar plate
2300‧‧‧ touch panel
2301‧‧‧Window glass
2400‧‧‧Touch controller
3100‧‧‧ processor
3200‧‧‧ display device
3210‧‧‧ panel
3220‧‧‧Drive circuit
3300‧‧‧ peripheral devices
3400‧‧‧ memory
3500‧‧‧System Bus
4000‧‧‧ display device
4100‧‧‧Mobile
4200‧‧‧TV
4300‧‧‧Automatic Teller Machine
4400‧‧‧Elevator
4500‧‧‧Vending Machine
4600‧‧‧ portable multimedia player
4700‧‧‧ e-book reader
4800‧‧‧Navigation equipment
AVDD‧‧‧ voltage
CMD1‧‧‧1st Directive
CNT1, CNT2‧‧‧ control signals
Cst‧‧‧ storage capacitor
DL1, DL2, DLk-1, DLk‧‧‧ data lines
EXE‧‧‧ end signal
GL1, GL2, GLj-1, GLj‧‧ ‧ gate line
Idrv‧‧‧ Current
PX‧‧ ‧ pixels
RGB‧‧‧1st image signal data
RGB'‧‧‧2nd image signal data
SSYNC1‧‧‧1st sync signal
S210, S220, S230, S240, S250‧‧‧ steps of the method flow chart drv: drive transistor
Tsw‧‧‧Switching transistor
VCI‧‧‧Power supply voltage
VDD‧‧‧Power supply voltage
Von‧‧‧voltage/gate conduction voltage
Voff‧‧‧ voltage
VSS‧‧‧ voltage

1 is a block diagram for explaining a display device according to an embodiment of the present invention. Figure 2 is a block diagram for explaining the timing controller shown in Figure 1. Fig. 3 is a block diagram showing an embodiment of the image signal processing unit of Fig. 2. 4 is a block diagram for explaining a display device according to another embodiment of the present invention. Figure 5 is a block diagram for explaining a display device according to still another embodiment of the present invention. Figure 6 shows a block diagram of an image capture device in accordance with some embodiments of the present invention. 7 is a flow chart of a method of operation of an image capture device in accordance with some embodiments of the present invention. Figure 8 is a diagram of a display module in accordance with an embodiment of the present invention. 9 is a diagram of a display system in accordance with an embodiment of the present invention. 10 is a diagram showing an application of a display device mounted on various electronic products in accordance with some embodiments of the present invention.

100‧‧‧ timing controller

190‧‧‧External memory

200‧‧‧Source Driver

300‧‧‧gate driver

340‧‧‧2nd interface circuit

400‧‧‧Voltage generator

500‧‧‧1st interface circuit

1000‧‧‧ display device

1100‧‧‧ panel

1201‧‧‧Display drive circuit

AVDD‧‧‧ voltage

CMD1‧‧‧1st Directive

CNT1, CNT2‧‧‧ control signals

Cst‧‧‧ storage capacitor

DL1, DL2, DLk-1, DLk‧‧‧ data lines

EXE‧‧‧ end signal

GL1, GL2, GLj-1, GLj‧‧ ‧ gate line

Idrv‧‧‧ Current

PX‧‧ ‧ pixels

RGB‧‧‧1st image signal data

RGB'‧‧‧2nd image signal data

SSYNC1‧‧‧1st sync signal

Tdrv‧‧‧ drive transistor

Tsw‧‧‧Switching transistor

VCI‧‧‧Power supply voltage

VDD‧‧‧Power supply voltage

Von‧‧‧voltage/gate conduction voltage

Voff‧‧‧ voltage

VSS‧‧‧ voltage

Claims (20)

A timing controller, comprising: a memory controller that reads compressed lookup table data from an external memory; decompresses the compressed lookup table data received from the memory controller, and generates an original lookup table data before compression a decompressor; a column buffer temporarily storing the original lookup table data received from the decompressor; and compensating for input image signal data using the original lookup table data stored in the column buffer Image signal processing unit for trace defects. The timing controller according to claim 1, wherein the image signal processing section includes: reading the original lookup table data from the column buffer, and receiving the image signal data from an external device And a descrambling control unit that synchronizes the original lookup table data with the image signal data; and receives the synchronized original lookup table data and the image signal from the descrambling control unit, and And using the original lookup table data to eliminate the trace defect included in the image signal, thereby generating a de-marking processing portion of the compensated image signal data. The timing controller of claim 1, wherein the trace defect comprises a non-uniform contrast, illuminance or luminance value between image signals of adjacent pixels. The timing controller of claim 1, wherein the decompressor generates the original lookup table data from the compressed lookup table data using a lossless decompression algorithm. The timing controller of claim 4, wherein the lossless decompression algorithm comprises a CTW, LZ77, or LZW decompression algorithm. The timing controller of claim 1, wherein the image signal data includes data about N pixels, the N is a natural number, and the original lookup table data includes all of the N pixels. Compensation value. The timing controller of claim 1, wherein the image signal data includes data about L*M pixels, the L and the M are natural numbers, and the original lookup table data includes The compensation values of the L vertical lines and the compensation values corresponding to the M horizontal lines. The timing controller of claim 1, wherein the image signal material includes data about N pixels, the N is a natural number, and the original lookup table data includes one for each K unit pixels. A compensation value, the K being a natural number smaller than the N. The timing controller of claim 1, wherein the timing controller is included in a semiconductor package that does not include the external memory. A display device comprising: a display panel; storing an external memory for compressing the lookup table data; for a plurality of uniformity test input images, capturing a plurality of output images of the display panel, and extracting the captured image a plurality of output images as a basis, generating original lookup table data corresponding to the compensation data, storing the compressed lookup table data in the image capturing device of the external memory; and utilizing the storage in the external memory The compressed lookup table data compensates for trace defects included in the image signal data input from the outside, and supplies the compensated image signal data to the timing controller of the display panel. The display device of claim 10, wherein the image capturing device comprises: a controller that applies the plurality of input images for uniformity testing to the display panel; and the display panel is captured a plurality of output image cameras; a processor that generates the original lookup table data corresponding to the compensation data based on the plurality of captured output images; and a compressor that compresses the original lookup table data; And transmitting the compressed lookup table data to a face of the external memory. The display device of claim 11, wherein the compressor compresses the original lookup table data by using a CTW, LZ77, or LZW compression algorithm. The display device of claim 10, wherein the image capturing device is included in the timing controller. The display device according to claim 10, wherein the image capturing device comprises a semiconductor package separately from the timing controller and the external memory. The display device of claim 10, wherein the timing controller comprises: a memory controller that reads compressed lookup table data from the external memory; decompresses the compressed lookup table data, and generates a decompressor of the original lookup table data before compression; a column buffer temporarily storing the original lookup table data received from the decompressor; and utilizing the original lookup table data stored in the column buffer An image signal processing unit that compensates for trace defects of the input image signal data. The display device of claim 15, wherein the decompressor processes the original lookup table data using an algorithm complementary to the compressor. A display device comprising: a plurality of pixels respectively disposed at intersections of a plurality of gate lines and a plurality of data lines; a gate driver driving the plurality of gate lines; driving a source of the plurality of data lines a memory; storing an external memory that compresses the lookup table data; and responding to the image signal data and the control signal input from the outside, controlling the gate driver and the source driver, and using the external memory storage device Compressing the lookup table data, compensating for the trace defects included in the input image signal data, and providing the compensated image signal data to the timing controller of the source driver. The display device of claim 17, wherein the timing controller comprises: a memory controller that reads compressed lookup table data from the external memory; decompresses the compressed lookup table data, and generates a decompressor of the original lookup table data before compression; a column buffer temporarily storing the original lookup table data received from the decompressor; and utilizing the original lookup table data stored in the column buffer An image signal processing unit that compensates for trace defects of the input image signal data. The display device of claim 17, further comprising: extracting, for the plurality of uniformity test input images, a plurality of output images of the plurality of pixels, and extracting the plurality of images Based on the output images, the original lookup table data corresponding to the compensation data is generated, and the compressed lookup table data is stored in the image capturing device of the external memory. The display device according to claim 19, wherein the image capturing device comprises: a control unit that applies the plurality of input images for uniformity testing to the plurality of pixels; a camera for outputting a plurality of pixels of a plurality of pixels; using the plurality of output images captured as a basis, generating a processor corresponding to the original lookup table data of the compensation data; compressing the compression of the original lookup table data And transmitting the compressed lookup table data to the interface of the external memory.