TW201705228A - Method of manufacturing a semiconductor device - Google Patents

Abstract

Provided is a method of manufacturing a semiconductor device, for suppressing channeling that may occur during ion implantation to a polycrystalline silicon layer (4), the method including: exposing, in an opening portion formed in a second photoresist layer (8), a first photoresist layer (5) that has been used for patterning the polycrystalline silicon layer (4); and implanting impurities by ion implantation with the first photoresist layer (5) being a mask for a gate electrode (4-1) formed of the polycrystalline silicon layer (4).

Description

Semiconductor device manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating an ion-implanted impurity layer in self-alignment with a pattern of a polycrystalline germanium layer.

As one of the utilization examples of the formation of the self-aligned impurity layer for the pattern of the polycrystalline germanium layer, the source of the transistor is formed in the manufacture of the conventional MOS transistor. An impurity layer in the bungee field. Take the project shown below.

First, as shown in FIG. 2(a), for example, the element isolation insulating film 12 and the gate insulating film 13 are formed on the germanium substrate 11. Next, after the polycrystalline germanium layer 14 is formed on the entire surface of the germanium substrate 11, a photoresist is applied, and the patterned photomask corresponding to the polycrystalline germanium layer 14 is exposed to form a first photoresist layer 15.

Next, as shown in FIG. 2(b), the first photoresist layer 15 is used as a mask, and the polycrystalline germanium layer 14 is removed by etching to form a gate electrode 14-1 made of the polycrystalline germanium layer 14, 14-2, after resistor 14-3 and wiring, remove The first photoresist layer 15.

Next, as shown in Fig. 2(c), the source of the MOS transistor, for example, using the gate electrode 14-1 as an electrode. The way in which the bungee can form the desired field, the second photoresist layer 16 is patterned, and the source is selectively formed by ion implantation. The drain impurity layer 17 is provided.

At this time, the opening of the second photoresist layer 16 in which ion implantation of impurities is performed is not only the source of the desired MOS transistor. In the field of bungee, it is also formed on the gate electrode 14-1. Therefore, the gate electrode 14-1 becomes a mask during ion implantation, so that the source can be formed in the self-aligned gate electrode 14-1. The drain impurity layer 17 is provided.

Thereby, there are advantages shown below.

(1) There is no need to consider the source. The alignment of the photoresist pattern of the gate electrode and the gate electrode is deviated, and the miniaturization of the portion of the transistor becomes possible.

(2) There is no need to source. The photoresist pattern for the drain impurity layer is microfabricated to more than necessary, and at least the source can be made more easily. Processing of the bungee impurity layer.

As shown above, the gate electrode pattern of the polycrystalline germanium layer is self-aligned to form the source. MOS transistor of the drain impurity layer.

Further, as shown in FIG. 2(d), for the MOS transistor using the gate electrode 14-2 as an electrode, for example, the above-mentioned FIG. 2(c) is repeated in the desired field to form a source. The drain impurity layer 18 forms a plurality of types of MOS transistors.

Self-aligned to hold the source. A MOS transistor having a drain impurity layer and a method of manufacturing the same are known, for example, disclosed in Non-Patent Document 1 The above works to form the source of the MOS transistor. A method of bungee impurity layer.

[Advanced technical literature] [Non-patent literature]

[Non-Patent Document 1] Kano is just "Super LSI Materials. The Foundation of Process" Ohmsha, Ltd., December 25, 2006, p.11-12

However, the method of manufacturing the MOS transistor described in Non-Patent Document 1 has the following disadvantages.

Since the polycrystalline germanium layer generally used as the gate electrode of the transistor is formed by a collection of single crystal grains, it is at the source. In the ion implantation of the bungee impurity, the gate electrode formed by the polycrystalline germanium layer is penetrated by the channel phenomenon in which the impurity is implanted through the gap between the crystal grains, and the channel region of the transistor under the gate electrode is also Inject impurities.

This is one of the important factors determining the critical value of the transistor, and the large variation in impurity concentration in the channel region is a major factor, which hinders the stabilization of the performance of the transistor.

Therefore, in the invention of the present invention, it is an object of the present invention to provide a method for manufacturing a MOS transistor which can prevent a channel phenomenon and stabilize the critical value of the transistor.

In order to solve the above problems, the present invention is a pattern for a polycrystalline germanium layer. When the impurity layer is formed by self-alignment, the means described below is taken.

(1) The patterned first photoresist layer used for the polycrystalline germanium layer is left, and impurities are ion-implanted.

(2) The patterned first photoresist layer used in the polycrystalline germanium layer is left, and the second photoresist layer for the impurity layer is patterned to ion-implant impurities.

In the present invention, the first photoresist layer is left in the pattern of the polycrystalline germanium layer, and ion implantation is performed to form the impurity layer, whereby the effects described below are exhibited.

(1) The channel phenomenon at the time of ion implantation through the pattern of the polycrystalline germanium layer can be suppressed, for example, the source of the MOS transistor is formed by ion implantation even if the gate electrode of the polycrystalline germanium layer is self-aligned. The drain impurity layer can also stabilize the critical value of the transistor because no impurity is implanted into the channel region of the transistor.

(2) It is not necessary to remove the first photoresist layer on the pattern of the polycrystalline germanium layer before ion implantation, and the first photoresist layer is removed in the subsequent photoresist removal process, for example, when the second photoresist layer is removed. Therefore, the project can be reduced.

1, 11‧‧‧矽 substrate

2, 12‧‧‧ component separation insulating film

3, 13‧‧‧ gate insulation film

4, 14‧‧‧ polycrystalline layer

4-1, 4-2, 14-1, 14-2‧‧‧ gate electrodes

4-3, 14-3‧‧‧Wiring made of polycrystalline germanium layer. Resistive film

5, 15‧‧‧1st photoresist layer

6‧‧‧Resist hardened layer

7, 9, 10, 17, 18‧‧‧ source. Bungee impurity layer

8, 16‧‧‧2nd photoresist layer

1 is a cross-sectional view showing the construction of a method of manufacturing a semiconductor device of the present invention.

2 is a cross-sectional view showing the construction of a conventional semiconductor device manufacturing method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, as shown in FIG. 1(a), for example, the element isolation insulating film 2 and the gate insulating film 3 are formed on the germanium substrate 1. Next, after the polycrystalline germanium layer 4 is formed on the entire surface of the germanium substrate 1, a photoresist is applied and exposed to a patterned photomask corresponding to the polycrystalline germanium layer 4 to form the first photoresist layer 5.

Next, the surface of the ruthenium substrate patterned by the first photoresist layer 5 is subjected to UV (ultraviolet) irradiation, and a resist hardened layer 6 having solvent resistance and exposure resistance is formed on the surface of the photoresist layer 5.

The UV irradiation at this time is a condition that the temperature is 170 to 190 ° C and the UV exposure amount is in the range of 12 to 15 J/cm ² , whereby the resist hardened layer 6 having the solvent resistance and the exposure resistance can be formed.

Generally expose the photoresist. After forming a pattern, the pattern is baked at a slightly elevated temperature, and the organic solvent in the photoresist is discharged to the outside. Although the baking resist layer is added, such simple baking cannot be expected. The effect of solvent resistance or exposure resistance on the surface of the photoresist layer.

Next, as shown in FIG. 1(b), the first photoresist layer 5 having the resist hardened layer 6 is used as a mask, and the polycrystalline germanium layer 4 is removed by etching to form a polycrystalline germanium layer 4. Gate electrodes 4-1, 4-2, resistive film 4-3, and wiring. As the gate electrode or the resistive film, in addition to the polycrystalline germanium layer, a single layer film or a laminated film of a high melting point metal such as titanium or tantalum or tungsten or the like may be used.

Next, the first photoresist layer 5 having the resist hardened layer 6 may be left on the gate electrodes 4-1, 4-2, the resistive film 4-3, and the wiring, as needed, The ion implantation is performed on the germanium substrate 1 in a comprehensive manner, and the source electrodes are formed in self-alignment for the gate electrodes 4-1 and 4-2 formed by the polycrystalline germanium layer. Bungee impurity layer 7. Since the first photoresist layer 5 having the resist hardened layer 6 is provided on the gate electrodes 4-1, 4-2, the resistive film 4-3, and the wiring, the channel phenomenon of the impurity ions implanted by the ions can be suppressed. .

Next, as shown in FIG. 1(c), the second photoresist layer 8 is applied from the first photoresist layer 5 having the resist hardened layer 6, and then patterned. Since the first photoresist layer 5 is patterned and the underlying polycrystalline germanium layer 4 is etched, the thickness of the first photoresist layer 5 and the thickness of the polycrystalline germanium layer 4 are present on the surface of the germanium substrate. The step difference. This step difference may hinder the coating spread of the second photoresist layer 8 and cause uneven coating.

By coating the amount of the resist when the resist is applied in the second photoresist layer is formed more than the amount of the resist when the resist is applied in the formation of the first photoresist layer, the above coating can be avoided. Uneven cloth. In the same manner as in the formation of the third photoresist layer to be described later, the amount of the resist dropped during the application of the resist in the formation of the third photoresist layer is higher than that in the formation of the resist in the formation of the first photoresist layer. The amount of the resist is dripped more, and the above uneven coating can be avoided. Further, even if the amount of the resist drop to form the second photoresist layer is the same as the amount of the resist drop to form the third photoresist layer. By using a method in which the viscosity of the resist applied by the resist in the second and third photoresist layers is higher than that of the resist coated in the first photoresist layer, Uneven coating can be avoided.

Next, the source of the MOS transistor, for example, with the gate electrode 4-1 as the electrode. The way in which the bungee can form a desired area is provided in the second photoresist layer 8 and is selectively formed by ion implantation. Source. The drain impurity layer 9. The first photoresist layer 5 having the resist hardened layer 6 which is initially formed in the opening portion is exposed.

The opening of the second photoresist layer 8 for performing ion implantation of impurities is not only the source of the desired MOS transistor. In the field of the drain, the gate electrode 4-1 is also formed. However, since the double resist method of forming the second photoresist layer 8 in the first photoresist layer 5 is used, the first one can be used. a photoresist layer to selectively mask the desired gate electrode, and for the gate electrode formed of the polycrystalline germanium layer, the impurity is selectively self-aligned in such a manner that only the desired portion is implanted with impurities. Ion Implantation. Since the first photoresist layer 5 having the resist hardening layer 6 is provided on the gate electrode 4-1, the channel phenomenon of the impurity ions implanted by the ions is suppressed.

Thereby, there are advantages shown below.

(1) There is no need to consider the source. The alignment of the photoresist pattern of the gate electrode and the gate electrode is deviated, and the miniaturization of the portion of the transistor becomes possible.

(2) There is no need to source. The photoresist pattern for the drain impurity layer is finely processed to more than necessary, and at least the source can be made more easily. Processing of the bungee impurity layer.

(3) Since the photoresist layer is formed on the gate electrode formed of the polycrystalline germanium layer, the channel phenomenon at the time of impurity ion implantation can be suppressed.

(4) Since it is not necessary to remove the first photoresist layer on the pattern of the polycrystalline germanium layer before ion implantation, the first photoresist can be removed in the subsequent photoresist removal process, for example, when the second photoresist layer is removed. Layers, so engineering can be cut.

Further, by having the resist hardening layer 6 in the first photoresist layer 5 shown in Fig. 1(a), even if the second photoresist layer 8 is applied, the solvent is not immersed. When the first photoresist layer 5 is passed through, the pattern of the first photoresist layer is not deformed.

Further, when the second photoresist layer 8 needs to be reworked, the surface of the second photoresist layer or the patterned ruthenium substrate can be uniformly exposed without using a photomask. Even if the second photoresist layer is patterned, the first photoresist layer 5 is exposed, and since the resist hardening layer 6 has exposure resistance and solvent resistance, the entire exposure and the second photoresist which is continued later are continued. The alkaline solvent treatment removed by the agent layer does not affect the first photoresist layer. As shown above, the gate electrode pattern of the polycrystalline germanium layer is self-aligned to form the source. MOS transistor of the drain impurity layer.

Further, although the formation of the resist hardened layer 6 by UV irradiation after the etching of the polycrystalline germanium layer 4 is performed after the patterning of the first photoresist layer 5, exposure resistance and solvent resistance can be obtained. However, since the first photoresist layer is retracted by baking by general UV irradiation, the resist hardening layer 6 is formed on the inner side of the pattern of the polycrystalline germanium layer 4 to be etched. 1 The photoresist layer 5, the portion after the retraction of the resist is exposed to the surface of the polycrystalline germanium layer.

The exposed portion of the surface of the polycrystalline germanium layer is the source after the subsequent connection. In the ion implantation of the bungee impurity, only the polycrystalline germanium layer is used as the mask material, and the channel field of the transistor under the gate electrode is also the channel region of the transistor under the gate electrode. Inject impurities to increase the critical value deviation of the transistor. Moreover, if the degree is serious, the source is also formed directly under the surface exposed portion of the polycrystalline germanium layer. In the bungee field, the formation of the source is self-aligned for the gate electrode pattern. Bungee impurity layer.

On the other hand, as described in the embodiment of the present invention, after the patterning of the first photoresist layer 5, UV irradiation is performed before the etching of the polycrystalline germanium layer 4, and if the resist hardened layer 6 is formed, the polycrystalline germanium layer is formed. The etching is performed by using the retracted photoresist pattern as a mask, so that the entire upper surface of the gate electrode of the polycrystalline germanium layer after etching can be maintained as the first photoresist layer of the resist hardening layer 6. The state covered is due to the source. The complete masking material for the bungee impurity ion implantation, so the source can be perfectly implemented. Prevention of self-aligned formation or channeling of the gate electrode by the drain impurity layer.

Further, as shown in FIG. 1(d), if necessary, for example, in the MOS transistor using the gate electrode 4-2 as an electrode, the above-described process of FIG. 1(c) is repeated in the desired field. Form the source. The gate impurity layer 10 can form a plurality of types of MOS transistors. That is, the applied photoresist layer, the opening portion, and the impurities are repeatedly changed: after the second photoresist layer is selectively removed, after the third photoresist layer is applied onto the first photoresist layer Patterning, a second opening is provided in a part of the third photoresist layer, the first photoresist layer is exposed to the second opening, and then the second impurity is ion-implanted from the second opening to form a source. A drain impurity layer, thereby forming a plurality of types of MOS transistors.

When the process of Figure 1 (c) is repeated, the source is formed as a double mask on the first photoresist layer on the polycrystalline germanium layer. The photoresist layer for the drain impurity layer is the source. When the ion implantation concentration of the drain impurity layer is 5 × 10 ¹⁴ atms/cm ² or less, even if it is a wet method, that is, only the solvent for removing the photoresist can be removed, the first photoresist having the resist hardened layer is provided. The solvent layer of the agent layer is continued, and the photoresist layer for the impurity layer which leaves the first photoresist layer on the polycrystalline germanium layer can be formed and ion-implanted.

On the other hand, the first photoresist layer holding the resist hardening layer is an ashing treatment for performing a photoresist which is generally applied to a photoresist layer after treatment such as high concentration implantation. Although the resistive hardening layer 6 is provided in the first photoresist layer 5, since only the resist surface portion is provided, the resist hardened layer 6 can be removed by ashing treatment, and the resist hardened layer 6 can be removed by The usual photoresist removal solvent removes both the first photoresist layer and the photoresist layer formed as a double mask.

Of course, after removing the photoresist layer formed as a double mask, the first photoresist is subjected to ashing treatment, and the first photoresist is removed by solvent treatment without any problem.

In addition, the source of the invention. The drain impurity layer is not limited to a high concentration of an N-type or P-type impurity layer, and is also included in the final form of the MOS transistor to constitute a source. Part of the bungee, such as LDD (Lightly Doped Drain) or DDD (Double Diffused Drain), as the source. A pocket implant layer or a ring-shaped implant layer for a punch-through stopper.

Similarly, although the invention is the source of the MOS transistor. The method for producing the gate impurity layer is an example, but the invention is not limited thereto, and it is of course applicable to a method of producing an impurity layer formed by self-alignment of the pattern of the polycrystalline germanium layer.

1‧‧‧矽 substrate

2‧‧‧Component separation insulating film

3‧‧‧gate insulating film

4‧‧‧Multi-crystalline layer

4-1, 4-2‧‧‧ gate electrode

4-3‧‧‧Wiring made of polycrystalline germanium layer. Resistive film

5‧‧‧1st photoresist layer

6‧‧‧Resist hardened layer

7, 9, 10‧‧ ‧ source. Bungee impurity layer

8‧‧‧2nd photoresist layer

Claims (11)

A method of manufacturing a semiconductor device, which is a method for fabricating a semiconductor device in which an impurity layer is formed by self-alignment of a pattern of a polycrystalline germanium layer on a semiconductor substrate, characterized in that it is composed of the following engineering, and a polycrystalline germanium is formed on the semiconductor substrate. Engineering of a layer; a process of patterning a first photoresist layer constituting a double mask layer on the polycrystalline germanium layer; and performing UV irradiation on the patterned first photoresist layer; The first photoresist layer after the UV irradiation is used as a mask, and the polycrystalline germanium layer is etched to form a gate electrode and a resistive film formed of the polycrystalline germanium layer; and the first light after the UV irradiation After coating the second photoresist layer on the resist layer, patterning is performed, and an opening is provided in a part of the second photoresist layer to expose the first photoresist layer to the opening; and the opening is Part of the process of ion implantation of the first impurity. The method of manufacturing a semiconductor device according to claim 1, further comprising: a process of removing the second photoresist layer in connection with ion implantation of the first impurity; and forming the first photoresist layer on the first photoresist layer After coating the third photoresist layer, patterning is performed, and a second opening is provided in a part of the third photoresist layer to expose the first photoresist layer to the second opening; and 2 The process of ion implantation of the second impurity in the opening portion. The method for producing a semiconductor device according to the second aspect of the invention, wherein the solvent for removing the photoresist is used in the process of removing the second photoresist layer. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the opening is formed at least in a source of the MOS transistor. The bungee impurity layer is formed in the field. The method of manufacturing a semiconductor device according to the first aspect of the invention, further comprising: after the step of forming a gate electrode and a resistive film formed of the polycrystalline germanium layer, leaving the first light after the UV irradiation The resist layer is ion-implanted in the entire semiconductor substrate, and the source electrode is self-aligned with the gate electrode formed by the polycrystalline germanium layer. The engineering of the bungee impurity layer. The method of manufacturing a semiconductor device according to claim 1 or 5, wherein the patterning is performed after the step of patterning the first photoresist layer and before etching the polycrystalline germanium layer The first photoresist layer is irradiated with UV. The method for producing a semiconductor device according to any one of claims 2 to 4, wherein, after the step of patterning the first photoresist layer, and before etching the polycrystalline germanium layer A process of irradiating the aforementioned patterned first photoresist layer with UV is performed. The method for producing a semiconductor device according to any one of claims 1 to 7, wherein a resist drop amount for forming the second photoresist layer is greater than a resistance for forming the first photoresist layer. The amount of the agent dropped more. For example, any one of items 2 to 4 of the patent application scope or item 7 In the method for producing a semiconductor device according to the aspect of the invention, the amount of the resist to be formed on the third photoresist layer is more than the amount of the resist to form the first photoresist layer. The method for producing a semiconductor device according to any one of claims 1 to 7, wherein a viscosity of a resist forming the second photoresist layer is higher than a resistance of forming the first photoresist layer. The viscosity of the agent is higher. The method for producing a semiconductor device according to any one of claims 2 to 4, wherein the viscosity of the resist forming the third photoresist layer is greater than the first photoresist. The viscosity of the agent layer of the agent layer is higher.