TW201703216A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a cover layer that enhances reliability of the semiconductor packages.

Description

Semiconductor package and method of manufacturing same

The present invention relates to semiconductor packaging and methods of making the same.

Cross-reference/inclusion of relevant applications as a reference

The present application is directed to Korean Patent Application No. 10-2015-0024957, filed on Jan. 23, 2015, to the Korean Intellectual Property Office, and entitled "Method for Manufacturing Semiconductor Packages and Semiconductor Packages Using the Same". Priority is given to the benefit of the Korean Patent Application, the entire disclosure of which is hereby incorporated by reference.

The present application is related to U.S. Patent Application Serial No. 14/823,689, filed on Aug. Reference.

Current semiconductor packages and methods for forming semiconductor packages are insufficient, for example, resulting in excessive cost, reduced reliability, or excessive package size. Further limitations and disadvantages of the conventional and conventional means for those skilled in the art, in this way, a comparison with the present disclosure as described with reference to the drawings in the remainder of the present application will become It is obvious.

Various features of this disclosure provide a semiconductor package and a method of fabricating a semiconductor package. By way of non-limiting example, various features of this disclosure provide various semiconductor packages and methods of making the same, including a cover layer that enhances the reliability of the semiconductor package.

10‧‧‧Support wafer

20‧‧‧Molded materials

30‧‧‧Interconnect structure

100‧‧‧Intermediary

110‧‧‧矽 Subject

111‧‧‧Dielectric layer

120‧‧‧Direct Through Crystal Perforation (TSV)

131‧‧‧ above the circuit pattern

132‧‧‧ below the circuit pattern

200A‧‧‧ implementation

200B‧‧‧example

200C‧‧‧ icon

200D‧‧‧ icon

200E‧‧‧ icon

200F‧‧‧ icon

200G‧‧‧ icon

200H‧‧‧ icon

200I‧‧‧ package

210‧‧‧Electrically conductive mat

220‧‧‧conductive column

300‧‧‧Semiconductor Module

310‧‧‧Semiconductor grain

320‧‧‧ solder pads

330‧‧‧ solder bumps

340‧‧‧Bottom glue filling (material)

400‧‧‧ Coverage

400A, 400B, 400C, 400D, 400E, 400F, 400G‧‧‧ icons

400H‧‧‧ package

1000‧‧‧ method

1107, 1110, 1120, 1130, 1140, 1150, 1160, 1170, 1180, 1190‧‧‧ blocks

3000‧‧‧ method

3107, 3110, 3120, 3130, 3140, 3150, 3160, 3170, 3190‧‧‧ blocks

H1, H2‧‧‧ height

1 is a flow chart showing a method of fabricating an example of a semiconductor package in accordance with various features of the present disclosure.

2A-2I are cross-sectional views showing an exemplary semiconductor package and a method of fabricating an example of a semiconductor package in accordance with various features of the present disclosure.

3 is a flow chart showing a method of fabricating an example of a semiconductor package in accordance with various features of the present disclosure.

4A-4H are cross-sectional views showing an exemplary semiconductor package and a method of fabricating an example of a semiconductor package in accordance with various features of the present disclosure.

The following discussion presents various features of the present disclosure by providing examples of the disclosure. Such examples are not limiting, and thus the scope of the various features of the present disclosure should not be necessarily limited to any particular feature of the examples provided. In the following discussion, the terms "such as", "such as" and "example" are not limiting, and are generally intended to be "exemplary and non-limiting", "such as, without limitation," Synonymous.

As used herein, "and/or" refers to any one or more of the items added by "and/or" in the list. For example, "x and / or y" is the representation of the three elements Any of the elements {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y, and/or z" is a set representing the seven elements {(x), (y), (z), (x, y), (x, z), ( Any of y, z), (x, y, z)}. In other words, "x, y, and/or z" means "one or more of x, y, and z."

The terminology used herein is for the purpose of describing the particular embodiments, and is not intended to As used herein, the singular is intended to include the plural, unless the context clearly dictates otherwise. It will be further understood that the terms "comprising", "comprising", "having", "the"," The existence of a component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, components and/or groups thereof.

It will be appreciated that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another. Thus, for example, a first component, a first component, or a first segment discussed below can be referred to as a second component, a second component, or a second segment without departing from the disclosure. Teaching. Similarly, various terms such as "upper", "lower", "side" and the like may be used to distinguish one element from another. However, it should be understood that the components can be oriented in different ways, for example a semiconductor device can be turned to the sides, such that its "top" surface is horizontally oriented and its "side" surface is vertically oriented without detachment The teachings of the disclosure.

Various features of the present disclosure provide a semiconductor device or package and a method of fabricating the same that can reduce cost, increase reliability, and/or increase manufacturability of the semiconductor device.

Various features of the present disclosure also provide a semiconductor device or package and a method of fabricating the same that avoids or inhibits the diffusion of conductive ions of a conductive pillar into a semiconductor die.

Various features of the present disclosure further provide a semiconductor device or package and a method of making the same that avoids or prohibits warpage or distortion from occurring during manufacturing and/or after fabrication.

Various features of the present disclosure provide a method of fabricating a semiconductor package, the method comprising forming an interposer (or redistribution structure) on a wafer; forming at least one electrically conductive pad on the interposer and at least a conductive pillar; at least one semiconductor die is disposed on the interposer and electrically connected to the conductive pad; forming a capping layer on various surfaces of the semiconductor die, the pillar, and/or the interposer; An encapsulating material to encapsulate the pillar and the semiconductor die on the interposer; and exposing the post to the cover layer and the exterior of the encapsulating material.

Various features of the present disclosure also provide a semiconductor package including an interposer; at least one electrically conductive pad on the interposer and at least one conductive post; at least one disposed on the interposer and electrically connected to the a semiconductor die of a conductive pad; a cover layer on the semiconductor die, the pillar, and/or various surfaces of the interposer; and a pillar and the semiconductor die encapsulated on the interposer An encapsulating material wherein one end of the post is exposed to the cover layer and to the exterior of the encapsulating material.

The above and other features of the present disclosure will be apparent from the following description of exemplary embodiments. Various features of the present disclosure will now be presented with reference to the appended drawings, so that those skilled in the art can Easily implement these various features.

1 is a flow chart showing a method 1000 of fabricating an example of a semiconductor package. The method 1000 of this example can share any or all of the features, for example, with any of the other methods discussed herein (eg, the method 3000 of the example of FIG. 3, etc.). 2A-2I are cross-sectional views showing an exemplary semiconductor package and a method of fabricating an example of a semiconductor package in accordance with various features of the present disclosure. The structure shown in Figures 2A-2I can share any or all of the features of the structure similar to that shown in Figures 4A-4H. 2A-2I, for example, may depict an exemplary semiconductor package at various stages (or blocks) of the method 1000 of the example of FIG. Figures 1 and 2A-2I will now be discussed together. It should be noted that the order of the example blocks of the method 1000 of this example may vary without departing from the scope of the disclosure.

The method 1000 of this example can include, at block 1107, preparing a logic wafer for processing (eg, for packaging). Block 1107 can include any of a variety of ways to prepare a logic wafer for processing, non-limiting ways of which are set forth herein.

For example, block 1107 can include, for example, a logic wafer that is delivered from a supplier, from an upstream process, or at a location at a manufacturing location, and the like. The logic wafer, for example, can include a semiconductor wafer that includes a plurality of active semiconductor dies. The semiconductor die can include, for example, a processor die, a memory die, a programmable logic die, a special application integrated circuit die, a general logic die, and the like.

Block 1107, for example, can include an interconnect structure that forms a conductive on the logic wafer. Such electrically conductive interconnect structures can include, for example, conductive pads, regions, bumps or balls, conductive posts or posts, and the like. The forming can include, for example, attaching a pre-formed interconnect structure to the logic wafer, plating the interconnect structures on the logic wafer, and the like.

In an exemplary embodiment, the electrically conductive structures may comprise a conductive post or a post comprising copper and/or nickel, and may include a solder cap (eg, including tin and/or silver). For example, a conductive structure comprising conductive pillars can include: (a) a bump bottom metallization ("UBM") structure comprising (i) a layer of titanium-tungsten (TiW) formed by sputtering (which) It may be referred to as a "seed layer"), and (ii) a layer of copper (Cu) formed by sputtering on the titanium-tungsten layer; (b) a UBM formed by electroplating a copper pillar or a cylinder; and (c) a layer of solder formed on the pillar, or a layer of nickel formed on the pillar and a layer of solder formed on the layer of nickel.

Moreover, in an exemplary embodiment, the electrically conductive structures may include a lead and/or lead-free wafer bump (eg, Pb/Sn, lead-free Sn, equivalents thereof, alloys thereof, etc. ). For example, lead-free wafer bumps (or interconnect structures) can be formed, at least in part, by: (a) forming a bump bottom metallization (UBM) structure by (i) by sputtering Forming a layer of titanium (Ti) or titanium-tungsten (TiW), (ii) sputtering on the titanium or titanium-tungsten layer to form a layer of copper (Cu), (iii), and on the copper layer Forming a layer of nickel (Ni) by electroplating; and (b) forming a lead-free solder material by electroplating on the nickel layer of the UBM structure, wherein the lead-free solder material has a weight of 1% to 4% A composition of silver (Ag), and the remainder of the weight of the composition is tin (Sn).

Block 1107 can include, for example, performing thinning (eg, grinding, etching, etc.) of a portion or the entirety of the logic wafer. Moreover, block 1107 can include, for example, cutting the logic wafer into individual dies or groups of dies for subsequent attachment (eg, at block 1130).

In general, block 1107 can include preparing a logic wafer for processing (eg, for packaging). Thus, the scope of this disclosure should not be limited by the particular type of logic wafer and/or die features, or any particular type of logic wafer and/or die processing.

At block 1110, the method 1000 of the example can include preparing an intermediate crystal Circle (or panel). In an exemplary embodiment, an interposer (eg, one of the bottom surfaces) can be attached to a surface (eg, one of the top surfaces) of a supporting wafer. Such attachment may be performed, for example, using an adhesive member (not shown) (e.g., a thermally detached adhesive, etc.), mechanical attachment, vacuum attachment, and the like. It is noted that the support wafer can include a semiconductor (eg, germanium, etc.) wafer, a glass wafer, a metal wafer, and the like. It is also noted that the support wafer need not be circular, but may also include a rectangular (or panel) shape.

The interposer 100 can be, for example, (or has been) formed using a semiconductor wafer fabrication (FAB) process. Such processing can be utilized, for example, to create fine pitch pads and/or lines, such as having a line width and/or spacing of 10 microns or less (eg, center-to-center spacing).

An exemplary embodiment 200A is shown in FIG. 2A, which shows that the interposer 100 includes a dielectric layer 111 (which may also be referred to herein as a protective layer), the dielectric layer 111 being formed in One of the top (or upper) and bottom (or lower) surfaces of the body 110. The dielectric layer 111 may, for example, comprise one or more of any of a variety of dielectric materials, such as inorganic dielectric materials (eg, Si ₃ N ₄ , SiO ₂ , SiON, oxides, nitrides, etc.) and/or Or organic dielectric materials (for example, polyimine (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), monophenol resin, ring Oxygen resin, etc.), but the scope of the disclosure is not limited thereto. The dielectric layer 111 can be formed using any one or more of various processes (eg, spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition ( CVD), plasma vapor deposition, sheet stacking, etc.), but the scope of the disclosure is not limited thereto.

In addition, a plurality of through-twisted vias (TSV) 120 are formed in the body of the crucible 110. Furthermore, a circuit pattern 131 (or a conductive layer) electrically connected to the TSVs 120 and exposed to the outside of the dielectric layer 111 (for example, through a hole formed therein) is formed on the 矽An upper side of the body 110 and a circuit pattern 132 (or conductive layer) electrically connected to the TSVs 120 and exposed to the outside of the dielectric layer 111 (eg, through a hole formed therein) It is formed on a lower side of the crucible body 110. The TSVs 120 may, for example, provide a conductive path between the upper circuit pattern 131 and the underlying circuit pattern 132. It is noted that the interposer 100 can also include one or more internal conductive layers. Any of the conductive layers may, for example, provide a vertical and/or horizontal distribution of electrical signals relative to the interposer 100.

In an exemplary scenario, the interposer 100 (or redistribution structure) can be formed separately from the support wafer 10 and then attached thereto. In another example scenario, the interposer 100 can be directly formed (or built) on a wafer, in which case the interposer 100 (or redistribution structure) has been attached to the support wafer. 10, thus no further adhesion or otherwise attached to the support wafer 10 is required. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The entire contents of this U.S. Patent Application is hereby incorporated by reference. For example, an interposer (or redistribution structure) can be formed by forming one or more dielectric and conductive layers on a germanium wafer. In such an example, the interposer 100 may not include a single body (or core).

It is noted that block 1110 can include receiving the interposer wafer from an adjacent or upstream manufacturing station at a manufacturing facility, from another geographic location, and the like. The interposer wafer can be, for example, received to be prepared, or additional preparation can be performed

In general, block 1110 can include preparing an interposer wafer. So this The scope of the disclosed content should not be limited by the characteristics of any particular type of interposer or interposer wafer, or by any particular manner in which such interposer or interposer wafers are formed.

At block 1120, the method 1000 of the example can include forming one or more electrically conductive pads and/or conductive posts (or columns) on the interposer. Block 1120 can include any of a variety of ways to form such electrically conductive pads and/or posts, non-limiting examples of which are provided herein. For example, the conductive pads and/or pillars can be formed by sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), general vacuum deposition, electroplating, electroless plating, and the like. form.

In an exemplary embodiment, the block 1120 can include electroplating the conductive pads and/or conductive posts on the exposed circuitry pattern 131 from the dielectric layer 111. In order to perform such electroplating, the block 1120 may include, for example, forming a seed layer on the upper side of the interposer 100. The seed layer can comprise any of a variety of materials. For example, the seed layer can comprise copper. Also for example, the seed layer may comprise one or more of any of a variety of metals (eg, copper, silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). The seed layer can be formed using any of a variety of techniques (eg, sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), electroless plating, etc.).

Block 1120, for example, can include forming a plate on the seed layer (eg, typically utilizing a photoresist, any of a variety of dielectric materials, lithography, etc.) to expose one of the seed layers The conductive pads and/or portions of the posts are electroplated. Block 1120 can then, for example, include electroplating the electrically conductive pads and/or posts and removing (or stripping) the pattern. The formation and plating of such a pattern can be performed, for example, multiple times. For example, the conductive pillars or a portion thereof may be formed in an electroplating process separate from an electroplating process for forming the electrically conductive pads.

The electrically conductive pads and/or posts can include any of a variety of features. The electrically conductive pads and/or posts may, for example, comprise plated copper. Also for example, the electrically conductive pads and/or posts may comprise one or more of any of a variety of materials (eg, copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, combinations thereof, Its alloy, etc.), but the scope of the disclosure is not limited thereto.

An example 200B is shown in Figure 2B. A conductive pad 210 electrically connected to the circuit pattern 131 above the interposer 100 and a conductive post 220 are formed on the upper surface of the crucible body 110. As suggested herein, the conductive pad 210 can be electrically connected to a semiconductor die, and the post 220 can be connected to another electrical device (eg, another semiconductor package, a substrate, a motherboard, etc. ). The electrically conductive pad 210 can be, for example, substantially flat. The conductive post 220 can be formed, for example, substantially like a cylinder that stands in a direction substantially perpendicular to the crucible body 110. As discussed herein, the conductive post 220 can be much higher than the electrically conductive pad 210. For example, the conductive pillar 220 can have an elongated length that is at least with the conductive pad 210, a conductive interconnect structure between the conductive pad 210 and a semiconductor die, and a combination of the semiconductor die. The thickness is the same.

Block 1120 can generally include forming one or more electrically conductive pads and/or conductive posts on the interposer. Thus, the scope of this disclosure should not be limited by the features of any particular type of electrically conductive pad or post, or by any particular manner of forming a conductive pad or post.

At block 1130, the method 1000 of the example can include attaching one or more semiconductor dies to the interposer (or redistribution (RD) structure). Block 1130 can include attaching the one or more semiconductor dies to the interposer in any of a variety of ways, non-limiting examples of which are provided herein.

The semiconductor die can include any of various types of semiconductor die Sign. For example, the semiconductor die can include a processor die, a memory die, a special application integrated circuit die, a general logic die, a generally active semiconductor component, and the like. It is noted that the passive member can also be attached at block 1130.

Block 1130 can include attaching the semiconductor die in any of a variety of ways (e.g., as prepared at block 1107), non-limiting examples of which are provided herein. For example, block 1130 can include attaching the semiconductor die using mass reflow, thermocompression bonding (TCB), conductive epoxy, or the like.

2C is an illustration 200C showing an example of various features of block 1130 (eg, die attach features). For example, the semiconductor die 310 (eg, which may have been cut from a logic wafer prepared at block 1107) is electrically and mechanically attached to the interposer 100. Similarly, other dies (e.g., which may have been cut from a logic wafer prepared at block 1107) may also be electrically and mechanically attached to the interposer 100. For example, as illustrated in block 1107, the logic wafer (or its die) may be prepared to have various types formed thereon (eg, on one of its active sides, etc.) Interconnect structures (eg, conductive pads, regions, bumps, balls, wafer bumps, conductive posts, etc.). An example of such a structure is shown in FIG. 2C as a pad 320 and solder bumps 330 on the bottom (eg, active) side of the die 310. The solder bumps 330 can, for example, mechanically and electrically couple the pad 320 and the conductive pads 210 to each other (eg, through a reflow process). Block 1130 can include, for example, any of a variety of attachment processes (eg, mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.) to electrically and mechanically interconnect such interconnects. Attached to the interposer 100 (eg, a conductive pad 210 thereon).

In the example embodiment 200C shown in FIG. 2C, the post 220 is in the middle The height H1 of the upper end above the mediator 100 is greater than the height H2 of the upper side of the semiconductor die 310 above the interposer 100. Such a height difference can, for example, prevent a cover layer formed on the semiconductor die 310 from being removed during a thinning (or conductive pillar exposure) process of the encapsulating material described later. In an exemplary embodiment, the H1 is greater than the thickness of the H2-cladding layer (eg, as formed at block 1140). In an exemplary embodiment, the H1 is greater than the thickness of H2 over a cover layer (eg, as formed by block 1140), which may be, for example, encapsulated (eg, at block 1150) and thinned (eg, After block 1160), at least a portion of the molding material or other dielectric material is left on an upper side of the semiconductor die 310.

Although the example embodiment 200C of FIG. 2C is generally illustrated with a single die of each package region of the interposer 100 (eg, as would be singulated into a single package at block 1190), it should be understood Any number of dies and/or passive components can be incorporated into each package area. For example, each package area may include two grains, three grains, four grains, or more than four grains.

Block 1130 can also include underfilling semiconductor dies and/or other components attached to the interposer. Block 1130 can include performing such a primer fill in any of a variety of ways, non-limiting examples of which are provided herein.

For example, after die attach, block 1130 can include filling the semiconductor die with a capillary underfill to fill the semiconductor die. For example, the primer fill can include a sufficiently viscous reinforced polymeric material that flows between the attached semiconductor die and the interposer in a capillary action. Also for example, block 1130 can include utilizing a non-conductive paste (NCP) and/or a non-conductive film (NCF) when the die is attached to block 1130 (eg, using a thermocompression bonding process). Or tape, filling the semiconductor die with a primer. For example, such a primer filling material can be attached The semiconductor die is deposited (e.g., printed, sprayed, etc.) prior to being attached (e.g., as a pre-applied primer fill). The primer fill may comprise any of various types of materials, such as an epoxy resin, a thermoplastic material, a heat curable material, a polyimide, a polyurethane, a polymeric material, a filler epoxy, and a Filler thermoplastic material, a filler of heat curable material, filler polyimine, filler polyurethane, a filler polymerized material, a fluxed primer fill, and equivalents thereof, but are not limited thereto .

As with all of the blocks depicted in the method 1000 of this example, the block 1130 can be executed anywhere in the flow of the method 1000 as long as the space between the die and the interposer is accessible, ie can. This primer fill can also occur at a different block of the method 1000 of the example. For example, the primer fill can be performed as part of the encapsulation (or wafer molding) block 1150 (eg, with a molded backing).

FIG. 2C also provides various other features of block 1130, such as an illustration of an example of the underfill feature. The underfill 340 is disposed between the semiconductor die 310 and the interposer 100, for example, surrounding the pad 320, the solder bump 330, and the side surface of the conductive pad 210, and covering the semiconductor crystal. The lower surface of the pellet 310. It is noted that the semiconductor die 310, the pads 320, the solder bumps 330, and the underfill 340 may be referred to herein as a semiconductor module 300.

Although the underfill 340 is generally depicted as being confined to a region below the die 310 and does not cover any of the lateral sides of the semiconductor die 310, the underfill 340 may rise and A fillet is formed on the sides of the semiconductor die 310 and/or other components. In an exemplary scenario, at least a quarter or at least half of the lateral side surfaces of the die may be covered by the primer fill material 340. In another example scenario, One or more or all of the entire lateral side surfaces of the die 310 may be covered by the primer fill material 340. Also for example, a majority of the space directly between the semiconductor die 310 and other components (not shown), and/or between other components (not shown) may be filled with the primer fill material. For example, at least half of the space or the entire space between laterally adjacent semiconductor dies, between the dies and other components, and/or between other components may be filled with the underfill material. In an exemplary embodiment, the primer fill 340 can cover an entire portion of the interposer 100 between the semiconductor die 310 and an adjacent conductive pillar 220. In another exemplary embodiment, the primer fill 340 can cover the entire interposer 100. In such an exemplary embodiment, such cuts may also be cut through the primer fill 340 when the interposer 100 is later singulated (eg, at block 1190).

After the underfill fills the semiconductor die 310, the primer fill 340 can then be cured. The primer fill 340, for example, can protect a bump bond and/or other bond from external impact (eg, mechanical shock or corrosion) that may occur during or after a semiconductor package process.

In general, block 1130 can include attaching one or more semiconductor dies to the interposer (or RD structure). Thus, the scope of this disclosure should not be limited by the characteristics of any particular die, or by the features of any particular multi-die layout, or by any particularity to which such a die is attached. The characteristics of the way, and so on. Moreover, the scope of this disclosure should not be limited by any particular type of underfill filling feature, or any particular manner of forming such a primer fill.

At block 1140, the method 1000 of the example can include forming a cap layer on the interposer 100, the conductive posts 220, and/or the semiconductor module 300 (or portions thereof).

The cover layer can comprise any of a variety of materials. For example, the cover layer may comprise one or more layers of any of various dielectric materials, such as inorganic dielectric materials (eg, SiN, Si ₃ N ₄ , SiO ₂ , SiON, oxides, nitrides, etc.) and / or organic dielectric materials (for example, a polymer, polyimine (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), A phenol resin, an epoxy resin, etc.), but the scope of the disclosure is not limited thereto. It is noted that in an embodiment in which the cover layer comprises a plurality of layers, such layers may comprise different materials and/or may be performed using different individual processes.

The cover layer can utilize any one or more of a variety of processes (eg, in a chamber or other device) (eg, spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD) ), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), plasma gas Phase deposition (PVD), sheet stacking, etc. are formed, but the scope of the disclosure is not limited thereto.

The cover layer may, for example, comprise a uniform (or fixed) thickness. For example, the cover layer can include a continuous layer on and around any or all of the covered members. For example, the cover layer 400 can comprise a single continuous layer. In an exemplary embodiment, the cover layer 400 has an average thickness, and the thickness of the cover layer 400 does not vary by more than 25% (or more than 10%) from the average thickness. In an exemplary embodiment (eg, using a particular deposition process), the thickness of the cap layer 400 does not vary from the average thickness by more than 2%.

The cover layer 400 can be, for example, less than 1 micron thick, such as in the range of 0.1 to 1 micron. Also for example, the cover layer 400 can be less than 10 microns thick, For example, in the range of 1 to 10 microns.

2D is an illustration of an example 200D that provides various features of block 1140, such as features that form a cover layer. The cover layer 400 of this example is formed on all of the members of the illustrated assembly 200D that are exposed when the cover layer 400 is formed. For example, the cover layer 400 covers the exposed upper surface of the interposer 100 (for example, all of the upper side of the interposer 100 that is not covered by the conductive pad 210, the conductive post 220, the underfill 340, etc.) ). Also for example, the cover layer 400 covers the upper ends of the conductive pillars 220 and the lateral sides. Further, the cover layer 400 covers, for example, lateral sides and an upper side of the semiconductor die 310. Again, the cover layer 400 is, for example, a portion that covers the exposed portion of the primer fill 340 (eg, lateral sides).

The cover layer 400 is substantially continuous, for example, along any or all of the components of the assembly 200D (eg, between adjacent conductive pillars 220, at the semiconductor die 310 (or bottom) An upper surface of the interposer 100 of the glue fill 340) and the conductive pillars 220 adjacent thereto, etc., extends continuously. In an exemplary embodiment, the capping layer 400 is formed over a wafer of an entire package assembly. As shown herein, after singulation (e.g., at block 1190), a lateral side surface of the cover layer 400 will be exposed at a lateral side of each singulated semiconductor package. . Thus, the cover layer 400 can also extend continuously from any of the components of the illustrated assembly 200D to the lateral sides of the singulated package.

It is noted that the cover layer 400 can directly contact any or all of the components of the assembly 200D on which the cover layer 400 is formed. However, it is also possible to have one or more materials in between.

The capping layer 400 can, for example, operate to inhibit conductive ions from a conductive pillar 220 from migrating and/or diffusing into the semiconductor die 310. Moreover, the cover layer 400 can, for example, provide structural support (eg, prevent or inhibit warpage or distortion of the semiconductor package during and/or after fabrication).

In general, block 1140 can include forming a cap layer on the interposer 100, the conductive posts 220, and/or the semiconductor module 300 (or portions thereof). Thus, the scope of this disclosure should not be limited by the characteristics of any particular overlay and/or the manner in which it is formed.

At block 1150, the method 1000 of the example can include encapsulating the component (either a wafer or a support structure). Block 1150 can, for example, comprise any of a variety of encapsulating materials (eg, a resin, a polymer, a polymer composite (eg, an epoxy having a filler, an epoxy acrylate having a filler, or having one) Suitable filler polymer), etc.). Block 1150 can include performing such a capsule in any of a variety of ways (eg, compression molding, transfer molding, liquid encapsulating material molding, vacuum lamination, paste printing, film assisted molding, etc.) seal.

For example, block 1150 can include molding the interposer 100 at a wafer level. For example, block 1150 can include pads, posts formed over block 1120 over the upper side of the wafer of the interposer 100, over the die and/or other components attached to block 1130. Or other interconnect structures, over the underfill formed by block 1130, over the cap formed by block 1140, and the like. In general, block 1150 can include molding on an upper surface and/or portion of any of such components that is exposed when the molding (or encapsulation) process is performed.

2E is an illustration 200E showing an example of various features (eg, molding features) of block 1150. For example, the molding assembly 200E is shown with the molding material 20 covering the conductive pillars 220, the semiconductor die 310, the primer fill 340, and the upper surface of the interposer 100. For example, the molding material 20 may completely surround the post 220 and may, for example, at least temporarily cover the upper end of the conductive post 220. Although the molding material 20 (which may also be referred to herein as an encapsulating material) is shown to completely cover the lateral sides and the upper side of the semiconductor die 310, this need not be the case. For example, block 1150 can include utilizing a film assist or die seal molding technique to maintain the upper side of the die free of molding material.

The molding material 20 can cover, for example, all of the exposed surfaces of the cover layer 400 formed by the block 1140. For example, the molding material 20 can directly contact the cover layer 400. In an exemplary embodiment, the cover layer 400 may also directly contact the upper side of the interposer 100, the conductive post 220, the underfill fill 340, and/or any or all of the semiconductor die 310. For example, the cover layer 400 can completely isolate other components of the example assembly 200E without direct contact with the molding material 20.

It is noted that the molding material 20 in the illustrated example is much thicker than the cover layer 400. For example, the molding material 20 may be more than 10 times thicker than the cover layer 400, or more than 100 times thicker.

In general, block 1150 can include a wafer that encapsulates the component (or wafer), such as a molded package component. Thus, the scope of this disclosure should not be limited by the characteristics of any particular molding material, structure, and/or technique.

At block 1160, the method 1000 of this example can include thinning the encapsulation material formed at block 1150. Block 1160 can include thinning the encapsulating material in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 1160 can include thinning by mechanical grinding or cutting, laser removal or other guided energy removal processes, chemical etching or other chemical removal processes, any combination thereof, and the like. The encapsulating material.

In an exemplary embodiment, the block 1160 includes a molding material (or encapsulating material) that is formed by grinding the block 1150. Block 1160 can, for example, include mechanically grinding (e.g., using a diamond grinder, etc.) the molding material to thin the molding material. Such thinning may, for example, cause the die and/or interconnect structure to be overmolded, or such thinning may expose one or more of the die and/or one or more interconnect structures (eg, one Or multiple conductive columns).

Block 1160 may, for example, include grinding other components than the molding material. For example, block 1160 can include grinding a tip of a conductive post formed at block 1120, for example, including polishing a cover layer 400 formed on the upper ends of the conductive posts. Such grinding can, for example, result in a flat planar surface on the top side of the ground component.

It is noted that in an embodiment in which the encapsulating material was originally formed to the desired thickness, block 1160 can be skipped. In such an example embodiment, block 1160, for example, can include stripping the cover layer 400 from the ends of the conductive posts, if necessary.

2F is an illustration of an example of various features of block 1160 (eg, features of the molded grinding). The assembly 200F is depicted as wherein the molding material 20 (eg, relative to the molding material 20 depicted in FIG. 200E) is thinned to expose an upper end surface of the conductive post 220. It is noted that in this example embodiment, the cover layer 400 formed on the upper end of the conductive pillar 220 at the block 1140 is removed during the grinding (eg, mechanically removed, etc. ). A portion of the conductive pillars 220 can also be ground to cause the conductive pillars 220 and/or molding material 20 to reach a desired height (or thickness). In an exemplary scenario, block 1160 also removes molding material 20 over the upper side of semiconductor die 310, such as to expose conductive layer 400 formed over die 310. For example, block 1160 can be performed until it reaches the cap layer 400 over the semiconductor die 310.

In the exemplary assembly 200F of the example shown in FIG. 2F, the cover layer 400 is removed from the upper end of the conductive post 220 after or during removal of the molding material, but still maintains the conductive post 220. The lateral side of the landscape. The cover layer 400 covers the lateral sides of the semiconductor die 310 and the underfill 340 and also continuously covers the upper side of the semiconductor die 310. In the illustrated example, the molding material 20 has been removed to a degree that exposes the cover layer 400 from the upper side of the molding material 20 (eg, the cover layer 400 is in the semiconductor die 310) The upper portion, a portion of the cover layer 400 on the lateral side of the conductive post 220, and the like). It is noted that in another exemplary embodiment, in addition to the cover layer 400, certain molding materials 20 may be left to cover the upper side of the die 310. In the illustrated example, the upper end of the conductive pillar 220 (eg, from the interposer 100) is higher than the thickness of the cap layer 400 above the die 310 above the upper side of the semiconductor die 310. It is also noted that the cover layer 400 extends upwardly from the lateral sides of the conductive pillars 220 to a height greater than the height of the semiconductor die 310. For example, the cover layer 400 extends upward from a lateral side of the conductive pillar 220 to a height equal to or greater than a height of the upper side of the cover layer 400 above the semiconductor die 310.

In general, block 1160 can include an encapsulation material that is thinned out at block 1150. Thus, the scope of this disclosure should not be limited by the features of any particular manner of thinning an encapsulating material (or molding material).

At block 1170, the method 100 of the example can include removing the wafer 10 (or support structure). Block 1170 can include removing the wafer 10 in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 1170 can include debonding (or separating) wafer 10 (or support structure) disposed at block 1110. Block 1170 can be included in various ways Any of these can be performed to perform such debonding, and its non-limiting features are set forth herein.

For example, in an exemplary scenario in which the interposer 100 is adhesively attached to the wafer 10, the adhesive can be disengaged (e.g., utilizing heat and/or force). Also for example, a chemical release agent can be utilized. In another example scenario in which the wafer support is attached using a vacuum force, the vacuum force can be removed. It is noted that in the context of an adhesive or other material to aid in the attachment of the wafer support, the block 1170 may include from the interposer 100 and/or from the debond after the debonding Wafer support 10 removes residue.

In another example scenario in which the interposer 100 is directly constructed on the wafer 10, the wafer 10 can be removed, for example, by mechanical and/or chemical techniques. For example, block 1170 can include mechanically grinding the wafer 10, and chemical etching can also be utilized to remove at least portions of the wafer 10. For example, block 1170 can include performing chemical mechanical planarization (CMP) (or polishing).

2F and 2G are diagrams 200F and 200G providing examples of various features of block 1170. For example, the wafer 10 depicted in Figure 2F is removed in Figure 2G. The underlying circuit pattern 132 is thus exposed during the wafer (or support) removal process for electrical and/or mechanical connections to interconnect structures as discussed herein.

In general, block 1170 can include removing the wafer (or support structure). Thus, the scope of this disclosure should not be limited by the features of any particular type of wafer support or by any particular manner of removing a wafer support.

At block 1180, the method 1000 of the example can include forming an interconnect structure. For example, the block 1180 can include an interconnection formed on the lower surface (or the side) of the interposer (eg, the underlying circuit pattern 132) exposed by the support wafer on the removal of the block 1170. Structure For example, package interconnect structure). Block 1180 can include any of a variety of ways to form the interconnect structures, non-limiting examples of which are provided herein.

Block 1180, for example, can include a bump bottom metallization (UBM) formed on the portion of the underlying circuit pattern 132 that is exposed by the removal of the support wafer 10. For example, the pads of the underlying circuit pattern 132 can be exposed through individual holes in a dielectric layer. Block 1180, for example, can include forming a bump bottom metallization on the exposed portion of the underlying circuit pattern 132. Non-limiting examples of the formation of such UBMs and/or the formation of interconnect structures are presented herein, for example, in relation to block 1107. It is noted that such bump bottom metallization does not need to be performed.

Block 1180 can then, for example, include attaching a conductive bump, or ball, or post, or other structure to the bump bottom metallization. Other interconnect structures can also be utilized, examples of which are presented herein (e.g., conductive pillars or pillars, solder balls, solder bumps, etc.).

2H is an illustration 200H that provides an example of various features of block 1180 (eg, forming features of the interconnect structure). For example, interconnect structure 30 (eg, conductive balls or bumps, conductive posts or pillars, etc.) is attached to the underlying circuit pattern 132 and/or the UBM formed thereon. It is noted that although the interconnect structures 30 are depicted as being smaller than the interconnect structures 320, this disclosure is not limited thereto. For example, the interconnect structures 30 may be the same size as the interconnect structures 320 or larger than the interconnect structures 320. Moreover, the interconnect structures 30 may be of the same type of interconnect structure as the interconnect structures 320, or may be of different types. Also for example, the interconnect structures 30 may be formed using the same type of process as the interconnect structures 320, or may be formed using different types of processes (eg, electroplating relative to falling balls, solder coverage, etc.) Attached to the solder ball, etc.).

Although the interposer 100 and the interconnect structure 30 are depicted generally in FIG. 2H in a fan-out configuration (eg, extending beyond the footprint of the die 310), they may alternatively and/or simultaneously be used. A fan-in configuration, such as where the interconnect structures 30 do not extend substantially beyond the footprint of the die 310.

In general, block 1180 can include forming an interconnect structure. Thus, the scope of this disclosure should not be limited by the features of any particular interconnect structure or by any particular way of forming the interconnect structure.

At block 1190, the method 1000 of the example can include singulating individual semiconductor packages from the wafer assembly. Again, such singulation may be referred to as dicing (eg, cutting from the interposer 100, or one of its wafers or panels). Block 1190 can include singulation of the wafer in any of a variety of ways, non-limiting examples of which are provided herein.

The discussion herein has focused primarily on the processing and/or structure of a single interposer and/or semiconductor package in a package of a wafer (or panel). Such a single interposer and/or semiconductor package that is focused on a wafer is for illustrative purposes only. It should be understood that all of the process steps discussed herein can be performed on a single wafer. For example, each of the illustrations presented in Figures 2A-2I and other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, prior to dicing, there may be no separation between one of the illustrated components and an adjacent one of such components of a wafer.

Block 1190 can include, for example, individual singulations from the wafer (eg, mechanical stamping, mechanical saw cutting, laser cutting, soft jet cutting, plasma cutting, etc.). The end result of such singulation can be, for example, the package 200I shown in Figure 2I. For example, the singulation may form a side surface of the package 200I, and the side surfaces include the package 200I Coplanar side surfaces of a plurality of members. For example, any or all of the side surfaces of the molding material 20, the cover layer 400, the interposer 100 (or any or all of the layers thereof), and the like may be on the lateral side of the package 200I. Coplanar.

In general, block 1190 can, for example, include singulating the wafer from the wafer assembly. Thus, the scope of this disclosure should not be limited by the characteristics of any particular way of singulation.

As discussed herein in the discussion of FIGS. 1 and 2, the block 1160 can include thinning the encapsulating material, for example, to expose the top ends of the conductive posts for exposure on the top end of the die. A cover layer, a top surface for exposing the die, etc., but such thinning can be skipped, or only partially performed. In an exemplary embodiment, the conductive posts can be exposed from the encapsulating material by removing individual portions of the encapsulating material (eg, by ablation, etc.). Examples of such methods and/or structures, as well as other methods and/or structural features, will now be discussed with reference to Figures 3 and 4A-4H.

At block 3107, the method 3000 of the example can include preparing a logic wafer for processing (eg, for packaging). Block 3107 may, for example, share any or all of the features with block 1107 of method 1000 of the example of FIG. Block 3107, for example, can include preparing the logic wafer for processing in any of a variety of ways.

At block 3110, the method 3000 of the example can include preparing an interposer wafer (or panel). Block 3110 may, for example, share any or all of the features with block 1110 of method 1000 of the example of FIG. Block 3110, for example, can include preparing an interposer wafer in any of a variety of ways. FIG. 4A is a diagram 400A showing an example of various features of block 3110. An example of the illustration 400A may be shared with the illustration 200A of the example of FIG. 2A, for example. Or all the features.

At block 3120, the method 3000 of the example can include forming one or more electrically conductive pads and/or conductive posts (or pillars) on the interposer. Block 3120 may, for example, share any or all of the features with block 1120 of method 1000 of the example of FIG. Block 3120, for example, can include preparing an interposer wafer in any of a variety of ways. FIG. 4B is an illustration 400B that provides an example of various features of block 3120. The illustrated illustration 400B may, for example, share any or all of the features with the illustration 200B of the example of FIG. 2B.

At block 3130, the method 3000 of the example can include attaching one or more semiconductor dies to the interposer (or RD structure). Block 3130 may, for example, share any or all of the features with block 1130 of method 1000 of the example of FIG. Block 3130, for example, can include attaching one or more semiconductor dies in any of a variety of ways. 4C is an illustration 400C that provides an example of various features of block 3130. The illustrated illustration 400C may, for example, share any or all of the features with the illustration 200C of the example of FIG. 2C.

At block 3140, the method 3000 of the example can include forming a cap layer on the interposer 100, the conductive posts 220, and/or the semiconductor module 300 (or portions thereof). Block 3140 may, for example, share any or all of the features with block 1140 of method 1000 of the example of FIG. Block 3140, for example, can include forming a cover layer in any of a variety of ways. 4D is an illustration 400D that provides an example of various features of block 3140. The illustrated illustration 400D may, for example, share any or all of the features with the illustration 200D of the example of FIG. 2D.

At block 3150, the method 3000 of the example can include encapsulating the component (or wafer). Block 3140 may, for example, share any or all of the features with block 1150 of method 1000 of the example of FIG. Block 3150 can, for example, include encapsulating the device in any of a variety of ways. Component (or wafer). 4E is an illustration 400E that provides an example of various features of block 3150. The illustrated illustration 400E may share any or all of the features, for example, with the illustration 200E of the example of FIG. 2E.

At block 3160, the method 3000 of the example can include exposing the conductive pillars (eg, as formed at block 3120). Block 3160 may, for example, share any or all of the features with block 1160 of method 1000 of the example of FIG. Block 3160 can expose the conductive posts in any of a variety of ways, non-limiting examples of which are provided herein.

For example, block 3160 can include abrading (or removing) molding material over the conductive posts to expose at least an end surface above one of them. Block 3160 can include, for example, mechanical ablation (or drilling), laser ablation (or drilling), chemical etching (or drilling), soft beam ablation (or drilling), and the like. Further, block 3160 can, for example, include removing the cover layer from the upper end of the conductive post.

FIG. 4F is an illustration of an example 400F that provides various features of block 3160 (eg, features that expose conductive posts). The illustrated illustration 400E may share any or all of the features, for example, with the illustration 200E of the example of FIG. 2E.

As discussed herein, for example, in the discussion of FIGS. 1 and 2, the upper side of the semiconductor die 310 can be covered by both the capping layer 400 and the molding material 20. In the exemplary embodiment depicted in FIG. 4F, the upper end of the conductive post 220 is recessed below the upper side of the molding material 20. The molding material 20 over the upper end of the conductive post 220 (eg, together with the cover layer 400 formed on the block 3140 on such an upper end) has been removed, thus providing a conductive Connected to the upper end of the conductive post 220. For example, another semiconductor package, another interposer, an additional redistribution structure layer, any of a variety of different types of interconnect structures, etc. The electrode can be electrically connected to the exposed upper end of the conductive post 220.

The conductive pillars 220 are shown to be higher than the semiconductor die 310. For example, the upper end of the conductive pillar 220 is higher than the upper side of the semiconductor die 310. However, the situation does not need to be the case. For example, the upper end of the conductive pillar 220 may be at a height lower than the upper side of the semiconductor die 310. Also for example, the upper end of the conductive pillar 220 may be at a height between the heights on the upper side and the lower side of the semiconductor die 310. In an exemplary embodiment, a hole formed in the molding material 20 to expose the upper end of the conductive post 220 may extend to a depth below the upper side of the semiconductor die.

Although the holes formed in the molding material 20 to expose the conductive pillars 220 are shown as having the same width as the conductive pillars 220 (for example, they are covered on the lateral sides of the conductive pillars 220). The thickness of layer 400), but this need not be the case. For example, the aperture can be wider than the conductive pillar 220 and/or wider than the combination of the thickness of the conductive pillar 220 and the cover layer 400. Moreover, the aperture may be, for example, only as wide (or narrower) as the top end of the conductive post 220, such as the cover layer 400 that is not exposed on the lateral sides of the conductive post 220. Again, although the hole system is generally depicted as having vertical sidewalls, this need not be the case. For example, the sidewall of the aperture can be sloped. For example, the aperture may be wider at the upper end (eg, on the upper side of the molding material 20) than at the lower end (eg, at or near the upper end of the conductive post 220).

Moreover, although the cover layer 400 is shown in FIG. 4F as covering the entire lateral side of the conductive post 220, this need not be the case. For example, at least an upper portion of the lateral sides of the conductive pillar 220 (eg, and an upper end of the conductive pillar 220) may be exposed from the cover layer 400. In an exemplary embodiment, utilized to expose the guide The same process (or a different process) of the upper end of the post 220 can remove a portion of the cover layer 400 on an upper portion of the lateral sides of the conductive post 220.

In general, block 3160 can include exposing the conductive posts. Thus, the scope of this disclosure should not be limited by the features of any particular way of performing such disclosure.

At block 3170, the method 3000 of this example can include removing the wafer 10 (or support structure) and forming an interconnect structure. Block 3170 may, for example, share any or all of the features with blocks 1170 and 1180 of method 1000 of the example of FIG. Block 3170 can include removing the wafer 10 and forming an interconnect structure in any of a variety of ways. 4F and 4G are diagrams 400F and 400G providing examples of various features of block 3170. For example, the wafer 10 shown in FIG. 4F is not present in FIG. 4G. Further, an interconnection structure 30 is formed on the lower side of the interposer 100 in FIG. 4G, for example, attached to the underlying circuit pattern 132.

At block 3190, the method 3000 of the example can include singulating individual semiconductor packages from the wafer assembly. Block 3190 may, for example, share any or all of the features with block 1190 of method 1000 of the example of FIG. Block 3190, for example, can include singulating the semiconductor package in any of a variety of ways. Figure 4H provides a package 400H that can be derived from an example of such singulation.

The discussion herein includes a number of illustrative figures showing various portions of a semiconductor package assembly and methods of making the same. For the sake of clarity of illustration, such figures do not show all of the features of each of the example components. Any of the components and/or methods of the examples presented herein may share any or all of the features with any or all of the other components and/or methods set forth herein. For example and without limitation, any or all of the components and/or methods of the examples shown and discussed with respect to Figures 1 and 2 may be incorporated in relation to Figures 3 and 4 Any of the components and/or methods of the examples discussed. Rather, any of the components and/or methods disclosed and discussed with respect to FIGS. 3 and 4 can be incorporated into the components and/or methods illustrated and discussed with respect to FIGS. 1 and 2.

In summary, various features of this disclosure provide a semiconductor package and a method of fabricating a semiconductor package. By way of non-limiting example, various features of this disclosure provide various semiconductor packages and methods of making the same, including a cover layer that enhances the reliability of the semiconductor package. Although the foregoing has been described with reference to certain features and examples, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure. Therefore, it is intended that the present disclosure not be limited to the specific examples disclosed, but the disclosure is intended to cover all of the examples within the scope of the appended claims.

20‧‧‧Molded materials

30‧‧‧Interconnect structure

100‧‧‧Intermediary

200I‧‧‧ package

220‧‧‧conductive column

300‧‧‧Semiconductor Module

310‧‧‧Semiconductor grain

320‧‧‧ solder pads

330‧‧‧ solder bumps

340‧‧‧Bottom glue filling (material)

400‧‧‧ Coverage

Claims (20)

A semiconductor package comprising: a redistribution (RD) structure including an upper RD side, a lower RD side, and a lateral direction extending between the upper RD side and the lower RD side RD side; a conductive pad on the upper RD side; a conductive post on the upper RD side, the conductive column includes an upper column end, a lower column end, And a lateral column side extending between the upper column end and the lower column end; a semiconductor die attached to the upper RD side and electrically connected to the conductive pad; a cover layer And covering at least a portion of the semiconductor die and at least a portion of the conductive pillar; and an encapsulating material covering at least a portion of the cap layer, at least a portion of the semiconductor die, and at least a portion of the conductive pillar . The semiconductor package of claim 1, wherein the cover layer is a continuous layer of dielectric material. The semiconductor package of claim 1, wherein the cover layer extends upward from the lateral side of the lateral pillar by a height higher than an upper side of the semiconductor die and covers an upper side of the semiconductor die. The semiconductor package of claim 1, wherein the cover layer has a substantially uniform thickness. The semiconductor package of claim 1, wherein a lateral side of the cover layer, a lateral side of the RD structure, and a lateral side of the encapsulation material are coplanar. The semiconductor package of claim 1, wherein the cover layer directly contacts the conductive pillar and the semiconductor die. The semiconductor package of claim 1, wherein the cover layer is over the RD structure and extends laterally from the semiconductor die to the conductive post. The semiconductor package of claim 1, wherein the cover layer is interposed between the encapsulation material and the RD structure and maintains the encapsulation material and the RD structure. The semiconductor package of claim 1, wherein a continuous portion of the cover layer covers the lateral pillar sides and extends to a lateral side of the semiconductor package. The semiconductor package of claim 1, comprising a primer filling material between the semiconductor die and the upper RD side, and wherein the covering layer covers one side surface of the primer filling material . A semiconductor package comprising: a redistribution (RD) structure including an upper RD side, a lower RD side, and a lateral direction extending between the upper RD side and the lower RD side RD side; a conductive pad on the upper RD side; a conductive post on the upper RD side, the conductive column includes an upper column end, a lower column end, And a lateral column side extending between the upper column end and the lower column end; a semiconductor die attached to the upper RD side and electrically connected to the conductive pad; a cover layer And covering at least a portion of the conductive pillar and at least a portion of the RD structure; and an encapsulating material covering at least a portion of the cap layer, at least a portion of the semiconductor die a portion, and at least a portion of the conductive pillar. The semiconductor package of claim 11, wherein the cover layer is a continuous layer of dielectric material. The semiconductor package of claim 11, wherein the cover layer is over the RD structure and extends laterally from the conductive post to a second conductive post. The semiconductor package of claim 11, wherein a continuous portion of the cover layer covers the lateral pillar sides and extends to a lateral side of the semiconductor package. The semiconductor package of claim 11, comprising a primer filling material between the semiconductor die and the upper RD side, and wherein the covering layer covers one side surface of the underfill material . A semiconductor package comprising: a redistribution (RD) structure including an upper RD side, a lower RD side, and a lateral direction extending between the upper RD side and the lower RD side RD side; a conductive pad on the upper RD side; a conductive post on the upper RD side, the conductive column includes an upper column end, a lower column end, And a lateral column side extending between the upper column end and the lower column end; a semiconductor die attached to the upper RD side and electrically connected to the conductive pad; a cover layer And covering at least a portion of the semiconductor die and at least a portion of the RD structure; and an encapsulating material covering at least a portion of the cap layer, at least a portion of the semiconductor die, and at least a portion of the conductive pillar . The semiconductor package of claim 16 wherein the cover layer is a continuous layer of dielectric material. The semiconductor package of claim 16 wherein the cover layer is over the RD structure and extends laterally from the semiconductor die toward the conductive pillar. The semiconductor package of claim 16 wherein a continuous portion of the cover layer covers a lateral side of the semiconductor die and extends to a lateral side of the semiconductor package. The semiconductor package of claim 16, wherein the cover layer covers an upper side of the semiconductor die and a lateral side.