TW201643995A - Power semiconductor device and the fabricating method thereof - Google Patents

Abstract

Present invention relates to a power semiconductor device and the fabricating method thereof. Two paddles are arranged side by side and each of the paddles has a semiconductor chip attached on its top surface, and an interconnection board is used for connecting one part of electrodes of first and second semiconductor chip to a same second lead, and a first conductive structure is used for connecting other part of electrodes of the first chip to a first lead, while a second conductive structure is used for connecting other part of electrodes of the second chip to a third lead.

Description

Power semiconductor device and preparation method thereof

The present invention generally relates to a power semiconductor device, and more particularly to a power semiconductor package device for use as a power switch, and a method of fabricating the same.

In a conventional power conversion system, a voltage is modulated by a switch to output a final output voltage having a small ripple, and the switch is related to a power semiconductor device. In the prior art packaging device of FIG. 1, the power transistor T1 is mounted on a metal base, the power transistor T2 is mounted on another metal base, and the source of the transistor T1 is wire-bonded to the pin S1. The gate of the transistor T1 is wire-bonded to the pin G1, the source of the transistor T2 is wire-bonded to the pin S2, and the gate of the transistor T2 is wire-bonded to the pin G2. In some power conversion systems, a common source connection of a dual chip is involved. For example, the dual source common source common source connection of the dual chip of FIG. 1 can be implemented at the board level, specifically soldering the pins S1 and S2 to the circuit board at the same time. A common pad on the other or the pins S1, S2 are coupled together by other conductive paths. The prior art has yet to be improved in optimizing the inter-source communication path of the bimorph, especially requiring no additional device size.

In an alternative embodiment of the present invention, a power semiconductor device is provided comprising: a pair of pedestals disposed side by side; and a pair of wafers each having a wafer adhered thereto; a first, second, and third pin nearby; an interconnecting plate that electrically connects a portion of the electrodes of each of the two wafers to the second pin; and connects another portion of the electrode of one of the wafers to one of the first pins A conductive structure and another conductive structure connecting another portion of the electrode of the other wafer to the third pin.

In the above power semiconductor device, the interconnection board has a T-shaped structure including a first portion and a second portion perpendicular to the first portion; the first portion spans over a pair of wafers on the susceptor, and one end portion of the first portion is adhered One electrode to the top surface of one wafer and the other end of the first portion are adhered to one electrode on the top surface of the other wafer; a free end of the second portion is first bent downward and then extended along the level to form an underlying structure Press against and bond to the second pin.

In the above power semiconductor device, the second pin is located on the dividing line between the pair of pedestals, and the first and third pins are respectively located on two sides of the second pin, and the two conductive structures are respectively located in the second part of the interconnecting board The two sides are arranged and mirrored symmetrically with each other with the second portion as the axis of symmetry.

In the above power semiconductor device, one or more through holes penetrating through their respective thicknesses are provided on the first portion and the second portion of the interconnection board.

In the above power semiconductor device, the conductive structure is a metal lead.

In the above power semiconductor device, the conductive structure is a metal piece including a base portion and an extending piece, a contact portion is extended inward on an inner side edge of the extending piece, and an outer side edge is provided on the outer side edge of the base portion but has a low position The underlying structure of the base and the extension piece; the contact portion of each of the conductive structures is correspondingly adhered to one electrode of one of the wafers, wherein the underlying structure of one of the conductive structures is correspondingly adhered to the first pin, and the other of the conductive structures The underlying structure is attached to the third pin.

In the above power semiconductor device, the extension piece is thinner than the base portion, and the thickness of the base portion is the same as the thickness of the contact portion.

In the above power semiconductor device, a mesa structure for carrying a wafer protruding from a top surface of the pedestal is disposed on a top surface of each of the pedestals; and at least one or more of the top surfaces of the second pins are disposed on the top surface of each of the pedestals a post protruding from the top surface of the second pin for carrying the underlying structure of the free end of the second portion of the interconnecting plate.

In the above power semiconductor device, the pair of wafers are power metal oxide semiconductor field effect transistors (MOSFETs), and the source of each of the top surfaces of the pair of wafers is electrically connected through the interconnection board, and the drain of the bottom surface of each wafer passes through The conductive adhesive material is electrically connected to the susceptor carrying the wafer, and the respective gates of the pair of wafers are electrically connected to the first and third leads, respectively.

The power semiconductor device further includes a molding body covering the pedestal and the first, second and third pins and the wafer, the conductive structure and the interconnection board, at least the first, second and third pins and the base The bottom surfaces of the seats are exposed on the bottom surface of the molded body.

In another embodiment of the present invention, a method of fabricating a power semiconductor device is provided, comprising the steps of: providing a lead frame comprising a plurality of mounting units, each mounting unit comprising at least a pair of pedestals disposed side by side and located First, second and third pins adjacent to the pedestal; one wafer is attached to each pedestal; two wafers placed on each mounting unit and a second pin of the mounting unit are pasted An interconnection board, wherein a part of electrodes of each of the two wafers on each mounting unit are electrically connected to the second pin of the mounting unit by the interconnection board; and another part of the electrodes of one wafer on each mounting unit is connected by a conductive structure Connecting to the first pin and connecting another portion of the other wafer on the mounting unit to the third pin; performing a laminating process, coating the lead frame and the wafer, the interconnecting plate, and the conductive structure with a plastic sealing layer; cutting the plastic sealing layer And the lead frame separates the mounting unit and the molding body forming the cladding mounting unit and the respective wafers, the respective conductive structures and the interconnection plates.

In the above method, in each mounting unit, the second pin is disposed on a dividing line between the pair of pedestals of the mounting unit, and the first and third pins of the mounting unit are collinear with the second pin The first and third pins are respectively arranged on both sides of the second pin.

In the above method, the conductive structure is a metal lead, and the metal wire is bonded between the wafer and the first and third pins after the bonding step of the interconnection board is completed or before the bonding step of the interconnection board is performed.

In the above method, the interconnection board is presented in a T-shaped structure including a first portion and a second portion perpendicular to the first portion, in the step of adhering the interconnection board: one end of the first portion is adhered to one wafer on each mounting unit One electrode of the top surface and the other end of the first portion are adhered to one electrode of the top surface of the other wafer on the mounting unit; a free end of the second portion is first bent downward and then extended along the level to form an underlying structure To resist and adhere to the second pin of the mounting unit.

In the above method, the conductive structure is a metal piece, and the two conductive structures are respectively located on two sides of the second portion of one of the interconnecting plates, and the two conductive structures are disposed such that the second portion of the interconnecting plate is an axis of symmetry and is mirror-symmetrical to each other.

In the above method, the conductive structure and the interconnection board are simultaneously adhered to the two wafers disposed on each of the mounting units and the first and third pins of the mounting unit.

In the above method, the conductive structure is a metal piece including a base portion and an extending piece, and a contact portion extends inwardly on an inner side edge of the extending piece, and an outer side extending on the outer side edge of the base portion but positioned lower than the base portion and the extending piece The lower structure, in the step of installing the conductive structure: two conductive structures are adhered on each mounting unit, wherein a contact portion of one conductive structure is adhered to one electrode of one of the mounting units and the lower structure corresponds to Adhered to the first pin, the contact portion of the other conductive structure is adhered to one electrode of the other wafer in the mounting unit and the underlying structure is adhered to the third pin.

In the above method, the extension piece is thinner than the base portion, and the thickness of the base portion is the same as the thickness of the contact portion.

In the above method, a top surface of each of the pedestals is provided with a mesa structure protruding from the top surface of the susceptor for carrying and pasting the wafer; and at least one or more of the top surfaces of the second pins are disposed A post protruding from the top surface of the second pin for carrying and adhering the underlying structure of the free end of the second portion of the interconnecting board.

In the above method, the pair of wafers are power metal oxide semiconductor field effect transistors (MOSFETs), and the sources of the top surfaces of the pair of wafers are electrically connected together through the interconnection board, and the drain of the bottom surface of each wafer is electrically conductively bonded. The material is electrically connected to the susceptor carrying the wafer, and the respective gates of the pair of wafers are electrically connected to the first and third pins, respectively.

In the above method, in the cutting step, each of the molding bodies formed by cutting the plastic sealing layer is coated with a mounting unit and a wafer, a conductive structure and an interconnection board mounted on the mounting unit, at least the first and the first of the mounting unit The bottom surfaces of the second and third pins and the base are exposed on the bottom surface of the molded body.

In an alternative embodiment of the present invention, a power semiconductor device is disclosed comprising: a pair of pedestals disposed side by side; a pair of wafers each having a wafer adhered thereto, each wafer including a bottom portion An electrode and a top second and third electrode, the bottom first electrode of each wafer being electrically connected to the corresponding pedestal; the first, second and third pins located adjacent the pair of pedestals; one of the two The second electrode of each of the wafers is simultaneously electrically connected to the interconnecting plate of the second pin, the interconnecting plate exhibiting a T-shaped structure including a first portion and a second portion perpendicular to the first portion, wherein the first portion spans Above the pair of wafers on the pedestal, the two ends of the first portion are respectively adhered to the second electrodes of the top surface of the pair of wafers, and a free end of the second portion is first bent downwards Extending along the level to form an underlying structure for resisting and bonding to the second pin; connecting the third electrode of one wafer to one conductive structure of the first pin and the third of the other wafer Electrode connected to the first Another conductive structure of three pins; wherein at least a top surface of the second pin is provided with one or more posts protruding from the top surface of the second pin for carrying the free end of the second portion of the interconnecting board Under structure.

In an alternative embodiment of the invention, a method of fabricating a power semiconductor device is disclosed, comprising the steps of providing a leadframe comprising a plurality of mounting units, each mounting unit comprising at least a pair of pedestals disposed side by side and located First, second and third pins adjacent to the pair of pedestals; a wafer is attached to each of the pedestals, each wafer comprising a bottom first electrode and a top second and third electrode, each wafer The bottom first electrode is electrically connected to the corresponding base; the two wafers disposed on each mounting unit and the second pin of the mounting unit are pasted with an interconnection board, so that each of the two mounting units on the mounting unit The top second electrode is electrically connected to the second pin of the mounting unit by the interconnection board; the third electrode of one wafer on each mounting unit is connected to the first pin by using a conductive structure and the other on the mounting unit a third electrode of a wafer is connected to the third pin; performing a laminating process, coating the lead frame and the wafer, the interconnecting plate, the conductive structure with a plastic sealing layer; cutting the plastic sealing layer and the lead frame, Separating the mounting unit and the molding body forming the cladding mounting unit and the wafer, the conductive structure and the interconnection board, each of the molding bodies formed by cutting the plastic sealing layer is coated with a mounting unit and a wafer and a conductive structure mounted on the mounting unit And the interconnection board, at least the bottom surfaces of the first, second and third pins of the mounting unit and the base are exposed on the bottom surface of the molding body.

Referring to Figure 2, there is shown a top plan view of a portion of a generally lead metal frame 100 having a plurality of illustrated wafer mounting units 101, as shown in Figure 3, each wafer mounting unit 101 including at least The pedestals 111, 112 and the first pin 113, the second pin 114, and the third pin 115 are disconnected from each other. In an alternative embodiment, two split pedestals 111, 112 of generally configured elongated cubes or cubes are arranged side by side, and the second pin 114 is located at a line of symmetry or dividing line between the pedestals 111, 112. 230 on. In some alternative embodiments, pedestals 111 and 112 are mirror symmetrical with split line 230 as a line of symmetry. The first pin 113, the second pin 114, and the third pin 115 are substantially collinear, and the first pin 113 and the third pin 115 are respectively disposed on both sides of the second pin 114. . These pins and pedestals are connected to the lateral or longitudinal lead frame edges of the lead frame 100 by a plurality of ribs 150 to hold the mounting unit 101, wherein each pedestal has two on each of the adjacent two lead frames. The rib 150 is connected to the lead frame, and on the side of the common lead frame of the pedestals 111, 112 which are disconnected from each other, one rib is disposed at a substantially central position of the pedestal, and the other rib is disposed adjacent to the pedestal 111, 112. Disconnected positions to achieve stability of the pedestal during wafer mounting. The present invention also performs some additional processing on the mounting unit 101, for example, the lead frame 100 is subjected to a similar process such as half etching or stamping/imprinting, and in FIG. 3, etching or stamping is performed on the top side of the susceptor 111. Forming a convex top mesa structure 111a, etching or stamping on the top side of the pedestal 112 to form a convex top mesa structure 112a, as an optional rather than an essential item, by the same processing means, One or more raised top surface posts 111b may also be formed on the top surface of the base 111 and one or more raised top surface posts 112b may be formed on the top surface of the base 112. On a common lead frame side of the susceptors 111, 112 that are disconnected from each other, a portion of the pillar 111b overlaps the rib 150 of the lead frame 100, and a portion of the pillar 112b overlaps the pedestal 112. Above the ribs 150 of the lead frame 100, the stability of the susceptor during wafer mounting is increased to a greater extent. Preferably, the columns 111b, 112b are arranged side by side. As an optional rather than an essential item, also through the half etching or stamping, one or more pillars 113a protruding from the top surface thereof may be formed on the top surface of the first pin 113, and at the second pin 114. The top surface forms one or more posts 114a projecting from the top surface thereof, and a top surface of the third pin 115 forms one or more posts 115a projecting from the top surface thereof. Wherein a portion of the pillar 113a may overlap the first pin 113 connected to the rib 150 of the lead frame 100, and a portion of the pillar 114a may overlap the second pin 114 connected to the rib 150 of the lead frame 100. The upper portion, and a portion of the pillar 115a, may overlap the third pin 115 connected to the tie rib 150 of the lead frame 100. Preferably, the columns 113a, 114a, 115a are arranged side by side.

In FIG. 4, a standard pasting process is performed to bond a first wafer 121 to the mesa structure 111a on the top surface of the pedestal 111 and a second wafer 122 to the pedestal 112 using a conductive adhesive material. The top surface of the mesa structure 112a. The first and second wafers 121, 122 mentioned herein may be vertical power metal oxide semiconductor field effect transistors (MOSFETs), and the top surface of the first wafer 121 is provided with a first electrode 121a (for example, a source) insulated from each other. And a second electrode 121b (for example, a gate), and the third electrode, such as the gate electrode, not disposed in the bottom surface of the first wafer 121, passes through a similar conductive adhesive material such as solder paste or conductive silver paste. Adhered to the top surface of the mesa structure 111a. Similarly, the top surface of the second wafer 122 is provided with a first electrode 122a (for example, a source) and a second electrode 122b (for example, a gate) which are insulated from each other, and the first surface of the second wafer 122 is not disposed in the figure. The three electrodes, such as the drain electrodes, are adhered to the top surface of the mesa structure 112a by a similar conductive bonding material such as solder paste or conductive silver paste. In addition, the bottom surface of each of the first and second wafers 121, 122 may be soldered to the top surface of each of the mesa structures 111a, 112a by a soldering method such as eutectic soldering instead of the conductive bonding material, so that the first wafer 121 The third electrode of the bottom surface is electrically connected to the pedestal 111 and the third electrode of the bottom surface of the second wafer 122 is electrically connected to the pedestal 112. In some alternative embodiments, the post 111b on the base 111 may extend slightly toward the center of the base 111, and the post 112b on the base 112 may extend slightly toward the center of the base 112 when the first and second When the area of the wafers 121, 122 is relatively large, the first wafer 121 can be straddle and adhered to the pillar 111b and the mesa structure 111a, and the second wafer 122 can be straddle and adhered to the pillar 112b and the mesa structure 112a. After the patch is completed, the first and second wafers 121, 122 are also arranged side by side with the susceptor.

Referring to Figures 5A-5E, there is shown a metal plate-like interconnecting plate 130 and first and second conductive structures 141, 142 embodied as metal sheets. The interconnecting plate 130 is presented as a T-shaped structure including a integrally formed one laterally extending first portion 131 and a longitudinally extending second portion 132 that is perpendicular to the first portion 131 and that has one end connected to the first portion 131 The intermediate position and the other end are free ends such that the interconnecting plate 130 has a T-shaped configuration. In some embodiments, the interconnection board 130 and the first and second conductive structures 141, 142 are disconnected from each other and disconnected from each other, and they can be used separately, but in other more convenient embodiments, the interconnection board 130 And the first and second conductive structures 141, 142 may be connected to each other by a connecting rod not shown in the drawing, for example, some of the connecting rods interconnecting them are cut off to leave the joint 151 in Fig. 5A. In some embodiments, one or more through holes 133 extending through their respective thicknesses are provided on the first portion 131 and the second portion 132 of the interconnection board 130, and the cross section of the through hole 133 may be arbitrarily set, for example, circular or A square or an arbitrary polygon or a cross shape as shown in the drawing, etc., will be mentioned later in the molding process by using the through hole 133 as a mold clamping. If we interconnect the interconnector 130 and the conductive structures 141, 142, in an optional, non-limiting embodiment, the first and second conductive structures 141, 142 are respectively located on opposite sides of the second portion 132, 1. The second conductive structures 141, 142 are mirror-symmetrical to each other with the elongated second portion 132 as the axis of symmetry, or between the two long edges of the second portion 132 extending in the longitudinal direction/longitudinal direction. The symmetrical centerline 240 is mirror symmetrical.

5A is a top view of the interconnecting plate 130 and the first and second conductive structures 141, 142 in a plan view, and FIG. 5B is a top view of the interconnecting plate 130 and the first and second conductive structures 141, 142 of each of the bottom surfaces, note that in order to avoid confusion, the first and second conductive structures 141, 142 need to be mutually adjusted in the positions of FIGS. 5A and 5B, and the two ends 131a, 131b of the first portion 131 of the interconnecting board 130 are The positions in Figures 5A and 5B also require intermodulation because the observed viewing angle changes. In FIG. 5B, the bottom surface of the intermediate portion between the both ends 131a, 131b of the first portion 131 is formed by recessing or stamping or the like to form a recess recessed in the bottom surfaces of the both ends 131a, 131b, and the first of the interconnecting plates 130. The bottom surface of the second portion 132 connected to one end of the first portion 131 is also formed by a half etching or stamping or the like to form a recess recessed in the bottom surface of the second portion 132. The grooves of the bottom surfaces of the first portion 131 and the second portion 132 are substantially intercommunicated. of. FIG. 5C is a schematic view showing the structure of the first portion 131 taken along the broken line AA of FIGS. 5A-5B. FIG. 5D is a schematic view of the first portion 131 and the second portion 132 taken along the broken line BB of FIG. 5A-5B. Shown. It is worth mentioning that a free end of the second portion 132 is first bent downward and then extended along the level to form an underlying structure 132a, which can be realized in advance by stamping, and the plane of the flat underlying structure 132a is located. The plane is substantially parallel to the plane in which the first portion 131 and the second portion 132 are located, except that the first portion 131 and the second portion 132 are positioned slightly higher than the lower structure 132a.

FIG. 5E illustrates a perspective view of the first conductive structure 141 as an example to illustrate its structure, and the second conductive structure 142 is similar to the structure only in mirror symmetry, so that the perspective view of the second conductive structure 142 is not separately shown. The first conductive structure 141 is a metal piece including a base portion 141b and an extending piece 141d which are connected to each other, and a contact portion 141a of the extending piece 141d extending inwardly from the inner edge of the base portion 141b in FIG. 5A is directed to the second portion 132, and At the outer edge of the base portion 141b away from the extending piece 141d, a lower structure 141c (Fig. 5E) extending outward but lower than the base portion 141b and the extending piece 141d is provided (Fig. 5E), and the flat lower structure 141c is substantially flat The base portion 141b and the extension piece 141d are parallel. However, as shown in FIGS. 5B and 5E, the original extending piece 141d is thinner than the base portion 141b at the bottom surface because it is half-etched or die-cut, etc., wherein the bottom surface of the base portion 141b and the bottom surface of the contact portion 141 are coplanar, but The bottom surface of the extending piece 141d is recessed in the bottom surface of the base portion 141b and the contact portion 141a. For the second conductive structure 142, including the interconnected base portion 142b and the extending piece 142d, the extending piece 142d extends inwardly away from the inner edge of the base portion 142b, and a contact portion 142a is directed toward the second portion 132, and at the base portion 142b. An underlying structure 142c (Figs. 5A-5B) extending outwardly but at a position lower than the base portion 142b and the extending piece 142d is provided away from the outer edge of the extending piece 142d, the flat lower structure 142c and the flat base portion 142b and extending The sheets 142d are parallel. The extending piece 142d is thinner than the base portion 142b at the bottom surface because of being half-etched or punched, etc., the bottom surface of the base portion 142b and the bottom surface of the contact portion 142a are coplanar, but the bottom surface of the extending piece 142d is recessed in the base portion 142b and the contact portion 142a. The bottom surface. Although the first conductive structure 141 and the second conductive structure 142 are divided into different regions for convenience of description, both of them are substantially integrally formed.

Referring to FIG. 6, the first electrode 121a and the second electrode 121b disposed on the top surface of the first wafer 121 are coated with a conductive adhesive, and the first electrode 122a and the second electrode 122b are disposed on the top surface of the second wafer 122. Coating the conductive adhesive material, and also coating the top surface of the first pin 113, the third pin 115 with a conductive adhesive material, and coating the top surface of the second pin 114 with a conductive adhesive material (if a pillar is provided) 114a may also be coated with a conductive adhesive to the top surface of the column 114a). Thereafter, the interconnection board 130 is pasted onto the first wafer 121, the second wafer 122 and the second lead 114, and the first conductive structure 141 is pasted onto the first wafer 121 and the first lead 113, and The second conductive structure 142 is pasted onto the second wafer 122 and the third pin 115. The specific adhesive relationship is embodied in that the first portion 131 of the interconnection board 130 spans over the first wafer and the second wafer, and the bottom surface of one end 131a thereof is aligned and adhered to the first electrode 121a and the first portion 131 of the first wafer. The bottom surface of the other end 131b is aligned and adhered to the first electrode 122a of the second wafer, and the lower end structure 132a of the free end of the second portion 132 can be adhered to the top surface of the second pin 114, preferably The lower structure 132a is aligned and adhered to the top surface of the column 114a. In addition, the contact portion 141a of the first conductive structure 141 is aligned and adhered to the second electrode 121b on the top surface of the first wafer 121, and the lower structure 141c of the first conductive structure 141 is aligned and pasted to the first lead. On the top surface of the foot 113. The contact portion 142a of the second conductive structure 142 is aligned and adhered to the second electrode 122b on the top surface of the second wafer 122, and the lower structure 142c of the second conductive structure 142 is aligned and adhered to the top surface of the third pin 115. on. In some preferred embodiments, if the interconnection board 130 and the first and second conductive structures 141, 142 are interconnected by a connecting rod, the steps of performing the bonding are synchronous, and as long as they are The connecting rod between the cuts can be cut off. However, in other alternative embodiments, if the interconnection board 130 and the first and second conductive structures 141 and 142 are not intended to be elbowed in the pasting step, the interconnection board 130 and the first and second layers may be individually adhered. The conductive structures 141, 142, the order of adhesion between them is arbitrary, and at this time, since they are not interconnected, it is not necessary to perform the cutting process of the connecting rod. In some optional embodiments, the base 141b of the first conductive structure 141 overlaps the pillar 113a of the first pin 113, the two may or may not be in contact, and the base 142b of the second conductive structure 142 overlaps Above the column 115a of the third pin 115, the two may or may not be in contact. In some alternative embodiments, the symmetrical centerline 240 between the two long edges of the second portion 132 of FIG. 5A may coincide vertically with the dividing line 230 between the pedestals 111, 112 of FIG.

Referring to FIG. 7, a standard molding process is performed, using the epoxy-based molding compound for the lead frame 100 of FIG. 2 and the first wafer 121, the second wafer 122, and the interconnection board 130 which are subsequently adhered to the susceptor. The first and second conductive structures 141, 142 and the like are plastically encapsulated, and they are covered by the molding compound or the plastic sealing layer 160 in FIG. 7, in such a manner that at least the pedestals 111, 112 of each of the mounting units 101 are respectively The bottom surface is exposed from the bottom surface of the plastic sealing layer 160, and the bottom surfaces of the first lead 113, the second lead 114, and the third lead 115 are exposed from the bottom surface of the plastic sealing layer 160. In the molding stage, the molding compound invades and fills into the through hole 133 under the molding pressure, and the more secure locking holds the interconnection board 130. FIG. 7 is a plastic seal layer 160 viewed from above. Then, a standard package cutting process is performed, and a laminate including the mold layer 160 and the lead frame 100 between the adjacent mounting units 101 is cut along a predetermined cutting line (dashed line in FIG. 7) to prepare a complete package. Device. In the step of cutting the plastic sealing layer 160 and the lead frame 100, each of the mounting units 101 is cut off from the lead frame 100 and a plurality of molding bodies 161 are formed by cutting the plastic sealing layer 160 (FIGS. 7-8). Each of the molding bodies 161 is coated with a mounting unit 101 corresponding to the plastic package. In the cutting package saw step, the connecting ribs 150 are cut and cut, so that the pedestals 111 and 112 are separated from the lead frame 100, and the first pins 113 and 2 are separated. The pin 114 and the third pin 115 are also separated from the lead frame 100. In the complete power semiconductor device of FIG. 8, including a covering base 111, 112 and covering the first, second and third pins 113, 114, 115 and covering the first wafer 121, the second The wafer 122 and the molding body 161 covering the interconnection board 130 and the first and second conductive structures 141 and 142, the pillars included in the base or the pins themselves are naturally sealed by the molding body 161, but we at least It is necessary to expose the bottom surfaces of the first, second and third leads 113, 114, 115 and the pedestals 111, 112 to the bottom surface of the molding body 161 (see the top view of the bottom surface of the molding 161 of FIG. 8) as The contact point where the external pad is docked. In some optional but non-limiting embodiments, the top surface of the interconnecting plate 130 may be exposed from the top surface of the molding body 161 or may not be exposed from the top surface of the molding body 161, but the lower portion 132a of the interconnection board 130 is It is arranged to be bent downward once and the position is low so that it is not exposed from the top surface of the molding body 161. Similarly, when the first and second conductive structures 141, 142 are metal sheets, the base portions 141b and 142b and the extending piece 141d are included. And 142d and including contact portions 141a, 142a, their respective top surfaces may be exposed from the top surface of the molding body 161 or may not be exposed from the top surface of the molding body 161, but the lower portions 141c, 142c may not be from the molding body 161. The top is exposed. When the first and second conductive structures 141 and 142 are leads, they are not exposed.

In an alternative embodiment of FIG. 9, the first and second conductive structures 141, 142 are replaced by metal leads 145 from the metal sheets above, that is, some may be performed before or after the adhesion of the interconnect board 130 is performed. The metal lead 145 is bonded to the second electrode 121b on the top surface of the first wafer 121 and bonded to the first lead 113, for example, to the top surface of the pillar 113a. A plurality of metal leads 145 are bonded to the second electrode 122b on the top surface of the second wafer 122 and bonded to the third pin 115, for example, to the top surface of the pillar 115a. The other steps are no different from the process flow of Figures 4 to 8. The metal lead 145 can also be replaced by an object such as a conductive metal conduction band. If the first wafer 121 and the second wafer 122 are power metal oxide semiconductor field effect transistors (MOSFETs), the first electrode 121a (source) of the first wafer 121 and the first electrode 122a of the second wafer 122 (source) The bi-wafer common source interconnection is implemented using the interconnect board 130. It is apparent that the present invention preferably achieves this in a three-dimensional 3D interconnect.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

Prior art:
T1, T2‧‧‧ power transistor
S1, S2, G1, G2‧‧‧ pin creation:
100‧‧‧ lead frame
101‧‧‧ wafer mounting unit
111,112‧‧‧Base
111a, 112a‧‧‧ countertop structure
113‧‧‧First pin
114‧‧‧second pin
115‧‧‧ third pin
111b, 112b, 113a, 114a, 115a‧‧ ‧ column
121‧‧‧First chip
121a‧‧‧first electrode
121b‧‧‧second electrode
122‧‧‧second chip
122a‧‧‧first electrode
122b‧‧‧second electrode
130‧‧‧Interconnect Board
131‧‧‧Part 1
131a, 131b‧‧‧ both ends
132‧‧‧Part II
132a‧‧‧Under structure
133‧‧‧through hole
141‧‧‧First conductive structure
141a‧‧Contacts
141b‧‧‧ base
141c‧‧‧Under structure
141d‧‧‧Extension
142‧‧‧Second conductive structure
142a‧‧Contacts
142b‧‧‧ base
142c‧‧‧Under structure
142d‧‧‧Extension
145‧‧‧metal leads
150‧‧‧Connected
151‧‧‧Connector
160‧‧‧plastic layer
161‧‧‧plastic body
230‧‧‧ dividing line
240‧‧‧ center line

Figure 1 illustrates the basic structure of a prior art power semiconductor device. 2 is a plan view of a lead frame according to the present invention. Figure 3 is a top plan view of a mounting unit belonging to a lead frame. Figure 4 is a schematic illustration of the mounting of two wafers on a mounting unit. 5A to 5E are schematic views of the structure of the interconnection board. Figure 6 is a schematic view showing the structure of mounting the interconnection board to the dual wafer. Figure 7 is a plan view of the lead frame of Figure 2 molded. Fig. 8 is a schematic view showing the bottom surface of a molded body after the cutting process is completed. Figure 9 is an embodiment in which a lead is substituted for a conductive structure of a metal sheet.

130‧‧‧Interconnect Board

131‧‧‧Part 1

131a, 131b‧‧‧ both ends

132‧‧‧Part II

132a‧‧‧Under structure

141‧‧‧First conductive structure

141a‧‧Contacts

141b‧‧‧ base

141c‧‧‧Under structure

142‧‧‧Second conductive structure

142a‧‧Contacts

142b‧‧‧ base

142c‧‧‧Under structure

Claims (14)

A power semiconductor device comprising: a pair of pedestals disposed side by side; a pair of wafers each having a wafer adhered thereto, each wafer including a bottom first electrode and top second and third electrodes The bottom first electrode of each wafer is electrically connected to the corresponding pedestal; the first, second and third pins located near the pair of pedestals; and the second electrodes of the two wafers are electrically connected to the second a two-pin interconnect board having a T-shaped structure including a first portion and a second portion perpendicular to the first portion, wherein the first portion spans the pair of wafers on the pedestal Above, the two ends of the first portion are respectively adhered to the second electrodes of the top surface of the pair of wafers, and a free end of the second portion is first bent downward and then extended along the level to form an underlying structure for pressing Bonding on the second pin and bonding thereto; connecting one third electrode of one wafer to one conductive structure of the first pin and the other conductive wire connecting the third electrode of the other chip to the third pin Structure Wherein at least the top surface of the second pin is provided with one or more posts protruding from the top surface of the second pin for carrying the underlying structure of the free end of the second portion of the interconnecting board. The power semiconductor device of claim 1, wherein the conductive structure is a metal lead. The power semiconductor device of claim 1, wherein the conductive structure is a metal piece including a base portion and an extending piece, and a contact portion extends inwardly on an inner side edge of the extending piece and is outside the base portion. An underlying structure extending outwardly but at a lower position than the base and the extension piece is disposed on the edge; the contact portion of each conductive structure is correspondingly adhered to one electrode of one of the wafers, and the underlying structure of one of the conductive structures is correspondingly adhered to On one pin, the underlying structure of the other conductive structure is correspondingly bonded to the third pin. The power semiconductor device according to claim 3, wherein the extension piece is thinner than the base portion, and the thickness of the base portion is the same as the thickness of the contact portion. The power semiconductor device of claim 1, wherein the pair of wafers are power metal oxide semiconductor field effect transistors (MOSFETs), and the source of each of the top surfaces of the pair of wafers is electrically connected through the interconnection board. Together, the drain of the bottom surface of each wafer is electrically connected to the susceptor carrying the wafer by a conductive bonding material, and the respective gates of the pair of wafers are electrically connected to the first and third pins, respectively. The power semiconductor device of claim 1, further comprising a package body and a first, second and third pins and a molded body of the wafer, the conductive structure and the interconnection board, at least the first The bottom surfaces of the second and third pins and the base are exposed on the bottom surface of the molding body. A method of fabricating a power semiconductor device, comprising the steps of: providing a lead frame comprising a plurality of mounting units, each mounting unit comprising at least a pair of pedestals disposed side by side and first and second adjacent to the pair of pedestals And a third pin; a wafer is attached to each of the pedestals, each wafer includes a bottom first electrode and top second and third electrodes, and the bottom first electrode of each wafer is electrically connected to the corresponding pedestal Attaching an interconnecting board to the two wafers disposed on each mounting unit and the second pins of the mounting unit, such that the top second electrodes of the two wafers on each mounting unit are electrically connected to the interconnecting board a second pin of the mounting unit; connecting a third electrode of one wafer on each mounting unit to the first pin and a third electrode of another wafer on the mounting unit to the third lead by using a conductive structure The plastic sealing process is performed by using a plastic sealing layer to cover the lead frame and the wafer, the interconnection board, and the conductive structure; cutting the plastic sealing layer and the lead frame, separating the mounting unit and forming the cladding And a molding body for the unit and the wafer, the conductive structure and the interconnection board, each of the molding bodies formed by cutting the plastic sealing layer correspondingly covers one mounting unit and the wafer, the conductive structure and the interconnection board mounted on the mounting unit, at least the mounting The respective bottom surfaces of the first, second and third pins of the unit and the base are exposed on the bottom surface of the molding body. The method of manufacturing a power semiconductor device according to claim 7, wherein the conductive structure is a metal lead, and the metal wire is bonded after the bonding step of the interconnection board is completed or before the bonding step of the interconnection board is performed. Between the wafer and the first and third pins. The method of fabricating a power semiconductor device according to claim 7, wherein the interconnection board has a T-shaped structure including a first portion and a second portion perpendicular to the first portion, in the step of pasting the interconnection board : one end of the first portion is adhered to one electrode on the top surface of one wafer on each mounting unit and the other end of the first portion is adhered to one electrode on the top surface of the other wafer on the mounting unit; The end is bent downward and then extended along the level to form an underlying structure to be pressed against and adhered to the second pin of the mounting unit. The method for manufacturing a power semiconductor device according to claim 9, wherein the conductive structure is a metal piece, and the two conductive structures are respectively located on two sides of the second portion of one of the interconnection boards, and two conductive structures are disposed to The second portion of the interconnecting plate is an axis of symmetry and is mirror symmetrical to each other. The method of manufacturing a power semiconductor device according to claim 10, wherein the conductive structure is bonded to the interconnecting board to the two wafers disposed in each mounting unit and the first and third pins of the mounting unit. Above. The method of producing a power semiconductor device according to claim 9, wherein the conductive structure is a metal piece including a base portion and an extending piece, and a contact portion is extended inward on an inner side edge of the extending piece at the base portion. The outer side edge is provided with an underlying structure extending outwardly but lower than the base portion and the extending piece. In the step of installing the conductive structure: two conductive structures are adhered on each mounting unit, and the contact portion of one of the conductive structures is adhered Going to one electrode of one wafer in the mounting unit and its underlying structure is correspondingly adhered to the first pin, the contact portion of the other conductive structure is adhered to one electrode of the other wafer in the mounting unit, and the underlying structure is Correspondingly adhered to the third pin. A method of fabricating a power semiconductor device according to claim 9, wherein a top surface of each of the pedestals is provided with a mesa structure for supporting and pasting the wafer on the top surface of the susceptor; At least a top surface of the second pin is provided with one or more posts protruding from the top surface of the second pin for carrying and adhering the underlying structure of the free end of the second portion of the interconnecting board. The method of manufacturing a power semiconductor device according to claim 7, wherein the pair of wafers are power metal oxide semiconductor field effect transistors (MOSFETs) through which the source of each of the top surfaces of the pair of wafers passes The plates are electrically connected together, the drain of the bottom surface of each wafer is electrically connected to the susceptor carrying the wafer by a conductive adhesive material, and the respective gates of the pair of wafers are electrically connected to the first and third pins, respectively. .