TWI829465B - Power module - Google Patents

Power module Download PDF

Info

Publication number
TWI829465B
TWI829465B TW111147725A TW111147725A TWI829465B TW I829465 B TWI829465 B TW I829465B TW 111147725 A TW111147725 A TW 111147725A TW 111147725 A TW111147725 A TW 111147725A TW I829465 B TWI829465 B TW I829465B
Authority
TW
Taiwan
Prior art keywords
pin
metal surface
power module
voltage pin
power
Prior art date
Application number
TW111147725A
Other languages
Chinese (zh)
Inventor
翁任賢
吳翰林
姜俊良
李泰廣
Original Assignee
台達電子工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台達電子工業股份有限公司 filed Critical 台達電子工業股份有限公司
Priority to TW111147725A priority Critical patent/TWI829465B/en
Application granted granted Critical
Publication of TWI829465B publication Critical patent/TWI829465B/en

Links

Images

Abstract

The present application provides a power module. The power module includes a substrate, a plurality of semiconductor elements, a plurality of pins and a package. The substrate includes a first metal surface, and the plurality of semiconductor elements are disposed on the first metal surface. The pin direction of each of the plurality of pins is perpendicular to the bottom of the first metal surface. The package is configured to cover the first metal surface and the plurality of semiconductor elements and covers each pin partially. Each of the plurality of pins extends out of the package along the same direction. The plurality of pins include a positive voltage pins and a negative voltage pins. An end of the positive voltage pin is attached to the middle position of the first side of the first metal surface. An end of the negative voltage pin is attached to the middle of the second side of the first metal surface. The first and second sides are spatially opposite each other, and the first and second sides are connected to the bottom of the first metal surface.

Description

功率模組Power module

本案係關於一種功率模組,尤指一種將多個半導體器件設置於一塊基板上的功率模組。This case relates to a power module, specifically a power module in which multiple semiconductor devices are arranged on a substrate.

在現有充電樁設備中,電源轉換單元需使用多顆TO247架構之離散式元件。每一顆TO247架構之離散式元件具有一顆MOSFET晶片,離散式元件的尺寸及功率密度固定。In existing charging pile equipment, the power conversion unit requires the use of multiple TO247 structured discrete components. Each TO247 structured discrete device has a MOSFET chip, and the size and power density of the discrete device are fixed.

由於每一顆離散式元件的尺寸及功率密度固定,因此若要滿足不斷上升之功率需求的設備,相較於傳統較低功率需求之設備,則須同時使用較多顆的離散式元件,以滿足高功率要求。然而,設備若使用較多顆的離散式元件將導致體積增加,且因電子元件的數量增加,設備內部之散熱更加困難。Since the size and power density of each discrete component are fixed, devices that meet rising power requirements must use more discrete components at the same time than traditional devices with lower power requirements. Meet high power requirements. However, if the device uses more discrete components, the volume will increase, and due to the increase in the number of electronic components, it will be more difficult to dissipate heat inside the device.

因此,如何發展一種可改善上述習知技術之功率模組,實為目前迫切之需求。Therefore, how to develop a power module that can improve the above-mentioned conventional technology is currently an urgent need.

本案之目的為提供一種功率模組將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而降低體積,並提升功率密度。此外,本案功率模組之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組之結構穩定性並延長使用壽命。The purpose of this project is to provide a power module that disposes multiple semiconductor devices on a substrate, thereby replacing multiple traditional discrete components with one power module, thereby reducing the volume and increasing the power density. In addition, the positive voltage and negative voltage pins of the power module in this case are respectively attached to the middle position on the side of the metal surface, thus increasing the structural stability of the power module and extending its service life.

根據本案之構想,本案提供一種功率模組,包含基板、多個半導體器件、多個引腳及封裝體。基板包含第一金屬表面,多個半導體器件設置於第一金屬表面上。每一引腳的出腳方向垂直於第一金屬表面的底邊。封裝體用於包覆第一金屬表面、多個半導體器件,並且部分包覆每一引腳,每一引腳沿著相同的方向延伸出封裝體。多個引腳包含正電壓引腳及負電壓引腳,且正電壓引腳的末端貼附於第一金屬表面的第一側邊的中間位置,且負電壓引腳的末端貼附於第一金屬表面的第二側邊的中間位置,第一及第二側邊在空間上彼此相對,且第一及第二側邊均連接於第一金屬表面的底邊。According to the concept of this case, this case provides a power module, including a substrate, multiple semiconductor devices, multiple pins and a package. The substrate includes a first metal surface, and a plurality of semiconductor devices are disposed on the first metal surface. The outlet direction of each pin is perpendicular to the bottom edge of the first metal surface. The package body is used to cover the first metal surface, the plurality of semiconductor devices, and partially cover each pin, and each pin extends out of the package body along the same direction. The plurality of pins include a positive voltage pin and a negative voltage pin, and the end of the positive voltage pin is attached to the middle position of the first side of the first metal surface, and the end of the negative voltage pin is attached to the first At the middle position of the second side of the metal surface, the first and second sides are spatially opposite to each other, and both the first and second sides are connected to the bottom side of the first metal surface.

體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案之範圍,且其中的說明及圖示在本質上係當作說明之用,而非架構於限制本案。Some typical embodiments embodying the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various changes in different aspects without departing from the scope of this case, and the descriptions and illustrations are essentially for illustrative purposes and are not intended to limit this case.

第1圖係為本案較佳實施例之功率模組1的立體結構示意圖,第2圖為第1圖之功率模組1的部分立體結構示意圖,第3圖為第2圖之功率模組1的俯視圖。如第1、2及3圖所示,功率模組1包含基板2、多個半導體器件3、多個引腳及封裝體5。基板2包含第一金屬表面20,多個半導體器件3設置於第一金屬表面20上。於一些實施例中,引腳的數量為奇數且大於或等於三。每一引腳的出腳方向垂直於第一金屬表面20的底邊21。封裝體5用於包覆第一金屬表面20、多個半導體器件3,並且部分包覆每一引腳,每一引腳沿著相同的方向延伸出封裝體5。多個引腳包含正電壓引腳40及負電壓引腳41,其中正電壓引腳40的末端400貼附於第一金屬表面20的第一側邊22的中間位置 (例如但不限於第一側邊22的中點),負電壓引腳41的末端410貼附於第一金屬表面20的第二側邊23的中間位置 (例如但不限於第二側邊23的中點)。由於正電壓引腳40的末端400及負電壓引腳41的末端410分別貼附於第一側邊22及第二側邊23的中間位置,因此,當功率模組1於組裝過程中若受外力影響時,功率模組1之結構較為穩定,進而提升功率模組1之可靠度與使用壽命。第一側邊22及第二側邊23在空間上彼此相對,且第一側邊22及第二側邊23均連接於第一金屬表面20的底邊21。本案之功率模組1將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而減少體積,並提升功率密度。此外,本案功率模組1之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組1之結構穩定性並延長使用壽命。Figure 1 is a schematic three-dimensional structural diagram of the power module 1 of the preferred embodiment of the present invention. Figure 2 is a partial three-dimensional structural diagram of the power module 1 of Figure 1. Figure 3 is a schematic diagram of the power module 1 of Figure 2. top view. As shown in Figures 1, 2 and 3, the power module 1 includes a substrate 2, a plurality of semiconductor devices 3, a plurality of pins and a package 5. The substrate 2 includes a first metal surface 20 on which a plurality of semiconductor devices 3 are disposed. In some embodiments, the number of pins is an odd number and greater than or equal to three. The outlet direction of each pin is perpendicular to the bottom edge 21 of the first metal surface 20 . The package body 5 is used to cover the first metal surface 20 and the plurality of semiconductor devices 3 and partially cover each pin, and each pin extends out of the package body 5 in the same direction. The plurality of pins include a positive voltage pin 40 and a negative voltage pin 41, wherein the end 400 of the positive voltage pin 40 is attached to the middle position of the first side 22 of the first metal surface 20 (such as but not limited to the first The end 410 of the negative voltage pin 41 is attached to the middle position of the second side 23 of the first metal surface 20 (for example, but not limited to the middle point of the second side 23 ). Since the end 400 of the positive voltage pin 40 and the end 410 of the negative voltage pin 41 are attached to the middle position of the first side 22 and the second side 23 respectively, when the power module 1 is damaged during the assembly process, When affected by external forces, the structure of the power module 1 is relatively stable, thereby improving the reliability and service life of the power module 1 . The first side 22 and the second side 23 are spatially opposite to each other, and both the first side 22 and the second side 23 are connected to the bottom side 21 of the first metal surface 20 . The power module 1 of this case arranges multiple semiconductor devices on a substrate, thereby replacing multiple traditional discrete components with one power module, thereby reducing the volume and increasing the power density. In addition, the positive voltage and negative voltage pins of the power module 1 in this case are respectively attached to the middle position on the side of the metal surface, thereby increasing the structural stability of the power module 1 and extending its service life.

於一些實施例中,正電壓引腳40的末端400設置於兩個半導體器件3之間,負電壓引腳41的末端410設置於兩個半導體器件3之間。由於正電壓引腳40及負電壓引腳41之末端400及410分別設置於兩個半導體器件3之間,因此可增加功率模組1之散熱效果。In some embodiments, the end 400 of the positive voltage pin 40 is disposed between the two semiconductor devices 3 , and the end 410 of the negative voltage pin 41 is disposed between the two semiconductor devices 3 . Since the ends 400 and 410 of the positive voltage pin 40 and the negative voltage pin 41 are respectively disposed between the two semiconductor devices 3, the heat dissipation effect of the power module 1 can be increased.

於一些實施例中,半導體器件3的數量為偶數個,如第1至3圖所示之功率模組1,其包含四個半導體器件3,且四個半導體器件3在第一金屬表面20上排列形成矩陣。矩陣之中心O、第一側邊22及第二側邊23的中間位置於空間上位於相同之水平線L。In some embodiments, the number of semiconductor devices 3 is an even number, such as the power module 1 shown in Figures 1 to 3, which includes four semiconductor devices 3, and the four semiconductor devices 3 are on the first metal surface 20 Arrange to form a matrix. The center O of the matrix, the middle position of the first side 22 and the second side 23 are spatially located on the same horizontal line L.

於一些實施例中,多個引腳還包含相電壓引腳42,且相電壓引腳42設置於正電壓引腳40及負電壓引腳41之間。相電壓引腳42的末端420貼附於第一金屬表面20,且末端420貼附於第一金屬表面20之位置較水平線L靠近底邊21。相電壓引腳42與正電壓引腳40之間的第一間距R1相同於相電壓引腳42與負電壓引腳41之間的第二間距R2。In some embodiments, the plurality of pins further include a phase voltage pin 42 , and the phase voltage pin 42 is disposed between the positive voltage pin 40 and the negative voltage pin 41 . The end 420 of the phase voltage pin 42 is attached to the first metal surface 20 , and the end 420 is attached to the first metal surface 20 closer to the bottom edge 21 than the horizontal line L. The first distance R1 between the phase voltage pin 42 and the positive voltage pin 40 is the same as the second distance R2 between the phase voltage pin 42 and the negative voltage pin 41 .

於一些實施例中,正電壓引腳40、負電壓引腳41及相電壓引腳42具有相同的截面積,且正電壓引腳40、負電壓引腳41及相電壓引腳42具有多個引腳4中最大之截面積,故正電壓引腳40、負電壓引腳41及相電壓引腳42可以承受自功率模組1外部所輸入之電源電流。In some embodiments, the positive voltage pin 40 , the negative voltage pin 41 and the phase voltage pin 42 have the same cross-sectional area, and the positive voltage pin 40 , the negative voltage pin 41 and the phase voltage pin 42 have multiple Pin 4 has the largest cross-sectional area, so the positive voltage pin 40, the negative voltage pin 41 and the phase voltage pin 42 can withstand the power supply current input from outside the power module 1.

於一些實施例中,多個引腳還包含第一閘極引腳43及第一源極引腳44,且第一閘極引腳43及第一源極引腳44設置於第一間距R1內,意即第一閘極引腳43及第一源極引腳44位於相電壓引腳42與正電壓引腳40之間。第一閘極引腳43的末端430及第一源極引腳44的末端440相鄰於第一金屬表面20的底邊21,且藉由至少一電力傳輸線6使第一閘極引腳43的末端430及第一源極引腳44的末端440電連接第一金屬表面20。本案之複數個電力傳輸線6中,部分之電力傳輸線6係用於訊號傳輸,部分之電力傳輸線6係用於電力傳輸。於一些實施例中,電力傳輸線6之訊號係由第一金屬表面20上之半導體器件3所提供。封裝體5包覆第一閘極引腳43的末端430及第一源極引腳44的末端440。需特別說明的是,為維持圖式簡潔,於圖式中僅給予部分電力傳輸線6標號。In some embodiments, the plurality of pins further include a first gate pin 43 and a first source pin 44, and the first gate pin 43 and the first source pin 44 are disposed at the first spacing R1 Within, that is, the first gate pin 43 and the first source pin 44 are located between the phase voltage pin 42 and the positive voltage pin 40 . The end 430 of the first gate pin 43 and the end 440 of the first source pin 44 are adjacent to the bottom edge 21 of the first metal surface 20 , and the first gate pin 43 is connected by at least one power transmission line 6 The end 430 of the first source pin 44 and the end 440 of the first source pin 44 are electrically connected to the first metal surface 20 . Among the plurality of power transmission lines 6 in this case, some of the power transmission lines 6 are used for signal transmission, and some of the power transmission lines 6 are used for power transmission. In some embodiments, the signal of the power transmission line 6 is provided by the semiconductor device 3 on the first metal surface 20 . The package 5 covers the end 430 of the first gate pin 43 and the end 440 of the first source pin 44 . It should be noted that in order to keep the diagram concise, only some power transmission lines 6 are given numbers 6 in the diagram.

於一些實施例中,多個引腳還包含第二閘極引腳45及第二源極引腳46,且第二閘極引腳45及第二源極引腳46設置於第二間距R2內,意即第二閘極引腳45及第二源極引腳46位於相電壓引腳42與負電壓引腳41之間。第二閘極引腳45的末端450及第二源極引腳46的末端460相鄰於第一金屬表面20的底邊21,且藉由至少一電力傳輸線6使第二閘極引腳45的末端450及第二源極引腳46的末端460電連接第一金屬表面20。於一些實施例中,電力傳輸線6之訊號係由第一金屬表面20上之半導體器件3所提供。封裝體5包覆第二閘極引腳45的末端450及第二源極引腳46的末端460。In some embodiments, the plurality of pins further include a second gate pin 45 and a second source pin 46, and the second gate pin 45 and the second source pin 46 are disposed at the second spacing R2 Within, that is, the second gate pin 45 and the second source pin 46 are located between the phase voltage pin 42 and the negative voltage pin 41 . The end 450 of the second gate pin 45 and the end 460 of the second source pin 46 are adjacent to the bottom edge 21 of the first metal surface 20 , and the second gate pin 45 is connected by at least one power transmission line 6 The end 450 of the second source pin 46 and the end 460 of the second source pin 46 are electrically connected to the first metal surface 20 . In some embodiments, the signal of the power transmission line 6 is provided by the semiconductor device 3 on the first metal surface 20 . The package 5 covers the end 450 of the second gate pin 45 and the end 460 of the second source pin 46 .

請參閱第4圖,第4圖為第3圖之功率模組1接收電源電流時的電流流向示意圖。每一半導體器件3分別藉由至少一電力傳輸線6電性連接第一金屬表面20。於第4圖中,實心箭頭方向代表電源電流經由正電壓引腳40及相電壓引腳42分別流入及流出功率模組1之方向。當正電壓引腳40接收電源電流時,經由第一金屬表面20及至少一電力傳輸線6,使電源電流流經相較於底邊21高於水平線L的半導體器件3 (即為與底邊21位於水平線L之相異側的半導體器件3),而後電源電流經由相電壓引腳42流出功率模組1。Please refer to Figure 4. Figure 4 is a schematic diagram of the current flow when the power module 1 in Figure 3 receives power current. Each semiconductor device 3 is electrically connected to the first metal surface 20 through at least one power transmission line 6 . In FIG. 4 , the direction of the solid arrow represents the direction in which the power supply current flows into and out of the power module 1 via the positive voltage pin 40 and the phase voltage pin 42 respectively. When the positive voltage pin 40 receives the power current, the power current flows through the semiconductor device 3 which is higher than the horizontal line L compared to the bottom edge 21 (that is, with the bottom edge 21 through the first metal surface 20 and at least one power transmission line 6 The semiconductor device 3) is located on the opposite side of the horizontal line L, and then the supply current flows out of the power module 1 via the phase voltage pin 42.

本案功率模組之引腳設置位置不限於第3及4圖所示之功率模組1,請參閱第5圖,第5圖所示之功率模組1與第4圖所示之功率模組1之差異在於本實施例之引腳設置位置之不同,於第5圖所示之實施例中,負電壓引腳41設置於相電壓引腳42及正電壓引腳40之間,第二閘極引腳45及第二源極引腳46位於正電壓引腳40與負電壓引腳41之間,第一閘極引腳43及第一源極引腳44位於負電壓引腳41與相電壓引腳42之間。於第5圖中,實心箭頭方向代表電源電流經由正電壓引腳40及相電壓引腳42分別流入及流出功率模組1之方向。於第5圖所示實施例中,在電源電流流經相較於底邊21高於水平線L的半導體器件3之後,電源電流經由相電壓引腳42流出功率模組1。The pin setting position of the power module in this case is not limited to the power module 1 shown in Figures 3 and 4. Please refer to Figure 5. The power module 1 shown in Figure 5 and the power module shown in Figure 4 The difference between 1 and 1 lies in the location of the pins in this embodiment. In the embodiment shown in Figure 5, the negative voltage pin 41 is set between the phase voltage pin 42 and the positive voltage pin 40. The second gate The gate pin 45 and the second source pin 46 are located between the positive voltage pin 40 and the negative voltage pin 41, and the first gate pin 43 and the first source pin 44 are located between the negative voltage pin 41 and the negative voltage pin 41. voltage between pins 42. In FIG. 5 , the direction of the solid arrow represents the direction in which the power supply current flows into and out of the power module 1 via the positive voltage pin 40 and the phase voltage pin 42 respectively. In the embodiment shown in FIG. 5 , after the supply current flows through the semiconductor device 3 which is higher than the horizontal line L compared to the bottom edge 21 , the supply current flows out of the power module 1 through the phase voltage pin 42 .

於一些實施例中,電源電流可經由相電壓引腳42流入功率模組1,並流經相較於底邊21低於水平線L之半導體器件3 (即為與底邊21位於水平線L之相同側的半導體器件3),電源電流經由相電壓引腳42流入功率模組1之實施例分別以第4及5圖例示說明如下。In some embodiments, the power supply current can flow into the power module 1 through the phase voltage pin 42 and flow through the semiconductor device 3 which is lower than the horizontal line L compared to the bottom edge 21 (that is, the same as the bottom edge 21 is located at the horizontal line L). Side semiconductor device 3), the embodiment in which the power supply current flows into the power module 1 through the phase voltage pin 42 is illustrated in Figures 4 and 5 as follows.

請參閱第4及5圖,於第4及5圖中,空心箭頭方向代表電源電流經由相電壓引腳42及負電壓引腳41分別流入及流出功率模組1之方向。於第4圖所示實施例中,當相電壓引腳42接收電源電流時,經由第一金屬表面20及至少一電力傳輸線6,使電源電流流經相較於底邊21低於水平線L的半導體器件3,而後電源電流經由負電壓引腳41流出功率模組1。Please refer to Figures 4 and 5. In Figures 4 and 5, the hollow arrow directions represent the directions in which the power supply current flows into and out of the power module 1 through the phase voltage pin 42 and the negative voltage pin 41 respectively. In the embodiment shown in FIG. 4 , when the phase voltage pin 42 receives the power current, the power current flows through the first metal surface 20 and at least one power transmission line 6 , which is lower than the horizontal line L compared to the bottom edge 21 . The semiconductor device 3 then supplies current out of the power module 1 via the negative voltage pin 41 .

本案功率模組於第一金屬表面20上之電力傳輸線6之連接方式不限於第3、4及5圖所示之功率模組1,請參閱第6圖,第6圖所示之功率模組1與第3、4及5圖所示之功率模組1之差異僅在於本實施例之電力傳輸線6之連接方式不同,其中,於不同實施例之間,電力傳輸線6之連接方式可根據半導體器件3及多個引腳之間的設置關係而有所不同。The connection method of the power transmission line 6 of the power module in this case on the first metal surface 20 is not limited to the power module 1 shown in Figures 3, 4 and 5. Please refer to Figure 6. The power module shown in Figure 6 The difference between 1 and the power module 1 shown in Figures 3, 4 and 5 is only that the connection method of the power transmission line 6 of this embodiment is different. Among different embodiments, the connection method of the power transmission line 6 can be based on the semiconductor Device 3 and the setting relationship between multiple pins vary.

請再參閱第1圖,於一些實施例中,封裝體5具有可拆卸之上層封膠50與下層封膠51以及兩個固定組件52。於一些實施例中,上層封膠50及下層封膠51為一體成形,且上層封膠50及下層封膠51為射出成型的環氧樹酯(Epoxy),上層封膠50及下層封膠51形成封裝體5。於另一些實施例中,上層封膠50及下層封膠51形成封裝體5後係透過兩個固定組件52相固接,固定組件52可為例如但不限於鎖固螺絲。Please refer to FIG. 1 again. In some embodiments, the package body 5 has a detachable upper sealant 50 and a lower sealant 51 and two fixing components 52 . In some embodiments, the upper sealant 50 and the lower sealant 51 are integrally formed, and the upper sealant 50 and the lower sealant 51 are injection molded epoxy resin (Epoxy). The upper sealant 50 and the lower sealant 51 Package 5 is formed. In other embodiments, after the upper sealant 50 and the lower sealant 51 form the package body 5, they are fixed to each other through two fixing components 52. The fixing components 52 can be, for example but not limited to, locking screws.

請參閱第7圖,第7圖為第1圖之功率模組1之剖面結構示意圖。本案之基板2還包含導熱絕緣板24及第二金屬表面25,導熱絕緣板24具有相對之第一面240及第二面241,第一金屬表面20貼附於導熱絕緣板24的第一面240,且第二金屬表面25貼附於導熱絕緣板24的第二面241,第二金屬表面25裸露於封裝體5。於一些實施例中,封裝體5是由制模化合物所製造,且制模化合物之製造材料為環氧樹脂。Please refer to Figure 7. Figure 7 is a schematic cross-sectional structural diagram of the power module 1 in Figure 1. The substrate 2 in this case also includes a thermally conductive insulating plate 24 and a second metal surface 25. The thermally conductive insulating plate 24 has an opposite first surface 240 and a second surface 241. The first metal surface 20 is attached to the first surface of the thermally conductive insulating plate 24. 240, and the second metal surface 25 is attached to the second surface 241 of the thermally conductive insulating plate 24, and the second metal surface 25 is exposed to the package body 5. In some embodiments, the package 5 is made of a molding compound, and the molding compound is made of epoxy resin.

綜上所述,本案提供一種功率模組將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而降低體積,並提升功率密度。此外,本案功率模組之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組之結構穩定性並延長使用壽命,且由於正電壓及負電壓引腳之末端設置於兩個半導體器件之間,因此可增加功率模組之散熱效果。To sum up, this project provides a power module that disposes multiple semiconductor devices on a substrate, thereby replacing multiple traditional discrete components with one power module, thereby reducing the volume and increasing the power density. In addition, the positive voltage and negative voltage pins of the power module in this case are respectively attached to the middle position on the side of the metal surface, thus increasing the structural stability of the power module and extending its service life. The end is disposed between two semiconductor devices, thereby increasing the heat dissipation effect of the power module.

須注意,上述僅是為說明本案而提出之較佳實施例,本案不限於所述之實施例,本案之範圍由如附專利申請範圍決定。且本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附專利申請範圍所欲保護者。It should be noted that the above are only preferred embodiments proposed to illustrate this case. This case is not limited to the embodiments described. The scope of this case is determined by the scope of the attached patent application. Moreover, this case may be modified in various ways by those who are familiar with this technology, but it will not deviate from the intended protection within the scope of the attached patent application.

1:功率模組 2:基板 20:第一金屬表面 21:底邊 22:第一側邊 23:第二側邊 24:導熱絕緣板 240:第一面 241:第二面 25:第二金屬表面 3:半導體器件 40:正電壓引腳 41:負電壓引腳 400、410:末端 42相電壓引腳 420:末端 43:第一閘極引腳 44:第一源極引腳 430、440:末端 45:第二閘極引腳 46:第二源極引腳 450、460:末端 5:封裝體 50:上層封膠 51:下層封膠 52:固定組件 6:電力傳輸線 O:矩陣之中心 L:水平線 R1:第一間距 R2:第二間距1: Power module 2:Substrate 20: First metal surface 21: Bottom 22:First side 23:Second side 24:Thermal conductive insulation board 240: First side 241:Second side 25: Second metal surface 3: Semiconductor devices 40: Positive voltage pin 41: Negative voltage pin 400, 410: end 42 phase voltage pins 420:end 43: First gate pin 44: First source pin 430, 440: end 45: Second gate pin 46: Second source pin 450, 460: end 5:Package 50: Upper sealant 51: Lower sealant 52: Fixed components 6:Power transmission line O: center of matrix L: horizontal line R1: first spacing R2: second spacing

第1圖係為本案較佳實施例之功率模組的立體結構示意圖。Figure 1 is a schematic three-dimensional structural diagram of a power module according to a preferred embodiment of the present invention.

第2圖為第1圖之功率模組的部分立體結構示意圖。Figure 2 is a partial three-dimensional structural diagram of the power module in Figure 1.

第3圖為第2圖之功率模組的俯視圖。Figure 3 is a top view of the power module in Figure 2.

第4圖為第3圖之功率模組接收電源電流時的電流流向示意圖。Figure 4 is a schematic diagram of the current flow when the power module in Figure 3 receives power current.

第5圖為本案另一較佳實施例之功率模組接收電源電流時的電流流向示意圖。Figure 5 is a schematic diagram of the current flow when the power module receives power current according to another preferred embodiment of the present invention.

第6圖為本案另一較佳實施例之功率模組接收電源電流時的電流流向示意圖。Figure 6 is a schematic diagram of the current flow when the power module receives power current according to another preferred embodiment of the present invention.

第7圖為第1圖之功率模組之剖面結構示意圖。Figure 7 is a schematic cross-sectional structural diagram of the power module in Figure 1.

1:功率模組 1: Power module

40:正電壓引腳 40: Positive voltage pin

41:負電壓引腳 41: Negative voltage pin

42:相電壓引腳 42: Phase voltage pin

43:第一閘極引腳 43: First gate pin

44:第一源極引腳 44: First source pin

45:第二閘極引腳 45: Second gate pin

46:第二源極引腳 46: Second source pin

5:封裝體 5:Package

50:上層封膠 50: Upper sealant

51:下層封膠 51: Lower sealant

52:固定組件 52: Fixed components

Claims (15)

一種功率模組,包含: 一基板,包含一第一金屬表面; 多個半導體器件,設置於該第一金屬表面上; 多個引腳,其中每一該引腳的出腳方向垂直於該第一金屬表面的一底邊;以及 一封裝體,用於包覆該第一金屬表面、該多個半導體器件,並且部分包覆每一該引腳,其中,每一該引腳沿著相同的方向延伸出該封裝體; 其中,該多個引腳包含一正電壓引腳及一負電壓引腳,且該正電壓引腳的一末端貼附於該第一金屬表面的一第一側邊的一中間位置,且該負電壓引腳的一末端貼附於該第一金屬表面的一第二側邊的一中間位置,其中該第一側邊及該第二側邊在空間上彼此相對,且該第一及該第二側邊均連接於該第一金屬表面的該底邊。 A power module containing: a substrate including a first metal surface; A plurality of semiconductor devices are disposed on the first metal surface; A plurality of pins, wherein the outlet direction of each pin is perpendicular to a bottom edge of the first metal surface; and A package body for covering the first metal surface, the plurality of semiconductor devices, and partially covering each of the pins, wherein each of the pins extends out of the package body along the same direction; Wherein, the plurality of pins include a positive voltage pin and a negative voltage pin, and an end of the positive voltage pin is attached to a middle position of a first side of the first metal surface, and the An end of the negative voltage pin is attached to a middle position of a second side of the first metal surface, wherein the first side and the second side are spatially opposite to each other, and the first and the second side are spatially opposite to each other. The second sides are connected to the bottom edge of the first metal surface. 如請求項1所述的功率模組,其中,該多個半導體器件的數量為偶數個,並且該多個半導體器件在該第一金屬表面上排列形成一矩陣; 其中,該矩陣的一中心、該第一及該第二側邊的該中間位置於空間上位於相同之一水平線。 The power module of claim 1, wherein the number of the plurality of semiconductor devices is an even number, and the plurality of semiconductor devices are arranged on the first metal surface to form a matrix; Wherein, a center of the matrix and the middle position of the first and second sides are spatially located on the same horizontal line. 如請求項2所述的功率模組,其中該多個引腳更包含一相電壓引腳,且該相電壓引腳設置於該正電壓引腳及該負電壓引腳之間; 其中該相電壓引腳的一末端貼附於該第一金屬表面的位置較該水平線靠近該底邊。 The power module as described in claim 2, wherein the plurality of pins further includes a phase voltage pin, and the phase voltage pin is disposed between the positive voltage pin and the negative voltage pin; One end of the phase voltage pin is attached to the first metal surface closer to the bottom edge than the horizontal line. 如請求項3所述的功率模組,其中該相電壓引腳與該正電壓引腳之間的一第一間距相同於該相電壓引腳與該負電壓引腳之間的一第二間距。The power module of claim 3, wherein a first spacing between the phase voltage pin and the positive voltage pin is the same as a second spacing between the phase voltage pin and the negative voltage pin. . 如請求項4所述的功率模組,其中該多個引腳更包含一第一閘極引腳及一第一源極引腳,且該第一閘極引腳及該第一源極引腳設置於該第一間距內; 其中該第一閘極引腳及該第一源極引腳的一末端相鄰於該第一金屬表面的該底邊,且藉由至少一電力傳輸線使該第一閘極引腳及該第一源極引腳的該末端電連接該第一金屬表面; 其中該封裝體包覆該第一閘極引腳及該第一源極引腳的該末端。 The power module of claim 4, wherein the plurality of pins further include a first gate pin and a first source pin, and the first gate pin and the first source pin The feet are arranged within the first distance; An end of the first gate pin and the first source pin is adjacent to the bottom edge of the first metal surface, and the first gate pin and the third source pin are connected by at least one power transmission line. The end of a source pin is electrically connected to the first metal surface; The package body covers the first gate pin and the end of the first source pin. 如請求項4所述的功率模組,其中該多個引腳更包含一第二閘極引腳及一第二源極引腳,且該第二閘極引腳及該第二源極引腳設置於該第二間距內; 其中該第二閘極引腳及該第二源極引腳的末端相鄰於該第一金屬表面的該底邊,且藉由至少一電力傳輸線使該第二閘極引腳及該第二源極引腳的該末端電連接該第一金屬表面; 其中該封裝體包覆該第二閘極引腳及該第二源極引腳的該末端。 The power module of claim 4, wherein the plurality of pins further include a second gate pin and a second source pin, and the second gate pin and the second source pin The feet are arranged within the second distance; The ends of the second gate pin and the second source pin are adjacent to the bottom edge of the first metal surface, and the second gate pin and the second source pin are connected by at least one power transmission line. The end of the source pin is electrically connected to the first metal surface; The package body covers the second gate pin and the end of the second source pin. 如請求項3所述的功率模組,其中每一該半導體器件分別藉由至少一電力傳輸線電性連接該第一金屬表面; 其中當該正電壓引腳接收一電源電流時,經由該第一金屬表面及該至少一電力傳輸線,使該電源電流流經相較於該底邊高於該水平線的該半導體器件。 The power module of claim 3, wherein each of the semiconductor devices is electrically connected to the first metal surface through at least one power transmission line; When the positive voltage pin receives a power current, the power current flows through the semiconductor device that is higher than the horizontal line compared to the bottom edge through the first metal surface and the at least one power transmission line. 如請求項7所述的功率模組,其中在該電源電流流經相較於該底邊高於該水平線的該半導體器件之後,該電源電流經由該相電壓引腳流出該功率模組。The power module of claim 7, wherein after the power current flows through the semiconductor device that is higher than the horizontal line compared to the bottom edge, the power current flows out of the power module through the phase voltage pin. 如請求項7所述的功率模組,其中在該電源電流流經相較於該底邊高於該水平線的該半導體器件之後,該電源電流經由該負電壓引腳流出該功率模組。The power module of claim 7, wherein after the power current flows through the semiconductor device that is higher than the horizontal line compared to the bottom edge, the power current flows out of the power module through the negative voltage pin. 如請求項7所述的功率模組,其中當該負電壓引腳接收該電源電流時,經由該第一金屬表面及該至少一電力傳輸線,使該電源電流相較於該底邊流經低於該水平線的該半導體器件; 其中,在該電源電流流經相較於該底邊低於該水平線的該半導體器件之後,該電源電流經由該相電壓引腳流出該功率模組。 The power module of claim 7, wherein when the negative voltage pin receives the power current, the power current flows through the first metal surface and the at least one power transmission line, which is lower than the bottom edge. the semiconductor device on the horizontal line; Wherein, after the power current flows through the semiconductor device which is lower than the horizontal line compared to the bottom edge, the power current flows out of the power module through the phase voltage pin. 如請求項7所述的功率模組,其中當該相電壓引腳接收該電源電流時,經由該第一金屬表面及該至少一電力傳輸線,使該電源電流流經相較於該底邊低於該水平線的該半導體器件; 其中,在該電源電流流經相較於該底邊低於該水平線的該半導體器件之後,該電源電流經由該負電壓引腳流出該功率模組。 The power module of claim 7, wherein when the phase voltage pin receives the power current, the power current flows through the first metal surface and the at least one power transmission line, which is lower than the bottom edge. the semiconductor device on the horizontal line; Wherein, after the power current flows through the semiconductor device which is lower than the horizontal line compared to the bottom edge, the power current flows out of the power module through the negative voltage pin. 如請求項3所述的功率模組,其中該多個引腳具有一截面積,該正電壓引腳、該負電壓引腳及該相電壓引腳具有該多個引腳中最大的該截面積。The power module as described in claim 3, wherein the plurality of pins have a cross-sectional area, and the positive voltage pin, the negative voltage pin and the phase voltage pin have the largest cross-section among the plurality of pins. area. 如請求項1所述的功率模組,其中該多個引腳的數量為奇數個,且該多個引腳的數量大於或等於三個。The power module as described in claim 1, wherein the number of the plurality of pins is an odd number, and the number of the plurality of pins is greater than or equal to three. 如請求項1所述的功率模組,其中該基板更包含一導熱絕緣板及一第二金屬表面; 其中該第一金屬表面貼附於該導熱絕緣板的一第一面,且該第二金屬表面貼附於該導熱絕緣板的一第二面,該第一面及該第二面相對,且該第二金屬表面裸露於該封裝體。 The power module of claim 1, wherein the substrate further includes a thermally conductive insulating plate and a second metal surface; wherein the first metal surface is attached to a first side of the thermally conductive insulating plate, and the second metal surface is attached to a second side of the thermally conductive insulating plate, the first side and the second side are opposite, and The second metal surface is exposed on the package body. 如請求項1所述的功率模組,其中該封裝體是由一制模化合物所製造,且該制模化合物之製造材料為環氧樹脂。The power module of claim 1, wherein the package is made of a molding compound, and the molding compound is made of epoxy resin.
TW111147725A 2022-12-13 2022-12-13 Power module TWI829465B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW111147725A TWI829465B (en) 2022-12-13 2022-12-13 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111147725A TWI829465B (en) 2022-12-13 2022-12-13 Power module

Publications (1)

Publication Number Publication Date
TWI829465B true TWI829465B (en) 2024-01-11

Family

ID=90459035

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111147725A TWI829465B (en) 2022-12-13 2022-12-13 Power module

Country Status (1)

Country Link
TW (1) TWI829465B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070176299A1 (en) * 2006-01-17 2007-08-02 Ralf Otremba Power Semiconductor Component Having Chip Stack
TW201643995A (en) * 2015-06-12 2016-12-16 萬國半導體股份有限公司 Power semiconductor device and the fabricating method thereof
US20170331209A1 (en) * 2013-02-07 2017-11-16 Samsung Electronics Co., Ltd. Substrate and terminals for power module and power module including the same
US20200035579A1 (en) * 2018-07-25 2020-01-30 Infineon Technologies Ag Semiconductor Package Having Symmetrically Arranged Power Terminals and Method for Producing the Same
TW202143420A (en) * 2020-04-07 2021-11-16 美商克里菲亞特維拉公司 Power module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070176299A1 (en) * 2006-01-17 2007-08-02 Ralf Otremba Power Semiconductor Component Having Chip Stack
US20170331209A1 (en) * 2013-02-07 2017-11-16 Samsung Electronics Co., Ltd. Substrate and terminals for power module and power module including the same
TW201643995A (en) * 2015-06-12 2016-12-16 萬國半導體股份有限公司 Power semiconductor device and the fabricating method thereof
US20200035579A1 (en) * 2018-07-25 2020-01-30 Infineon Technologies Ag Semiconductor Package Having Symmetrically Arranged Power Terminals and Method for Producing the Same
TW202143420A (en) * 2020-04-07 2021-11-16 美商克里菲亞特維拉公司 Power module

Similar Documents

Publication Publication Date Title
JP4455488B2 (en) Semiconductor device
US6400014B1 (en) Semiconductor package with a heat sink
US7847395B2 (en) Package and package assembly of power device
KR100752239B1 (en) Power module package structure
JP4954356B1 (en) Circuit board for peripheral circuit of large capacity module, and large capacity module including peripheral circuit using the circuit board
JP2011253862A (en) Power semiconductor device
CN101958307A (en) Power semiconductor module and method of manufacturing the same
CN111261598B (en) Packaging structure and power module applicable to same
JPWO2018185974A1 (en) Semiconductor device, method of manufacturing the same, and power converter
TW201642404A (en) Package structure
US11658089B2 (en) Semiconductor device
US3936866A (en) Heat conductive mounting and connection of semiconductor chips in micro-circuitry on a substrate
JP2009246063A (en) Cooling structure of power module and semiconductor device using same
US10945333B1 (en) Thermal management assemblies having cooling channels within electrically insulated posts for cooling electronic assemblies
JP2019149501A (en) Wiring board and electronic device
WO2007138681A1 (en) Resin-sealed semiconductor device and electronic device using such semiconductor device
TWI829465B (en) Power module
JP5318304B1 (en) Semiconductor module and semiconductor device
JP2020087966A (en) Semiconductor module and semiconductor device using the same
TWI767543B (en) Package structure
CN114975342A (en) Power module and vehicle-mounted power circuit
JP7354550B2 (en) External connection part of semiconductor module, semiconductor module, external connection terminal, and method for manufacturing external connection terminal of semiconductor module
JPWO2013018330A1 (en) Device mounting substrate and semiconductor power module
JP2009231296A (en) Heat radiation type multiple hole semiconductor package
JP2020205337A (en) Semiconductor module and semiconductor device