TWI829465B - Power module - Google Patents
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- TWI829465B TWI829465B TW111147725A TW111147725A TWI829465B TW I829465 B TWI829465 B TW I829465B TW 111147725 A TW111147725 A TW 111147725A TW 111147725 A TW111147725 A TW 111147725A TW I829465 B TWI829465 B TW I829465B
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- 239000002184 metal Substances 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims description 22
- 239000011159 matrix material Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000000565 sealant Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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Abstract
Description
本案係關於一種功率模組,尤指一種將多個半導體器件設置於一塊基板上的功率模組。This case relates to a power module, specifically a power module in which multiple semiconductor devices are arranged on a substrate.
在現有充電樁設備中,電源轉換單元需使用多顆TO247架構之離散式元件。每一顆TO247架構之離散式元件具有一顆MOSFET晶片,離散式元件的尺寸及功率密度固定。In existing charging pile equipment, the power conversion unit requires the use of multiple TO247 structured discrete components. Each TO247 structured discrete device has a MOSFET chip, and the size and power density of the discrete device are fixed.
由於每一顆離散式元件的尺寸及功率密度固定,因此若要滿足不斷上升之功率需求的設備,相較於傳統較低功率需求之設備,則須同時使用較多顆的離散式元件,以滿足高功率要求。然而,設備若使用較多顆的離散式元件將導致體積增加,且因電子元件的數量增加,設備內部之散熱更加困難。Since the size and power density of each discrete component are fixed, devices that meet rising power requirements must use more discrete components at the same time than traditional devices with lower power requirements. Meet high power requirements. However, if the device uses more discrete components, the volume will increase, and due to the increase in the number of electronic components, it will be more difficult to dissipate heat inside the device.
因此,如何發展一種可改善上述習知技術之功率模組,實為目前迫切之需求。Therefore, how to develop a power module that can improve the above-mentioned conventional technology is currently an urgent need.
本案之目的為提供一種功率模組將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而降低體積,並提升功率密度。此外,本案功率模組之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組之結構穩定性並延長使用壽命。The purpose of this project is to provide a power module that disposes multiple semiconductor devices on a substrate, thereby replacing multiple traditional discrete components with one power module, thereby reducing the volume and increasing the power density. In addition, the positive voltage and negative voltage pins of the power module in this case are respectively attached to the middle position on the side of the metal surface, thus increasing the structural stability of the power module and extending its service life.
根據本案之構想,本案提供一種功率模組,包含基板、多個半導體器件、多個引腳及封裝體。基板包含第一金屬表面,多個半導體器件設置於第一金屬表面上。每一引腳的出腳方向垂直於第一金屬表面的底邊。封裝體用於包覆第一金屬表面、多個半導體器件,並且部分包覆每一引腳,每一引腳沿著相同的方向延伸出封裝體。多個引腳包含正電壓引腳及負電壓引腳,且正電壓引腳的末端貼附於第一金屬表面的第一側邊的中間位置,且負電壓引腳的末端貼附於第一金屬表面的第二側邊的中間位置,第一及第二側邊在空間上彼此相對,且第一及第二側邊均連接於第一金屬表面的底邊。According to the concept of this case, this case provides a power module, including a substrate, multiple semiconductor devices, multiple pins and a package. The substrate includes a first metal surface, and a plurality of semiconductor devices are disposed on the first metal surface. The outlet direction of each pin is perpendicular to the bottom edge of the first metal surface. The package body is used to cover the first metal surface, the plurality of semiconductor devices, and partially cover each pin, and each pin extends out of the package body along the same direction. The plurality of pins include a positive voltage pin and a negative voltage pin, and the end of the positive voltage pin is attached to the middle position of the first side of the first metal surface, and the end of the negative voltage pin is attached to the first At the middle position of the second side of the metal surface, the first and second sides are spatially opposite to each other, and both the first and second sides are connected to the bottom side of the first metal surface.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案之範圍,且其中的說明及圖示在本質上係當作說明之用,而非架構於限制本案。Some typical embodiments embodying the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various changes in different aspects without departing from the scope of this case, and the descriptions and illustrations are essentially for illustrative purposes and are not intended to limit this case.
第1圖係為本案較佳實施例之功率模組1的立體結構示意圖,第2圖為第1圖之功率模組1的部分立體結構示意圖,第3圖為第2圖之功率模組1的俯視圖。如第1、2及3圖所示,功率模組1包含基板2、多個半導體器件3、多個引腳及封裝體5。基板2包含第一金屬表面20,多個半導體器件3設置於第一金屬表面20上。於一些實施例中,引腳的數量為奇數且大於或等於三。每一引腳的出腳方向垂直於第一金屬表面20的底邊21。封裝體5用於包覆第一金屬表面20、多個半導體器件3,並且部分包覆每一引腳,每一引腳沿著相同的方向延伸出封裝體5。多個引腳包含正電壓引腳40及負電壓引腳41,其中正電壓引腳40的末端400貼附於第一金屬表面20的第一側邊22的中間位置 (例如但不限於第一側邊22的中點),負電壓引腳41的末端410貼附於第一金屬表面20的第二側邊23的中間位置 (例如但不限於第二側邊23的中點)。由於正電壓引腳40的末端400及負電壓引腳41的末端410分別貼附於第一側邊22及第二側邊23的中間位置,因此,當功率模組1於組裝過程中若受外力影響時,功率模組1之結構較為穩定,進而提升功率模組1之可靠度與使用壽命。第一側邊22及第二側邊23在空間上彼此相對,且第一側邊22及第二側邊23均連接於第一金屬表面20的底邊21。本案之功率模組1將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而減少體積,並提升功率密度。此外,本案功率模組1之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組1之結構穩定性並延長使用壽命。Figure 1 is a schematic three-dimensional structural diagram of the
於一些實施例中,正電壓引腳40的末端400設置於兩個半導體器件3之間,負電壓引腳41的末端410設置於兩個半導體器件3之間。由於正電壓引腳40及負電壓引腳41之末端400及410分別設置於兩個半導體器件3之間,因此可增加功率模組1之散熱效果。In some embodiments, the
於一些實施例中,半導體器件3的數量為偶數個,如第1至3圖所示之功率模組1,其包含四個半導體器件3,且四個半導體器件3在第一金屬表面20上排列形成矩陣。矩陣之中心O、第一側邊22及第二側邊23的中間位置於空間上位於相同之水平線L。In some embodiments, the number of
於一些實施例中,多個引腳還包含相電壓引腳42,且相電壓引腳42設置於正電壓引腳40及負電壓引腳41之間。相電壓引腳42的末端420貼附於第一金屬表面20,且末端420貼附於第一金屬表面20之位置較水平線L靠近底邊21。相電壓引腳42與正電壓引腳40之間的第一間距R1相同於相電壓引腳42與負電壓引腳41之間的第二間距R2。In some embodiments, the plurality of pins further include a
於一些實施例中,正電壓引腳40、負電壓引腳41及相電壓引腳42具有相同的截面積,且正電壓引腳40、負電壓引腳41及相電壓引腳42具有多個引腳4中最大之截面積,故正電壓引腳40、負電壓引腳41及相電壓引腳42可以承受自功率模組1外部所輸入之電源電流。In some embodiments, the
於一些實施例中,多個引腳還包含第一閘極引腳43及第一源極引腳44,且第一閘極引腳43及第一源極引腳44設置於第一間距R1內,意即第一閘極引腳43及第一源極引腳44位於相電壓引腳42與正電壓引腳40之間。第一閘極引腳43的末端430及第一源極引腳44的末端440相鄰於第一金屬表面20的底邊21,且藉由至少一電力傳輸線6使第一閘極引腳43的末端430及第一源極引腳44的末端440電連接第一金屬表面20。本案之複數個電力傳輸線6中,部分之電力傳輸線6係用於訊號傳輸,部分之電力傳輸線6係用於電力傳輸。於一些實施例中,電力傳輸線6之訊號係由第一金屬表面20上之半導體器件3所提供。封裝體5包覆第一閘極引腳43的末端430及第一源極引腳44的末端440。需特別說明的是,為維持圖式簡潔,於圖式中僅給予部分電力傳輸線6標號。In some embodiments, the plurality of pins further include a
於一些實施例中,多個引腳還包含第二閘極引腳45及第二源極引腳46,且第二閘極引腳45及第二源極引腳46設置於第二間距R2內,意即第二閘極引腳45及第二源極引腳46位於相電壓引腳42與負電壓引腳41之間。第二閘極引腳45的末端450及第二源極引腳46的末端460相鄰於第一金屬表面20的底邊21,且藉由至少一電力傳輸線6使第二閘極引腳45的末端450及第二源極引腳46的末端460電連接第一金屬表面20。於一些實施例中,電力傳輸線6之訊號係由第一金屬表面20上之半導體器件3所提供。封裝體5包覆第二閘極引腳45的末端450及第二源極引腳46的末端460。In some embodiments, the plurality of pins further include a
請參閱第4圖,第4圖為第3圖之功率模組1接收電源電流時的電流流向示意圖。每一半導體器件3分別藉由至少一電力傳輸線6電性連接第一金屬表面20。於第4圖中,實心箭頭方向代表電源電流經由正電壓引腳40及相電壓引腳42分別流入及流出功率模組1之方向。當正電壓引腳40接收電源電流時,經由第一金屬表面20及至少一電力傳輸線6,使電源電流流經相較於底邊21高於水平線L的半導體器件3 (即為與底邊21位於水平線L之相異側的半導體器件3),而後電源電流經由相電壓引腳42流出功率模組1。Please refer to Figure 4. Figure 4 is a schematic diagram of the current flow when the
本案功率模組之引腳設置位置不限於第3及4圖所示之功率模組1,請參閱第5圖,第5圖所示之功率模組1與第4圖所示之功率模組1之差異在於本實施例之引腳設置位置之不同,於第5圖所示之實施例中,負電壓引腳41設置於相電壓引腳42及正電壓引腳40之間,第二閘極引腳45及第二源極引腳46位於正電壓引腳40與負電壓引腳41之間,第一閘極引腳43及第一源極引腳44位於負電壓引腳41與相電壓引腳42之間。於第5圖中,實心箭頭方向代表電源電流經由正電壓引腳40及相電壓引腳42分別流入及流出功率模組1之方向。於第5圖所示實施例中,在電源電流流經相較於底邊21高於水平線L的半導體器件3之後,電源電流經由相電壓引腳42流出功率模組1。The pin setting position of the power module in this case is not limited to the
於一些實施例中,電源電流可經由相電壓引腳42流入功率模組1,並流經相較於底邊21低於水平線L之半導體器件3 (即為與底邊21位於水平線L之相同側的半導體器件3),電源電流經由相電壓引腳42流入功率模組1之實施例分別以第4及5圖例示說明如下。In some embodiments, the power supply current can flow into the
請參閱第4及5圖,於第4及5圖中,空心箭頭方向代表電源電流經由相電壓引腳42及負電壓引腳41分別流入及流出功率模組1之方向。於第4圖所示實施例中,當相電壓引腳42接收電源電流時,經由第一金屬表面20及至少一電力傳輸線6,使電源電流流經相較於底邊21低於水平線L的半導體器件3,而後電源電流經由負電壓引腳41流出功率模組1。Please refer to Figures 4 and 5. In Figures 4 and 5, the hollow arrow directions represent the directions in which the power supply current flows into and out of the
本案功率模組於第一金屬表面20上之電力傳輸線6之連接方式不限於第3、4及5圖所示之功率模組1,請參閱第6圖,第6圖所示之功率模組1與第3、4及5圖所示之功率模組1之差異僅在於本實施例之電力傳輸線6之連接方式不同,其中,於不同實施例之間,電力傳輸線6之連接方式可根據半導體器件3及多個引腳之間的設置關係而有所不同。The connection method of the
請再參閱第1圖,於一些實施例中,封裝體5具有可拆卸之上層封膠50與下層封膠51以及兩個固定組件52。於一些實施例中,上層封膠50及下層封膠51為一體成形,且上層封膠50及下層封膠51為射出成型的環氧樹酯(Epoxy),上層封膠50及下層封膠51形成封裝體5。於另一些實施例中,上層封膠50及下層封膠51形成封裝體5後係透過兩個固定組件52相固接,固定組件52可為例如但不限於鎖固螺絲。Please refer to FIG. 1 again. In some embodiments, the
請參閱第7圖,第7圖為第1圖之功率模組1之剖面結構示意圖。本案之基板2還包含導熱絕緣板24及第二金屬表面25,導熱絕緣板24具有相對之第一面240及第二面241,第一金屬表面20貼附於導熱絕緣板24的第一面240,且第二金屬表面25貼附於導熱絕緣板24的第二面241,第二金屬表面25裸露於封裝體5。於一些實施例中,封裝體5是由制模化合物所製造,且制模化合物之製造材料為環氧樹脂。Please refer to Figure 7. Figure 7 is a schematic cross-sectional structural diagram of the
綜上所述,本案提供一種功率模組將複數個半導體器件設置於一個基板上,藉此以一顆功率模組取代多顆傳統之離散式元件,進而降低體積,並提升功率密度。此外,本案功率模組之正電壓及負電壓引腳分別貼附於金屬表面側邊的中間位置,因此增加功率模組之結構穩定性並延長使用壽命,且由於正電壓及負電壓引腳之末端設置於兩個半導體器件之間,因此可增加功率模組之散熱效果。To sum up, this project provides a power module that disposes multiple semiconductor devices on a substrate, thereby replacing multiple traditional discrete components with one power module, thereby reducing the volume and increasing the power density. In addition, the positive voltage and negative voltage pins of the power module in this case are respectively attached to the middle position on the side of the metal surface, thus increasing the structural stability of the power module and extending its service life. The end is disposed between two semiconductor devices, thereby increasing the heat dissipation effect of the power module.
須注意,上述僅是為說明本案而提出之較佳實施例,本案不限於所述之實施例,本案之範圍由如附專利申請範圍決定。且本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附專利申請範圍所欲保護者。It should be noted that the above are only preferred embodiments proposed to illustrate this case. This case is not limited to the embodiments described. The scope of this case is determined by the scope of the attached patent application. Moreover, this case may be modified in various ways by those who are familiar with this technology, but it will not deviate from the intended protection within the scope of the attached patent application.
1:功率模組
2:基板
20:第一金屬表面
21:底邊
22:第一側邊
23:第二側邊
24:導熱絕緣板
240:第一面
241:第二面
25:第二金屬表面
3:半導體器件
40:正電壓引腳
41:負電壓引腳
400、410:末端
42相電壓引腳
420:末端
43:第一閘極引腳
44:第一源極引腳
430、440:末端
45:第二閘極引腳
46:第二源極引腳
450、460:末端
5:封裝體
50:上層封膠
51:下層封膠
52:固定組件
6:電力傳輸線
O:矩陣之中心
L:水平線
R1:第一間距
R2:第二間距1: Power module
2:Substrate
20: First metal surface
21: Bottom
22:First side
23:Second side
24:Thermal conductive insulation board
240: First side
241:Second side
25: Second metal surface
3: Semiconductor devices
40: Positive voltage pin
41:
第1圖係為本案較佳實施例之功率模組的立體結構示意圖。Figure 1 is a schematic three-dimensional structural diagram of a power module according to a preferred embodiment of the present invention.
第2圖為第1圖之功率模組的部分立體結構示意圖。Figure 2 is a partial three-dimensional structural diagram of the power module in Figure 1.
第3圖為第2圖之功率模組的俯視圖。Figure 3 is a top view of the power module in Figure 2.
第4圖為第3圖之功率模組接收電源電流時的電流流向示意圖。Figure 4 is a schematic diagram of the current flow when the power module in Figure 3 receives power current.
第5圖為本案另一較佳實施例之功率模組接收電源電流時的電流流向示意圖。Figure 5 is a schematic diagram of the current flow when the power module receives power current according to another preferred embodiment of the present invention.
第6圖為本案另一較佳實施例之功率模組接收電源電流時的電流流向示意圖。Figure 6 is a schematic diagram of the current flow when the power module receives power current according to another preferred embodiment of the present invention.
第7圖為第1圖之功率模組之剖面結構示意圖。Figure 7 is a schematic cross-sectional structural diagram of the power module in Figure 1.
1:功率模組 1: Power module
40:正電壓引腳 40: Positive voltage pin
41:負電壓引腳 41: Negative voltage pin
42:相電壓引腳 42: Phase voltage pin
43:第一閘極引腳 43: First gate pin
44:第一源極引腳 44: First source pin
45:第二閘極引腳 45: Second gate pin
46:第二源極引腳 46: Second source pin
5:封裝體 5:Package
50:上層封膠 50: Upper sealant
51:下層封膠 51: Lower sealant
52:固定組件 52: Fixed components
Claims (15)
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TW111147725A TWI829465B (en) | 2022-12-13 | 2022-12-13 | Power module |
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TW111147725A TWI829465B (en) | 2022-12-13 | 2022-12-13 | Power module |
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TWI829465B true TWI829465B (en) | 2024-01-11 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070176299A1 (en) * | 2006-01-17 | 2007-08-02 | Ralf Otremba | Power Semiconductor Component Having Chip Stack |
TW201643995A (en) * | 2015-06-12 | 2016-12-16 | 萬國半導體股份有限公司 | Power semiconductor device and the fabricating method thereof |
US20170331209A1 (en) * | 2013-02-07 | 2017-11-16 | Samsung Electronics Co., Ltd. | Substrate and terminals for power module and power module including the same |
US20200035579A1 (en) * | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Semiconductor Package Having Symmetrically Arranged Power Terminals and Method for Producing the Same |
TW202143420A (en) * | 2020-04-07 | 2021-11-16 | 美商克里菲亞特維拉公司 | Power module |
-
2022
- 2022-12-13 TW TW111147725A patent/TWI829465B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070176299A1 (en) * | 2006-01-17 | 2007-08-02 | Ralf Otremba | Power Semiconductor Component Having Chip Stack |
US20170331209A1 (en) * | 2013-02-07 | 2017-11-16 | Samsung Electronics Co., Ltd. | Substrate and terminals for power module and power module including the same |
TW201643995A (en) * | 2015-06-12 | 2016-12-16 | 萬國半導體股份有限公司 | Power semiconductor device and the fabricating method thereof |
US20200035579A1 (en) * | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Semiconductor Package Having Symmetrically Arranged Power Terminals and Method for Producing the Same |
TW202143420A (en) * | 2020-04-07 | 2021-11-16 | 美商克里菲亞特維拉公司 | Power module |
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