TW201639150A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of connecting portions. The stacks are disposed on the substrate. Each of the stacks comprises alternately-stacked conductive layers and insulating layers. The memory layers are disposed on sidewalls of the stacks, respectively. The channel layers are disposed on the memory layers, respectively, wherein each of the channel layers comprises a surface being exposed. The connecting portions connect the surface of each of the channel layers to the substrate, respectively.

Description

Semiconductor structure and method of manufacturing same 【0001】

The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor structure in which a channel layer is attached to a substrate, and a method of fabricating the same.

【0002】

In order to reduce the volume and weight, increase the power density, and improve the portability, the industry is working to increase the density of semiconductor devices. One way to achieve this is to replace the traditional two-dimensional (2D) structure with a three-dimensional (3D) structure. The three-dimensional semiconductor structure may include multiple stacks formed on a substrate. These stacks are separated from one another by high aspect ratio trenches or holes. Certain structures may be formed in the trenches or holes along the sidewalls of the stack and/or at the bottom of the trenches or holes. However, as the height of the stack increases, certain problems with these structures may arise. For example, such structures may be more difficult to form and maintain their intended shape and state.

[0003]

The present invention relates to a semiconductor structure that focuses on a structure formed on a sidewall of a stack, and a method of fabricating the same.

[0004]

In accordance with some embodiments, a method of fabricating a semiconductor structure is provided. This method includes the following steps. First, a plurality of stacks are formed on a substrate. A plurality of memory layers are formed on the sidewalls of the stacks, respectively. A plurality of channel layers are formed on the memory layer, respectively, and a surface of each of the channel layers is exposed. Thereafter, a plurality of connecting portions are formed, and the connecting portions respectively connect the surfaces of the channel layers to the substrate.

[0005]

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of stacked layers, a plurality of memory layers, a plurality of channel layers, and a plurality of connections. The stack is disposed on the substrate. The stack includes alternating conductive layers and insulating layers, respectively. The memory layers are respectively disposed on the sidewalls of the stack. The channel layers are respectively disposed on the memory layer, and the channel layers respectively include a surface exposed. The connecting portion connects the surfaces of each of the channel layers to the substrate, respectively.

[0006]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0062]

102, 202, 302, 402, 502, 602‧‧‧ substrates
104, 204, 304, 408, 508, 608‧‧‧ stack
106, 206, 306‧‧‧ sacrificial layer
108, 208, 308, 412, 512, 612‧‧ ‧ insulation
110, 210, 310, 414, 514, 614‧‧‧ hard mask layers
112, 212, 312‧‧‧Selective epitaxial growth layer
114, 214, 314, 416, 516, 616‧‧‧ memory layers
120, 220, 324, 422, 522, 626‧‧‧ channel layer
122, 424‧‧‧ spacers
124‧‧‧Connecting Department
126‧‧‧Selective epitaxial growth layer
128, 226, 330‧‧‧ oxide
130, 228, 332‧‧ ‧ air gap
132, 230, 334‧‧‧ conductive layer
134, 232, 336 ‧ ‧ barrier layer
222‧‧‧Connection layer
224‧‧‧Connecting Department
316, 618‧‧‧ remaining
320, 622‧‧‧ virtual channel layer
322, 624‧‧‧ oxide
326‧‧‧Connection layer
328‧‧‧Connecting Department
404, 504, 604‧‧ ‧ buried layer
406, 506, 606‧‧‧ source line
410, 510, 610‧‧‧ conductive layer
426‧‧‧Connecting Department
428‧‧‧Selective epitaxial growth layer
526‧‧‧Connection layer
528‧‧‧Connecting Department
530‧‧‧Connecting Department
628‧‧‧Connection layer
630‧‧‧Connecting Department
632‧‧‧Connecting Department
1040, 2040, 3040, 4080, 5080, 6080‧‧‧ stack
1060, 2060, 3060‧‧‧ sacrificial layer
1080, 2080, 3080, 4120, 5120, 6120‧‧‧ insulation
1100, 2100, 3100, 4140, 5140, 6140‧‧‧ hard mask layers
1140, 2140, 4160, 5160‧‧‧ conformal memory layers
1160, 2160, 3160, 4180, 5180, 6180‧‧‧ oxide layers
1180, 2180, 3180, 4200, 5200, 6200‧‧‧ nitride layer
1200, 2200, 3240, 4220, 5220, 6260‧‧‧ conformal channel layers
1220, 4240‧‧‧ spacer layer
2220, 5240‧‧‧ spacer layer
3140, 6160‧‧‧ conformal memory layer
3142, 6162‧‧‧ main part
3200, 6220‧‧‧ virtual conformal channel layer
4100, 5100, 6100‧‧‧ conductive layer
S‧‧‧ surface

【0007】

FIGS. 1A-1H illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.
2A-2I illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.
3A-3J illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.
4A-4F illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.
5A-5H illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.
6A-6I illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

[0008]

A method of fabricating a semiconductor structure, and a semiconductor structure fabricated thereby, will now be described in this specification, with particular attention to structures formed on the sidewalls of the stack. This method includes the following steps. First, a plurality of stacks are formed on a substrate. A plurality of memory layers are formed on the sidewalls of the stacks, respectively. A plurality of channel layers are formed on the memory layer, respectively, and a surface of each of the channel layers is exposed. Thereafter, a plurality of connecting portions are formed, and the connecting portions respectively connect the surfaces of the channel layers to the substrate.

【0009】

FIGS. 1A-1H illustrate a method of fabricating a semiconductor structure in accordance with an embodiment. Referring to FIG. 1A, a substrate 102 is provided. The substrate 102 may be formed of tantalum and is p-type doped. A stack 1040 is formed on the substrate 102. In the present embodiment, the stack 1040 includes a plurality of sacrificial layers 1060 and a plurality of insulating layers 1080 alternately stacked on the substrate 102. The sacrificial layer 1060 may be formed of tantalum nitride (SiN), and the insulating layer 1080 may be formed of an oxide. Alternatively, in another embodiment, the sacrificial layer 1060 can be replaced by a conductive layer, such as a doped polysilicon. The stack 1040 can also optionally include a hard mask layer 1100 formed over the sacrificial layer 1060 and over the insulating layer 1080. The hard mask layer 1100 may be formed of SiN. The hard mask layer 1100 formed of SiN can prevent the stack 1040 from bending or collapsing. In addition, it can also be used as a stop layer in chemical mechanical polishing (CMP) processing.

[0010]

Please refer to FIG. 1B to pattern stack 1040. As such, a plurality of stacks 104 are formed on the substrate 102. Stacks 104 include sacrificial layers 106 and insulating layers 108 (and optionally hard mask layers 110) that are alternately stacked. In one embodiment, as shown in FIG. 1C, a plurality of Selective Epitaxial Growing (SEG) layers 112 may be formed on the substrate 102 between the stacks 104. The selective epitaxial growth layer 112 is formed of undoped polysilicon. By providing the selective epitaxial growth layer 112, the resistance of the source line when it is turned on can be reduced. In the following figures, the depiction of the selective epitaxial growth layer 112 is omitted, even though it may still be present.

[0011]

Referring to FIG. 1D, a conformal memory layer 1140 is formed over the stack 104. In an embodiment, the conformal memory layer 1140 includes a blocking layer, a trapping layer, and a tunneling layer. The conformal memory layer 1140 may have an oxide-nitride-oxide (ONO) structure, an oxide-nitride-oxide-nitride-oxide (ONONO) structure, or an oxide-nitride-oxide-nitrogen A compound-oxide-nitride-oxide (ONONONO) structure or the like. The ONONONO structure including the oxide layer 1160 and the nitride layer 1180 is illustrated. A conformal channel layer 1200 is formed over the conformal memory layer 1140. The conformal channel layer 1200 can be formed of polysilicon. In one example, the conformal channel layer 1200 has a thickness of about 150 Å. The conformal memory layer 1140, and the conformal channel layer 1200 can be formed by deposition.

[0012]

Referring to FIG. 1E, a spacer layer 1220 is formed on the conformal channel layer 1200. According to an embodiment, the spacer layer 1220 can be formed by oxidizing the conformal channel layer 1200. As such, in the previous step, the deposited polysilicon can have a thicker thickness. In addition, polycrystalline germanium grains may grow in the oxidation process. Larger grain sizes favor higher mobility, resulting in higher cell currents. In one example, after the oxidation process, the remaining conformal channel layer 1200 has a thickness of about 100 Å and the spacer layer 1220 formed has a thickness of about 110 Å. Alternatively, in another embodiment, the spacer layer 1220 can be formed by depositing an oxide. The oxide layer protects the underlying polysilicon layer.

[0013]

Referring to FIG. 1F, the spacer layer 1220, the conformal channel layer 1200, and the conformal memory layer 1140 are separated. As a result, the memory layer 114, the channel layer 120, and the spacers 122 are formed. Memory layers 114 are formed on the sidewalls of stack 104, respectively. The channel layers 120 are formed on the memory layer 114, respectively. At this time, a surface S of each of the channel layers 120 is exposed. Spacers 122 are formed on the channel layer 120, respectively. This separate process can be performed by etching (e.g., dry etching).

[0014]

Referring to FIG. 1G, a selective epitaxial growth process is performed to form a plurality of connection portions 124. The connecting portion 124 connects the surface S of each of the channel layers 120 to the substrate 102, respectively. The connection portion 124 is a selective epitaxial growth layer formed by the undoped germanium grown from the germanium substrate 102. At the same time, a selective epitaxial growth layer 126 may be formed on the channel layer 120 of the polysilicon. In one embodiment, a dip process using dilute hydrofluoric acid may be selectively performed to remove naturally grown oxides prior to the selective epitaxial growth process. However, the spacer 122 formed of oxide should remain intact.

[0015]

Various processes can then be performed. In an embodiment, as shown in FIG. 1H, oxide 128 is filled into the space between stacks 104, where an air gap 130 may be formed in oxide 128. Also, the selective epitaxial growth layer 126 formed on the channel layer 120 can be removed by a chemical mechanical polishing process associated with the oxide 128. Moreover, in the embodiment illustrated in FIGS. 1A-1H, the sacrificial layer 106 in the stack 104 may be replaced by the conductive layer 132. The conductive layer 132 may be formed of a metal such as tungsten (W). Further, a barrier layer 134 may be formed, and the barrier layer 134 is formed of, for example, titanium nitride (TiN).

[0016]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 102, a plurality of stacks 104, a plurality of memory layers 114, a plurality of channel layers 120, and a plurality of connections 124. The stack 104 is disposed on the substrate 102. The stack 104 includes alternating conductive layers 132 and insulating layers 108, respectively. Memory layers 114 are disposed on the sidewalls of stack 104, respectively. The channel layers 120 are respectively disposed on the memory layer 114, and the channel layers 120 respectively include a surface S exposed. In an embodiment, the semiconductor structure may further include a plurality of spacers 122 disposed on the channel layer 120, respectively. The connecting portion 124 connects the surface S of each of the channel layers 120 to the substrate 102, respectively. In this embodiment, the connecting portion 124 is a selective epitaxial growth layer. For the sake of brevity, other features are not repeated here.

[0017]

2A-2I illustrate a method of fabricating a semiconductor structure in accordance with another embodiment. Referring to FIG. 2A, a substrate 202 is provided. The substrate 202 may be formed of tantalum and is p-type doped. A stack 2040 is formed on the substrate 202. In the present embodiment, the stack 2040 includes a plurality of sacrificial layers 2060 and a plurality of insulating layers 2080 that are alternately stacked on the substrate 202. The sacrificial layer 2060 may be formed of SiN, and the insulating layer 2080 may be formed of an oxide. The stack 2040 can also optionally include a hard mask layer 2100 formed over the sacrificial layer 2060 and the insulating layer 2080.

[0018]

Please refer to FIG. 2B to pattern stack 2040. As such, a plurality of stacks 204 are formed on the substrate 202. Stack 204 includes sacrificial layers 206 and insulating layers 208 (and optionally hard mask layer 210) that are alternately stacked. In an embodiment, as shown in FIG. 2C, a plurality of selective epitaxial growth layers 212 may be formed on the substrate 202 between the stacks 204. The selective epitaxial growth layer 212 is formed of undoped polysilicon. In the following figures, the depiction of the selective epitaxial growth layer 212 is omitted, even though it may still be present.

[0019]

Referring to FIG. 2D, a conformal memory layer 2140 is formed over the stack 204. In an embodiment, the conformal memory layer 2140 includes a barrier layer, a capture layer, and a tunneling layer. The conformal memory layer 2140 may have an ONO structure, an ONONO structure, an ONONONO structure, or the like. The ONONONO structure including the oxide layer 2160 and the nitride layer 2180 is illustrated in the drawings. A conformal channel layer 2200 is formed over the conformal memory layer 2140. The conformal channel layer 2200 can be formed of polysilicon. Since another polysilicon layer will be formed in the next step of the embodiment, the thickness of the conformal channel layer 2200 can be thinner than the thickness of the conformal channel layer 1200. In one example, the conformal channel layer 2200 has a thickness of about 100 Å. The conformal memory layer 2140, and the conformal channel layer 2200 can be formed by deposition.

[0020]

Referring to FIG. 2E, a spacer layer 2220 is formed on the conformal channel layer 2200. According to an embodiment, the spacer layer 2220 can be formed by oxidizing the conformal channel layer 2200. In one example, after the oxidation treatment, the remaining conformal channel layer 2200 has a thickness of about 60 Å, and the spacer layer 2220 is formed to have a thickness of about 100 Å.

[0021]

Referring to FIG. 2F, the spacer layer 2220, the conformal channel layer 2200, and the conformal memory layer 2140 are separated. As a result, the memory layer 214 and the channel layer 220 are formed. Memory layers 214 are formed on the sidewalls of stack 204, respectively. Channel layers 220 are formed on memory layer 214, respectively. A surface S of each of the channel layers 220 is exposed. This separate process can be performed by etching (e.g., dry etching). At this time, part of the spacer layer 2220 remains on the channel layer 220. Next, the spacer layer 2220 remaining on the channel layer 220 is removed, as shown in FIG. 2G. This removal process can be carried out by using an immersion treatment of dilute hydrofluoric acid. In some cases, portions of the oxide layer in memory layer 214 that are exposed may also be etched.

[0022]

Referring to FIG. 2H, a connection layer 222 is formed on the channel layer 220, and the connection layer 222 extends from the channel layer 220 to the substrate 202. The connection layer 222 includes a connection portion 224 that connects the surface S of each of the channel layers 220 to the substrate 202, respectively. The connection layer 222 may be formed of undoped polysilicon. The tie layer 222 can be formed by depositing over the entire structure. In one example, the tie layer 222 has a thickness of about 70 Å.

[0023]

Various processes can then be performed. In an embodiment, as shown in FIG. 2I, oxide 226 is filled into the space between stacks 204, wherein an air gap 228 may be formed in oxide 226. Also, portions of the tie layer 222 formed on the stack 204 can be removed by a chemical mechanical polishing process associated with the oxide 226. Moreover, in the embodiment illustrated in FIGS. 2A-2I, the sacrificial layer 206 in the stack 204 can be replaced by the conductive layer 230. Conductive layer 230 may be formed of a metal, such as tungsten. Further, a barrier layer 232 may be formed, and the barrier layer 232 is formed of, for example, TiN.

[0024]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 202, a plurality of stacks 204, a plurality of memory layers 214, a plurality of channel layers 220, and a connection layer 222. The stack 204 is disposed on the substrate 202. The stack 204 includes alternating conductive layers 230 and insulating layers 208, respectively. Memory layers 214 are disposed on the sidewalls of stack 204, respectively. The channel layers 220 are respectively disposed on the memory layer 214, and the channel layers 220 respectively include a surface S exposed. The connection layer 222 is disposed on the channel layer 220 and further extends from the channel layer 220 to the substrate 202. The connection layer 222 includes a connection portion 224 that connects the surface S of each of the channel layers 220 to the substrate 202, respectively. For the sake of brevity, other features are not repeated here.

[0025]

3A-3J illustrate a method of fabricating a semiconductor structure according to still another embodiment. Referring to FIG. 3A, a substrate 302 is provided. The substrate 302 may be formed of tantalum and is p-type doped. A stack 3040 is formed on the substrate 302. In the present embodiment, the stack 3040 includes a plurality of sacrificial layers 3060 and a plurality of insulating layers 3080 that are alternately stacked on the substrate 302. The sacrificial layer 3060 may be formed of SiN, and the insulating layer 30800 may be formed of an oxide. The stack 3040 can also optionally include a hard mask layer 3100 formed over the sacrificial layer 3060 and the insulating layer 3080.

[0026]

Please refer to FIG. 3B to pattern stack 3040. As a result, a plurality of stacks 304 are formed on the substrate 302. Stacks 304 include sacrificial layers 306 and insulating layers 308 (optionally including hard mask layer 310) that are alternately stacked, respectively. In an embodiment, as shown in FIG. 3C, a plurality of selective epitaxial growth layers 312 may be formed on the substrate 302 between the stacks 304. The selective epitaxial growth layer 312 is formed of undoped polysilicon. In the following figures, the depiction of the selective epitaxial growth layer 312 is omitted, even though it may still exist.

[0027]

Referring to FIG. 3D, a conformal memory layer 3140 is formed over the stack 304. The conformal memory layer 3140 can have a nitride-oxide (NO) structure, a nitride-oxide-nitride-oxide (NONO) structure, or a nitride-oxide-nitride-oxide-nitride-oxidation. (NONONO) structure and so on. The NONONO structure including the oxide layer 3160 and the nitride layer 3180 is illustrated in the drawings. A virtual conformal channel layer 3200 is formed over the conformal memory layer 3140. The virtual conformal channel layer 3200 can be formed of polysilicon. In one example, the virtual conformal channel layer 3200 has a thickness of about 100 Å. The conformal memory layer 3140, and the virtual conformal channel layer 3200 can be formed by deposition.

[0028]

Referring to FIG. 3E, the virtual conformal channel layer 3200 and the conformal memory layer 3140 are separated. In this way, one of the main portions 3142 of the memory layer and the virtual channel layer 320 are formed. The main portions 3142 of the memory layer are formed on the sidewalls of the stack 304, respectively. Virtual channel layers 320 are formed on the main portion 3142 of each of the memory layers. This separate process can be performed by etching (e.g., dry etching). Next, as shown in FIG. 3F, the dummy channel layer 320 is removed and the outermost nitride layer in the main portion 3142 of the memory layer is exposed. This removal process can be performed by etching using diluted NH ₄ OH. In some cases, the germanium substrate 302 may also be etched. However, the main portion 3142 of the memory layer will remain intact.

[0029]

Referring to FIG. 3G, a remaining portion 316 of each of the memory layers 314 is formed. In one embodiment, the formed memory layer 314 includes a barrier layer, a capture layer, and a tunneling layer. According to an embodiment, the remaining portion 316 (the oxide layer) of the memory layer 314 can be formed by oxidizing the outermost nitride layer of the memory portion 10142 in the main portion 3142 of the In-Situ Steam Generation (ISSG). At the same time, an oxide 322 may be formed at a portion exposed by the substrate 302. In one example, the oxide layer formed by the ISSG oxidation in the memory layer 314 has a thickness of about 10 to 13 Å and the oxide 322 has a thickness of about 30 Å. In one embodiment, an immersion treatment using dilute hydrofluoric acid may be selectively performed to remove naturally grown oxides prior to the ISSG oxidation treatment. In this embodiment, since the outermost oxide layer of the memory layer is formed by an additional process after the etching process, even if the oxide layer is very thin, for example, only about 10 to 20 Å (typical in the memory layer) An oxide layer, for example, about 50 Å), is also not damaged by the etching process.

[0030]

A conformal channel layer 3240 is formed over the stack 304 and the memory layer 314. The conformal channel layer 3240 can be formed of undoped polysilicon. The conformal channel layer 3240 can be formed by deposition. In one example, the conformal channel layer 3240 has a thickness of about 80 Å.

[0031]

Referring to Figure 3H, the conformal channel layer 3240 is separated. As a result, a plurality of channel layers 324 are formed. Channel layers 324 are formed on memory layer 314, respectively. A surface S of each of the channel layers 324 is exposed. This separate process can be performed by etching. In this etching process, the channel layer 324 remains almost or completely intact. That is, the method according to the present embodiment has an advantage in relation to the maintenance of channel layer integrity.

[0032]

Referring to Figure 3I, oxide 322 is removed, for example, by an immersion treatment using dilute hydrofluoric acid. Next, a tie layer 326 is formed over the channel layer 324, and the tie layer 326 extends further from the channel layer 324 to the substrate 302. The connection layer 326 includes a connection portion 328 that connects the surface S of each of the channel layers 324 to the substrate 302, respectively. Connection layer 326 can be formed of undoped polysilicon. The tie layer 326 can be formed by deposition over the entire structure.

[0033]

Various processes can then be performed. In an embodiment, as shown in FIG. 3J, oxide 330 is filled into the space between stacks 304, wherein an air gap 332 may be formed in oxide 330. Also, portions of the tie layer 326 formed on the stack 304 can be removed by a chemical mechanical polishing process associated with the oxide 330. Moreover, in the embodiment illustrated in FIGS. 3A-3J, the sacrificial layer 306 in the stack 304 can be replaced by the conductive layer 334. Conductive layer 334 can be formed of a metal, such as tungsten. Further, a barrier layer 336 may be formed, which is formed, for example, of TiN.

[0034]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 302, a plurality of stacks 304, a plurality of memory layers 314, a plurality of channel layers 324, and a connection layer 326. The stack 304 is disposed on the substrate 302. The stack 304 includes alternating conductive layers 334 and insulating layers 308, respectively. Memory layers 314 are disposed on the sidewalls of stack 304, respectively. The channel layers 324 are respectively disposed on the memory layer 314, and the channel layers 324 respectively include a surface S exposed. The connection layer 326 is disposed on the channel layer 324 and extends from the channel layer 324 to the substrate 302. The connection layer 326 includes a connection portion 328 that connects the surface S of each of the channel layers 324 to the substrate 302, respectively. For the sake of brevity, other features are not repeated here.

[0035]

4A-4F illustrate a method of fabricating a semiconductor structure in accordance with yet another embodiment. Referring to FIG. 4A, a substrate 402 is provided. In this embodiment, the substrate 402 includes a buried layer 404 and a source line formed on the buried layer 404. The buried layer 404 can be an oxide buried layer. Source line 406 can be heavily doped with n-type. A stack 4080 is formed on the substrate 402. In the present embodiment, the stack 4080 includes a plurality of conductive layers 4100 and a plurality of insulating layers 4120 alternately stacked on the substrate 402. The conductive layer 4100 may be formed of a p-type heavily doped polysilicon, and the insulating layer 4120 may be formed of an oxide. The stack 4080 can also optionally include a hard mask layer 4140 formed over the conductive layer 4100 and the insulating layer 4120. The hard mask layer 4140 may be formed of SiN.

[0036]

Please refer to FIG. 4B to pattern stack 4080. As such, a plurality of stacks 408 are formed on the substrate 402. Stack 408 includes alternating conductive layers 410 and insulating layers 412 (and optionally hard mask layer 414).

[0037]

Referring to FIG. 4C, a conformal memory layer 4160 is formed over the stack 408. In an embodiment, the conformal memory layer 4160 includes a barrier layer, a capture layer, and a tunneling layer. The conformal memory layer 4160 may have an ONO structure, an ONONO structure, or an ONONONO or the like. The ONONONO structure including the oxide layer 4180 and the nitride layer 4200 is illustrated in the drawings. A conformal channel layer 4220 is formed over the conformal memory layer 4160. The conformal channel layer 4220 can be formed of polysilicon. In one example, the conformal channel layer 4220 has a thickness of about 150 Å. The conformal memory layer 4160, and the conformal channel layer 4220 can be formed by deposition.

[0038]

Referring to FIG. 4D, a spacer layer 4240 is formed on the conformal channel layer 4220. According to an embodiment, the spacer layer 4240 can be formed by oxidizing the conformal channel layer 4220. In one example, after the oxidation process, the remaining conformal channel layer 4220 has a thickness of about 100 Å, and the spacer layer 4240 is formed to have a thickness of about 110 Å. The oxide layer protects the underlying polysilicon layer.

[0039]

Referring to FIG. 4E, the spacer layer 4240, the conformal channel layer 4220, and the conformal memory layer 4160 are separated. As a result, the memory layer 416, the channel layer 422, and the spacer 424 are formed. Memory layers 416 are formed on the sidewalls of stack 408, respectively. Channel layers 422 are formed on memory layer 416, respectively. At this time, a surface S of each of the channel layers 422 is exposed. Spacers 424 are formed on channel layer 422, respectively. This separate process can be performed by etching (e.g., dry etching).

[0040]

Referring to FIG. 4F, a selective epitaxial growth process is performed to form a plurality of connection portions 426. The connecting portion 426 connects the surface S of each of the channel layers 422 to the substrate 402, respectively. More specifically, the connection portion 426 is connected to the source line 406. The connection portion 426 is a selective epitaxial growth layer formed of n-type heavily doped germanium grown from the n-type heavily doped source line 406. At the same time, a selective epitaxial growth layer 428 may be formed on the channel layer 422 of the polysilicon. The selective epitaxial growth layer 428 can be removed in a later step. In one embodiment, an immersion treatment using dilute hydrofluoric acid may be selectively performed to remove naturally grown oxides prior to the selective epitaxial growth process. However, the spacer 424 formed of oxide should remain intact.

[0041]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 402, a plurality of stacks 408, a plurality of memory layers 416, a plurality of channel layers 422, and a plurality of connections 426. The substrate 402 can include a buried layer 404 and a source line 406 formed on the buried layer 404. The stack 408 is disposed on the substrate 402. The stack 408 includes alternating conductive layers 410 and insulating layers 412, respectively. Memory layers 416 are disposed on the sidewalls of stack 408, respectively. The channel layers 422 are respectively disposed on the memory layer 416, and the channel layers 422 respectively include a surface S exposed. In an embodiment, the semiconductor structure may further include a plurality of spacers 424 disposed on the channel layer 422, respectively. The connecting portion 426 connects the surface S of each of the channel layers 422 to the substrate 402, respectively. More specifically, the connecting portion 426 connects the surface S of each of the channel layers 422 to the source line 406, respectively. In the present embodiment, the connecting portion 426 is a selective epitaxial growth layer. The connection portion 426 can be heavily doped n-type. For the sake of brevity, other features are not repeated here.

[0042]

5A-5H illustrate a method of fabricating a semiconductor structure according to still another embodiment. Referring to FIG. 5A, a substrate 502 is provided. In the present embodiment, the substrate 502 includes a buried layer 504 and a source line 506 formed on the buried layer 504. The buried layer 504 can be an oxide buried layer. Source line 506 can be heavily doped n-type. A stack 5080 is formed on the substrate 502. In the present embodiment, the stack 5080 includes a plurality of conductive layers 5100 and a plurality of insulating layers 5120 alternately stacked on the substrate 502. The conductive layer 5100 may be formed of a p-type heavily doped polysilicon, and the insulating layer 5120 may be formed of an oxide. The stack 5080 can also optionally include a hard mask layer 5140 formed over the conductive layer 5100 and the insulating layer 5120.

[0043]

Please refer to FIG. 5B to pattern stack 5080. As such, a plurality of stacks 508 are formed on the substrate 502. Stack 508 includes alternating conductive layers 510 and insulating layers 512 (and optionally hard mask layer 514).

[0044]

Referring to FIG. 5C, a conformal memory layer 5160 is formed over the stack 508. In an embodiment, the conformal memory layer 5160 includes a barrier layer, a capture layer, and a tunneling layer. The conformal memory layer 5160 may have an ONO structure, an ONONO structure, an ONONONO structure, or the like. The ONONONO structure including the oxide layer 5180 and the nitride layer 5200 is illustrated in the drawings. A conformal channel layer 5220 is formed over the conformal memory layer 5160. The conformal channel layer 5220 can be formed of polysilicon. Since another polysilicon layer will be formed in the next step of the embodiment, the thickness of the conformal channel layer 5220 can be thinner than the thickness of the conformal channel layer 4220. In one example, the conformal channel layer 5220 has a thickness of about 100 Å. The conformal memory layer 5160, and the conformal channel layer 5220 can be formed by deposition.

[0045]

Referring to FIG. 5D, a spacer layer 5240 is formed on the conformal channel layer 5220. According to an embodiment, the spacer layer 5240 can be formed by oxidizing the conformal via layer 5220. In one example, after the oxidation process, the remaining conformal channel layer 5220 has a thickness of about 60 Å, and the spacer layer 5240 is formed to have a thickness of about 100 Å.

[0046]

Referring to FIG. 5E, the spacer layer 5240, the conformal channel layer 5220, and the conformal memory layer 5160 are separated. As a result, the memory layer 516 and the channel layer 522 are formed. Memory layers 516 are formed on the sidewalls of stack 508, respectively. Channel layers 5220 are formed on the memory layer 51, respectively. A surface S of each of the channel layers 522 is exposed. This separate process can be performed by etching (e.g., dry etching). At this time, part of the spacer layer 5240 remains on the channel layer 522. Next, the spacer layer 5240 remaining on the channel layer 522 is removed, as shown in FIG. 5F. This removal process can be carried out by using an immersion treatment of dilute hydrofluoric acid. In some cases, portions of the oxide layer in memory layer 516 that are exposed may also be etched.

[0047]

Referring to FIG. 5G, a connection layer 526 is formed on the channel layer 522, and the connection layer 526 extends from the channel layer 522 to the substrate 502. The connection layer 526 includes a connection portion 528 that connects the surface S of each of the channel layers 522 to the substrate 502, respectively. More specifically, the connection portion 528 is connected to the source line 506. Connection layer 526 can be formed of undoped polysilicon. Connection layer 526 can be formed by deposition over the entire structure. The tie layer 526 has a thickness of about 70 Å in one example.

[0048]

Referring to FIG. 5H, the connection portion 528 can be converted into an n-type heavily doped. According to an embodiment, the doped junction 530 can be formed by rapid thermal treatment. With this treatment, the dopant diffuses from the n-type heavily doped source line 506 toward the channel layer 522. Alternatively, in another embodiment, ion implantation can be performed.

[0049]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 502, a plurality of stacked layers 508, a plurality of memory layers 516, a plurality of channel layers 522, and a connection layer 526. The substrate 502 can include a buried layer 504 and a source line 506 formed on the buried layer 504. The stack 508 is disposed on the substrate 502. The stack 508 includes alternating conductive layers 510 and insulating layers 512, respectively. Memory layers 516 are disposed on the sidewalls of stack 508, respectively. The channel layers 522 are respectively disposed on the memory layer 516, and the channel layers 522 respectively include a surface S exposed. The connection layer 526 is disposed on the channel layer 522 and extends from the channel layer 522 to the substrate 502. The connection layer 526 includes a connection portion 530 that connects the surface S of each of the channel layers 522 to the substrate 502, respectively. More specifically, the connecting portion 530 connects the surface S of each of the channel layers 522 to the source line 506, respectively. The connection portion 530 may be heavily doped n-type. For the sake of brevity, other features are not repeated here.

[0050]

6A-6I illustrate a method of fabricating a semiconductor structure in accordance with yet another different embodiment. Referring to FIG. 6A, a substrate 602 is provided. In the present embodiment, the substrate 602 includes a buried layer 604 and a source line 606 formed on the buried layer 604. The buried layer 604 can be an oxide buried layer. Source line 606 can be heavily doped with n-type. A stack 6080 is formed on the substrate 602. In the present embodiment, the stack 6080 includes a plurality of conductive layers 6100 and a plurality of insulating layers 6120 alternately stacked on the substrate 602. The conductive layer 6100 may be formed of a p-type heavily doped polysilicon, and the insulating layer 6120 may be formed of an oxide. The stack 6080 can also optionally include a hard mask layer 6140 formed over the conductive layer 6100 and the insulating layer 6120.

[0051]

Please refer to FIG. 6B to pattern stack 6080. As such, a plurality of stacks 608 are formed on the substrate 602. Stack 608 includes alternating conductive layers 610 and insulating layers 612 (and optionally hard mask layer 614).

[0052]

Referring to FIG. 6C, a conformal memory layer 6160 is formed over the stack 608. The conformal memory layer 616 can have a nitride-oxide (NO) structure, a nitride-oxide-nitride-oxide (NONO) structure, or a nitride-oxide-nitride-oxide-nitride-oxidation. (NONONO) structure and so on. The NONONO structure including the oxide layer 6180 and the nitride layer 6200 is illustrated in the drawings. A virtual conformal channel layer 6220 is formed over the conformal memory layer 6160. The virtual conformal channel layer 6220 can be formed of polysilicon. In one example, the virtual conformal channel layer 6220 has a thickness of about 100 Å. The conformal memory layer 6160, and the virtual conformal channel layer 6220 can be formed by deposition.

[0053]

Referring to FIG. 6D, the virtual conformal channel layer 6220 and the conformal memory layer 6160 are separated. As a result, one of the main portions 6162 of the memory layer and the virtual channel layer 622 are formed. The main portions 6162 of the memory layer are formed on the sidewalls of the stack 608, respectively. Virtual channel layers 622 are formed on the main portion 6162 of each of the memory layers. This separate process can be performed by etching (e.g., dry etching). Next, as shown in FIG. 6E, the dummy channel layer 622 is removed and the outermost nitride layer in the memory layer main portion 6162 is exposed. This removal process can be performed by etching using diluted NH ₄ OH. In some cases, the germanium substrate 602 may also be etched. However, the main portion of the memory layer 6162 will remain intact.

[0054]

Referring to FIG. 6F, a remaining portion 618 of each of the memory layers 616 is formed. In one embodiment, the formed memory layer 616 includes a barrier layer, a capture layer, and a tunneling layer. According to an embodiment, the remaining portion 618 (oxide layer) of the memory layer 616 can be formed by oxidizing the outermost nitride layer in the main portion 6162 of the memory layer by ISSG. At the same time, an oxide 624 may be formed at a portion of the substrate 602 that is exposed. In one example, the oxide layer formed by the ISSG oxidation in the memory layer 616 has a thickness of about 10 to 13 Å and the oxide 624 has a thickness of about 30 Å. In one embodiment, an immersion treatment using dilute hydrofluoric acid may be selectively performed to remove naturally grown oxides prior to the ISSG oxidation treatment. In this embodiment, since the outermost oxide layer of the memory layer is formed by an additional process after the etching process, even if the oxide layer is very thin, for example, only about 10-20 Å (typical in the memory layer) An oxide layer, for example, about 50 Å), is also not damaged by the etching process.

[0055]

A conformal channel layer 6260 is formed over the stack 608 and the memory layer 616. The conformal channel layer 6260 can be formed of polysilicon. The conformal channel layer 6260 can be formed by deposition. In one example, the conformal channel layer 6260 has a thickness of about 80 Å.

[0056]

Please refer to Figure 6G to separate the conformal channel layer 6260. As a result, a plurality of channel layers 626 are formed. Channel layers 626 are formed on memory layer 616, respectively. A surface S of each of the channel layers 626 is exposed. This separate process can be performed by etching. In this etch process, the channel layer 626 remains almost or completely intact. That is, the method according to the present embodiment has an advantage in relation to the maintenance of channel layer integrity.

[0057]

Referring to Figure 6H, oxide 624 is removed, for example, by an immersion treatment using dilute hydrofluoric acid. Next, a tie layer 628 is formed over the channel layer 626, and the tie layer 628 extends further from the channel layer 626 to the substrate 602. The connection layer 628 includes a connection portion 630 that connects the surface S of each of the channel layers 626 to the substrate 602, respectively. More specifically, the connection portion 630 is connected to the source line 606. The tie layer 628 can be formed of polysilicon. The tie layer 628 can be formed by deposition over the entire structure.

[0058]

Referring to FIG. 6I, the connection portion 630 can be converted into n-type heavily doped. According to an embodiment, the doped connection portion 632 can be formed by rapid thermal processing. With this treatment, dopants diffuse from the n-type heavily doped source line 606 toward the channel layer 626. Alternatively, in another embodiment, ion implantation can be performed.

[0059]

The semiconductor structure fabricated by the method according to the present embodiment includes a substrate 602, a plurality of stacks 608, a plurality of memory layers 616, a plurality of channel layers 626, and a connection layer 628. The substrate 602 can include a buried layer 604 and a source line 606 formed on the buried layer 604. The stack 608 is disposed on the substrate 602. The stack 608 includes alternating conductive layers 610 and insulating layers 612, respectively. Memory layers 616 are disposed on the sidewalls of stack 608, respectively. The channel layers 626 are respectively disposed on the memory layer 616, and the channel layers 626 respectively include a surface S exposed. The tie layer 628 is disposed on the channel layer 626 and extends from the channel layer 626 to the substrate 602. The connection layer 628 includes a connection portion 632 that connects the surface S of each of the channel layers 626 to the substrate 602, respectively. More specifically, the connecting portion 632 connects the surface S of each of the channel layers 626 to the source line 606, respectively. The connection portion 632 may be heavily doped n-type. For the sake of brevity, other features are not repeated here.

[0060]

According to an embodiment, the channel layer formed on the sidewalls of the stack can be attached to the substrate in a simple manner while maintaining the desired shape and state of the structure (e.g., without damaging the channel layer and the memory layer). The semiconductor structure in the embodiment may be, but not limited to, a three-dimensional memory such as a three-dimensional single gate vertical channel memory (for example, an example of FIGS. 4A-6I) or a three-dimensional inverse (NAND) memory (eg, 1A- An example of a 3J diagram), which is a linear pattern pattern or a hole pattern pattern.

[0061]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

402‧‧‧Substrate

404‧‧‧ buried layer

406‧‧‧ source line

408‧‧‧Stacking

410‧‧‧ Conductive layer

412‧‧‧Insulation

414‧‧‧hard mask layer

416‧‧‧ memory layer

422‧‧‧channel layer

424‧‧‧ spacers

426‧‧‧Connecting Department

428‧‧‧Selective epitaxial growth layer

Claims (10)

[Item 1] A method of fabricating a semiconductor structure, comprising:
Forming a plurality of stacks on a substrate;
Forming a plurality of memory layers on the sidewalls of the stacks;
Forming a plurality of channel layers on the memory layers and exposing a surface of each of the channel layers; and forming a plurality of connecting portions respectively connecting the surfaces of the channel layers to the substrate. [Item 2] The method for manufacturing a semiconductor structure according to claim 1, comprising:
After forming the stacks, forming a conformal memory layer over the stacks;
Forming a conformal channel layer over the conformal memory layer;
Forming a spacer layer on the conformal channel layer; and separating the spacer layer, the conformal channel layer, and the conformal memory layer to form the memory layers, the channel layers, and respectively formed on the spacer layer a plurality of spacers on the channel layers, and the surface exposing each of the channel layers;
Wherein the connecting portions are selective epitaxial growth layers. [Item 3] The method for manufacturing a semiconductor structure according to claim 1, comprising:
After forming the stacks, forming a conformal memory layer over the stacks;
Forming a conformal channel layer over the conformal memory layer;
Forming a spacer layer on the conformal channel layer;
Separating the spacer layer, the conformal channel layer, and the conformal memory layer to form the memory layers, the channel layers, and exposing the surface of each of the channel layers;
Removing the spacer layer remaining on the channel layers; and forming a connection layer on the channel layers, the connection layer further extending from the channel layers to the substrate, the connection layer including the connection portions. [Item 4] The method for manufacturing a semiconductor structure according to claim 1, comprising:
After forming the stacks, forming a conformal memory layer over the stacks;
Forming a virtual conformal channel layer over the conformal memory layer;
Separating the virtual conformal channel layer and the conformal memory layer to form a main portion of each of the memory layers and a plurality of virtual channel layers respectively formed on the main portion of each of the memory layers;
Removing the virtual channel layers;
Forming a remaining portion of each of the memory layers;
Forming a conformal channel layer over the stacks and the memory layers;
Separating the conformal channel layers to form the channel layers; and forming a connecting layer on the channel layers, the connecting layer further extending from the channel layers to the substrate, the connecting layer including the connecting portions. [Item 5] The method of fabricating a semiconductor structure according to claim 1, wherein the substrate comprises a buried layer and a source line formed on the buried layer, the connecting portions being connected to the source line. [Item 6] The method of fabricating a semiconductor structure according to claim 5, wherein the connecting portions are n-type heavily doped. [Item 7] A semiconductor structure comprising:
a substrate;
a plurality of stacked, disposed on the substrate, the stacks respectively comprising alternating conductive layers and insulating layers;
a plurality of memory layers respectively disposed on sidewalls of the stacks;
A plurality of channel layers are respectively disposed on the memory layers, the channel layers respectively including an exposed surface; and a plurality of connecting portions respectively connecting the surfaces of the channel layers to the substrate. [Item 8] For example, the semiconductor structure described in claim 7 includes:
a plurality of spacers respectively disposed on the channel layers;
Wherein the connecting portions are selective epitaxial growth layers. [Item 9] The semiconductor structure as described in claim 7 of the patent scope includes:
A connecting layer is disposed on the channel layers and further extends from the channel layers to the substrate, the connecting layer including the connecting portions. [Item 10] The semiconductor structure of claim 7, wherein the substrate comprises a buried layer and a source line formed on the buried layer, the connecting portions being connected to the source line.