TW201639106A - Fan-out stacked system in package (SIP) having dummy dies and methods of making the same - Google Patents

Fan-out stacked system in package (SIP) having dummy dies and methods of making the same Download PDF

Info

Publication number
TW201639106A
TW201639106A TW104139373A TW104139373A TW201639106A TW 201639106 A TW201639106 A TW 201639106A TW 104139373 A TW104139373 A TW 104139373A TW 104139373 A TW104139373 A TW 104139373A TW 201639106 A TW201639106 A TW 201639106A
Authority
TW
Taiwan
Prior art keywords
fan
layer
die
rdl
package
Prior art date
Application number
TW104139373A
Other languages
Chinese (zh)
Other versions
TWI601257B (en
Inventor
林宗澍
陳憲偉
謝政傑
黃昶嘉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201639106A publication Critical patent/TW201639106A/en
Application granted granted Critical
Publication of TWI601257B publication Critical patent/TWI601257B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/043—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Wrappers (AREA)

Abstract

An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the fan-out RDLs. The first fan-out tier includes one or more first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out tier includes one or more second device dies bonded to fan-out RDLs, a dummy die bonded to the fan-out RDLs, and a second molding compound extending along sidewalls of the one or more second device dies and the dummy die. The fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies, and the dummy die is substantially free of any active devices.

Description

具有虛設晶粒之扇出堆疊系統級封裝(SIP)及其製造方法 Fan-out stacking system-in-package (SIP) with dummy die and manufacturing method thereof

本揭露係關於具有虛設晶粒之扇出堆疊系統級封裝(SIP)及其製造方法。 The present disclosure relates to a fan-out stack system-in-package (SIP) with dummy dies and a method of fabricating the same.

3D封裝應用(如堆疊式封裝(PoP))日益流行，並廣泛用於移動設備上，此係因其等能夠藉由(例如)整合邏輯晶片(例如，應用處理器(AP))、高容量/帶寬記憶體晶片(例如，動態隨機存取記憶體(DRAM)、寬輸入/寬輸出(WIO)晶片、低功率雙倍資料傳輸率X(LPDDRX)晶片等)及/或其他異質晶片(例如，感測器、微電子系統(MEM)、網路設備等)增強電氣性能。現有的PoP裝置與封裝結構面臨著滿足下一代應用中細小通道及高密度佈線需求的挑戰。 3D packaging applications, such as stacked package (PoP), are becoming increasingly popular and widely used on mobile devices because they can, for example, integrate logic chips (eg, application processors (APs)), high capacity. /Bandwidth memory chips (eg, dynamic random access memory (DRAM), wide input/wide output (WIO) chips, low power double data rate X (LPDDR X ) wafers, etc.) and/or other heterogeneous wafers ( For example, sensors, microelectronic systems (MEM), network devices, etc., enhance electrical performance. Existing PoP devices and package structures face the challenge of meeting the needs of small-channel and high-density cabling in next-generation applications.

根據一實施例，一種封裝包括第一扇出層、該第一扇出層上方的扇出重佈層(RDL)、以及該扇出RDL上方的第二扇出層。該第一扇出層包含一或複數第一裝置晶粒、及沿著該一或複數第一裝置晶粒的側壁延伸之第一模塑料。該第二扇出層包含接合至該扇出RDL的一或複數第二裝置晶粒、接合至該扇出RDL的虛設晶粒、及沿著該一或複數第二裝置晶粒與該虛設晶粒之側壁延伸的第二模塑料。該扇出 RDL將該一或複數第一裝置晶粒電性連接至該一或複數第二裝置晶粒，且該虛設晶粒實質上未具有任何有源裝置。 According to an embodiment, a package includes a first fan-out layer, a fan-out redistribution layer (RDL) above the first fan-out layer, and a second fan-out layer above the fan-out RDL. The first fan-out layer includes one or a plurality of first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out layer includes one or a plurality of second device dies bonded to the fan-out RDL, dummy dies bonded to the fan-out RDL, and the dummy crystal along the one or more second device dies a second molding compound extending from the sidewall of the grain. The fanout The RDL electrically connects the one or more first device dies to the one or more second device dies, and the dummy dies have substantially no active devices.

根據另一實施例，一種封裝包含第一裝置層、第二裝置層、及該第一裝置層與該第二裝置層之間的扇出重佈層(RDL)。該第一裝置層包含一或複數第一裝置晶粒、及環繞該一或複數第一晶粒的第一模塑料。第二裝置層包含一或複數第二裝置晶粒、虛設晶粒、及環繞該一或複數第二晶粒與該虛設晶粒的第二模塑料。該虛設晶粒的尺寸與材料係根據該第二裝置層所需的有效熱膨脹係數(CTE)而選擇。該一或複數第一裝置晶粒與該一或複數第二裝置晶粒電性連接至該扇出RDL。 In accordance with another embodiment, a package includes a first device layer, a second device layer, and a fan-out redistribution layer (RDL) between the first device layer and the second device layer. The first device layer includes one or a plurality of first device dies and a first molding compound surrounding the one or more first dies. The second device layer includes one or more second device dies, dummy dies, and a second molding compound surrounding the one or more second dies and the dummy dies. The size and material of the dummy die are selected based on the effective coefficient of thermal expansion (CTE) required for the second device layer. The one or more first device dies are electrically coupled to the one or more second device dies to the fanout RDL.

根據再一實施例，一種形成封裝的方法包含形成第一扇出層、在該第一扇出層上方形成扇出重佈層(RDL)以及在該扇出RDL上方形成第二扇出層。形成該第一扇出層包含繞一或複數第一裝置晶粒形成第一模塑料。形成該第二扇出層包含將一或複數第二裝置晶粒接合至該扇出RDL、將虛設晶粒接合至該扇出RDL、以及圍繞該一或複數第二裝置晶粒與該虛設晶粒分散第二模塑料。該虛設晶粒的尺寸與材料係根據該第二扇出層的所需的有效熱膨脹係數(CTE)而選擇。 In accordance with still another embodiment, a method of forming a package includes forming a first fan-out layer, forming a fan-out redistribution layer (RDL) over the first fan-out layer, and forming a second fan-out layer over the fan-out RDL. Forming the first fan-out layer includes forming a first molding compound around one or more first device dies. Forming the second fan-out layer includes bonding one or more second device dies to the fan-out RDL, bonding dummy dies to the fan-out RDL, and surrounding the one or more second device dies and the dummy crystal The particles disperse the second molding compound. The size and material of the dummy die are selected based on the desired effective coefficient of thermal expansion (CTE) of the second fan-out layer.

100‧‧‧封裝 100‧‧‧Package

101A‧‧‧扇出層 101A‧‧‧Fan sector

101B‧‧‧扇出層 101B‧‧‧Fan sector

102‧‧‧半導體晶粒 102‧‧‧Semiconductor grains

104‧‧‧半導體晶粒 104‧‧‧Semiconductor grains

106‧‧‧虛設晶粒 106‧‧‧Virtual dies

108A‧‧‧RDL 108A‧‧‧RDL

108B‧‧‧RDL 108B‧‧‧RDL

108C‧‧‧RDL 108C‧‧‧RDL

110‧‧‧柱形塊 110‧‧‧column block

118‧‧‧黏膠層 118‧‧‧Adhesive layer

120‧‧‧外部連接件 120‧‧‧External connectors

124‧‧‧模塑料 124‧‧‧Molded plastic

126‧‧‧TIV 126‧‧‧TIV

150‧‧‧連接件 150‧‧‧Connecting parts

100A‧‧‧中間部分 100A‧‧‧ middle part

100B‧‧‧邊緣部分 100B‧‧‧Edge section

P1‧‧‧間距 P1‧‧‧ spacing

x‧‧‧軸 X‧‧‧axis

y‧‧‧軸 Y‧‧‧Axis

W1‧‧‧寬度 W1‧‧‧Width

W2‧‧‧寬度 W2‧‧‧Width

W3‧‧‧寬度 W3‧‧‧Width

W4‧‧‧寬度 W4‧‧‧Width

L1‧‧‧長度 L1‧‧‧ length

L2‧‧‧長度 L2‧‧‧ length

L3‧‧‧長度 L3‧‧‧ length

L4‧‧‧長度 L4‧‧‧ length

T1‧‧‧高度差 T1‧‧‧ height difference

T2‧‧‧高度差 T2‧‧‧ height difference

200‧‧‧封裝 200‧‧‧Package

300‧‧‧封裝 300‧‧‧Package

自後述詳細說明與附屬圖式，可最佳理解本揭露之各方面。須注意，依據產業之標準實施方式，各種構件並非依比例繪製。實際上，為了清楚討論，可任意增大或減小各種構件之尺寸。 The various aspects of the disclosure are best understood from the detailed description and the appended drawings. It should be noted that, depending on the standard implementation of the industry, the various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion.

圖1A與圖1B根據一些實施例顯示第一裝置封裝的剖面圖及俯視圖。 1A and 1B show cross-sectional and top views of a first device package, in accordance with some embodiments.

圖2A至圖2C根據一些實施例顯示第一裝置封裝的各個剖面輪廓。 2A-2C show various cross-sectional profiles of a first device package in accordance with some embodiments.

圖3A至圖3G根據一些實施例顯示製造第一裝置封裝件之中間步驟的剖面圖。 3A-3G show cross-sectional views of intermediate steps in the fabrication of a first device package, in accordance with some embodiments.

圖4根據本揭露一些實施例顯示第二裝置封裝的剖面圖。 4 shows a cross-sectional view of a second device package in accordance with some embodiments of the present disclosure.

圖5根據本揭露一些實施例顯示第三裝置封裝的剖面圖。 Figure 5 shows a cross-sectional view of a third device package in accordance with some embodiments of the present disclosure.

圖6根據本揭露一些其他實施例顯示形成具有虛設晶粒之裝置封裝的流程圖。 6 shows a flow chart showing the formation of a device package with dummy dies in accordance with some other embodiments of the present disclosure.

以下揭露之內容提供許多不同的實施例或範例，用於實施本案所提供之主題的不同特徵。元件與配置的特定範例之描述如下，以簡化本揭露。自然，此等僅為範例，並非旨在限制本揭露。例如，以下在第二構件上或上方形成第一構件的敘述，可包含形成直接接觸之第一與第二構件的實施例，亦可包含在該第一與第二構件之間形成其他構件，因而該第一與第二構件並未直接接觸的實施例。另外，本揭露可在不同範例中重複元件符號及/或字母。此一重複之目的係為了簡化與清晰化，而非支配所討論的各實施例及/或架構之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided herein. Specific examples of components and configurations are described below to simplify the disclosure. Naturally, these are merely examples and are not intended to limit the disclosure. For example, the following description of forming a first member on or over a second member may include embodiments for forming first and second members in direct contact, and may also include forming other members between the first and second members, Thus the embodiment in which the first and second members are not in direct contact. In addition, the present disclosure may repeat the component symbols and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not govern the relationship between the various embodiments and/or structures discussed.

另，為了易於描述，可使用空間對應語詞，例如「之下」、「下方」、「較低」、「上方」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或構件與另一元件或構件的關係。空間對應詞語係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置可被定位(旋轉90度或是其他位向)，並可相應解釋本揭露使用的空間對應描述。 In addition, for ease of description, space-specific words such as "below", "below", "lower", "above", "higher" and the like may be used to describe a component in the drawing or The relationship of a component to another component or component. Spatially corresponding terms are used to include different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device can be positioned (rotated 90 degrees or other orientations) and the corresponding description of the space used in the disclosure can be interpreted accordingly.

在一些方面，各種例示性實施例可實現整合例如記憶體(例如，DRAM、LPDDRX、WIO等)與邏輯晶片之薄型封裝輪廓。在薄輪廓之堆疊扇出封裝中可以達到改善之記憶體容量與帶寬。實施例可使用通孔間貫穿(through-intervias,TIV)作為代替貫穿基板通孔(through substrate vias,TSV)之選項，或者在TSV之基礎上使用 TIV，以減少矽資源之損失以及製造成本。所提供之實施例亦可提供更好的堆疊系統級封裝(SiP)之熱性能及更低的RLC寄生效應。 In some aspects, various exemplary embodiments may enable integration of thin package outlines such as memory (eg, DRAM, LPDDR X , WIO, etc.) with logic wafers. Improved memory capacity and bandwidth can be achieved in a thin profile stacked fanout package. Embodiments may use through-intervias (TIV) as an alternative to through substrate vias (TSVs) or TIVs based on TSVs to reduce the loss of germanium resources and manufacturing costs. The embodiments provided may also provide better thermal performance of stacked system in package (SiP) and lower RLC parasitics.

在一些實施例中，將各種裝置晶片整合於扇出SiP中。各種晶片可以配置於堆疊扇出層中，而每一層之間的RDL提供晶片及/或外部連接件之間的電性連接。例如，核心邏輯晶片(例如，應用處理器(AP)、晶片單系統(SoC)等)使用封裝之TIV(配置於每一扇出層中)與RDL(配置於每一層之上或之下)與其他扇出層之晶片通訊。TSV亦可可選地在晶片中作為進一步之電性連接使用。裝置封裝之每一扇出層可包括如下元件中之一或複數個：動態隨機存取記憶體(DRAM)、低功率雙倍資料傳輸率X(LPDDRX)、寬輸入/寬輸出(WIO)記憶體、NAND快閃記憶體、SRAM高速緩衝記憶體等類似記憶體晶片。亦可包括其他類型之晶片，例如，邏輯晶片、類比晶片、感測器晶片、網路晶片、微電子機械系統(MEMS)晶片等。每一扇出層中晶片之數目可大於或等於一。整合扇出SiP可使用在各種應用，例如，行動運算、行動醫療(例如健康監測)、穿戴式電子產品、物聯網(IoT)、大數據(big data)等。 In some embodiments, various device wafers are integrated into a fan-out SiP. Various wafers can be placed in the stacked fan-out layer, and the RDL between each layer provides an electrical connection between the wafer and/or external connectors. For example, a core logic chip (eg, an application processor (AP), a chip single system (SoC), etc.) uses a packaged TIV (configured in each fanout layer) and an RDL (configured on or under each layer) Communicate with other fan-out layers. The TSV can also optionally be used in the wafer as a further electrical connection. Each fan-out layer of the device package may include one or more of the following components: dynamic random access memory (DRAM), low power double data rate X (LPDDR X ), wide input / wide output (WIO) Memory, NAND flash memory, SRAM cache memory and other similar memory chips. Other types of wafers may also be included, such as logic wafers, analog wafers, sensor wafers, network wafers, microelectromechanical systems (MEMS) wafers, and the like. The number of wafers in each fanout layer may be greater than or equal to one. Integrated fan-out SiP can be used in a variety of applications, such as mobile computing, mobile medical (such as health monitoring), wearable electronics, Internet of Things (IoT), big data, and more.

不同扇出層之晶粒的各種配置可能導致熱膨脹係數(CTE)的不匹配。例如，參見圖1A，每一扇出層101(標為101A與101B)包括一或複數個半導體晶粒102/104，由於此等晶粒102/104中存在之半導體材料(例如，矽)，其具有約為3.0之有效CTE。層101可更包含各種其他材料(例如，模塑料124及/或TIV126)，其具有更高之有效CTE。層101中存在晶粒102與104的，自每一層101的整體有效CTE之中減去周邊材料的有效CTE(例如，模塑料124及/或TIV126)，以作為每層之晶粒的總尺寸之函數。例如，具有更大晶粒的層，較具有更小晶粒的層擁有相對較低之有效CTE。 Various configurations of grains of different fan-out layers may result in a mismatch in coefficient of thermal expansion (CTE). For example, referring to FIG. 1A, each fan-out layer 101 (labeled 101A and 101B) includes one or more semiconductor dies 102/104 due to the presence of semiconductor material (eg, germanium) in the dies 102/104, It has an effective CTE of about 3.0. Layer 101 may further comprise various other materials (eg, molding compound 124 and/or TIV 126) that have a higher effective CTE. The presence of grains 102 and 104 in layer 101 subtracts the effective CTE of the surrounding material (e.g., molding compound 124 and/or TIV 126) from the overall effective CTE of each layer 101 as the total size of the grains of each layer. The function. For example, a layer with larger grains has a relatively lower effective CTE than a layer with smaller grains.

實施例各種晶粒可具有各種尺寸。例如，在當前之一些應用 中，邏輯晶粒(例如，晶粒102)可比複數個記憶體晶粒(例如，晶粒104)之組合表面積佔有明顯更大之表面積/覆蓋區域。於是，在沒有其他晶粒之情況下，具有邏輯晶粒之扇出層的有效CTE，可能低於具有複數個記憶體晶粒之扇出層的有效CTE。當裝置封裝處於室溫(例如，約25℃)且當裝置晶粒暴露於高溫環境(例如，約260℃或更高)時，各種層之CTE的不匹配可能導致翹曲。例如，所獲得之封裝可具有如圖2A所示之難以接受的大“哭”輪廓，其中封裝之中間部分100A高於封裝之邊緣部分100B。 Embodiments Various dies can have a variety of sizes. For example, in some current applications The logic grains (e.g., die 102) may occupy a significantly larger surface area/coverage area than the combined surface area of a plurality of memory grains (e.g., die 104). Thus, in the absence of other grains, the effective CTE of the fan-out layer with logic grains may be lower than the effective CTE of the fan-out layer with a plurality of memory grains. When the device package is at room temperature (eg, about 25 ° C) and when the device die is exposed to a high temperature environment (eg, about 260 ° C or higher), mismatching of CTEs of the various layers may result in warpage. For example, the resulting package may have an unacceptably large "cry" profile as shown in Figure 2A, with the middle portion 100A of the package being higher than the edge portion 100B of the package.

在一些實施例中，可將虛設晶粒(例如，虛設晶粒106)插入至一或複數個扇出層101，以減少CET不匹配並改善所獲得之封裝的翹曲輪廓。虛設晶粒可包含將扇出層之有效CTE調整至理想水準之任何合適材料。虛設晶粒可包括用於降低一層之有效CTE之材料，例如矽或玻璃。在其他實施例中，虛設晶粒可包括用於提高一層之有效CTE之材料，例如銅或聚合物。藉由包括虛設晶粒，可減少具有“哭”形狀之封裝的最高點與最低點之間的差(圖2A之尺寸T1)。或者，包括虛設晶粒可能導致封裝具有如圖2B所示之實質上水平的側表面。在另一個實施例中，包括虛設晶粒可能導致封裝具有如圖2C所示之“笑”輪廓，其中中間部分100A低於邊緣部分100B。 In some embodiments, dummy dies (eg, dummy dies 106) can be inserted into one or more of the fan-out layers 101 to reduce CET mismatch and improve the warp profile of the resulting package. The dummy die can include any suitable material that adjusts the effective CTE of the fan-out layer to an ideal level. The dummy die can include a material for reducing the effective CTE of a layer, such as germanium or glass. In other embodiments, the dummy grains may include materials for increasing the effective CTE of a layer, such as copper or a polymer. By including the dummy grains, the difference between the highest point and the lowest point of the package having the "crying" shape can be reduced (the size T1 of Fig. 2A). Alternatively, including dummy dies may result in the package having a substantially horizontal side surface as shown in Figure 2B. In another embodiment, including dummy dies may result in the package having a "smile" profile as shown in Figure 2C, with the middle portion 100A being lower than the edge portion 100B.

圖1A與圖1B顯示在裝置封裝100中包含虛設晶粒106以減少因層間之CTE不匹配所導致的翹曲。圖1A顯示兩扇出層101A與101B之剖面圖，其可為具有任何數目之扇出層的更大裝置封裝100之一部分。圖1B顯示與層101B對應之俯視圖。儘管1A顯示特定之封裝配置，但在其他實施例中，一或複數個虛設晶粒106可整合至具有任何封裝配置之裝置層中。 1A and 1B show the inclusion of dummy dies 106 in device package 100 to reduce warpage caused by CTE mismatch between layers. 1A shows a cross-sectional view of two fan-out layers 101A and 101B, which may be part of a larger device package 100 having any number of fan-out layers. FIG. 1B shows a top view corresponding to layer 101B. Although 1A shows a particular package configuration, in other embodiments, one or more dummy dies 106 can be integrated into a device layer having any package configuration.

扇出層101A包括邏輯晶粒102、圍繞邏輯晶粒102之模塑料124、及延伸穿過模塑料124之TIV 126。邏輯晶粒102可為AP、SoC等，且 邏輯晶粒102可提供封裝100之核心控制功能。在一些實施例中，核心邏輯晶粒102可為裝置封裝中功耗最多之晶粒(例如，產熱最多之晶粒)。晶粒102可包括半導體基板、有源裝置以及互連結構(未圖示)。基板可為塊狀矽基板，但亦可使用包括第III族、第IV族與第V族元素之其他半導體材料。或者，基板可為絕緣體上覆矽基板、絕緣體上覆鍺基板等。可於基板之頂表面形成例如電晶體之有源裝置。可於有源裝置上方且於基板之前面形成互連結構。本文使用之術語“面”或“正面”或側面係指裝置之主要表面，其上形成有源裝置與互連層。同樣地，晶粒之“背面”是與“面”或“正面”相對之主要表面。 The fan-out layer 101A includes a logic die 102, a molding compound 124 surrounding the logic die 102, and a TIV 126 extending through the molding compound 124. The logic die 102 can be an AP, a SoC, etc., and The logic die 102 can provide the core control functions of the package 100. In some embodiments, the core logic die 102 can be the most power consuming die in the device package (eg, the heat producing die). The die 102 can include a semiconductor substrate, active devices, and interconnect structures (not shown). The substrate may be a bulk germanium substrate, but other semiconductor materials including Group III, Group IV, and Group V elements may also be used. Alternatively, the substrate may be an overlying insulator substrate, an insulator overlying substrate, or the like. An active device such as a transistor can be formed on the top surface of the substrate. An interconnect structure can be formed over the active device and on the front side of the substrate. The term "face" or "front" or side as used herein refers to the major surface of the device on which the active device and interconnect layers are formed. Similarly, the "back" of the die is the major surface opposite the "face" or "front".

互連結構可包括層間介電質(ILD)及/或金屬間介電質(IMD)層，其包含使用任何合適方法形成之導電構件(例如，包含銅、鋁、鎢，其等之組合等之導線與通孔)。ILD與IMD可包括配置於此等導電構件之間的低k介電材料，所具有之k值例如低於約4.0或甚至2.8。在一些實施例中，ILD與IMD可由例如二氧化矽、SiCOH、聚合物等製成。互連結構電性連接各種有源裝置以形成晶粒102內之功能電路，例如邏輯控制電路。 The interconnect structure can include an interlayer dielectric (ILD) and/or an inter-metal dielectric (IMD) layer comprising conductive features formed using any suitable method (eg, comprising copper, aluminum, tungsten, combinations thereof, etc.) Wires and through holes). The ILD and IMD can comprise a low-k dielectric material disposed between the electrically conductive members, having a k value of, for example, less than about 4.0 or even 2.8. In some embodiments, the ILD and IMD can be made, for example, from cerium oxide, SiCOH, polymers, and the like. The interconnect structure electrically connects the various active devices to form functional circuits within the die 102, such as logic control circuits.

可於互連結構上形成輸入/輸出(I/O)與鈍化構件。例如，接觸墊可於互連結構上方形成並可藉由互連結構中之各種導電構件電性連接至有源裝置。接觸墊可包含例如鋁、銅等之導電材料。而且，可於互連結構與接觸墊上形成鈍化層。在一些實施例中，鈍化層可由例如二氧化矽、無摻雜矽酸鹽玻璃、氮氧化矽等材料形成。亦可使用其他合適之鈍化材料。鈍化層之部分可以覆蓋接觸墊之邊緣部分。柱形塊110可配置於接觸墊上方，介電材料112(例如，鈍化層)可以配置於相鄰的柱形塊110之間。在一些實施例中，介電材料112可包含聚合物。 Input/output (I/O) and passivation members can be formed on the interconnect structure. For example, the contact pads can be formed over the interconnect structure and can be electrically connected to the active device by various conductive members in the interconnect structure. The contact pads may comprise a conductive material such as aluminum, copper or the like. Moreover, a passivation layer can be formed on the interconnect structure and the contact pads. In some embodiments, the passivation layer can be formed of materials such as cerium oxide, undoped silicate glass, cerium oxynitride, and the like. Other suitable passivating materials can also be used. A portion of the passivation layer may cover an edge portion of the contact pad. The stud block 110 can be disposed over the contact pads, and a dielectric material 112 (eg, a passivation layer) can be disposed between adjacent stud blocks 110. In some embodiments, the dielectric material 112 can comprise a polymer.

柱形塊110可將晶粒102電性連接至沿晶粒102之邊緣側向延伸的正面RDL 108A。在圖1A所示之封裝100的方向，RDL 108A配置於扇出層101A之底表面。可於RDL 108A上形成外部連接件120(例如，球柵陣列(BGA)球等)，RDL 108A可將晶粒102電性連接至此等連接件。連接件120可進一步將封裝100與其他封裝元件接合，例如，其他裝置晶粒、中介層、封裝基板、印刷電路板、主機板等。在其他實施例中，RDL 108A可將晶粒102與形成於RDL 108A下方之其他扇出層電性連接。在此等實施例中，可將外部連接件120配置於封裝100之不同部分。 The stud block 110 can electrically connect the die 102 to the front side RDL 108A that extends laterally along the edge of the die 102. In the direction of the package 100 shown in FIG. 1A, the RDL 108A is disposed on the bottom surface of the fan-out layer 101A. An external connector 120 (e.g., a ball grid array (BGA) ball, etc.) can be formed on the RDL 108A, and the RDL 108A can electrically connect the die 102 to the connectors. The connector 120 can further bond the package 100 to other package components, such as other device dies, interposers, package substrates, printed circuit boards, motherboards, and the like. In other embodiments, the RDL 108A can electrically connect the die 102 to other fan-out layers formed under the RDL 108A. In such embodiments, the external connectors 120 can be disposed in different portions of the package 100.

背面RDL 108B可配置於扇出層101A之頂表面。TIV 126(例如，延伸穿過模塑料124)可提供RDL 108A與RDL 108B之間的訊號路徑，而晶粒102可藉由封裝110電性連接至RDL 108A、RDL 108B及TIV 126。在一些實施例中，晶粒102可更包含TSV(未圖示)以提供RDL 108A與RDL 108B之間的訊號路徑。晶粒102可藉由黏膠層(例如，晶粒附接膜(DAF)層118)附接於RDL 108B。 The back RDL 108B may be disposed on the top surface of the fan-out layer 101A. TIV 126 (eg, extending through molding compound 124) can provide a signal path between RDL 108A and RDL 108B, while die 102 can be electrically coupled to RDL 108A, RDL 108B, and TIV 126 by package 110. In some embodiments, the die 102 may further include a TSV (not shown) to provide a signal path between the RDL 108A and the RDL 108B. The die 102 can be attached to the RDL 108B by an adhesive layer (eg, a die attach film (DAF) layer 118).

第二扇出層101B配置於RDL 108B上。層101B包括晶粒104，晶粒104小於晶粒102。晶粒104可藉由連接件150(例如，柱形塊)電性連接至RDL 108B(以及晶粒102、TIV 126與RDL 108A)。在一些實施例中，晶粒104可包括類似於晶粒102之構件(例如，半導體基板、有源裝置、互連層、接觸墊等)。晶粒104中之功能電路可提供與晶粒102相同或不同之功能。例如，晶粒104可為任何類型之積體電路，例如記憶體晶粒(例如，DRAM、LPDDRX、WIO、NAND快閃記憶體等)、類比電路、數位電路、混合訊號電路、感測器晶粒、微電子機械系統(MEMS)晶粒、網路晶粒等。可在扇出層101B上方配置另外的RDL 108C，藉由黏膠層118將晶粒104附接至RDL 108C。在一些實施例中，晶粒104中之TSV(未圖示)可提供RDL 108B與RDL 108C之 間的訊號路徑。在一些實施例中，亦可在扇出層101B中形成TIV以提供RDL 108B與RDL 108C之間的訊號路徑。可於RDL 108C上方及/或層101B中形成另外的扇出層及/或互連構件以電性連接各種晶粒與RDL。 The second fan-out layer 101B is disposed on the RDL 108B. Layer 101B includes die 104, which is smaller than die 102. The die 104 can be electrically connected to the RDL 108B (and the die 102, TIV 126, and RDL 108A) by a connector 150 (eg, a pillar). In some embodiments, die 104 may include features similar to die 102 (eg, a semiconductor substrate, active devices, interconnect layers, contact pads, etc.). The functional circuitry in die 104 can provide the same or a different function than die 102. For example, the die 104 can be any type of integrated circuit, such as a memory die (eg, DRAM, LPDDR X , WIO, NAND flash memory, etc.), analog circuits, digital circuits, mixed signal circuits, sensors Die, microelectromechanical systems (MEMS) die, network die, etc. An additional RDL 108C can be placed over the fan-out layer 101B to attach the die 104 to the RDL 108C via the adhesive layer 118. In some embodiments, a TSV (not shown) in die 104 can provide a signal path between RDL 108B and RDL 108C. In some embodiments, a TIV may also be formed in the fan-out layer 101B to provide a signal path between the RDL 108B and the RDL 108C. Additional fan-out layers and/or interconnecting features may be formed over the RDL 108C and/or in the layer 101B to electrically connect the various dies and RDLs.

如圖1B之俯視圖所示，晶粒102(如虛線所示)所占之區域大於各個晶粒104之組合。例如，在所示之實施例中，晶粒102虛設晶粒106具有縱向尺寸L1、橫向尺寸W1、以及L1乘以W1之表面積。在一些實施例中，L1/W1之比約為0.8至1.2。每一個晶粒104具有縱向尺寸L2、橫向尺寸W2、以及L2乘以W2之表面積。在一些實施例中，L2/W2之比接近約1.0，例如為約0.8至1.2。在一些實施例中，晶粒102之表面積(例如，L1乘以W1)大於晶粒104之組合表面積(例如，L2乘以W2之兩倍)。在各個實施例中，各個寬度(例如，W1及/或W2)可為約3mm至約11mm。在這些實施例中，各個長度(例如，L1及/或L2)可為約10mm至約13mm。在其他實施例中亦可使用晶粒102及/或104之其他尺寸及/或比例。 As shown in the top view of FIG. 1B, the area of the die 102 (shown in dashed lines) is greater than the combination of the individual dies 104. For example, in the illustrated embodiment, the die 102 dummy die 106 has a longitudinal dimension L1, a lateral dimension W1, and a surface area of L1 multiplied by W1. In some embodiments, the ratio of L1/W1 is between about 0.8 and 1.2. Each of the dies 104 has a longitudinal dimension L2, a lateral dimension W2, and a surface area of L2 multiplied by W2. In some embodiments, the ratio of L2/W2 is approximately 1.0, such as from about 0.8 to 1.2. In some embodiments, the surface area of the die 102 (eg, L1 multiplied by W1) is greater than the combined surface area of the die 104 (eg, L2 times W2). In various embodiments, each width (eg, W1 and/or W2) can be from about 3 mm to about 11 mm. In these embodiments, each length (eg, L1 and/or L2) can be from about 10 mm to about 13 mm. Other dimensions and/or ratios of the dies 102 and/or 104 may also be used in other embodiments.

在沒有虛設晶粒106之情況下，層101A將比層101B包含更多之半導體材料(例如，矽)並具有更低之有效CTE。於是，層101B中包含至少一個虛設晶粒106以將層101B之有效CTE減少至所需的水準(例如，接近層101A之有效CTE)。虛設晶粒106可不包括任何功能電路或有源裝置。包含虛設晶粒106係為了降低層101A與101B之間的CTE不匹配，虛設晶粒106可不施行任何電功能並與封裝100內之其他構件(例如，RDL108及/或晶粒102/104)電性隔離。例如，虛設晶粒106可為一塊實質上純矽，以增加層101之半導體材料的量，減少層101A與101B之間的CTE不匹配。在其他實施例中，虛設晶粒106可包含其他合適之材料(例如，玻璃)以減少層101B之有效CTE。 Without the dummy die 106, layer 101A will contain more semiconductor material (e.g., germanium) than layer 101B and have a lower effective CTE. Thus, layer 101B includes at least one dummy die 106 to reduce the effective CTE of layer 101B to a desired level (e.g., near the effective CTE of layer 101A). The dummy die 106 may not include any functional circuits or active devices. Including dummy dies 106 in order to reduce the CTE mismatch between layers 101A and 101B, dummy dies 106 may not perform any electrical function and are electrically coupled to other components within package 100 (eg, RDL 108 and/or die 102/104). Sexual isolation. For example, dummy die 106 can be a substantially pure germanium to increase the amount of semiconductor material of layer 101, reducing the CTE mismatch between layers 101A and 101B. In other embodiments, dummy die 106 may comprise other suitable materials (eg, glass) to reduce the effective CTE of layer 101B.

在一些實施例中，虛設晶粒106具有縱向尺寸L3與橫向尺寸W3。 在一些實施例中，L3/W3之比接近約2.0。層101B之晶粒間的距離(例如，P1)可為約0.1mm。扇出層101B可具有縱向尺寸L4與橫向尺寸W4。對於虛設晶粒106，亦可使用具有不同尺寸與間隔之其他配置。可依據配置虛設晶粒106之扇出層(例如，層101B)的所需之有效CTE來選擇虛設晶粒106的材料與尺寸。例如，參見圖1B之扇出層配置，可根據如下公式計算沿著穿過晶粒104/106之x軸的層101B之有 效CTE：，其中α Si 為矽之CTE，α dummy 為虛設晶粒106的材料(例如，矽或玻璃)之CTE，而α MC 為模塑料124之CTE。可根據如下公式計算沿著穿過虛設晶粒106 之y軸的層101B之有效CTE：。可使用其他模式確定虛設晶粒106之尺寸與材料以獲得理想有效CTE。 In some embodiments, the dummy die 106 has a longitudinal dimension L3 and a lateral dimension W3. In some embodiments, the ratio of L3/W3 is approximately 2.0. The distance between the grains of layer 101B (e.g., P1) may be about 0.1 mm. The fan-out layer 101B may have a longitudinal dimension L4 and a lateral dimension W4. For dummy dies 106, other configurations with different sizes and spacings can also be used. The material and size of the dummy die 106 can be selected in accordance with the desired effective CTE of the fan-out layer (e.g., layer 101B) configuring the dummy die 106. For example, referring to the fan-out layer configuration of FIG. 1B, the effective CTE along layer 101B through the x-axis of die 104/106 can be calculated according to the following equation: Wherein α Si is the CTE of the crucible, α dummy is the CTE of the material of the dummy crystal 106 (for example, germanium or glass), and α MC is the CTE of the molding compound 124. The effective CTE along layer 101B across the y-axis of dummy die 106 can be calculated according to the following formula: . Other modes can be used to determine the size and material of the dummy die 106 to achieve an ideal effective CTE.

已經觀察到，當層101B之晶粒(例如，晶粒104/106)與層101A之晶粒(例如，晶粒102)的總表面積之比在約0.8至約1.2之間時，封裝可獲得相對低的翹曲。例如，當包括上述虛設晶粒時，所獲得之封裝的頂表面高度差(例如，圖2A所示之T1)在高溫條件下可以從當前應用之約140μm減少至約60μm。亦可觀察到，當層101B之有效CTE與層101A之有效CTE的比為約0.9至約1.1時，可實現相對低的翹曲。 It has been observed that when the ratio of the total surface area of the grains of layer 101B (e.g., die 104/106) to the grains of layer 101A (e.g., die 102) is between about 0.8 and about 1.2, the package is available. Relatively low warpage. For example, when the dummy dies described above are included, the difference in the top surface height of the obtained package (for example, T1 shown in FIG. 2A) can be reduced from about 140 μm to about 60 μm in the current application under high temperature conditions. It can also be observed that when the ratio of the effective CTE of layer 101B to the effective CTE of layer 101A is from about 0.9 to about 1.1, relatively low warpage can be achieved.

而且，除了周邊扇出層(例如，層101A)，亦可依據周邊裝置層(例如，RDL 108)的有效CTE選擇所需之有效CTE。已經觀察到，周邊裝置層在不同溫度影響層101B之翹曲。例如，因扇出層101B與RDL 108B之間的CTE不匹配所導致的翹曲，在室溫條件下更為普遍，而因扇出層101A與101B之間的CTE不匹配所導致之翹曲，在高溫條件下更為普遍。因此，當選擇所需的虛設晶粒106之有效CTE時，需要將所有之周邊層(包括RDL 108與層101A)考慮在內。 Moreover, in addition to the peripheral fan-out layer (e.g., layer 101A), the desired effective CTE can be selected based on the effective CTE of the peripheral device layer (e.g., RDL 108). It has been observed that the peripheral device layer affects the warpage of layer 101B at different temperatures. For example, warpage due to CTE mismatch between fan-out layer 101B and RDL 108B is more common at room temperature, and warpage due to CTE mismatch between fan-out layers 101A and 101B. It is more common under high temperature conditions. Therefore, when selecting the effective CTE of the desired dummy die 106, all of the surrounding layers (including RDL 108 and layer 101A) need to be taken into account.

封裝100可亦包括其他構件，例如散熱構件(未圖示)。例如，可將熱介面材料(thermal interface material,TIM)與散熱蓋配置於最 頂層之扇出層(例如，層101B/RDL 108C)上方。TIM可包含，例如具有良好熱傳導係數(為約3W/m．K至約5W/m．K或更多)之聚合物。散熱蓋可更具有高導熱性能，例如，為約200W/m．K至約400W/m．K之間或更多，且可使用金屬、金屬合金、石墨烯、碳奈米管(CNT)等類似物形成。 Package 100 may also include other components, such as heat dissipating members (not shown). For example, a thermal interface material (TIM) and a heat sink cover can be placed at the most Above the fan-out layer of the top layer (eg, layer 101B/RDL 108C). The TIM may comprise, for example, a polymer having a good thermal conductivity (from about 3 W/m.K to about 5 W/m.K or more). The heat dissipation cover can have higher thermal conductivity, for example, about 200 W/m. K to about 400W/m. K or more, and may be formed using a metal, a metal alloy, graphene, a carbon nanotube (CNT) or the like.

圖3A至圖3G根據一些實施例顯示製造圖1A之扇出層的各中間步驟。在圖3A中，提供背面RDL 108C。可將RDL 108C形成於載體(未圖示)上。RDL 108C可包括一或複數介電材料層，該介電材料層具有在其中例如形成有導線與通孔的導電構件(未圖示)。RDL 108C中之介電材料可由任何合適之材料(例如，聚醯亞胺(PI)、聚苯並惡唑(PBO)、BCB、環氧樹脂、矽酮樹脂、丙烯酸酯、奈米填充酚醛樹脂、矽氧烷、氟化聚合物、聚降冰片烯、氧化物、氮化物等)使用任何合適之方法(例如，旋塗技術、濺射等)形成。在一些實施例中，RDL 108C之形成包括圖案化介電材料(例如，使用光微影及/或蝕刻製程)並在圖案化的介電質層內及/或上形成導電構件。例如，藉由沉積晶種層、使用遮罩層限定導電構件之形狀並使用無電式電鍍/電化學電鍍製程形成導電構件。 3A-3G illustrate various intermediate steps of fabricating the fan-out layer of FIG. 1A, in accordance with some embodiments. In Figure 3A, a back RDL 108C is provided. The RDL 108C can be formed on a carrier (not shown). The RDL 108C can include one or a plurality of layers of dielectric material having conductive members (not shown) in which, for example, wires and vias are formed. The dielectric material in RDL 108C can be made of any suitable material (for example, polyimine (PI), polybenzoxazole (PBO), BCB, epoxy resin, fluorenone resin, acrylate, nano-filled phenolic resin , siloxanes, fluorinated polymers, polynorbornenes, oxides, nitrides, etc.) are formed using any suitable method (eg, spin coating techniques, sputtering, etc.). In some embodiments, the formation of RDL 108C includes patterning a dielectric material (eg, using a photolithography and/or etching process) and forming a conductive member within and/or over the patterned dielectric layer. For example, the conductive member is formed by depositing a seed layer, defining a shape of the conductive member using a mask layer, and using an electroless plating/electroplating process.

可以使用黏膠層118將半導體晶粒104與虛設晶粒106接合至背面RDL。如上所述，晶粒104可包括有源裝置/功能電路，而虛設晶粒106可不包括任何有源裝置或功能電路。可依據晶粒104之尺寸以及所形成之扇出層(例如，層101B)的所需有效CTE，決定虛設晶粒106之尺寸。 The semiconductor die 104 and the dummy die 106 can be bonded to the backside RDL using an adhesive layer 118. As noted above, die 104 may include active device/function circuitry, while dummy die 106 may not include any active or functional circuitry. The size of the dummy die 106 can be determined based on the size of the die 104 and the desired effective CTE of the resulting fan-out layer (e.g., layer 101B).

接著，在圖3B中，可施行晶圓級模塑/研磨背面。例如，可將模塑料124配置於接合的晶粒104/106之間。模塑料124可包括任何合適之材料，例如，環氧樹脂、模塑底膠填充等。形成模塑料24之合適方法包括壓縮成型、轉移成型、液體密封劑成型等。例如，模塑料124 能夠以液體形式配置於晶粒104/106之間。而後，施行固化製程以固化模塑料124。填充之模塑料124可溢出晶粒104/106，以使模塑料124覆蓋晶粒104/106之頂表面。採用機械研磨、化學機械拋光(CMP)或其他回蝕技術移除模塑料124之過量部分並暴露出晶粒104之連接件(例如，柱形塊150)。在平坦化後，模塑料124，晶粒104與虛設晶粒106之頂表面實質上水平。於是，封裝100中完成扇出層101B。 Next, in FIG. 3B, a wafer level molding/grinding back surface can be performed. For example, the molding compound 124 can be disposed between the bonded dies 104/106. Molding compound 124 can comprise any suitable material, such as epoxy, molded backing, and the like. Suitable methods of forming the molding compound 24 include compression molding, transfer molding, liquid sealant molding, and the like. For example, molding compound 124 It can be disposed in a liquid form between the crystal grains 104/106. Then, a curing process is performed to cure the molding compound 124. The filled molding compound 124 can overflow the die 104/106 such that the molding compound 124 covers the top surface of the die 104/106. The excess portion of the molding compound 124 is removed using mechanical grinding, chemical mechanical polishing (CMP) or other etch back techniques and the connectors of the die 104 (e.g., the cylindrical block 150) are exposed. After planarization, the molding compound 124, the die 104 and the top surface of the dummy die 106 are substantially horizontal. Thus, the fan-out layer 101B is completed in the package 100.

圖3C顯示於層101B上方形成RDL 108B。RDL 108B可與晶粒104B之柱形塊150電性連接。在圖3D中，在RDL 108B上形成TIV 126。TIV 126可包括導電材料(例如，銅)並藉由任何合適之製程形成。例如，具有開口之圖案化遮罩層(未圖示)可使用於限定此等TIV之形狀。開口可暴露出形成於RDL 108B上方的晶種層(未圖示)。可將遮罩層中之開口中填充導電材料(例如，在無電式電鍍製程/電化學電鍍製程中)。鍍覆製程可單向地填充圖案化之光阻中的開口(例如，從晶種層向上)。單向填充可對此等開口更均勻地填充，特別是對於高縱橫比之TIV。或者，可在圖案化遮罩層開口之側壁與底表面上形成晶種層，並多向地填充此等開口。然後，在灰化製程及/或濕剝離製程中移除圖案化遮罩層。亦可使用蝕刻製程移除晶種層之多餘部分，於上方留下TIV 126並與RDL 108B電性連接。使用銅線柱藉由銅線接合製程(例如，無需遮罩、光阻、及鍍覆)形成TIV 126。在圖3E中，另一個半導體晶粒(例如，核心邏輯晶粒102)可如同晶粒104/106地接合至(例如，使用黏膠層118)RDL 108之對面。 Figure 3C shows the formation of RDL 108B over layer 101B. The RDL 108B can be electrically connected to the stud 150 of the die 104B. In FIG. 3D, TIV 126 is formed on RDL 108B. TIV 126 may comprise a conductive material (eg, copper) and formed by any suitable process. For example, a patterned mask layer (not shown) having an opening can be used to define the shape of such TIVs. The opening may expose a seed layer (not shown) formed over the RDL 108B. The openings in the mask layer may be filled with a conductive material (eg, in an electroless plating process/electroplating process). The plating process can unidirectionally fill the openings in the patterned photoresist (eg, from the seed layer up). Unidirectional filling can fill these openings more evenly, especially for high aspect ratio TIVs. Alternatively, a seed layer can be formed on the sidewalls and bottom surface of the patterned mask layer opening and filled in a multi-directional manner. The patterned mask layer is then removed during the ashing process and/or the wet strip process. An etch process can also be used to remove excess portions of the seed layer, leaving TIV 126 on top and electrically connecting to RDL 108B. The TIV 126 is formed using a copper wire post by a copper wire bonding process (eg, without masking, photoresist, and plating). In FIG. 3E, another semiconductor die (eg, core logic die 102) can be bonded (eg, using adhesive layer 118) to the opposite side of RDL 108 as die 104/106.

隨後，如圖3F所示施行另一晶圓級模塑/研磨背面。例如，可將模塑料124配置於晶粒102與各種TIV 126之間，施行平坦化以暴露出晶粒102上之連接件(例如，柱形塊110)。如此一來，在裝置封裝中形成第二扇出層101A。在一些實施例中，層101A之晶粒(例如，晶粒102)的表面積與層101B之晶粒(例如，晶粒101/106)的表面積之 比為約0.8至1.2。 Subsequently, another wafer level molding/grinding back surface is performed as shown in Fig. 3F. For example, the molding compound 124 can be disposed between the die 102 and the various TIVs 126 and planarized to expose the connectors on the die 102 (eg, the pillars 110). As a result, the second fan-out layer 101A is formed in the device package. In some embodiments, the surface area of the grains (eg, grains 102) of layer 101A and the surface area of the grains of layer 101B (eg, grains 101/106) The ratio is about 0.8 to 1.2.

接著，在圖3G中，使用類似上述之製程在層101A上形成一或複數RDL(RDL 108A)。RDL 108A可電性連接至晶粒102與TIV 126。TIV 126可進一步電性連接至RDL 108A與108B。隨後可形成其他構件(例如，外部連接件、另外的層、另外的RDL、功能晶粒、虛設晶粒、封裝、散熱構件等)。 Next, in FIG. 3G, one or a plurality of RDLs (RDLs 108A) are formed on the layer 101A using a process similar to that described above. The RDL 108A can be electrically connected to the die 102 and the TIV 126. TIV 126 can be further electrically coupled to RDLs 108A and 108B. Other components may then be formed (eg, external connectors, additional layers, additional RDLs, functional dies, dummy dies, packages, heat dissipating members, etc.).

圖4根據另外一些實施例顯示裝置封裝200之剖面圖。封裝200可實質上與封裝100相似，類似符號表示相同之元件。然而，在封裝200中，晶粒102比晶粒104佔有更小之區域。於是，在沒有虛設晶粒106之情況下，層101A之有效CTE可低於層101B之有效CTE。從而，包含相對低CTE材料(例如，矽或玻璃)之虛設晶粒106可被包括在層101A中以降低其有效CTE，減少CTE不匹配與翹曲。此外，可依據製程限制、配置設計、製造效率等，於扇出層之各個位置包含多個虛設晶粒106。 4 shows a cross-sectional view of device package 200 in accordance with further embodiments. Package 200 can be substantially similar to package 100, like symbols representing the same elements. However, in package 200, die 102 occupies a smaller area than die 104. Thus, without the dummy die 106, the effective CTE of layer 101A can be lower than the effective CTE of layer 101B. Thus, dummy dies 106 comprising relatively low CTE materials (eg, germanium or glass) can be included in layer 101A to reduce their effective CTE, reducing CTE mismatch and warpage. In addition, a plurality of dummy dies 106 may be included at various locations of the fan-out layer depending on process constraints, configuration design, manufacturing efficiency, and the like.

圖5根據另外一些實施例顯示裝置封裝300之剖面圖。封裝300可實質上與封裝200相似，類似之符號表示相同之元件。類似於封裝200，在封裝300中，晶粒102比晶粒104佔有更小之區域。於是，在沒有虛設晶粒106之情況下，層101A之有效CTE可低於層101B之有效CTE。然而，在封裝300中，虛設晶粒106可包括在層101B中以提升其有效CTE，減少CTE不匹配與翹曲。例如，虛設晶粒106可包含相對高之CTE材料(例如，CTE為約18的銅)。當高CTE虛設晶粒106包括在層101B中時，層101B之有效CTE增加。於是，在各個實施例中，可使用虛設晶粒106增加或降低有效CTE至依據周邊層(例如，RDL、其他層等)的所需水準。 FIG. 5 shows a cross-sectional view of device package 300 in accordance with further embodiments. Package 300 can be substantially similar to package 200, like symbols representing the same elements. Similar to package 200, in package 300, die 102 occupies a smaller area than die 104. Thus, without the dummy die 106, the effective CTE of layer 101A can be lower than the effective CTE of layer 101B. However, in package 300, dummy die 106 may be included in layer 101B to boost its effective CTE, reducing CTE mismatch and warpage. For example, dummy die 106 can comprise a relatively high CTE material (eg, copper having a CTE of about 18). When the high CTE dummy die 106 is included in layer 101B, the effective CTE of layer 101B increases. Thus, in various embodiments, the dummy die 106 can be used to increase or decrease the effective CTE to a desired level depending on the perimeter layer (eg, RDL, other layers, etc.).

圖6根據一些實施例顯示形成裝置封裝之流程400。在步驟402中，形成第一扇出層(例如，層101A)。該第一扇出層可包括裝置晶 粒(例如，邏輯晶粒102)與繞該裝置晶粒延伸之模塑料(例如，模塑料124)。在步驟404中，於該第一扇出層上方形成一或複數個扇出RDL(例如，RDL 108B)。可使用裝置晶粒中之連接件(例如，柱形塊110)將扇出RDL電性連接至裝置晶粒。在步驟406中，在該一或複數個RDL上形成第二扇出層(例如，扇出層101B)。該第二扇出層可包括一或複數個裝置晶粒(例如，晶粒104)。而且，該第一扇出層或該第二扇出層中之至少一者包括一或複數個虛設晶粒(例如，虛設晶粒106)，可根據該扇出層所需之CTE選擇該虛設晶粒之尺寸。在一些實施例中，該扇出層所需之CTE可依據相鄰之裝置封裝層(例如，其他扇出層及/或RDL)。 FIG. 6 shows a flow 400 for forming a device package in accordance with some embodiments. In step 402, a first fan-out layer (eg, layer 101A) is formed. The first fan-out layer may include a device crystal Particles (e.g., logic die 102) and a molding compound (e.g., molding compound 124) extending around the die of the device. In step 404, one or more fan-out RDLs (eg, RDL 108B) are formed over the first fan-out layer. The fan-out RDL can be electrically connected to the device die using connectors in the device die (eg, the pillar block 110). In step 406, a second fan-out layer (eg, fan-out layer 101B) is formed on the one or more RDLs. The second fan-out layer can include one or more device dies (eg, die 104). Moreover, at least one of the first fan-out layer or the second fan-out layer includes one or a plurality of dummy dies (eg, dummy dies 106), and the dummy can be selected according to a CTE required for the fan-out layer The size of the grain. In some embodiments, the CTE required for the fan-out layer may be based on adjacent device encapsulation layers (eg, other fan-out layers and/or RDLs).

此處描述之各個實施例包括接合至各種封裝配置之其他晶粒(例如，記憶體、邏輯、感測器、網路等電路)之核心邏輯晶粒。每一晶粒可配置於各個扇出層中。虛設晶粒可包括在各個扇出層中，且可選擇虛設晶粒之尺寸及/或材料以減少各個扇出層之間的CTE不匹配。可將RDL配置於此等扇出層之正面及/或背面，在層間延伸之TIV可提供不同RDL之間的電性連接。如此一來，封裝中之晶粒可電性連接至其他晶粒及/或外部連接件。 Various embodiments described herein include core logic dies that are bonded to other dies (eg, memory, logic, sensors, networks, etc.) of various package configurations. Each die can be disposed in each fan-out layer. The dummy dies may be included in each of the fan-out layers, and the size and/or material of the dummy dies may be selected to reduce CTE mismatch between the individual fan-out layers. The RDL can be configured on the front side and/or the back side of the fan-out layer, and the TIV extending between the layers can provide electrical connection between different RDLs. In this way, the die in the package can be electrically connected to other die and/or external connectors.

以上內容概述若干實施例的特徵，因而所屬技術領域中通常知識者可更為理解本揭露之各方面。所屬技術領域中具有通常知識者應理解可輕易使用本揭露作為基礎，用於設計或修改其他製程與結構而與本文所述之實施例具有相同目的及/或達到相同優點。所屬技術領域中具有通常知識者亦應理解此均等架構並未悖離本揭露之精神與範圍，且在不悖離本揭露之精神與範圍的情況下，所屬技術領域中具有通常知識者可進行各種變化、取代與替換。 The above summary is a summary of the features of the various embodiments, and those of ordinary skill in the art can understand the various aspects of the disclosure. It should be understood by those of ordinary skill in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. It should be understood by those of ordinary skill in the art that the present invention may be practiced without departing from the spirit and scope of the disclosure. Various changes, substitutions and substitutions.

100‧‧‧封裝 100‧‧‧Package

101A‧‧‧扇出層 101A‧‧‧Fan sector

101B‧‧‧扇出層 101B‧‧‧Fan sector

102‧‧‧半導體晶粒 102‧‧‧Semiconductor grains

104‧‧‧半導體晶粒 104‧‧‧Semiconductor grains

106‧‧‧虛設晶粒 106‧‧‧Virtual dies

108A‧‧‧RDL 108A‧‧‧RDL

108B‧‧‧RDL 108B‧‧‧RDL

108C‧‧‧RDL 108C‧‧‧RDL

110‧‧‧柱形塊 110‧‧‧column block

118‧‧‧黏膠層 118‧‧‧Adhesive layer

120‧‧‧外部連接件 120‧‧‧External connectors

124‧‧‧模塑料 124‧‧‧Molded plastic

126‧‧‧TIV 126‧‧‧TIV

150‧‧‧連接件 150‧‧‧Connecting parts

Claims (10)

一種封裝，包含：第一扇出層，其包含：一或複數第一裝置晶粒；及第一模塑料，沿著該一或複數第一裝置晶粒之側壁延伸；扇出重佈層(RDL)，位於該第一扇出層上方；以及第二扇出層，位於該扇出RDL上方，其中該第二扇出層包含：一或複數第二裝置晶粒，接合至該扇出RDL，其中該扇出RDL電性連接至該一或複數第一裝置晶粒與該一或複數第二裝置晶粒；虛設晶粒，接合至該扇出RDL，其中該虛設晶粒實質上未具有任何有源裝置；及第二模塑料，沿著該一或複數第二裝置晶粒與該虛設晶粒之側壁延伸。 A package comprising: a first fan-out layer comprising: one or a plurality of first device dies; and a first molding compound extending along a sidewall of the one or more first device dies; a fan-out redistribution layer ( RDL), located above the first fan-out layer; and a second fan-out layer above the fan-out RDL, wherein the second fan-out layer includes: one or a plurality of second device dies bonded to the fan-out RDL The fan-out RDL is electrically connected to the one or more first device dies and the one or more second device dies; the dummy dies are bonded to the fan-out RDL, wherein the dummy dies have substantially no Any active device; and a second molding compound extending along the sidewall of the one or more second device die and the dummy die. 如請求項1所述之封裝，其中，該虛設晶粒之尺寸、該虛設晶粒之材料、或其等之組合，係根據該第二扇出層所需之有效熱膨脹係數(Coefficient of Thermal Expansion,CTE)。 The package of claim 1, wherein the size of the dummy die, the material of the dummy die, or a combination thereof is based on a coefficient of thermal expansion required for the second fan-out layer (Coefficient of Thermal Expansion) , CTE). 如請求項2所述之封裝，其中，該所需之有效CTE係依據該第一扇出層之有效CTE、該扇出RDL之有效CTE、或其等之組合。 The package of claim 2, wherein the required effective CTE is based on a valid CTE of the first fan-out layer, an effective CTE of the fan-out RDL, or a combination thereof. 如請求項1所述之封裝，其中，該一或複數第一裝置晶粒具有第一總表面積，該一或複數第二裝置晶粒與該虛設晶粒具有第二總表面積，且該第一總表面積與該第二總表面積之比為約0.8至1.2。 The package of claim 1, wherein the one or more first device dies have a first total surface area, the one or more second device dies and the dummy dies have a second total surface area, and the first The ratio of the total surface area to the second total surface area is from about 0.8 to 1.2. 如請求項1所述之封裝，其中，該一或複數第一裝置晶粒具 有第一總表面積，該一或複數第二裝置晶粒具有第三總表面積，且該第一總表面積大於該第三總表面積，其中該虛設晶粒包含矽或玻璃。 The package of claim 1, wherein the one or more first device die There is a first total surface area, the one or more second device dies having a third total surface area, and the first total surface area is greater than the third total surface area, wherein the dummy grains comprise ruthenium or glass. 如請求項1所述之封裝，其中，該一或複數第一裝置晶粒具有第一總表面積，該一或複數第二裝置晶粒具有第二總表面積，且該第一總表面積小於該第二總表面積，其中該虛設晶粒包含銅。 The package of claim 1, wherein the one or more first device dies have a first total surface area, the one or more second device dies have a second total surface area, and the first total surface area is less than the first Two total surface areas, wherein the dummy grains comprise copper. 如請求項1所述之封裝，其中，該第一扇出層具有第一有效熱膨脹係數(CTE)，該第二扇出層具有第二有效CTE，且該第一有效CTE與該第二有效CTE之比為約0.9至1.1。 The package of claim 1, wherein the first fan-out layer has a first effective thermal expansion coefficient (CTE), the second fan-out layer has a second effective CTE, and the first effective CTE and the second effective The CTE ratio is about 0.9 to 1.1. 如請求項1所述之封裝，其中，該虛設晶粒係配置於該一或複數第二裝置晶粒中的兩個晶粒之間。 The package of claim 1, wherein the dummy die is disposed between two of the one or more second device dies. 一種封裝，包含：第一裝置層，其包含：一或複數第一裝置晶粒；及第一模塑料，環繞該一或複數第一晶粒；第二裝置層，其包含：一或複數第二裝置晶粒；虛設晶粒，其中該虛設晶粒之尺寸與材料係根據該第二裝置層所需之有效熱膨脹係數(CTE)；及第二模塑料，環繞該一或複數第二晶粒與該虛設晶粒；以及扇出重佈層(RDL)，位於該第一裝置層與該第二裝置層之間，其中該一或複數第一裝置晶粒與該一或複數第二裝置晶粒電性連接至該扇出RDL。 A package comprising: a first device layer comprising: one or a plurality of first device dies; and a first molding compound surrounding the one or more first dies; and a second device layer comprising: one or plural a device die; wherein the size and material of the dummy die are based on an effective thermal expansion coefficient (CTE) required for the second device layer; and a second molding compound surrounding the one or more second grains And the dummy die; and a fan-out redistribution layer (RDL) between the first device layer and the second device layer, wherein the one or more first device die and the one or more second device crystals The pellets are electrically connected to the fan-out RDL. 一種形成封裝之方法，包含： 形成第一扇出層，其中形成該第一扇出層包含形成繞一或複數第一裝置晶粒之第一模塑料；於該第一扇出層上方形成扇出重佈層(RDL)；以及於該扇出RDL上方形成第二扇出層，其中形成該第二扇出層包含：將一或複數第二裝置晶粒接合至該扇出RDL；將虛設晶粒接合至該扇出RDL，其中該虛設晶粒之尺寸與材料係根據該第二扇出層之所需有效熱膨脹係數(CTE)而選擇；以及圍繞該一或複數第二裝置晶粒與該虛設晶粒配置第二模塑料。 A method of forming a package, comprising: Forming a first fan-out layer, wherein the forming the first fan-out layer comprises forming a first molding compound around one or more first device grains; forming a fan-out redistribution layer (RDL) above the first fan-out layer; And forming a second fan-out layer above the fan-out RDL, wherein forming the second fan-out layer comprises: bonding one or a plurality of second device die to the fan-out RDL; bonding the dummy die to the fan-out RDL Wherein the size and material of the dummy die are selected according to a desired effective thermal expansion coefficient (CTE) of the second fan-out layer; and the second mode is disposed around the one or more second device die and the dummy die plastic.
TW104139373A 2015-04-30 2015-11-26 Fan-out stacked system in package (sip) having dummy dies and methods of making the same TWI601257B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/701,255 US9613931B2 (en) 2015-04-30 2015-04-30 Fan-out stacked system in package (SIP) having dummy dies and methods of making the same

Publications (2)

Publication Number Publication Date
TW201639106A true TW201639106A (en) 2016-11-01
TWI601257B TWI601257B (en) 2017-10-01

Family

ID=57205560

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104139373A TWI601257B (en) 2015-04-30 2015-11-26 Fan-out stacked system in package (sip) having dummy dies and methods of making the same

Country Status (4)

Country Link
US (1) US9613931B2 (en)
KR (1) KR101884971B1 (en)
CN (1) CN106098637B (en)
TW (1) TWI601257B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI645524B (en) * 2016-12-13 2018-12-21 Nanya Technology Corporation Semiconductor structure and method for preparing the same
US10304784B2 (en) 2017-09-27 2019-05-28 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10529690B2 (en) 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
TWI682509B (en) * 2018-06-29 2020-01-11 台灣積體電路製造股份有限公司 Package and method of forming the same
TWI727523B (en) * 2019-09-17 2021-05-11 台灣積體電路製造股份有限公司 Package structure and method of manufacturing the same
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US10032756B2 (en) * 2015-05-21 2018-07-24 Mediatek Inc. Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US10236245B2 (en) * 2016-03-23 2019-03-19 Dyi-chung Hu Package substrate with embedded circuit
US9824988B1 (en) 2016-08-11 2017-11-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9859245B1 (en) * 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
US10163802B2 (en) * 2016-11-29 2018-12-25 Taiwan Semicondcutor Manufacturing Company, Ltd. Fan-out package having a main die and a dummy die, and method of forming
KR102351676B1 (en) 2017-06-07 2022-01-17 삼성전자주식회사 A semiconductor package and a method for manufacturing the same
CN109103167B (en) * 2017-06-20 2020-11-03 晟碟半导体（上海）有限公司 Heterogeneous fan out structure for memory devices
US10304805B2 (en) 2017-08-24 2019-05-28 Micron Technology, Inc. Dual sided fan-out package having low warpage across all temperatures
US10431517B2 (en) 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
CN107425031B (en) * 2017-09-05 2022-03-01 盛合晶微半导体(江阴)有限公司 Packaging structure and packaging method of back-illuminated CMOS sensor
CN109786362B (en) * 2017-11-14 2021-01-05 旺宏电子股份有限公司 External fan crystal grain laminated structure without welding pad and manufacturing method thereof
US10566261B2 (en) 2017-11-15 2020-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages with embedded heat dissipation structure
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
CN109841601B (en) * 2017-11-28 2020-09-04 长鑫存储技术有限公司 Chip stack three-dimensional packaging structure and manufacturing method
KR101933423B1 (en) * 2017-11-28 2018-12-28 삼성전기 주식회사 Fan-out sensor package
KR102052804B1 (en) * 2017-12-15 2019-12-05 삼성전기주식회사 Fan-out sensor package
US10312221B1 (en) * 2017-12-17 2019-06-04 Advanced Micro Devices, Inc. Stacked dies and dummy components for improved thermal performance
KR102397902B1 (en) 2018-01-29 2022-05-13 삼성전자주식회사 Semiconductor package
CN108389823A (en) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
US11101260B2 (en) * 2018-02-01 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a dummy die of an integrated circuit having an embedded annular structure
KR102395199B1 (en) 2018-02-22 2022-05-06 삼성전자주식회사 Semiconductor package
KR20190115911A (en) 2018-04-04 2019-10-14 엘지이노텍 주식회사 Printed circuit board and printed circuit board strip
US10770364B2 (en) * 2018-04-12 2020-09-08 Xilinx, Inc. Chip scale package (CSP) including shim die
US10714462B2 (en) * 2018-04-24 2020-07-14 Advanced Micro Devices, Inc. Multi-chip package with offset 3D structure
US11728334B2 (en) * 2018-06-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structures and method of forming the same
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10790210B2 (en) * 2018-07-31 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
CN110010500B (en) * 2018-10-10 2021-01-26 浙江集迈科微电子有限公司 Highly integrated radio frequency chip system-in-package process
TWI700802B (en) 2018-12-19 2020-08-01 財團法人工業技術研究院 Structure of integrated radio frequency multi-chip package and method of fabricating the same
US11476213B2 (en) 2019-01-14 2022-10-18 Invensas Bonding Technologies, Inc. Bonded structures without intervening adhesive
US10770430B1 (en) 2019-03-22 2020-09-08 Xilinx, Inc. Package integration for memory devices
CN111727503B (en) * 2019-04-15 2021-04-16 长江存储科技有限责任公司 Unified semiconductor device with programmable logic device and heterogeneous memory and method of forming the same
US11637056B2 (en) * 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
TWI717896B (en) * 2019-11-12 2021-02-01 力成科技股份有限公司 High heat dissipation stacked semiconductor package structure and packing method of the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US12125822B2 (en) * 2020-11-13 2024-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device package having dummy dies
US20220165625A1 (en) * 2020-11-20 2022-05-26 Intel Corporation Universal electrically inactive devices for integrated circuit packages
US11756933B2 (en) * 2021-02-12 2023-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Inactive structure on SoIC
US11515268B2 (en) * 2021-03-05 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
KR20230040392A (en) * 2021-09-15 2023-03-23 삼성전자주식회사 Semiconductor package
US11749534B1 (en) 2022-07-21 2023-09-05 Deca Technologies Usa, Inc. Quad flat no-lead (QFN) package without leadframe and direct contact interconnect build-up structure and method for making the same
CN117438319A (en) 2022-05-31 2024-01-23 德卡科技美国公司 Quad flat no-lead (QFN) package and direct contact interconnect stack structure without lead frame and method of making same
US11973051B2 (en) 2022-05-31 2024-04-30 Deca Technologies Usa, Inc. Molded direct contact interconnect structure without capture pads and method for the same

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (en) 2001-02-09 2002-12-16 삼성전자 주식회사 Chip-Level Three-Dimensional Multi-Chip Package Having Chip Selection Pad Formed On Chip-Level And Making Method Therefor
EP1401020A4 (en) 2001-06-07 2007-12-19 Renesas Tech Corp Semiconductor device and manufacturing method thereof
KR100394808B1 (en) 2001-07-19 2003-08-14 삼성전자주식회사 Wafer level stack chip package and method for manufacturing the same
KR100435813B1 (en) 2001-12-06 2004-06-12 삼성전자주식회사 Multi chip package using metal bar and manufacturing method thereof
EP1457337A4 (en) 2001-12-18 2009-04-29 Sony Corp Printer head
DE10200399B4 (en) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale A method for producing a three-dimensionally integrated semiconductor device and a three-dimensionally integrated semiconductor device
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
CN100524706C (en) * 2002-05-31 2009-08-05 富士通微电子株式会社 Semiconductor device manufacturing method
TWI234253B (en) 2002-05-31 2005-06-11 Fujitsu Ltd Semiconductor device and manufacturing method thereof
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
JP2004071947A (en) 2002-08-08 2004-03-04 Renesas Technology Corp Semiconductor device
CN1199271C (en) 2002-08-28 2005-04-27 威盛电子股份有限公司 Constructed integrated circuit with balance structure
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (en) 2003-08-26 2005-12-21 삼성전자주식회사 Chip stack package and manufacturing method thereof
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (en) 2003-11-19 2006-09-13 삼성전자주식회사 structure and method of wafer level stack for devices of different kind and system-in-package using the same
KR100570514B1 (en) 2004-06-18 2006-04-13 삼성전자주식회사 Manufacturing method for wafer level chip stack package
KR100618837B1 (en) 2004-06-22 2006-09-01 삼성전자주식회사 Method for forming thin wafer stack for wafer level package
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
JP4265997B2 (en) 2004-07-14 2009-05-20 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US20060278975A1 (en) * 2005-06-09 2006-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Ball grid array package with thermally-enhanced heat spreader
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
JP4958257B2 (en) 2006-03-06 2012-06-20 オンセミコンダクター・トレーディング・リミテッド Multi-chip package
US20080157327A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package on package structure for semiconductor devices and method of the same
JP5143451B2 (en) 2007-03-15 2013-02-13 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US20080284037A1 (en) 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
KR101213175B1 (en) 2007-08-20 2012-12-18 삼성전자주식회사 Semiconductor package having memory devices stacked on logic chip
JP2009212315A (en) 2008-03-04 2009-09-17 Elpida Memory Inc Semiconductor device and manufacturing method thereof
JP4828559B2 (en) 2008-03-24 2011-11-30 新光電気工業株式会社 Wiring board manufacturing method and electronic device manufacturing method
US7973310B2 (en) 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5199855B2 (en) 2008-12-17 2013-05-15 三井ホーム株式会社 Wooden frame wall
US7915080B2 (en) 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US8674513B2 (en) 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8648615B2 (en) 2010-06-28 2014-02-11 Xilinx, Inc. Testing die-to-die bonding and rework
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
TWI460834B (en) 2010-08-26 2014-11-11 Unimicron Technology Corp Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof
US9082869B2 (en) 2010-09-14 2015-07-14 Terapede Systems, Inc. Apparatus and methods for high-density chip connectivity
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8421073B2 (en) 2010-10-26 2013-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
JP5703010B2 (en) * 2010-12-16 2015-04-15 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
KR101215975B1 (en) 2011-02-28 2012-12-27 에스케이하이닉스 주식회사 Semiconductor device and fabrication method of the same
US8922230B2 (en) 2011-05-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC testing apparatus
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8779599B2 (en) 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
CN103594451B (en) 2013-11-18 2016-03-16 华进半导体封装先导技术研发中心有限公司 Multi-layer multi-chip fan-out structure and manufacture method
US10049977B2 (en) * 2014-08-01 2018-08-14 Qualcomm Incorporated Semiconductor package on package structure and method of forming the same

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10867965B2 (en) 2016-11-14 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10529690B2 (en) 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
TWI717561B (en) * 2016-11-14 2021-02-01 台灣積體電路製造股份有限公司 Package structures and methods of forming the same
TWI645524B (en) * 2016-12-13 2018-12-21 Nanya Technology Corporation Semiconductor structure and method for preparing the same
US10304784B2 (en) 2017-09-27 2019-05-28 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
TWI677059B (en) * 2017-09-27 2019-11-11 南韓商三星電子股份有限公司 Fan-out semiconductor package
TWI682509B (en) * 2018-06-29 2020-01-11 台灣積體電路製造股份有限公司 Package and method of forming the same
US10651131B2 (en) 2018-06-29 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US10886238B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US11764165B2 (en) 2018-06-29 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
US11164855B2 (en) 2019-09-17 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with a heat dissipating element and method of manufacturing the same
TWI727523B (en) * 2019-09-17 2021-05-11 台灣積體電路製造股份有限公司 Package structure and method of manufacturing the same
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US12057369B2 (en) 2020-02-19 2024-08-06 Intel Corporation Enhanced base die heat path using through-silicon vias

Also Published As

Publication number Publication date
TWI601257B (en) 2017-10-01
CN106098637A (en) 2016-11-09
KR101884971B1 (en) 2018-08-02
CN106098637B (en) 2018-11-09
KR20160129687A (en) 2016-11-09
US9613931B2 (en) 2017-04-04
US20160322330A1 (en) 2016-11-03

Similar Documents

Publication Publication Date Title
TWI601257B (en) Fan-out stacked system in package (sip) having dummy dies and methods of making the same
US12033976B2 (en) Semiconductor package having a through intervia through the molding compound and fan-out redistribution layers disposed over the respective die of the stacked fan-out system-in-package
US10515930B2 (en) Three-layer package-on-package structure and method forming same
TWI735551B (en) Semiconductor structure and manufacturing method thereof
TWI720094B (en) Integrated fan-out package on package structure and methods of forming same
KR101368538B1 (en) Multi-chip wafer level package
US10381326B2 (en) Structure and method for integrated circuits packaging with increased density
US9209048B2 (en) Two step molding grinding for packaging applications
US9991190B2 (en) Packaging with interposer frame
TW201727826A (en) System on integrated chips and methods of forming same
TW201826403A (en) Methods of forming cowos structures
US20200006194A1 (en) Heat dissipation structures
KR102524244B1 (en) Heat dissipation in semiconductor packages and methods of forming same
KR20230164619A (en) Package structure, semiconductor device and manufacturing method thereof
US20210272872A1 (en) Thermal management materials for semiconductor devices, and associated systems and methods
CN110660759A (en) Heat radiation structure
US11915994B2 (en) Package structure comprising a semiconductor die with a thermoelectric structure and manufacturing method thereof
CN221596446U (en) Chip packaging structure
TWI851467B (en) Chip package structure and method for preventing warpage of chip package structure
TWI796884B (en) Semiconductor package structure