CN110660759A - Heat radiation structure - Google Patents

Abstract

The present disclosure describes heat dissipation structures that may be formed in functional or non-functional areas of a three-dimensional system-on-chip structure. In some embodiments, the heat dissipation structure maintains an average operating temperature of the memory die or chip below about 90 ℃. For example, a structure includes a stack having wafer layers, where each wafer layer includes one or more wafers and an edge portion. The structure also includes a thermal interface material disposed on an edge portion of each wafer layer, a thermal interface material layer disposed over a top wafer layer of the stack, and a heat spreader over the thermal interface material layer.

Description

Heat radiation structure

Technical Field

The present disclosure relates to a heat dissipation structure.

Background

Three-dimensional system-on-chip structures with increased chip density can exhibit high heat density and poor heat dissipation performance compared to their two-dimensional counterparts. Increased thermal density in three-dimensional system-on-chip structures may lead to electromigration and reliability problems.

Disclosure of Invention

According to an embodiment of the present disclosure, a heat dissipation structure is provided, including: a stack of one or more wafer layers, a layer of thermal interface material, and a heat spreader. Each wafer layer includes: a center portion including one or more wafers, and an edge portion surrounding the center portion and including a ring of thermal interface material. A layer of thermal interface material is disposed on a top wafer layer of the stack. The heat spreader is positioned over the layer of thermal interface material.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale in accordance with conventional practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a partial isometric view of a three-dimensional system-integrated wafer structure having a thermal interface ring according to some embodiments;

FIG. 2A is a cross-sectional view of a three-dimensional system-integrated wafer structure having a thermal interface ring in a dummy region according to some embodiments;

FIG. 2B is a cross-sectional view of a three-dimensional system-integrated wafer structure with a thermal interface ring and vertical heat conducting structures in a dummy region according to some embodiments;

FIG. 3 is a thermal map of a three-dimensional system integrated wafer structure having a thermal interface ring in a virtual area, in accordance with some embodiments;

fig. 4 is a thermal map of a three-dimensional system integrated wafer structure without thermal interface rings in the virtual area, in accordance with some embodiments;

FIG. 5 is an isometric partial view of a three-dimensional system-integrated wafer structure with vertical thermal structures arranged in two exemplary layouts according to some embodiments;

FIG. 6 is a top view of a layer of a wafer having thermally conductive structures disposed between electrically conductive structures, according to some embodiments;

fig. 7 is a cross-sectional view of a virtual thermally conductive structure having a liner containing metal particles according to some embodiments;

FIG. 8 is a cross-sectional view of a three-dimensional system-integrated wafer structure having vertical heat-conducting structures in a molding region (molding region) according to some embodiments;

fig. 9 is a flow diagram of a method for fabricating a three-dimensional system-integrated wafer structure having a thermal interface ring and a thermally conductive structure, in accordance with some embodiments.

[ notation ] to show

1003D system integration wafer structure

100A wafer layer

100B wafer layer

100C wafer layer

100D wafer layer

110 wafer

120 vertical conductive structure

130 ring of thermal interface material

140 blanket thermal interface material layer on top

200A 3D system integration wafer structure

200B 3D system integration wafer structure

210 memory chip Stack

220 virtual area

230 vertical conduction structure

240 vertical conduction structure

250 joint pad structure

260 bottom layer

260A logic chip

270 arrow head

280 heat sink

290 Ball Grid Array (BGA) connector

295A complementary heat conducting structure

295B complementary structure

300A Hot zone

300B Hot zone

310A hot zone

310B hot zone

400 hot zone

410 hot zone

420 Hot zone

500 vertical thermal structure

Pitch of 500p

Pitch 500p

510 wafer layer

520 heat dissipation layer

530 lateral offset

540A Heat dissipation Path

540B Heat dissipation Path

600 wafer area

610 silicon through hole

700 virtual vertical structure

710 wafer layer

720 middle layer

730 metal core

740 backing material

8003D system integration wafer structure

810 molding area

820 memory stack

830 memory die

840 hybrid junction structure

850 System on chip (SoC)

860 interfacial layer

870 Electrical connection

880 vertical structure

890 arrow head

900 method

910 operation

920 operation

930 operation

940 operation

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are intended to be limiting. For example, forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to simplify description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device/element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "nominal" as used herein refers to a desired or target value, and a range of values above and/or below the desired value, of a characteristic or parameter of a component or process operation set during the design phase of the product or process. The range of values may be due to minor variations in manufacturing processes or tolerances.

The term "vertical" as used herein means nominally perpendicular to the substrate surface.

The term "substantially" as used herein means that the value of a given quantity may vary based on the particular technology node associated with the subject semiconductor device. In some embodiments, the term "substantially" may indicate that a given amount of value varies within, for example, ± 5% of a target (or expected) value, based on a particular technology node.

The term "about" as used herein means that the value of a given quantity can vary based on the particular technology node associated with the subject semiconductor device. In some embodiments, the term "about" can indicate that a given amount of a value varies within, for example, 5-30% of the value (e.g., ± 5%, ± 10%, ± 20%, or ± 30% of the value), based on the particular technology node.

Three-dimensional system on integrated chip (3D SoIC) structures are non-monolithic vertical structures that include two to eight two-dimensional (2D) flip chips stacked on top of each other. The 2D flip chip may be an assembly of chips with different functions, such as logic chips, memory chips, Radio Frequency (RF) chips, etc. By way of example and not limitation, the logic chip may include a Central Processing Unit (CPU), and the memory chip may include a static access memory (SRAM) array, a Dynamic Random Access Memory (DRAM) array, a Magnetic Random Access Memory (MRAM) array, or other memory array. In a 3D system integrated wafer structure, each 2D wafer may be interconnected via micro bumps (microbump), bond pads (bonding pad), by Through Silicon Vias (TSV), or by other interconnect structures, which may be shorter than the interconnects used in the 2D system integrated wafer structure. Thus, a 3D system integrated wafer structure may be faster, denser, and have additional functionality than its 2D counterpart. In addition, the 3D system-integrated wafer structure may have a smaller footprint than the 2D system-integrated wafer structure.

On the other hand, since 3D system-integrated wafer structures have increased wafer density and reduced footprint (which can translate into limited heat dissipation area), they also have higher thermal density per unit area and are more susceptible to heat dissipation problems than 2D system-integrated wafer structures. Increased thermal density in 3D system integrated wafer structures can lead to electromigration and reliability issues. For example, electromigration may increase the resistance of interconnects and through-silicon-vias, degrade the performance of the wafer, and shorten the lifetime of the 3D system integrated wafer structure. Reliability issues may arise due to the materials included in the 3D system integrated wafer structure, including materials with different Coefficients of Thermal Expansion (CTE). Materials with different coefficients of thermal expansion can cause thermomechanical stress between Integrated Circuit (IC) wafers. In addition, different types of IC wafers may have different heat resistance. For example, a memory chip (e.g., an SRAM array) may have a lower thermal resistance (e.g., equal to or less than about 90 ℃) than a logic chip, which may have a higher thermal resistance (e.g., equal to or greater than about 120 ℃). For the above reasons, the problem of heat dissipation in the 3D system integrated chip structure should be solved.

To address the above disadvantages, embodiments described herein relate to a heat dissipation structure that may be formed in a functional region or a non-functional region of a 3D system integration wafer structure. In some embodiments, the heat dissipation structure may include a Thermal Interface Material (TIM) ring, a vertical conductive structure disposed in a dummy region (e.g., a non-functional region) or a molding region of the 3D system integrated wafer structure, a vertical conductive structure disposed within an active wafer region and around a high heat output region (hot spot), or a combination thereof. In some embodiments, existing vertical structures in the 3D system integrated wafer structure may be reused as additional heat dissipation paths. The embodiments described herein may be applied to a range of 3D system-integrated wafer structures, including but not limited to 3D system-integrated wafer structures having a dummy region and a molding region.

Fig. 1 is a partial isometric view of a 3D system integrated wafer structure 100, according to some embodiments. The 3D system integrated wafer structure 100 includes four wafer layers (e.g., 100A, 100B, 100C, and 100D); however, the number of wafer layers is not limiting, and fewer or additional wafer layers (e.g., 2, 6, or 8) may be used. For purposes of illustration, fig. 1 includes selected portions of a 3D system integration wafer structure, and may include other portions (not shown). For example, micro-bumps, molding/dummy areas, adhesive layers, heat sinks, interconnects, Ball Grid Array (BGA) connectors, silicon interposers, and other components or structural elements may be included. Each wafer level may include one or more wafers 110 and is electrically connected to wafers in adjacent wafer levels by vertical conductive structures 120. In some embodiments, the vertical conductive structure 120 may include a through silicon via or other type of vertical conductive structure. By way of example and not limitation, the bottom wafer layer 100A may include one or more microprocessors or CPUs, while the wafer layers 100B-100D may include one or more memory wafers (e.g., SRAM wafers, DRAM wafers, MRAM wafers, other types of memory wafers, or combinations thereof). In some embodiments, the bottom wafer layer 100A generates more heat than the wafer layers 100B, 100C, and 100D. By way of example and not limitation, the temperature of the bottom wafer layer 100A in operation may be greater than about 100 ℃ (e.g., about 105 ℃, about 110 ℃, about 115 ℃, or about 130 ℃).

In terms of heat dissipation, the 3D system integrated wafer structure 100 includes a ring of thermal interface material 130 on the periphery of each wafer layer, and a top blanket thermal interface material layer 140 on the entire top wafer layer 100D. By way of example and not limitation, the ring of thermal interface material 130 and the layer of thermal interface material 140 may comprise a material such as silver, aluminum nitride, silicon carbide, or combinations thereof. In further embodiments, the ring of thermal interface material 130 and the layer of thermal interface material 140 may include thermal paste (thermal grease) having a thermal conductivity between about 1.5W/(m · K) and about 15W/(m · K). By way of example and not limitation, the thickness of the thermal interface material layer 140 may range from about 0.1mm to about 0.5mm, and the thickness of the thermal interface material ring 130 may range from about 0.3mm to about 0.8 mm. In some embodiments, each ring of thermal interface material 130 forms a continuous layer around one or more of the wafers 110 of each wafer layer in the non-functional area of the wafer layer. For example, the periphery of the wafer layers 100A-100D may not include active/functional components. Alternatively, the periphery of the wafer layers 100A-100D may be occupied by layers that provide structural support for the 3D system integrated wafer structure 100. According to some embodiments, the periphery of the wafer layers 100A-100D may be used to carry the thermal interface material ring 130. A heat sink (not shown in fig. 1) may be disposed over top blanket thermal interface material layer 140. According to some embodiments, thermal interface material ring 130 and blanket thermal interface material layer 140 form a heat dissipation path that transfers heat generated by bottom wafer layer 100A to a heat spreader over blanket thermal interface material layer 140. As shown in fig. 1 and described above, a ring of thermal interface material 130 is located at the periphery of each wafer layer and forms a continuous layer that includes non-functional regions of the 3D system integrated wafer structure.

Fig. 2A is a cross-sectional view of a 3D system integrated wafer structure 200A. According to some embodiments, the 3D system integrated wafer structure 200A is similar to the 3D system integrated wafer structure 100. However, the 3D system integrated wafer structure 200A is more elaborate and therefore includes additional electrical components or structural elements. For example, the 3D system on chip structure 200A includes a memory chip stack 210, a dummy region 220 surrounding the memory chip stack 210, vertical conductive structures 230 and 240, a bond pad structure 250, a bottom layer 260, and a heat spreader 280. The bottom layer 260 has a logic chip 260A under the memory chip stack 210 and the dummy area 220. A heat spreader 280 is over the top thermal interface material layer 140. The dummy regions 220 are non-electrically functional structures that are poorly conductive (e.g., less than about 1.3W/(m K)). By way of example and not limitation, the dummy region 220 (e.g., non-functional region) may provide structural support for the 3D system integrated wafer structure 200A and include a combination of an electrically insulating material and a metal conductive structure or a metal-containing conductive structure. By way of example and not limitation, the dummy region 220 may include a molding compound (e.g., epoxy-based material) that electrically isolates various components of the memory die and provides structural support for the 3D system integrated die structure 200A. In an alternative example, the dummy region 220 may include an oxide-based dielectric material (e.g., silicon oxide) and a metal conductive structure or a metal-containing conductive structure. The wafers in the 3D system integrated wafer structure 200A may be electrically coupled to adjacent top and bottom wafers via conductive structures 230 (e.g., bond pads), vertical conductive structures 240 (e.g., through silicon vias), and bond pad structures 250. The above structures are merely examples, and alternative or additional structures or methods may be used to electrically couple the wafers in the 3D system integrated wafer structure 200A. In some embodiments, the conductive structures 230, the vertical conductive structures 240, and the bond pad structures 250 may be used for signal propagation and/or power distribution between the memory die 210 and the logic die 260A. In some embodiments, logic chip 260A may include one or more CPU chips that may generate more heat than memory chip 210.

In some embodiments, the purpose of the 3D system integrated chip structure 200A is to form a heat dissipation path to guide a portion of the heat generated by the logic chip 260A to the heat sink 280 via the dummy region 220, so that the average operating temperature of the memory chip 210 may be lower than about 90 ℃. To facilitate forming a heat dissipation path, the ring of thermal interface material 130 is disposed in the dummy region 220 and interposed between adjacent memory chips 210. In addition, a top blanket thermal interface material layer 140 is interposed between the surface of top memory chip 210 and the backside surface of heat spreader 280. In some embodiments, the placement of the ring of thermal interface material 130 may improve the thermal conductivity of the dummy region 220 and reduce the average operating temperature of the memory die 210 by directing most of the heat generated in the logic die 260A through the dummy region 220. By way of example and not limitation, the thermal interface material ring 130 may reduce the average operating temperature of the memory die 210 from about 100 ℃ to about 90 ℃, which is a reduction of about 10%. The thermal map may reveal the thermal profile achieved by the ring of thermal interface material 130. For example, fig. 3 is a heat map corresponding to the 3D system integrated wafer structure 200A when the 3D system integrated wafer structure 200A is viewed from the top (e.g., looking down from the heat spreader 280 of fig. 2A). In FIG. 3, hot zones 300A and 300B correspond to regions above the memory chip 210 and the dummy zone 220, respectively. Thus, hot zone 310A corresponds to the region between the memory die 210 and the virtual zone 220, and hot zone 310B corresponds to the edge of the 3D system integrated die structure 200A outside the periphery of the logic die 260A. In some embodiments, the temperature of the hot zones 300A and 300B is about 90 ℃, while the temperature of the hot zones 310A and 310B is less than about 90 ℃ (e.g., about 85 ℃, about 80 ℃, or about 70 ℃). By way of example and not limitation, arrow 270 in fig. 2A illustrates a heat dissipation path in the 3D system integrated wafer structure 200A. As shown in FIG. 2A, a portion of the heat generated in logic die 260A is directed through thermal interface material ring 230 in dummy area 220, thereby reducing the amount of heat dissipated directly through memory die 210. Thus, heat may escape to a Printed Circuit Board (PCB) or another substrate not shown in fig. 2A via Ball Grid Array (BGA) connector 290.

In contrast, fig. 4 is another heat map corresponding to a 3D system integrated wafer structure that does not include thermal interface material ring 230 in virtual area 220. Therefore, the thermal profile of the 3D system-integrated wafer structure is different from the thermal profile of the 3D system-integrated wafer structure 200A shown in fig. 3. For example, the hot zone 400 corresponds to a region above the memory die 210, the hot zone 410 corresponds to a region between the memory die 210 and above the virtual zone 220, and the hot zone 420 corresponds to a corner of the 3D system integrated die structure. In this example, the temperature corresponding to the hot zone 400 (e.g., above the memory wafer 210) is about 100 ℃, while the temperatures corresponding to the hot zones 410 and 420 are less than about 100 ℃, respectively. This means that the average operating temperature of the memory die can be higher without the ring of thermal interface material 130 and the dummy region 220 shares less thermal load with the memory die 210.

According to some embodiments, fig. 2B is a cross-sectional view of a 3D system-integrated wafer structure 200B, and the 3D system-integrated wafer structure 200B may be a variation of the 3D system-integrated wafer structure 200A shown in fig. 2A. By way of example and not limitation, the 3D system-on-chip structure 200B may have a dummy area 220, and the dummy area 220 may extend under the memory chip stack 210 and surround the bottom layer 260. In addition, the 3D system integrated wafer structure 200B may include complementary thermally conductive structures 295A and 295B in the dummy area 220. According to some embodiments, the heat conducting structure 295 may also increase the heat dissipation rate of the 3D system integrated chip structure 200B in addition to the thermal interface material ring 130. By way of example and not limitation, the thermally conductive structures 295A may form a network of structures extending laterally in the dummy area 220, while the thermally conductive structures 295B may extend vertically through the dummy area 220. In some embodiments, the thermally conductive structures 295A and 295B may comprise copper, aluminum, metal alloys, or materials having a thermal conductivity greater than about 200W/(m K). The thermally conductive structures 295A and 295B can be in physical contact with the ring of thermal interface material 130 and can be configured to enhance heat dissipation via the dummy region 220. Furthermore, the layout of the thermally conductive structures 295A and 295B is not limited to that illustrated in FIG. 2B. Accordingly, additional arrangements are within the spirit and scope of the present disclosure. Arrow 270 in fig. 2B represents a heat dissipation path between the logic chip 260A and the heat sink 280 in the 3D system integrated chip structure 200B.

In addition to the above, vertical heat conducting structures may be used within each wafer layer to provide additional heat dissipation paths in the 3D system integrated wafer structure. By way of example and not limitation, the vertical thermally conductive structures may include through-silicon vias that may be formed in predetermined locations across the various wafer layers to improve heat dissipation between the layers in a vertical direction (e.g., the z-direction). According to some embodiments, these vertical structures are collectively referred to as "vertical thermal structures" or "thermal through silicon vias.

Fig. 5 is an isometric partial view of a 3D system integration wafer structure with a vertical thermal structure 500 according to two exemplary layouts a and B, according to some embodiments. In the example of layout a, the vertical thermal structure 500 may be vertically aligned (e.g., may be stacked) between the wafer layer 510 and the heat spreading layer 520. Thus, the thermal path 540A of layout a may be limited to a vertical direction (e.g., the z-direction). In layout B, the vertical thermal structure 500 may be formed with a lateral offset 530 in each wafer layer 510 such that the thermal path 540B may be vertical (e.g., in the z-direction) and lateral (e.g., in the x-direction and the y-direction). By way of example and not limitation, lateral offset 530 may be configured to have different directions from one wafer layer to another. Thus, the length and direction of each heat dissipation path 540A and 540B for each layout (e.g., layout a and layout B) may vary. Thus, each layout may serve a different purpose. For example, layout a may be used to create a vertical heat dissipation path, while layout B may be used to provide a combination of lateral and vertical heat dissipation paths from one layer to the next. Thus, a 3D system integrated wafer structure may include layout a, layout B, or a combination thereof to improve heat transfer between one location of the wafer and another.

In the example of 3D system integrated wafer structures 200A and 200B of fig. 2A and 2B, respectively, vertical heat conducting structures may be disposed in bottom wafer layer 260 and arranged according to layouts a and B to form vertical and lateral/vertical heat dissipation paths between logic wafer 260A and heat sink 280. In addition, both layouts a and B may be used to provide targeted heat dissipation to localized heat sources or "hot spots" within the wafer layer. For example, the vertical thermal structure 500 may be arranged above a local hot spot according to layout A, layout B, or a combination thereof to increase the heat transfer rate near the hot spot. In some embodiments, the local hot spots may occur on any wafer level, and are not limited to wafer levels having logic wafers. Thus, vertical thermal structures can be formed at any wafer level 510 on an "as needed" basis to transfer heat away from local hot spots.

In some embodiments, referring to fig. 5, the spacing between vertical thermal structures 500 within the same wafer layer 510 may be in the range of about 1 μm to about 100 μm (e.g., from 1 μm to 20 μm, from 5 μm to 25 μm, from 15 μm to 30 μm, from 25 μm to 60 μm, from 50 μm to 80 μm, from 70 μm to 100 μm, etc.), depending on the design and heat dissipation requirements of the 3D system integrated wafer structure. Further, the diameter of the vertical thermal structure 500 may be in the range of about 0.5 μm to about 2 μm. According to some embodiments, the rate of heat dissipation increases as the pitch of the vertical thermal structures 500 within the wafer layer 510 decreases. In other words, the rate of heat dissipation is inversely proportional to the spacing between vertical thermal structures within the wafer layer. Furthermore, the rate of heat dissipation increases as the ratio of the total area occupied by the vertical thermal structures to the total area occupied by the wafer increases. However, the number of vertical thermal structures cannot be increased indefinitely because the wafer density within the wafer layer may suffer. Therefore, it is desirable to balance the density of vertical thermal structures with the wafer density to achieve optimal heat dissipation performance within a 3D system integrated wafer structure.

Fig. 6 is a top view of one exemplary wafer layer 510 of fig. 5 illustrating an exemplary distribution of vertical thermal structures 500 among other through-silicon vias 610 within a wafer area 600. In some embodiments, through silicon vias 610 may be electrical connections to a CPU die or a memory die (such as SRAM, DRAM, MRAM, and/or other memory die). In some embodiments, as described above, pitch 500p (e.g., within wafer region 600) and pitch 500p' (e.g., between adjacent wafer regions 600) may be adjusted according to the desired heat dissipation characteristics of the 3D system integrated wafer structure and/or the presence of hot spots in wafer region 600. The distribution of the vertical thermal structures 500 shown in fig. 6 is not limiting and layouts having fewer or additional vertical structures 500 are within the spirit and scope of the present disclosure.

According to some embodiments, modifying existing structural elements present in a 3D system integrated wafer structure may improve heat dissipation of the 3D system integrated wafer structure. By way of example and not limitation, a "dummy" vertical structure, which is a non-functional structural element used to improve the process window for certain operations (e.g., etching, chemical mechanical polishing, patterning), may be modified to also serve as a heat sink element. More specifically, incorporating metal particles into the backing material of the virtual vertical structures may "transform" structural elements, such as the virtual vertical structures, into heat dissipating elements.

Fig. 7 is a cross-sectional view of a dummy vertical structure 700 disposed between wafer layers 710, according to some embodiments. In the example of fig. 7, wafer layers 710 are separated by intermediate layers 720. In some embodiments, the intermediate layer 720 comprises a dielectric material, such as silicon oxide or hafnium oxide. By way of example and not limitation, the dummy vertical structure 700 may include a metal core 730 and a liner material 740, the liner material 740 surrounding the metal core 730. By way of example and not limitation, the gasket material 740 may include silicon oxide, organosilicate glass, and the like. By way of example and not limitation, the metal core 730 may comprise a material (e.g., copper, aluminum, etc.) having a thermal conductivity greater than about 200W/(m K). In some embodiments, liner material 740, which may be a dielectric layer (e.g., silicon oxide) that serves as an adhesion layer for metal core 730, is impregnated with metal particles or metal-containing particles that may improve the thermal conductivity of dummy vertical structure 700. By way of example and not limitation, the metal particles or metal-containing particles may include tungsten, tungsten silicide, titanium nitride, titanium, copper, or combinations thereof. According to some embodiments, the metal particles may be incorporated into the gasket material 740 during formation of the gasket material 740, and may be about 50 μm in diameter. The thickness of the liner material 740 may be in the range of about 100nm to about 800 nm.

In some embodiments, the virtual vertical structures may be collectively referred to as "virtual through silicon vias" and, like the vertical thermal structures or thermal through silicon vias, are interposed between wafer layers of the 3D system integrated wafer structure and have substantially equal sizes (e.g., about 0.5 μm to about 2 μm in diameter). However, the difference between the virtual through-silicon-via and the vertical thermal structure is that the position of the virtual through-silicon-via does not change based on the presence of hot spots in the 3D system integrated wafer structure, as opposed to the position of the vertical thermal structure. In other words, the dummy through-silicon vias remain in their original locations, which are determined by the process requirements and not the hot spot locations. On the other hand, the dummy through-silicon-via and the vertical thermal structure may share the same liner material and metal core material. For example, both the dummy through-silicon-vias and the vertical thermal structure may have: a gasket material including silicon oxide, organosilicate glass, or the like; and a core (e.g., copper, aluminum, etc.) comprising a material having a thermal conductivity greater than about 200W/(m.K).

Some types of 3D system integrated wafer structures do not include a virtual region, but instead have a molded region. According to some embodiments, for these types of 3D system integrated wafer structures having a mold region, vertical structures and thermal interface material ring structures may be formed in the mold region to assist in the heat dissipation process. By way of example and not limitation, the molding region of the 3D system integrated wafer structure may include a molding compound (e.g., an epoxy-based material) that encapsulates the wafer or die throughout the die layer and provides structural support for the 3D system integrated wafer structure. This means that the mold region may extend over the area of each wafer layer (e.g., the entire area of each wafer layer) and is therefore not limited to the periphery or edges of the wafer layer (e.g., virtual regions in other types of 3D system integration wafer structures). Further, the molding compound may be an electrical insulator (e.g., a dielectric material) that is poorly thermally conductive. Thus, a 3D system integrated wafer structure with a molding region may suffer from poor heat dissipation when there is a hot spot in the 3D system integrated wafer structure or the 3D system integrated wafer structure includes multiple die layers (e.g., between about 2 and about 8 die layers).

By way of example and not limitation, fig. 8 is a cross-sectional view of a 3D system integrated wafer structure 800. According to some embodiments, the 3D system integrated wafer structure 800 has a molding region 810 (e.g., a region with a molding compound). By way of example and not limitation, the 3D system-integrated chip structure 800 further includes a memory stack 820, the memory stack 820 having a plurality of memory dies 830 embedded in the molding region 810. A plurality of memory dies 830 are stacked on top of each other as shown in FIG. 8. Memory die 830 in memory stack 820 can include, for example, an SRAM die, a DRAM die, an MRAM die, other types of memory dies, a logic die, or a combination thereof. The number of memory dies forming the stack 820 shown in FIG. 8 is not limiting, and additional or fewer memory dies are within the spirit and scope of the present disclosure. Furthermore, the 3D system integrated wafer structure 800 may include additional circuits and electrical components that are not illustrated in fig. 8 for simplicity. The 3D system integrated chip structure 800 may also include a system on chip (SoC)850, where the system on chip (SoC)850 may include a chip or chip stack (e.g., CPU, heating element, power distribution circuit, etc.) that may generate excess heat that needs to be dissipated from the memory stack 820 towards the heat sink 280. An interfacial layer 860 is disposed under each memory die 830 and is electrically coupled with each memory die 830 via a hybrid junction structure 840. Interface layer 860 may provide electrical connections 870 within a single memory die and between adjacent memory dies 830 via a network of vertical connections (not shown in fig. 8 for simplicity). In some embodiments, the interface layer 860 is a redistribution layer (RDL) or back-end of the line (BEOL) metallization network (e.g., an interconnect layer).

In some embodiments, excess heat generated by the system chip 850 needs to be dissipated from the memory stack 820 towards the heat sink 280 such that the temperature of the memory stack 820 is below about 90 ℃. To this end, the 3D system integrated wafer structure 800 (similar to the 3D system integrated wafer structure 200 shown in fig. 2A and 2B) may include a ring of thermal interface material 130 on each molding region 810. The 3D system integrated wafer structure 800 further includes a top thermal interface material layer 140, the top thermal interface material layer 140 being located under the heat spreader 280. In some embodiments, a ring of thermal interface material 130 is disposed at the periphery of the molding region 810 to enhance heat dissipation of the system chip 850 around the memory stack 820. According to some embodiments, virtual vertical structures 700 and vertical structures 880 (which may be disposed in interface layer 860 and molding region 810, respectively) are coupled with the ring of thermal interface material 130 to provide an upward heat dissipation path from the system wafer 850 toward the heat spreader 280. According to some embodiments, each vertical structure 880 in the molding region 810 has a diameter that is about twice the diameter of the virtual vertical structure 700 and can provide electrical connections between adjacent dies in the memory stack 820. Further, the vertical structures 880 may comprise a thermally conductive material having a thermal conductivity greater than about 200W/(m K). By way of example and not limitation, the vertical structures 880 may comprise a metal, such as copper or aluminum.

In addition to the above-described heat conducting structures in the molding region 810 of the 3D system integrated wafer structure, the system wafer 850 may also include vertical thermal structures (not shown in fig. 8) combined according to the layout of fig. 5 to dissipate heat generated by the wafers in the system wafer 850 toward the periphery of the 3D system integrated wafer structure 800 and along the heat dissipation path formed by the virtual vertical structures 700, the vertical structures 880, and the thermal interface material ring 130. According to some embodiments, arrow 890 illustrates a heat dissipation path from the system die 850 toward the heat sink 280. Thus, the combination of the vertical thermal structures in the system wafer 850, the ring of thermal interface material 130, the dummy vertical structures 700, and the vertical structures 880 in the molding region 810 may direct heat generated by the system wafer 850 around the memory stack 820 to limit the temperature of the memory stack 820 to below about 90 ℃.

Fig. 9 is an exemplary method 900 for fabricating a 3D system integrated wafer structure (such as the 3D system integrated wafer structure shown in fig. 1, 2A, 2B, and 8), according to some embodiments. The method of manufacture 900 is exemplary and not limiting. Accordingly, in the method 900, additional or alternative operations may be performed in place of the operations shown in fig. 9. Further, the order in which the operations of method 900 are illustrated in FIG. 9 is not limiting.

The method 900 begins at operation 910 and a ring of thermal interface material is formed in a dummy area of a wafer layer. The wafer layer may include one or more wafers attached to a substrate, for example, as shown in fig. 1 for any of wafer layers 100A-100D. It should be noted that in fig. 1, the substrate on which the wafer 110 is attached is not illustrated for simplicity. In some embodiments, the substrate comprises a Polyimide (PI) or Polybenzoxazole (PBO) material and one or more redistribution layers. As described above, the dummy area of the wafer layer may be located, for example, at the periphery of the wafer layer. In some embodiments, the periphery of the wafer layers is preserved as a means for providing structural support to structures formed when two or more wafer layers are vertically stacked. At this stage of the fabrication process, the periphery of the wafer layer is not occupied. According to some embodiments, a ring of thermal interface material may be formed at the periphery of the wafer layer to form a ring of the wafer around the wafer layer. In some embodiments, the thermal interface material ring may be formed prior to attachment of the wafer to the substrate. For example, the thermal interface material ring may be deposited and patterned prior to attaching the wafer. Alternatively, the ring of thermal interface material may be disposed (e.g., with a nozzle) on the substrate after the wafer is attached to the substrate.

The method 900 continues with operation 920 where a dielectric material is deposited to encapsulate the thermal interface material ring and the component of the wafer layer (e.g., the wafer). In some embodiments, the dielectric material may be an oxide-based dielectric, such as silicon oxide, deposited using plasma enhanced chemical vapor deposition or other suitable methods. The dielectric material may then be planarized by Chemical Mechanical Polishing (CMP). In an alternative embodiment, the dielectric material is a molding compound, such as an epoxy-based material, that is dispensed (e.g., coated) and naturally cooled and hardened. Once the molding compound is hardened, the molding compound may be partially ground and polished. As a result of the above process, the chip and thermal interface material ring are encapsulated in a dielectric material. In some embodiments, the dielectric layer extends over the entire surface of the wafer layer. In further embodiments, the dielectric material provides structural support when two or more wafer layers are stacked together. By way of example and not limitation, the dielectric material of operation 920 may be similar to the material in dummy region 220 in fig. 2A and 2B and the material in mold region 810 in fig. 8.

Referring to fig. 9, the method 900 continues with operation 930 where a thermally conductive structure is formed in the dielectric material. In some embodiments, the thermally conductive structure may be formed by: openings are formed in the dielectric material using photolithography and etching operations, and a thermally conductive material is then deposited in the openings to form thermally conductive structures. The thermally conductive structures may be arranged to form a heat dissipation path at the periphery of the wafer layer by physical contact with the ring of thermal interface material, such as (i) sections of complementary thermally conductive structures 295A and complementary structures 295B as shown in fig. 2B; and (ii) a vertical structure 880 as shown in fig. 8. In some embodiments, if the dielectric material is a molding compound, the thermally conductive structure is formed prior to application of the molding compound onto the wafer layer. For example, the thermally conductive structure may be formed in a sacrificial photoresist layer that is removed prior to forming the molding compound. Thus, when the molding compound is dispensed onto the wafer layer, there is a thermally conductive structure. In this case, operation 930 may be performed before operation 920, depending on the type of dielectric material.

Referring to fig. 9, the method 900 continues with operation 940 where two or more wafer layers are stacked together to form a 3D system integrated wafer structure. In some embodiments, a bond structure (such as bond pad structure 250 shown in fig. 2A and 2B, or hybrid bond structure 840 shown in fig. 8) and an interface layer (such as interface layer 860 shown in fig. 8) may be formed prior to stacking the wafer layers together to facilitate mechanical and electrical coupling of adjacent wafer layers. In alternative embodiments, an interface layer (such as interface layer 860 shown in fig. 8) or bonding structure may be present on the substrate before the wafer is attached to the substrate to form a wafer layer. In some embodiments, the wafer layers are then aligned via an alignment process using the alignment marks as a guide so that their respective mechanical and electrical connection points are properly aligned when the wafer layers are stacked. The aligned wafer layers are then bonded together to form a stack. In some embodiments, the wafer layer stack is diced at the end of the bonding process.

The present disclosure relates to a heat dissipation structure that may be formed in a functional area or a non-functional area of a 3D system integrated chip structure. In some embodiments, the heat dissipation structure maintains an average operating temperature of the memory die or chip below about 90 ℃. By way of example and not limitation, the heat dissipation structure may include a ring of Thermal Interface Material (TIM) and vertical conductive structures disposed in a dummy region or a molding region of the 3D system integrated wafer structure, vertical conductive structures disposed within the wafer region and around a heat output region (hot spot), or a combination thereof. In some embodiments, existing vertical structures in the 3D system integrated wafer structure may be structurally modified to serve as additional heat dissipation paths. The embodiments described herein may be applied to a range of 3D system integrated wafer structures including, but not limited to, 3D system integrated wafer structures having a virtual area and a molding area.

In some embodiments, the heat dissipation structure comprises a stack of one or more wafer layers, wherein each wafer layer comprises: a central portion having one or more dies, and an edge portion surrounding the central portion, the edge portion having a ring of thermal interface material. The structure also includes a thermal interface material layer disposed over the top wafer layer of the stack, and a heat spreader over the thermal interface material layer.

In some embodiments, the heat dissipation structure further comprises a dummy region located at an edge portion of each of the wafer layers, wherein the dummy region comprises a dielectric material disposed on and in physical contact with the thermal interface material ring; a first thermally conductive structure extending laterally through the dielectric material of the dummy region; and a second thermally conductive structure extending vertically through the dielectric material of the dummy region, wherein the first thermally conductive structure, the second thermally conductive structure, and the ring of thermal interface material are configured to direct heat generated in the stack toward the heat sink via an edge portion of each of the wafer layers.

In some embodiments, the first and second thermally conductive structures comprise a material having a thermal conductivity greater than about 200W/m-K.

In some embodiments, the ring of thermal interface material forms a continuous layer around one or more of the wafer layers.

In some embodiments, the continuous layer has a thickness between about 0.3mm and about 0.8 mm.

In some embodiments, the one or more chips include a memory chip.

In some embodiments, a method includes attaching one or more wafers in a first region of a substrate, wherein the substrate with the one or more wafers forms a first wafer layer. The method further includes depositing a thermal interface material on a second region of the substrate, wherein the thermal interface material forms a closed loop around the one or more wafers; forming one or more thermally conductive structures on the thermal interface material; and depositing a dielectric layer on the substrate such that the one or more wafers and the thermally conductive structure are embedded in the dielectric layer.

In some embodiments, the above method further comprises: forming a second wafer layer; and vertically stacking the first and second wafer layers to form a stack such that the one or more thermally conductive structures of the first wafer layer are aligned with the corresponding one or more thermally conductive structures of the second wafer layer, and wherein the thermal interface material of the first wafer layer is aligned with the corresponding thermal interface material of the second wafer layer.

In some embodiments, the above method further comprises: forming a thermal interface material layer on the dielectric layer of the second wafer layer, wherein the thermal interface material layer covers the entire surface of the dielectric layer; and disposing a heat spreader on the layer of thermal interface material such that heat generated by the first and second wafer layers is directed to the heat spreader via the thermal interface material of the first and second wafer layers and the thermally conductive structures of the first and second wafer layers.

In some embodiments, forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures to have a thermal conductivity greater than about 200W/(m-K).

In some embodiments, depositing the thermal interface material includes depositing a thermal interface material having a thickness between about 0.3mm and about 0.8 mm.

In some embodiments, forming the one or more thermally conductive structures includes forming the one or more thermally conductive structures to have a diameter between about 0.5 μm and about 2 μm.

In some embodiments, a structure includes a bottom wafer layer and a die stack on the bottom wafer layer. The stack includes an interconnect layer configured to provide an interconnect for the die, wherein the interconnect layer includes a first vertical thermally conductive structure. The stack also includes a molding region surrounding each die in the stack, wherein the molding region includes a second vertical thermally conductive structure and a thermal interface material.

In some embodiments, the diameter of the first vertical heat conducting structure is greater than the diameter of the second vertical heat conducting structure.

In some embodiments, a thermal interface material is interposed between a top surface of the first vertical thermally conductive structure and a bottom surface of the second vertical thermally conductive structure.

In some embodiments, the thermal interface material forms a continuous layer around the periphery of each die in the stack.

In some embodiments, the first and second vertical thermally conductive structures comprise a material having a thermal conductivity greater than about 200W/(m-K).

In some embodiments, the above structure further comprises: an additional thermal interface material over the stack of the plurality of die, wherein the additional thermal interface material covers an entire surface of the stack; and a heat spreader over the other thermal interface material layer.

In some embodiments, the above structure further comprises: a plurality of conductive structures disposed in the bottom wafer layer; and a plurality of third vertical heat conducting structures disposed in the bottom wafer layer and distributed between the electrically conductive structures, wherein the third vertical heat conducting structures are configured to direct heat generated by the bottom wafer layer to the heat sink via the first vertical heat conducting structures, the thermal interface material, the second vertical heat conducting structures, and the other thermal interface material.

In some embodiments, the first vertical heat conducting structure, the second vertical heat conducting structure, the third vertical heat conducting structure, and the thermal interface material are configured to transfer heat away from the die stack.

It should be understood that the detailed description section, and not the abstract section, of the disclosure is intended to be used to interpret the claims. The abstract section of the disclosure may set forth one or more, but not all possible embodiments of the disclosure as contemplated by the inventors, and is therefore not intended to limit the appended claims in any way.

The foregoing disclosure summarizes features of several embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. A heat dissipation structure, comprising:

a stack of one or more wafer layers, wherein each wafer layer comprises:

a central portion including one or more wafers; and

a rim portion surrounding the central portion and comprising a ring of thermal interface material;

a thermal interface material layer disposed on a top wafer layer of the stack; and

a heat spreader over the thermal interface material layer.

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