TW201635472A - Integrated electronic packaging method - Google Patents
Integrated electronic packaging method Download PDFInfo
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- TW201635472A TW201635472A TW104108461A TW104108461A TW201635472A TW 201635472 A TW201635472 A TW 201635472A TW 104108461 A TW104108461 A TW 104108461A TW 104108461 A TW104108461 A TW 104108461A TW 201635472 A TW201635472 A TW 201635472A
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- melting point
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- ball grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
本發明係開發一種整合性電子構裝方法，其係利用一套高熔點球柵陣列，結合另一套高熔點球柵陣列，來開發整合型的系統單晶片(SoC)。 The present invention develops an integrated electronic assembly method that utilizes a high melting point ball grid array in combination with another high melting ball grid array to develop an integrated system single wafer (SoC).
隨著積體電路(Integrated Circuit，IC)製程技術不斷的精進，電子產品全面朝輕薄短小的整合型系統單晶片開發。傳統打線(Wire Bond)技術已經不能符合通訊和其他先進IC對高傳輸速率的需求；覆晶式的晶圓構裝(Wafer Level Package)成為晶片尺吋構裝(CSP)的技術主流。然而球柵陣列式覆晶構裝，錫球的生命週期(life times)完全取決於錫球的高度，如果錫球品質未能達到可靠性品質要求，必須要在覆晶球柵陣列和基板或印刷電路板之間添加一層封晶底膠(underfill)來進一步保證錫球和基板，或是印刷電路板的接合強度，才足以通過可靠性檢測。加了封晶底膠之後，不易在後續製程再做測試修補(repair)，使得添加封裝底膠成為製程瓶頸。同時錫球高度和錫球間距(Solder Pitch)有著密切關聯，目前不加封裝底膠的單套式覆晶構裝侷限在低腳數I/O，無法作更廣泛應用。 With the continuous advancement of integrated circuit (IC) process technology, electronic products are being developed in a single, thin, integrated system. Traditional Wire Bond technology has been unable to meet the high transmission rate requirements of communications and other advanced ICs; the Wafer Level Package has become the mainstream technology for wafer size (CSP). However, the ball grid array flip chip structure, the life cycle of the solder ball depends entirely on the height of the solder ball. If the quality of the solder ball fails to meet the reliability quality requirements, it must be on the flip chip array and substrate or An underfill is added between the printed circuit boards to further ensure the bonding strength of the solder balls and the substrate, or the printed circuit board, to pass the reliability test. After the sealant is added, it is not easy to repair and repair in the subsequent process, so that the addition of the package primer becomes a process bottleneck. At the same time, the height of the solder ball is closely related to the solder ball pitch (Solder Pitch). At present, the single-layer flip chip mounting without the package primer is limited to the low-number I/O, which cannot be widely used.
作者在我國專利第I233673案號已經提出了兩套式球柵陣列結構，晶片上的高熔點球柵陣列經由球柵陣列封裝(Ball Grid Array，BGA) 基板或晶片上的高熔點球柵陣列，直接接合主機板上相對應的高熔點球柵陣列，雖然可以有效的提昇錫球可靠性生命週期，由於BGA基板之錫球間距無法有效地降低，無法滿足高腳數I/O對於晶片尺吋(CSP)需求，同時無法有效整合其他IC，無法滿足顧客對於整合性系統單晶片的功能需求。 The author has proposed a two-piece ball grid array structure in the patent No. I233673 of the Chinese patent. The high melting ball grid array on the wafer is encapsulated by a Ball Grid Array (BGA). The high-melting ball grid array on the substrate or the wafer directly connects the corresponding high-melting ball grid array on the motherboard, although the reliability life cycle of the solder ball can be effectively improved, because the solder ball pitch of the BGA substrate cannot be effectively reduced, Satisfying the high-count I/O requirements for chip size (CSP), while not effectively integrating other ICs, can not meet the customer's functional requirements for integrated system single-chip.
本發明方法說明如下：主體晶片(該晶片)被使用作矽基板，提供至少一主體晶片，包括一主體晶片上層(背面)和一主體晶片下層(正面)；安置一套第一組高熔點球柵陣列於該主體晶片下層；安置至少一組獨立電訊指定區域於該主體晶片上層；安置一套第一組晶片於該主體晶片上層各指定區域正上方；安置一套第二組高熔點球柵陣列於該主體晶片上層各獨立指定區域上；主體晶片上層各指定區域的高熔點球柵陣列，正面朝上，與第一組晶片的指定區域相對應；安置一套第一組高熔點錫球陣列於第一組晶片之指定區域，第一組晶片的高熔點球柵陣列正面朝下，與主體晶片上層各指定區域之高熔點球柵陣列一對一相對應；經由迴銲製程連結主體晶片上層球柵陣列與第一組晶片各相對應球柵陣列，迴銲製程時，第一組高熔點錫球和第二組高熔點錫球不會熔融，低熔點錫球會熔融，冷卻，凝固；接合主體晶片上層球柵陣列，與第一組晶片各相對應球柵陣列；主體晶片上層指定區域安置之複數高熔點錫球與晶片下層相對應之複數高熔點錫球，電訊相通。 The method of the present invention is described as follows: a main body wafer (the wafer) is used as a germanium substrate, and at least one main body wafer is provided, including a main body wafer upper layer (back surface) and a main body wafer lower layer (front surface); and a first set of high melting point balls are disposed. Grid array is disposed on the lower layer of the main body wafer; at least one set of independent telecommunication designated areas are disposed on the upper layer of the main body wafer; a set of the first set of wafers is disposed directly above each designated area of the upper layer of the main body wafer; and a second set of high melting point ball grids is disposed Arrays are respectively disposed on the respective designated areas of the upper layer of the main body wafer; the high-melting-point ball grid arrays of the designated areas of the upper layer of the main body wafer face up, corresponding to the designated areas of the first group of wafers; and the first set of high-melting-point solder balls are disposed Arrayed in a designated area of the first set of wafers, the high melting point ball grid array of the first set of wafers facing downward, corresponding to the high melting ball grid array of each designated area of the upper layer of the main body wafer; the main body wafer is connected via a reflow process The upper ball grid array and the first group of wafers respectively correspond to the ball grid array. During the reflow process, the first set of high melting point solder balls and the second set of high melting point solder balls do not melt The low melting point solder ball will melt, cool and solidify; the upper ball grid array of the main body wafer is bonded to the ball grid array corresponding to the first group of wafers; and the plurality of high melting point tin balls disposed in the designated area of the upper layer of the main body wafer correspond to the lower layer of the wafer High melting point solder balls, telecommunications.
接著下來，提供該主體晶片與主機板接合的流程，說明如下：提供一印刷電路板；其係位於主體晶片下層之下方；該主體晶片下層的高熔點球柵陣列，正面朝下與該印刷電路板上指定區域相對應；安置一 套第二組高熔點球柵陣列於該印刷電路板上指定區域，該印刷電路板的球柵陣列與該主體晶片下層球柵陣列一對一相對應；經由迴銲製程，相接合印刷電路板球柵陣列和晶片球柵陣列；迴銲製程時，第一組高熔點錫球和第二組高熔點錫球不會熔融，低熔點錫球會熔融，冷卻，凝固，接合晶片下層球柵陣列與印刷電路板之球柵陣列；或是該主體晶片下層的高熔點球柵陣列，正面朝下與該印刷電路板上指定區域相對應，並直接相接合印刷電路板的指定區域和晶片球柵陣列，而不需在印刷電路板上增設球柵陣列。 Next, the process of bonding the main body chip to the motherboard is provided as follows: a printed circuit board is provided; the system is located below the lower layer of the main body wafer; the high melting point ball grid array of the lower layer of the main body wafer faces down and the printed circuit Corresponding to the designated area on the board; Locating a second set of high melting point ball grid arrays on designated areas of the printed circuit board, the ball grid array of the printed circuit board corresponding to the main wafer lower layer ball grid array one-to-one; through the reflow process, bonding the printed circuit board Ball grid array and wafer ball grid array; during the reflow process, the first set of high melting point solder balls and the second set of high melting point solder balls will not melt, and the low melting point solder balls will melt, cool, solidify, and bond the lower layer of the ball grid array a ball grid array with a printed circuit board; or a high-melting ball grid array of the lower layer of the main body wafer, facing downwardly corresponding to a designated area on the printed circuit board, and directly bonding a specified area of the printed circuit board and the wafer ball grid The array does not require the addition of a ball grid array on the printed circuit board.
本發明主要目的係提供一種整合性電子構裝方法，其係利用兩套式錫球封裝之覆晶式封裝，應用矽基板結合多晶片系統單晶片構裝(SIP)來開發整合型系統單晶片。 The main object of the present invention is to provide an integrated electronic assembly method for developing an integrated system single chip by using a two-chip tin-ball package flip-chip package using a germanium substrate combined with a multi-wafer system single-chip package (SIP). .
本發明之另一目的係提供一種整合性電子構裝方法，應用矽基板結合多晶片系統單晶片構裝(SIP)；開發記憶體系統單晶片。 Another object of the present invention is to provide an integrated electronic assembly method using a germanium substrate in combination with a multi-wafer system single wafer package (SIP); a memory system single wafer is developed.
主體晶片可以被選擇為中央處理器(CPU)或是繪圖處理器(GPU)或微處理器(MCU)，ARM架構的微處理具備低耗功能特性，適合整合性晶片使用，運算單元為8位元至128位元。本發明所提供的第一組晶片，應用於整合性的系統單晶片，應用很廣，例如物聯網(Internet of Things)的獨立晶片，包含感測晶片，網通晶片，運算晶片，控制晶片和儲存晶片，整合性功能包括多層次量測、上網、即時運算、資訊反饋和傳輸，感測晶片包括對外在環境變動因子例如溫度，壓力的偵測；網通晶片包含對外部區域網路系統和外部網際網路系統的傳輸包括雲端系統資料傳輸、監控。儲存晶片包括動態隨機記憶體(DRAM)的整合應用。 The main body chip can be selected as a central processing unit (CPU) or a graphics processing unit (GPU) or a microprocessor (MCU). The ARM architecture micro-processing has low-power function and is suitable for integrated wafer use. The arithmetic unit is 8-bit. Yuan to 128 bits. The first set of wafers provided by the present invention is applied to an integrated system single chip, which is widely used, such as an independent wafer of the Internet of Things, including a sensing wafer, a Netcom wafer, an arithmetic wafer, a control wafer, and a storage. The integrated functions of the chip include multi-level measurement, Internet access, real-time operation, information feedback and transmission. The sensing chip includes external environmental variation factors such as temperature and pressure detection. The Netcom chip includes external network system and external network. The transmission of the network system includes data transmission and monitoring of the cloud system. Storage chips include integrated applications of dynamic random access memory (DRAM).
記憶體系統單晶片的開發，其中主體晶片使用記憶體控制晶 片，應用於第一組晶片的獨立晶片為可以選擇為堆疊式快閃記憶體(Nand Flash)晶片或是堆疊式動態隨機記憶體晶片(DRAM)，其他應用晶片尚且包括SRAM和其他記憶體運算晶片。 Memory system single chip development, in which the main body wafer uses memory control crystal The individual wafers applied to the first set of wafers can be selected as stacked flash memory (Nand Flash) chips or stacked dynamic random access memory (DRAM) chips. Other application chips include SRAM and other memory operations. Wafer.
兩套式錫球封裝的第一組高熔點球柵陣列結合第二組高熔點球柵陣列，被有效應用此發明結構中，其中第一組高熔點球柵(上套)陣列係被安置在主體晶片的正面層，和第一組晶片的正面層；第二組高熔點球柵陣列係被安置在印刷電路板上層和主體晶片背面層的各個指定區域上。第一組高熔點球柵陣列包括高熔點錫球陣列或高熔點錫球合金陣列所組成的球柵陣列；同樣的，第二組高熔點球柵陣列包括高熔點錫球陣列或高熔點錫球合金陣列；高熔點錫球合金，例如銅柱(高熔點錫球)凸塊錫球陣列係在高熔點錫球前端安置一短幅度的低熔點錫球接合區。迴銲製程時，第一組高熔點錫球和第二組高熔點錫球不會熔融，低熔點錫球會熔融，冷卻，凝固再接合第一組球柵陣列和第二組球柵陣列。第一組球柵陣列和第二組球柵陣列的接合製程，如果第一組錫球使用高熔點錫球合金，在迴銲製程時，不需使用到錫膏，依靠高熔點錫球合金所包含的低熔點錫球來完成接合製程。 The first set of high melting point ball grid arrays of the two sets of solder ball packages combined with the second set of high melting point ball grid arrays are effectively applied in the structure of the invention, wherein the first set of high melting point ball grid (top sleeve) arrays are placed in The front side of the body wafer, and the front side of the first set of wafers; the second set of high melting point ball grid arrays are disposed on each of the designated areas of the printed circuit board layer and the back side layer of the body wafer. The first set of high melting point ball grid arrays comprises a ball grid array of high melting point solder ball arrays or high melting point solder ball alloy arrays; likewise, the second set of high melting point ball grid arrays comprises high melting point solder ball arrays or high melting point solder balls Alloy array; high melting point tin ball alloy, such as copper column (high melting point tin ball) bump solder ball array is placed at the front end of the high melting point solder ball with a short range of low melting point solder ball joint. During the reflow process, the first set of high melting point solder balls and the second set of high melting point solder balls do not melt, the low melting point solder balls melt, cool, solidify and then join the first set of ball grid arrays and the second set of ball grid arrays. The bonding process of the first set of ball grid arrays and the second set of ball grid arrays, if the first group of solder balls uses a high melting point tin ball alloy, no solder paste is needed during the reflow process, and the high melting point tin ball alloy is used. The low melting point tin ball is included to complete the bonding process.
第一組高熔點球柵陣列和第二組高熔點球柵陣列相對應高熔點錫球前端，設計一平坦區，可以充做錫墊(solder pad)使用。參照專利案號I233673，第二組高熔點錫球前端可進一步被設計成一中間凹兩邊高的平坦區，如此可有效承載上端第一組高熔點球柵陣列的低熔點錫球或高熔點錫球或低熔點錫膏；迴銲製程時，第一組高熔點錫球和第二組高熔點錫球不會熔融，第一組低熔點錫球會熔融，冷卻凝固後，接合第一組高熔 點球柵陣列和第二組高熔點球柵陣列。 The first set of high melting ball grid arrays and the second set of high melting ball grid arrays correspond to the high melting point solder ball front end, and a flat area is designed to be used as a solder pad. Referring to Patent No. I233673, the front end of the second set of high melting point solder balls can be further designed as a flat area with two concave sides on both sides, so as to effectively carry the low melting point solder balls or high melting point solder balls of the first set of high melting point ball grid arrays at the upper end. Or a low melting point solder paste; during the reflow process, the first set of high melting point solder balls and the second set of high melting point solder balls will not melt, the first set of low melting point tin balls will melt, after cooling and solidification, the first set of high melting is joined A ball grid array and a second set of high melting ball grid arrays.
底下藉由具體實例，配合所附的圖示詳加說明，當更瞭解發明之目的，技術內容，特點及其達成之功效。 The specific examples, with the accompanying drawings, are explained in detail below, and the purpose of the invention, the technical content, the features and the effects achieved are better understood.
8‧‧‧第一組晶片 8‧‧‧First set of wafers
10‧‧‧主體晶片 10‧‧‧Subject wafer
11‧‧‧第一組高熔點錫球陣列 11‧‧‧The first set of high melting point solder ball arrays
12‧‧‧第一組高熔點錫球合金陣列 12‧‧‧The first set of high melting point solder ball alloy arrays
13‧‧‧第一組高熔點錫球 13‧‧‧The first group of high melting point solder balls
14‧‧‧第二組高熔點錫球陣列 14‧‧‧Second group of high melting point solder ball arrays
15‧‧‧錫膏 15‧‧‧ solder paste
16‧‧‧低熔點錫球 16‧‧‧low melting point solder balls
18‧‧‧印刷電路板 18‧‧‧Printed circuit board
25‧‧‧平坦區 25‧‧‧flat area
30‧‧‧主體晶片 30‧‧‧Subject wafer
32‧‧‧感測晶片 32‧‧‧Sensor wafer
34‧‧‧網通晶片 34‧‧‧ Netcom Chip
36‧‧‧運算晶片 36‧‧‧Operating chip
38‧‧‧控制晶片 38‧‧‧Control chip
40‧‧‧高熔點錫球 40‧‧‧High melting point solder balls
第1a~d圖係為本發明的第一實施例流程示意圖。 1a to d are schematic views of the flow of the first embodiment of the present invention.
第2a~d圖係為本發明的第二實施例流程示意圖。 2a~d are schematic views of the flow of the second embodiment of the present invention.
第3a圖係為本發明使用於微處理器晶片的平面正視圖。 Figure 3a is a plan elevational view of the microprocessor wafer used in the present invention.
第3b圖係為本發明第3a圖高熔點錫球對接的側視圖。 Figure 3b is a side view of the docking of the high melting point solder balls of Figure 3a of the present invention.
第4a~d圖係為本發明的第三實施例流程示意圖。 4a~d are schematic views of the flow of the third embodiment of the present invention.
傳統的記憶體儲存器，例如DRAM記憶體模組或SSD(固態硬碟)都要經由PCI匯流排的插槽來輸入，記憶體系統整合性單晶片則沒有這限制，應用層面有其特殊的考量。 Traditional memory storage devices, such as DRAM memory modules or SSDs (solid-state hard disks), are input through the slots of the PCI bus. The memory system integrated single chip does not have this limitation, and the application layer has its special Consideration.
為了改善散熱需求，安置金屬散熱片在第一組晶片的背面晶片上，散熱片可以是鋁片，銅片或其他合金金屬片。接著下來，利用圖例對本發明變更清晰說明，如第1a~d圖所示，以晶圓封裝的覆晶封裝為主體，第一組高熔點球錫球合金陣列12結合第二組高熔點錫球陣列14，製作整合性系統單晶片，製程流程圖如第1a圖所顯示，提供至少一獨立指定區域於主體晶片10的背面晶片層，提供一獨立第一組晶片8，其係位於該主體晶片10各個指定區域正上方，安置一套第二組高熔點錫球陣列14於該主體晶片10各個獨立指定區域上；安置一套第一組高熔點錫球合金陣列12於各個第 一組獨立第一組晶片8的指定區域上；第一組高熔點錫球合金陣列12的每一高熔點錫球合金，其係在第一組高熔點錫球13前端延伸生長一短幅度低熔點錫球合金接合區的低熔點錫球16，作為接合使用，第一組高熔點錫球合金陣列12正面朝下，與正下方第二組各個指定區域上的第二組高熔點錫球陣列14一對一相對應；第一組高熔點錫球13所組成的第一組高熔點錫球合金陣列和第二組高熔點錫球陣列14之高熔點錫球前端設計有一平坦區25；經由迴銲製程，接合第一組晶片8的第一組高熔點錫球合金陣列12與該主體晶片10背面層相對應各個指定區域上的第二組高熔點錫球陣列14，迴銲過程時，第一組高熔點錫球13和第二組高熔點錫球陣列14的高熔點錫球不會熔融，低熔點錫球16會熔融，冷卻凝固後，接合第一組晶片8各高熔點合金陣列和相對應之第二組高熔點錫球陣列14如第1b圖所示。 In order to improve the heat dissipation requirement, the metal heat sink is placed on the back wafer of the first set of wafers, and the heat sink may be an aluminum sheet, a copper sheet or other alloy metal sheet. Next, a clear description of the present invention will be made using the legend. As shown in Figures 1a to d, the first set of high melting point ball solder alloy array 12 is combined with a second set of high melting point solder balls. Array 14, an integrated system single wafer, process flow diagram as shown in Figure 1a, providing at least one independently designated area on the back wafer layer of the body wafer 10, providing a separate first set of wafers 8 located in the body wafer 10 directly above each designated area, a second set of high melting point solder ball arrays 14 are disposed on each of the independent designated areas of the main body wafer 10; a first set of high melting point solder ball alloy arrays 12 are disposed in each of the first a set of independent first set of wafers 8 on a designated area; each of the high melting point tin ball alloys of the first set of high melting point solder ball arrays 12, which are grown at a front end of the first set of high melting point solder balls 13 for a short period of low a low melting point solder ball 16 of a melting point solder ball alloy joint region, used as a joint, the first set of high melting point solder ball alloy array 12 facing downward, and a second set of high melting point solder ball arrays on the respective designated areas of the second group directly below 14 one-to-one correspondence; a first set of high melting point solder ball arrays composed of a first set of high melting point solder balls 13 and a high melting point solder ball front end of a second set of high melting point solder ball arrays 14 are designed with a flat zone 25; a reflow process, the first set of high melting point solder ball alloy arrays 12 joining the first set of wafers 8 and the second set of high melting point solder ball arrays 14 on the respective designated areas corresponding to the back side layer of the main body wafer 10, during the reflow process, The high melting point solder balls of the first set of high melting point solder balls 13 and the second set of high melting point solder ball arrays 14 are not melted, and the low melting point solder balls 16 are melted. After cooling and solidifying, the first set of wafers 8 are bonded to each of the high melting point alloy arrays. And the corresponding second set of high melting point solder ball arrays 14 as shown in Figure 1b.
接著下來，討論主體晶片正面層的球柵陣列與印刷電路板的接合。如第1c圖所顯示提供一印刷電路板18位於該主體晶片10下方；安置一套第一組高熔點錫球合金陣列12於該主體晶片10正面層，該主體晶片10正面層的高熔點錫球合金陣列12，正面朝下與該印刷電路板18上層指定區域相對應；安置一套第二組高熔點錫球陣列14於該印刷電路板18上指定區域，該印刷電路板18上的第二組高熔點錫球陣列14正面朝上，與該主體晶片10的第一組高熔點錫球合金陣列12相對應；經由迴銲製程接合該主體晶片10第一組高熔點錫球合金陣列12與印刷電路板18的第二組高熔點錫球陣列14；迴銲製程時，第一組高熔點錫球13和第二組高熔點錫球陣列14的高熔點錫球不會熔融，低熔點錫球16會熔融，冷卻，凝固後接合該主體晶片10正面層球柵陣列12與相對應印刷電路板18之球柵陣列14如第1d圖所示。 該主體晶片10背面層上的高熔點錫球與該主體晶片10正面層相對應之高熔點錫球電訊相通。第一組高熔點錫球陣列13和第二組高熔點錫球陣列14之高熔點錫球前端設計有一平坦區25。 Next, the bonding of the ball grid array of the front side of the main body wafer to the printed circuit board is discussed. A printed circuit board 18 is disposed under the main body wafer 10 as shown in FIG. 1c; a first set of high melting point solder ball alloy array 12 is disposed on the front surface of the main body wafer 10, and the high melting point tin of the front surface of the main body wafer 10 is disposed. A ball alloy array 12, facing downwardly corresponding to a designated area of the printed circuit board 18; a second set of high melting point solder ball arrays 14 disposed on a designated area of the printed circuit board 18, the printed circuit board 18 Two sets of high melting point solder ball arrays 14 face up, corresponding to the first set of high melting point solder ball alloy arrays 12 of the body wafer 10; the first set of high melting point solder ball alloy arrays 12 bonded to the body wafer 10 via a reflow process a second set of high melting point solder ball arrays 14 with printed circuit board 18; the high melting point solder balls of the first set of high melting point solder balls 13 and the second set of high melting point solder ball arrays 14 do not melt, low melting point during the reflow process The solder balls 16 are melted, cooled, and solidified to bond the front side ball grid array 12 of the main body wafer 10 and the ball grid array 14 of the corresponding printed circuit board 18 as shown in Fig. 1d. The high melting point tin ball on the back layer of the main body wafer 10 is in communication with the high melting point tin ball corresponding to the front layer of the main body wafer 10. The first set of high melting point solder ball arrays 13 and the second set of high melting point solder ball arrays 14 have a flat region 25 at the front end of the high melting point solder ball.
如第2a~d圖所示，如果第一組的高熔點錫球合金12置換成第一組高熔點錫球陣列11，它需要安置一層錫膏15在第一組高熔點錫球陣列11和第二組高熔點錫球陣列14之間，迴銲製程時錫膏15會熔融，冷卻後接合第一組高熔點錫球陣列11和第二組高熔點錫球陣列14，其餘製程不變，請參照第2a圖至第2d圖的流程圖所示。 As shown in Figures 2a to d, if the first set of high melting point tin ball alloys 12 are replaced by the first set of high melting point solder ball arrays 11, it is necessary to place a layer of solder paste 15 in the first set of high melting point solder ball arrays 11 and Between the second set of high melting point solder ball arrays 14, the solder paste 15 will melt during the reflow process, and after cooling, the first set of high melting point solder ball arrays 11 and the second set of high melting point solder ball arrays 14 are bonded, and the remaining processes are unchanged. Please refer to the flowcharts in Figures 2a to 2d.
如第3a~b圖所示，主體晶片30使用微處理器(MCU)來整合第一組晶片，例如物聯網(IoT)的感測晶片32、網通晶片34、運算晶片36或其他控制晶片38，更可包含儲存晶片(圖中未示)，平面正視圖如第3a圖所示。再請同時參照第3b顯示側面結構圖係為高熔點錫球40對接的側視圖。 As shown in Figures 3a-b, the body wafer 30 uses a microprocessor (MCU) to integrate a first set of wafers, such as an IoT sensing wafer 32, a Netcom wafer 34, an operational wafer 36, or other control wafer 38. It may further include a storage wafer (not shown), and the front view of the plane is as shown in Fig. 3a. Please also refer to the side view of the 3b side as a side view of the high melting point solder ball 40 butt joint.
再者，除了上述之實施例外，本發明另外提供一種實施例，刷電路板18位於該主體晶片10下方；安置一套第一組高熔點錫球合金陣列12於該主體晶片10正面層，該主體晶片10正面層的高熔點錫球合金陣列12，正面朝下與該印刷電路板18上層指定區域相對應；該印刷電路板18上的指定區域正面朝上，與該主體晶片10的第一組高熔點錫球合金陣列12相對應；經由迴銲製程接合該主體晶片10第一組高熔點其係於主體晶片10正面層的球柵陣列與印刷電路板18的另一接合方法，提供一印錫球合金陣列12與印刷電路板18的指定區域；迴銲製程時，第一組高熔點錫球13的高熔點錫球不會熔融，低熔點錫球會熔融，冷卻，凝固後接合該主體晶片10正 面層球柵陣列與相對應印刷電路板18之指定區域，於本段所述之實施例僅此步驟與前述之實施例不相同，提供另一種接合方法，使主體晶片10正面層的球柵陣列直接與印刷電路板18的指定區域相接合，使印刷電路板18可不需設置球柵陣列，組合過程請參照第4a圖至第4d圖所示。本段的實施例其餘步驟方法皆與前述之實施例相同，故不在此贅述。 Furthermore, in addition to the above-described implementation, the present invention further provides an embodiment in which the brush circuit board 18 is located under the main body wafer 10; a first set of high melting point solder ball alloy array 12 is disposed on the front surface of the main body wafer 10, The high melting point solder ball alloy array 12 on the front side of the main body wafer 10 faces downwardly corresponding to a designated area on the upper surface of the printed circuit board 18; the designated area on the printed circuit board 18 faces up, and the first of the main body wafer 10 The high-melting-point solder ball array 12 corresponds to a high-melting-point solder ball array 12; and the first group of high-melting-point ball grid arrays of the main wafer 10 and the printed circuit board 18 are bonded to each other by a reflow process. The specified area of the solder ball alloy array 12 and the printed circuit board 18; during the reflow process, the high melting point solder balls of the first set of high melting point solder balls 13 will not melt, the low melting point solder balls will melt, cool, and solidify and bond Body wafer 10 is positive The surface ball grid array and the designated area of the corresponding printed circuit board 18, the embodiment described in this paragraph is only different from the foregoing embodiment, and another bonding method is provided to make the ball grid of the front layer of the main body wafer 10. The array is directly bonded to a designated area of the printed circuit board 18 so that the printed circuit board 18 does not need to be provided with a ball grid array. The combination process is shown in Figures 4a through 4d. The rest of the steps of the embodiment of this paragraph are the same as the foregoing embodiments, and therefore are not described herein.
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。 The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.
8‧‧‧第一組晶片 8‧‧‧First set of wafers
10‧‧‧主體晶片 10‧‧‧Subject wafer
13‧‧‧第一組高熔點錫球 13‧‧‧The first group of high melting point solder balls
14‧‧‧第二組高熔點錫球陣列 14‧‧‧Second group of high melting point solder ball arrays
18‧‧‧印刷電路板 18‧‧‧Printed circuit board
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